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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.15 95.95 94.24 100.00 84.62 92.33 99.49 99.42


Total test records in report: 659
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T540 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2456455571 Jul 03 06:00:39 PM PDT 24 Jul 03 06:00:39 PM PDT 24 44904616 ps
T541 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.4019196410 Jul 03 06:00:14 PM PDT 24 Jul 03 06:00:15 PM PDT 24 35416421 ps
T542 /workspace/coverage/cover_reg_top/4.hmac_intr_test.697094450 Jul 03 06:00:18 PM PDT 24 Jul 03 06:00:19 PM PDT 24 14309041 ps
T110 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1818425035 Jul 03 06:00:12 PM PDT 24 Jul 03 06:00:13 PM PDT 24 43685324 ps
T543 /workspace/coverage/cover_reg_top/9.hmac_intr_test.471887642 Jul 03 06:00:32 PM PDT 24 Jul 03 06:00:34 PM PDT 24 80243461 ps
T79 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1797709286 Jul 03 06:00:30 PM PDT 24 Jul 03 06:00:33 PM PDT 24 599751466 ps
T544 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1914469927 Jul 03 06:00:12 PM PDT 24 Jul 03 06:00:13 PM PDT 24 13455135 ps
T545 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1446362212 Jul 03 06:00:16 PM PDT 24 Jul 03 06:00:23 PM PDT 24 4265123760 ps
T546 /workspace/coverage/cover_reg_top/33.hmac_intr_test.206647412 Jul 03 06:00:40 PM PDT 24 Jul 03 06:00:41 PM PDT 24 79894133 ps
T547 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3352194097 Jul 03 06:00:43 PM PDT 24 Jul 03 06:00:45 PM PDT 24 51090018 ps
T548 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2289673297 Jul 03 06:00:35 PM PDT 24 Jul 03 06:00:36 PM PDT 24 47756164 ps
T111 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1121936691 Jul 03 06:00:31 PM PDT 24 Jul 03 06:00:32 PM PDT 24 21010850 ps
T112 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.26926365 Jul 03 06:00:27 PM PDT 24 Jul 03 06:00:28 PM PDT 24 16789457 ps
T549 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1837435181 Jul 03 06:00:35 PM PDT 24 Jul 03 06:00:36 PM PDT 24 22841944 ps
T550 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2630779375 Jul 03 06:00:45 PM PDT 24 Jul 03 06:00:46 PM PDT 24 18099698 ps
T551 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3177540764 Jul 03 06:00:49 PM PDT 24 Jul 03 06:00:50 PM PDT 24 56444206 ps
T552 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2204746836 Jul 03 06:00:40 PM PDT 24 Jul 03 06:00:41 PM PDT 24 13220171 ps
T80 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3343761087 Jul 03 06:00:32 PM PDT 24 Jul 03 06:00:36 PM PDT 24 250754887 ps
T553 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1263104636 Jul 03 06:00:31 PM PDT 24 Jul 03 06:00:36 PM PDT 24 159650552 ps
T81 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1157142870 Jul 03 06:00:13 PM PDT 24 Jul 03 06:00:18 PM PDT 24 1404539675 ps
T554 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3300281682 Jul 03 06:00:32 PM PDT 24 Jul 03 06:00:33 PM PDT 24 145041968 ps
T113 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.249720822 Jul 03 06:00:19 PM PDT 24 Jul 03 06:00:21 PM PDT 24 22743213 ps
T125 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4176378834 Jul 03 06:00:33 PM PDT 24 Jul 03 06:00:36 PM PDT 24 552555380 ps
T555 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2387313047 Jul 03 06:00:15 PM PDT 24 Jul 03 06:00:16 PM PDT 24 23255130 ps
T556 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1162771056 Jul 03 06:00:14 PM PDT 24 Jul 03 06:00:17 PM PDT 24 128165857 ps
T126 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.199333413 Jul 03 06:00:38 PM PDT 24 Jul 03 06:00:39 PM PDT 24 215957309 ps
T557 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2862883615 Jul 03 06:00:34 PM PDT 24 Jul 03 06:00:36 PM PDT 24 59879217 ps
T558 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1633351666 Jul 03 06:00:41 PM PDT 24 Jul 03 06:00:42 PM PDT 24 32549352 ps
T559 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.700871779 Jul 03 06:00:36 PM PDT 24 Jul 03 06:00:39 PM PDT 24 130868985 ps
T127 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2509968020 Jul 03 06:00:31 PM PDT 24 Jul 03 06:00:33 PM PDT 24 108738906 ps
T560 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1929150615 Jul 03 06:00:31 PM PDT 24 Jul 03 06:00:35 PM PDT 24 187735385 ps
T561 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.652728116 Jul 03 06:00:37 PM PDT 24 Jul 03 06:00:38 PM PDT 24 145365160 ps
T562 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2848350187 Jul 03 06:00:22 PM PDT 24 Jul 03 06:00:25 PM PDT 24 29323100 ps
T563 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3261623315 Jul 03 06:00:44 PM PDT 24 Jul 03 06:00:45 PM PDT 24 17961558 ps
T128 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.34619199 Jul 03 06:00:16 PM PDT 24 Jul 03 06:00:17 PM PDT 24 224868745 ps
T142 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2350963191 Jul 03 06:00:37 PM PDT 24 Jul 03 06:00:42 PM PDT 24 328754073 ps
T564 /workspace/coverage/cover_reg_top/3.hmac_intr_test.713278209 Jul 03 06:00:16 PM PDT 24 Jul 03 06:00:17 PM PDT 24 14439250 ps
T565 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.288979708 Jul 03 06:00:18 PM PDT 24 Jul 03 06:00:21 PM PDT 24 2490484403 ps
T114 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2527663145 Jul 03 06:00:14 PM PDT 24 Jul 03 06:00:15 PM PDT 24 35393553 ps
T566 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3139130302 Jul 03 06:00:30 PM PDT 24 Jul 03 06:00:32 PM PDT 24 71904782 ps
T129 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1194099976 Jul 03 06:00:32 PM PDT 24 Jul 03 06:00:34 PM PDT 24 176898448 ps
T130 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.420968934 Jul 03 06:00:31 PM PDT 24 Jul 03 06:00:34 PM PDT 24 121190674 ps
T115 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2053560081 Jul 03 06:00:33 PM PDT 24 Jul 03 06:00:34 PM PDT 24 17512558 ps
T567 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1235887259 Jul 03 06:00:36 PM PDT 24 Jul 03 06:00:38 PM PDT 24 40473188 ps
T116 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.36654452 Jul 03 06:00:31 PM PDT 24 Jul 03 06:00:32 PM PDT 24 35973093 ps
T120 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.748037369 Jul 03 06:00:10 PM PDT 24 Jul 03 06:00:17 PM PDT 24 1471709579 ps
T568 /workspace/coverage/cover_reg_top/7.hmac_intr_test.4109535895 Jul 03 06:00:33 PM PDT 24 Jul 03 06:00:34 PM PDT 24 11800662 ps
T569 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.222782795 Jul 03 06:00:35 PM PDT 24 Jul 03 06:00:38 PM PDT 24 122328919 ps
T131 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2254083720 Jul 03 06:00:30 PM PDT 24 Jul 03 06:00:33 PM PDT 24 256481460 ps
T570 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1655185619 Jul 03 06:00:10 PM PDT 24 Jul 03 06:00:11 PM PDT 24 39326084 ps
T571 /workspace/coverage/cover_reg_top/34.hmac_intr_test.780354316 Jul 03 06:00:46 PM PDT 24 Jul 03 06:00:47 PM PDT 24 14942052 ps
T117 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1173136295 Jul 03 06:00:24 PM PDT 24 Jul 03 06:00:38 PM PDT 24 385342218 ps
T140 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1569774528 Jul 03 06:00:31 PM PDT 24 Jul 03 06:00:34 PM PDT 24 100599074 ps
T572 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2096289440 Jul 03 06:00:13 PM PDT 24 Jul 03 06:00:16 PM PDT 24 105860279 ps
T132 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1075935159 Jul 03 06:00:33 PM PDT 24 Jul 03 06:00:36 PM PDT 24 161473674 ps
T118 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2930530474 Jul 03 06:00:36 PM PDT 24 Jul 03 06:00:37 PM PDT 24 13476951 ps
T573 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.432139347 Jul 03 06:00:30 PM PDT 24 Jul 03 06:00:31 PM PDT 24 214044095 ps
T574 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3182286803 Jul 03 06:00:33 PM PDT 24 Jul 03 06:00:34 PM PDT 24 54039738 ps
T575 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.415981277 Jul 03 06:00:35 PM PDT 24 Jul 03 06:00:38 PM PDT 24 39890122 ps
T576 /workspace/coverage/cover_reg_top/49.hmac_intr_test.3249157089 Jul 03 06:00:46 PM PDT 24 Jul 03 06:00:47 PM PDT 24 20048677 ps
T119 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.632596250 Jul 03 06:00:40 PM PDT 24 Jul 03 06:00:41 PM PDT 24 20580042 ps
T577 /workspace/coverage/cover_reg_top/30.hmac_intr_test.2735439963 Jul 03 06:00:39 PM PDT 24 Jul 03 06:00:40 PM PDT 24 108861662 ps
T121 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.869631390 Jul 03 06:00:15 PM PDT 24 Jul 03 06:00:18 PM PDT 24 321849330 ps
T578 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1798879471 Jul 03 06:00:09 PM PDT 24 Jul 03 06:00:11 PM PDT 24 26548453 ps
T150 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2483451438 Jul 03 06:00:17 PM PDT 24 Jul 03 06:00:19 PM PDT 24 1282657049 ps
T579 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1724339846 Jul 03 06:00:31 PM PDT 24 Jul 03 06:00:32 PM PDT 24 66267063 ps
T152 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.560479718 Jul 03 06:00:30 PM PDT 24 Jul 03 06:00:35 PM PDT 24 515440041 ps
T580 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3799888694 Jul 03 06:00:34 PM PDT 24 Jul 03 06:00:35 PM PDT 24 58947315 ps
T581 /workspace/coverage/cover_reg_top/29.hmac_intr_test.448863367 Jul 03 06:00:37 PM PDT 24 Jul 03 06:00:38 PM PDT 24 19476177 ps
T582 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1883521913 Jul 03 06:00:24 PM PDT 24 Jul 03 06:00:25 PM PDT 24 128795252 ps
T122 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2209607701 Jul 03 06:00:15 PM PDT 24 Jul 03 06:00:17 PM PDT 24 26451850 ps
T583 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2919538528 Jul 03 06:00:09 PM PDT 24 Jul 03 06:00:12 PM PDT 24 303021573 ps
T584 /workspace/coverage/cover_reg_top/14.hmac_intr_test.3441053241 Jul 03 06:00:32 PM PDT 24 Jul 03 06:00:33 PM PDT 24 29960883 ps
T585 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1675608886 Jul 03 06:00:38 PM PDT 24 Jul 03 06:00:39 PM PDT 24 30808451 ps
T586 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2750986504 Jul 03 06:00:09 PM PDT 24 Jul 03 06:00:12 PM PDT 24 66290110 ps
T587 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1899749028 Jul 03 06:00:21 PM PDT 24 Jul 03 06:00:22 PM PDT 24 26179125 ps
T141 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2177431105 Jul 03 06:00:09 PM PDT 24 Jul 03 06:00:13 PM PDT 24 170769812 ps
T145 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.268196834 Jul 03 06:00:35 PM PDT 24 Jul 03 06:00:39 PM PDT 24 360472911 ps
T588 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.826005506 Jul 03 06:00:32 PM PDT 24 Jul 03 06:00:36 PM PDT 24 1654288886 ps
T589 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1474538110 Jul 03 06:00:36 PM PDT 24 Jul 03 06:00:38 PM PDT 24 87295674 ps
T590 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2842509549 Jul 03 06:00:29 PM PDT 24 Jul 03 06:00:31 PM PDT 24 24896063 ps
T591 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2692892550 Jul 03 06:00:31 PM PDT 24 Jul 03 06:00:35 PM PDT 24 659429931 ps
T592 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3023077934 Jul 03 06:00:13 PM PDT 24 Jul 03 06:00:16 PM PDT 24 221839303 ps
T123 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1291432676 Jul 03 06:00:18 PM PDT 24 Jul 03 06:00:19 PM PDT 24 26931367 ps
T151 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2974512335 Jul 03 06:00:16 PM PDT 24 Jul 03 06:00:18 PM PDT 24 158398868 ps
T593 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1926693478 Jul 03 06:00:31 PM PDT 24 Jul 03 06:00:33 PM PDT 24 30904343 ps
T594 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3916490284 Jul 03 06:00:33 PM PDT 24 Jul 03 06:00:35 PM PDT 24 92827793 ps
T595 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2383334386 Jul 03 06:00:35 PM PDT 24 Jul 03 06:00:37 PM PDT 24 412583871 ps
T596 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3294247183 Jul 03 06:00:12 PM PDT 24 Jul 03 06:00:14 PM PDT 24 254619774 ps
T597 /workspace/coverage/cover_reg_top/13.hmac_intr_test.58593348 Jul 03 06:00:33 PM PDT 24 Jul 03 06:00:35 PM PDT 24 54616676 ps
T598 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3795471112 Jul 03 06:00:44 PM PDT 24 Jul 03 06:00:45 PM PDT 24 15436122 ps
T599 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2913187838 Jul 03 06:00:36 PM PDT 24 Jul 03 06:00:39 PM PDT 24 144677945 ps
T600 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.4154839402 Jul 03 06:00:30 PM PDT 24 Jul 03 06:00:32 PM PDT 24 84942913 ps
T601 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.365748702 Jul 03 06:00:40 PM PDT 24 Jul 03 06:00:42 PM PDT 24 88139302 ps
T124 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2680074978 Jul 03 06:00:24 PM PDT 24 Jul 03 06:00:25 PM PDT 24 24144752 ps
T602 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1618420078 Jul 03 06:00:37 PM PDT 24 Jul 03 06:00:38 PM PDT 24 10921131 ps
T603 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3899678584 Jul 03 06:00:37 PM PDT 24 Jul 03 06:00:38 PM PDT 24 50214400 ps
T146 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3962987820 Jul 03 06:00:34 PM PDT 24 Jul 03 06:00:38 PM PDT 24 181118914 ps
T604 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.536901907 Jul 03 06:00:32 PM PDT 24 Jul 03 06:00:33 PM PDT 24 20548574 ps
T605 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2757944779 Jul 03 06:00:24 PM PDT 24 Jul 03 06:00:26 PM PDT 24 98454219 ps
T606 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2771644333 Jul 03 06:00:15 PM PDT 24 Jul 03 06:00:18 PM PDT 24 111598493 ps
T607 /workspace/coverage/cover_reg_top/48.hmac_intr_test.481918012 Jul 03 06:00:44 PM PDT 24 Jul 03 06:00:45 PM PDT 24 53861910 ps
T147 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2857288198 Jul 03 06:00:34 PM PDT 24 Jul 03 06:00:38 PM PDT 24 362246466 ps
T608 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3328500567 Jul 03 06:00:34 PM PDT 24 Jul 03 06:00:36 PM PDT 24 35536674 ps
T609 /workspace/coverage/cover_reg_top/17.hmac_intr_test.3488571005 Jul 03 06:00:34 PM PDT 24 Jul 03 06:00:35 PM PDT 24 47310562 ps
T610 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2834143752 Jul 03 06:00:39 PM PDT 24 Jul 03 06:00:40 PM PDT 24 133694883 ps
T611 /workspace/coverage/cover_reg_top/35.hmac_intr_test.487888093 Jul 03 06:00:43 PM PDT 24 Jul 03 06:00:44 PM PDT 24 13707527 ps
T612 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1614187145 Jul 03 06:00:12 PM PDT 24 Jul 03 06:00:14 PM PDT 24 87183381 ps
T613 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2908829620 Jul 03 06:00:36 PM PDT 24 Jul 03 06:00:38 PM PDT 24 12624499 ps
T614 /workspace/coverage/cover_reg_top/20.hmac_intr_test.817726281 Jul 03 06:00:39 PM PDT 24 Jul 03 06:00:40 PM PDT 24 17602804 ps
T615 /workspace/coverage/cover_reg_top/42.hmac_intr_test.809162883 Jul 03 06:00:43 PM PDT 24 Jul 03 06:00:44 PM PDT 24 24452971 ps
T616 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3150436674 Jul 03 06:00:32 PM PDT 24 Jul 03 06:00:35 PM PDT 24 1052269105 ps
T617 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.966689831 Jul 03 06:00:30 PM PDT 24 Jul 03 06:00:34 PM PDT 24 318560939 ps
T148 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1256058413 Jul 03 06:00:36 PM PDT 24 Jul 03 06:00:40 PM PDT 24 244303236 ps
T618 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2781896244 Jul 03 06:00:29 PM PDT 24 Jul 03 06:00:32 PM PDT 24 56206189 ps
T619 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.4086706819 Jul 03 06:00:34 PM PDT 24 Jul 03 06:00:36 PM PDT 24 52134200 ps
T620 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1932970476 Jul 03 06:00:13 PM PDT 24 Jul 03 06:09:58 PM PDT 24 39407403164 ps
T621 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1515996199 Jul 03 06:00:32 PM PDT 24 Jul 03 06:00:33 PM PDT 24 23302974 ps
T622 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3553767666 Jul 03 06:00:31 PM PDT 24 Jul 03 06:00:33 PM PDT 24 30382361 ps
T623 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1412989241 Jul 03 06:00:16 PM PDT 24 Jul 03 06:00:19 PM PDT 24 136843604 ps
T624 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3227706568 Jul 03 06:00:34 PM PDT 24 Jul 03 06:00:36 PM PDT 24 83752874 ps
T625 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3100812109 Jul 03 06:00:31 PM PDT 24 Jul 03 06:00:32 PM PDT 24 14237281 ps
T626 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2668037862 Jul 03 06:00:13 PM PDT 24 Jul 03 06:00:17 PM PDT 24 685624284 ps
T627 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.545423177 Jul 03 06:00:12 PM PDT 24 Jul 03 06:00:13 PM PDT 24 75835289 ps
T628 /workspace/coverage/cover_reg_top/47.hmac_intr_test.4266805045 Jul 03 06:00:44 PM PDT 24 Jul 03 06:00:46 PM PDT 24 13818632 ps
T629 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1883228735 Jul 03 06:00:31 PM PDT 24 Jul 03 06:00:34 PM PDT 24 106095084 ps
T630 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3119211242 Jul 03 06:00:31 PM PDT 24 Jul 03 06:00:32 PM PDT 24 104047665 ps
T631 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3994385651 Jul 03 06:00:12 PM PDT 24 Jul 03 06:00:18 PM PDT 24 356198448 ps
T632 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3039975901 Jul 03 06:00:24 PM PDT 24 Jul 03 06:00:28 PM PDT 24 2178037906 ps
T633 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3969583371 Jul 03 06:00:43 PM PDT 24 Jul 03 06:00:44 PM PDT 24 40238787 ps
T634 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2933912535 Jul 03 06:00:08 PM PDT 24 Jul 03 06:00:10 PM PDT 24 34130351 ps
T635 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.578440376 Jul 03 06:00:38 PM PDT 24 Jul 03 06:00:41 PM PDT 24 1959115111 ps
T636 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2038740168 Jul 03 06:00:32 PM PDT 24 Jul 03 06:00:37 PM PDT 24 211462022 ps
T637 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1380055329 Jul 03 06:00:39 PM PDT 24 Jul 03 06:00:40 PM PDT 24 24154842 ps
T638 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3355153498 Jul 03 06:00:16 PM PDT 24 Jul 03 06:00:27 PM PDT 24 2920244436 ps
T639 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1955460276 Jul 03 06:00:31 PM PDT 24 Jul 03 06:00:33 PM PDT 24 86625937 ps
T640 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2755215033 Jul 03 06:00:34 PM PDT 24 Jul 03 06:00:37 PM PDT 24 339331365 ps
T641 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2523389367 Jul 03 06:00:46 PM PDT 24 Jul 03 06:00:47 PM PDT 24 16766740 ps
T642 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.663950969 Jul 03 06:00:24 PM PDT 24 Jul 03 06:00:26 PM PDT 24 243927757 ps
T643 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3462187920 Jul 03 06:00:35 PM PDT 24 Jul 03 06:00:37 PM PDT 24 49761775 ps
T644 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2789009072 Jul 03 06:00:26 PM PDT 24 Jul 03 06:00:30 PM PDT 24 58606848 ps
T645 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1925025418 Jul 03 06:00:36 PM PDT 24 Jul 03 06:00:38 PM PDT 24 11813372 ps
T646 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2227080540 Jul 03 06:00:38 PM PDT 24 Jul 03 06:00:39 PM PDT 24 39528874 ps
T647 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2129755495 Jul 03 06:00:36 PM PDT 24 Jul 03 06:00:37 PM PDT 24 126957083 ps
T648 /workspace/coverage/cover_reg_top/21.hmac_intr_test.650480763 Jul 03 06:00:35 PM PDT 24 Jul 03 06:00:37 PM PDT 24 157635010 ps
T649 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3179678591 Jul 03 06:00:32 PM PDT 24 Jul 03 06:00:34 PM PDT 24 80021773 ps
T650 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3669386480 Jul 03 06:00:17 PM PDT 24 Jul 03 06:00:19 PM PDT 24 163258445 ps
T143 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3170123412 Jul 03 06:00:17 PM PDT 24 Jul 03 06:00:21 PM PDT 24 171500671 ps
T651 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.245933871 Jul 03 06:00:33 PM PDT 24 Jul 03 06:09:57 PM PDT 24 222853038815 ps
T652 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4089820187 Jul 03 06:00:34 PM PDT 24 Jul 03 06:00:37 PM PDT 24 713473944 ps
T144 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.473829089 Jul 03 06:00:33 PM PDT 24 Jul 03 06:00:38 PM PDT 24 2161142590 ps
T149 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3077511844 Jul 03 06:00:13 PM PDT 24 Jul 03 06:00:17 PM PDT 24 365722832 ps
T653 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3097242324 Jul 03 06:00:45 PM PDT 24 Jul 03 06:00:46 PM PDT 24 24404282 ps
T654 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1921504265 Jul 03 06:00:09 PM PDT 24 Jul 03 06:00:14 PM PDT 24 430832333 ps
T655 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1054206440 Jul 03 06:00:36 PM PDT 24 Jul 03 06:00:38 PM PDT 24 68576579 ps
T656 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.928348054 Jul 03 06:00:33 PM PDT 24 Jul 03 06:00:35 PM PDT 24 22563723 ps
T657 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2682427202 Jul 03 06:00:12 PM PDT 24 Jul 03 06:00:18 PM PDT 24 1253408163 ps
T658 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.361503370 Jul 03 06:00:33 PM PDT 24 Jul 03 06:00:35 PM PDT 24 90655014 ps
T659 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3666709572 Jul 03 06:00:18 PM PDT 24 Jul 03 06:00:21 PM PDT 24 176498671 ps

Test location /workspace/coverage/default/40.hmac_stress_all.83782474
Short name T1
Test name
Test status
Simulation time 26825471683 ps
CPU time 635.66 seconds
Started Jul 03 07:21:04 PM PDT 24
Finished Jul 03 07:31:41 PM PDT 24
Peak memory 601484 kb
Host smart-b568167a-bf89-4b69-b136-7c055f0b57e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83782474 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.83782474
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1031146340
Short name T3
Test name
Test status
Simulation time 4613850912 ps
CPU time 267.08 seconds
Started Jul 03 07:19:40 PM PDT 24
Finished Jul 03 07:24:10 PM PDT 24
Peak memory 216816 kb
Host smart-c230b58a-efaf-4566-8361-2bf2e8791340
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031146340 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1031146340
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.859140767
Short name T6
Test name
Test status
Simulation time 86793235329 ps
CPU time 1708.49 seconds
Started Jul 03 07:19:46 PM PDT 24
Finished Jul 03 07:48:18 PM PDT 24
Peak memory 216612 kb
Host smart-4803542d-6354-493b-aea7-8d94ea5d3cbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=859140767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.859140767
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3076363168
Short name T22
Test name
Test status
Simulation time 13099120481 ps
CPU time 713.7 seconds
Started Jul 03 07:20:01 PM PDT 24
Finished Jul 03 07:31:58 PM PDT 24
Peak memory 200436 kb
Host smart-2ee26a4d-4b0e-42f3-a611-c3f1a33f64a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076363168 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3076363168
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1569774528
Short name T140
Test name
Test status
Simulation time 100599074 ps
CPU time 2.89 seconds
Started Jul 03 06:00:31 PM PDT 24
Finished Jul 03 06:00:34 PM PDT 24
Peak memory 199512 kb
Host smart-e02fac58-4005-414a-8707-46ef791c2aa2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569774528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1569774528
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.1721605765
Short name T23
Test name
Test status
Simulation time 117899303260 ps
CPU time 3404.94 seconds
Started Jul 03 07:19:39 PM PDT 24
Finished Jul 03 08:16:28 PM PDT 24
Peak memory 783624 kb
Host smart-74f85e69-79d0-4812-b613-5be182797c1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1721605765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.1721605765
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.374472951
Short name T67
Test name
Test status
Simulation time 88900398 ps
CPU time 1.01 seconds
Started Jul 03 07:19:35 PM PDT 24
Finished Jul 03 07:19:39 PM PDT 24
Peak memory 219528 kb
Host smart-c16de751-4da0-4208-86f3-d0b9e44db6e1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374472951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.374472951
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/18.hmac_stress_all.824485160
Short name T28
Test name
Test status
Simulation time 6592762512 ps
CPU time 377.32 seconds
Started Jul 03 07:20:04 PM PDT 24
Finished Jul 03 07:26:25 PM PDT 24
Peak memory 200340 kb
Host smart-82683018-9c04-4ca9-8e8b-2593380d786d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824485160 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.824485160
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2527663145
Short name T114
Test name
Test status
Simulation time 35393553 ps
CPU time 0.87 seconds
Started Jul 03 06:00:14 PM PDT 24
Finished Jul 03 06:00:15 PM PDT 24
Peak memory 199060 kb
Host smart-6962cbe1-b1b5-4129-a21e-0c9566bec25e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527663145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2527663145
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/default/35.hmac_stress_all.2430252634
Short name T27
Test name
Test status
Simulation time 717976001787 ps
CPU time 3433.87 seconds
Started Jul 03 07:20:48 PM PDT 24
Finished Jul 03 08:18:05 PM PDT 24
Peak memory 765544 kb
Host smart-0edfb428-b194-4e09-bb5f-19bf591c36bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430252634 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2430252634
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_stress_all.782949712
Short name T108
Test name
Test status
Simulation time 9645753574 ps
CPU time 526.93 seconds
Started Jul 03 07:21:11 PM PDT 24
Finished Jul 03 07:29:59 PM PDT 24
Peak memory 200420 kb
Host smart-9fb71612-4fb7-47da-84e8-c151f85ec5c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782949712 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.782949712
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3077511844
Short name T149
Test name
Test status
Simulation time 365722832 ps
CPU time 3.11 seconds
Started Jul 03 06:00:13 PM PDT 24
Finished Jul 03 06:00:17 PM PDT 24
Peak memory 199544 kb
Host smart-d3942507-5c1e-4cd1-965a-714abf581665
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077511844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3077511844
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3859486676
Short name T203
Test name
Test status
Simulation time 11271968 ps
CPU time 0.6 seconds
Started Jul 03 07:19:53 PM PDT 24
Finished Jul 03 07:19:56 PM PDT 24
Peak memory 196224 kb
Host smart-11ce3609-829e-49e9-97d7-d0a9e4ad32ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859486676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3859486676
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.327210713
Short name T57
Test name
Test status
Simulation time 2956668394 ps
CPU time 39.81 seconds
Started Jul 03 07:20:56 PM PDT 24
Finished Jul 03 07:21:37 PM PDT 24
Peak memory 200432 kb
Host smart-d013c1a2-3c01-4c38-8065-a86acffcb9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327210713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.327210713
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.473829089
Short name T144
Test name
Test status
Simulation time 2161142590 ps
CPU time 4.5 seconds
Started Jul 03 06:00:33 PM PDT 24
Finished Jul 03 06:00:38 PM PDT 24
Peak memory 199572 kb
Host smart-3abe32e5-fe65-4b1c-8159-d427a05e8abe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473829089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.473829089
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.420968934
Short name T130
Test name
Test status
Simulation time 121190674 ps
CPU time 2.39 seconds
Started Jul 03 06:00:31 PM PDT 24
Finished Jul 03 06:00:34 PM PDT 24
Peak memory 199564 kb
Host smart-5b7dc62d-fd54-4cd3-bc6a-d4a042f5e766
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420968934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.420968934
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2168082039
Short name T400
Test name
Test status
Simulation time 2581973635 ps
CPU time 36.61 seconds
Started Jul 03 07:19:54 PM PDT 24
Finished Jul 03 07:20:34 PM PDT 24
Peak memory 200484 kb
Host smart-24f4f159-8bc0-49b6-a842-f7e800c02f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168082039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2168082039
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.2378077424
Short name T12
Test name
Test status
Simulation time 280454222734 ps
CPU time 1207.19 seconds
Started Jul 03 07:19:39 PM PDT 24
Finished Jul 03 07:39:49 PM PDT 24
Peak memory 465728 kb
Host smart-51ce0ec7-b7d5-4b9d-9766-0d3e8762e1e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2378077424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.2378077424
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3994385651
Short name T631
Test name
Test status
Simulation time 356198448 ps
CPU time 5.7 seconds
Started Jul 03 06:00:12 PM PDT 24
Finished Jul 03 06:00:18 PM PDT 24
Peak memory 199540 kb
Host smart-46e21bda-fb88-464f-b2e3-15ea23699880
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994385651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3994385651
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1921504265
Short name T654
Test name
Test status
Simulation time 430832333 ps
CPU time 4.94 seconds
Started Jul 03 06:00:09 PM PDT 24
Finished Jul 03 06:00:14 PM PDT 24
Peak memory 199516 kb
Host smart-c83d5d34-b3bb-4096-82b2-26de95720e5b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921504265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1921504265
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2750986504
Short name T586
Test name
Test status
Simulation time 66290110 ps
CPU time 1.79 seconds
Started Jul 03 06:00:09 PM PDT 24
Finished Jul 03 06:00:12 PM PDT 24
Peak memory 199752 kb
Host smart-38a350d6-53e9-4209-8cb6-b9d8ea7929dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750986504 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2750986504
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1614187145
Short name T612
Test name
Test status
Simulation time 87183381 ps
CPU time 0.79 seconds
Started Jul 03 06:00:12 PM PDT 24
Finished Jul 03 06:00:14 PM PDT 24
Peak memory 199060 kb
Host smart-838b4df1-a256-4254-8d9f-65caced701d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614187145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1614187145
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1655185619
Short name T570
Test name
Test status
Simulation time 39326084 ps
CPU time 0.59 seconds
Started Jul 03 06:00:10 PM PDT 24
Finished Jul 03 06:00:11 PM PDT 24
Peak memory 194600 kb
Host smart-4e0e9ca4-1190-4e6c-83f7-c319dce27b8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655185619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1655185619
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3294247183
Short name T596
Test name
Test status
Simulation time 254619774 ps
CPU time 1.69 seconds
Started Jul 03 06:00:12 PM PDT 24
Finished Jul 03 06:00:14 PM PDT 24
Peak memory 199548 kb
Host smart-e919f506-fbb4-441b-8e7e-82403e01c34f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294247183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3294247183
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2668037862
Short name T626
Test name
Test status
Simulation time 685624284 ps
CPU time 3.39 seconds
Started Jul 03 06:00:13 PM PDT 24
Finished Jul 03 06:00:17 PM PDT 24
Peak memory 199560 kb
Host smart-e3a6d6fc-c633-4615-a745-85787736b2c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668037862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2668037862
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1157142870
Short name T81
Test name
Test status
Simulation time 1404539675 ps
CPU time 4.52 seconds
Started Jul 03 06:00:13 PM PDT 24
Finished Jul 03 06:00:18 PM PDT 24
Peak memory 199528 kb
Host smart-e58d8f8e-2bb6-4599-ba5c-050104ac1ed3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157142870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1157142870
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2682427202
Short name T657
Test name
Test status
Simulation time 1253408163 ps
CPU time 6.15 seconds
Started Jul 03 06:00:12 PM PDT 24
Finished Jul 03 06:00:18 PM PDT 24
Peak memory 199532 kb
Host smart-0b11dfbc-a326-453d-b208-a736b3cb308d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682427202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.2682427202
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.748037369
Short name T120
Test name
Test status
Simulation time 1471709579 ps
CPU time 5.69 seconds
Started Jul 03 06:00:10 PM PDT 24
Finished Jul 03 06:00:17 PM PDT 24
Peak memory 199576 kb
Host smart-b104ba87-2c01-4845-bfdb-0a35e3ca39a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748037369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.748037369
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2933912535
Short name T634
Test name
Test status
Simulation time 34130351 ps
CPU time 0.76 seconds
Started Jul 03 06:00:08 PM PDT 24
Finished Jul 03 06:00:10 PM PDT 24
Peak memory 197912 kb
Host smart-e22338eb-1e03-462f-8799-a8546ebc77be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933912535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2933912535
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1932970476
Short name T620
Test name
Test status
Simulation time 39407403164 ps
CPU time 584.16 seconds
Started Jul 03 06:00:13 PM PDT 24
Finished Jul 03 06:09:58 PM PDT 24
Peak memory 215416 kb
Host smart-305f77e8-daff-4553-8ea4-5c7d65aff88c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932970476 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1932970476
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1798879471
Short name T578
Test name
Test status
Simulation time 26548453 ps
CPU time 0.69 seconds
Started Jul 03 06:00:09 PM PDT 24
Finished Jul 03 06:00:11 PM PDT 24
Peak memory 197536 kb
Host smart-b15e0e1f-c22c-40f5-bc2e-a84213581fe1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798879471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1798879471
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1914469927
Short name T544
Test name
Test status
Simulation time 13455135 ps
CPU time 0.62 seconds
Started Jul 03 06:00:12 PM PDT 24
Finished Jul 03 06:00:13 PM PDT 24
Peak memory 194528 kb
Host smart-8825e3da-614a-4518-8112-13eb75106191
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914469927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1914469927
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.545423177
Short name T627
Test name
Test status
Simulation time 75835289 ps
CPU time 1.13 seconds
Started Jul 03 06:00:12 PM PDT 24
Finished Jul 03 06:00:13 PM PDT 24
Peak memory 199372 kb
Host smart-276f0915-5201-4068-a601-ca03bc28e3f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545423177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.545423177
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2919538528
Short name T583
Test name
Test status
Simulation time 303021573 ps
CPU time 1.9 seconds
Started Jul 03 06:00:09 PM PDT 24
Finished Jul 03 06:00:12 PM PDT 24
Peak memory 199576 kb
Host smart-b9ca4b39-03f4-48f0-8250-9655d4cb78e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919538528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2919538528
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2177431105
Short name T141
Test name
Test status
Simulation time 170769812 ps
CPU time 3.14 seconds
Started Jul 03 06:00:09 PM PDT 24
Finished Jul 03 06:00:13 PM PDT 24
Peak memory 199524 kb
Host smart-15da44b8-deb4-4b24-a784-18e29506b2fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177431105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2177431105
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1054206440
Short name T655
Test name
Test status
Simulation time 68576579 ps
CPU time 1.92 seconds
Started Jul 03 06:00:36 PM PDT 24
Finished Jul 03 06:00:38 PM PDT 24
Peak memory 207884 kb
Host smart-96e0f8c2-d92b-44cc-a45c-0ccf3bde8d27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054206440 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1054206440
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.4086706819
Short name T619
Test name
Test status
Simulation time 52134200 ps
CPU time 0.91 seconds
Started Jul 03 06:00:34 PM PDT 24
Finished Jul 03 06:00:36 PM PDT 24
Peak memory 199436 kb
Host smart-5cebc662-87dc-44fd-86de-ad2e01e598db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086706819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.4086706819
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.81082126
Short name T537
Test name
Test status
Simulation time 51788820 ps
CPU time 0.62 seconds
Started Jul 03 06:00:31 PM PDT 24
Finished Jul 03 06:00:32 PM PDT 24
Peak memory 194572 kb
Host smart-708b5645-f315-41d9-a4ee-d6612940d9a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81082126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.81082126
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.928348054
Short name T656
Test name
Test status
Simulation time 22563723 ps
CPU time 1.1 seconds
Started Jul 03 06:00:33 PM PDT 24
Finished Jul 03 06:00:35 PM PDT 24
Peak memory 198096 kb
Host smart-8c300db1-b4a4-490e-bfb6-c59659f6bcef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928348054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.928348054
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.4154839402
Short name T600
Test name
Test status
Simulation time 84942913 ps
CPU time 1.88 seconds
Started Jul 03 06:00:30 PM PDT 24
Finished Jul 03 06:00:32 PM PDT 24
Peak memory 199564 kb
Host smart-310c2949-1666-413e-9114-0e3dab6f729c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154839402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.4154839402
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.365748702
Short name T601
Test name
Test status
Simulation time 88139302 ps
CPU time 1.85 seconds
Started Jul 03 06:00:40 PM PDT 24
Finished Jul 03 06:00:42 PM PDT 24
Peak memory 199504 kb
Host smart-f18877ff-fc9f-421f-8c69-e4e53d5d93b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365748702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.365748702
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3553767666
Short name T622
Test name
Test status
Simulation time 30382361 ps
CPU time 1.78 seconds
Started Jul 03 06:00:31 PM PDT 24
Finished Jul 03 06:00:33 PM PDT 24
Peak memory 199600 kb
Host smart-ff4d6732-0c1c-4846-8e31-edb7ca2c5e28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553767666 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3553767666
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.536901907
Short name T604
Test name
Test status
Simulation time 20548574 ps
CPU time 0.72 seconds
Started Jul 03 06:00:32 PM PDT 24
Finished Jul 03 06:00:33 PM PDT 24
Peak memory 197584 kb
Host smart-9509023f-e8d5-4843-b10d-12a2d06b3d4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536901907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.536901907
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2872233104
Short name T535
Test name
Test status
Simulation time 33333025 ps
CPU time 0.56 seconds
Started Jul 03 06:00:39 PM PDT 24
Finished Jul 03 06:00:40 PM PDT 24
Peak memory 194588 kb
Host smart-29a8fa61-478f-4a67-a4f3-080092127d89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872233104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2872233104
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2692892550
Short name T591
Test name
Test status
Simulation time 659429931 ps
CPU time 3.36 seconds
Started Jul 03 06:00:31 PM PDT 24
Finished Jul 03 06:00:35 PM PDT 24
Peak memory 199544 kb
Host smart-d506def8-e620-451d-ac31-371120be40e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692892550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2692892550
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3227706568
Short name T624
Test name
Test status
Simulation time 83752874 ps
CPU time 1.77 seconds
Started Jul 03 06:00:34 PM PDT 24
Finished Jul 03 06:00:36 PM PDT 24
Peak memory 199420 kb
Host smart-615d6594-332f-40de-9862-d97314a489bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227706568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3227706568
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.245933871
Short name T651
Test name
Test status
Simulation time 222853038815 ps
CPU time 562.97 seconds
Started Jul 03 06:00:33 PM PDT 24
Finished Jul 03 06:09:57 PM PDT 24
Peak memory 216012 kb
Host smart-16f943b7-c904-41d7-ba8e-e2a56d0c6fc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245933871 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.245933871
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.632596250
Short name T119
Test name
Test status
Simulation time 20580042 ps
CPU time 0.79 seconds
Started Jul 03 06:00:40 PM PDT 24
Finished Jul 03 06:00:41 PM PDT 24
Peak memory 199252 kb
Host smart-ee8461b9-d545-4917-b2a0-55d43b33bb63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632596250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.632596250
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3100812109
Short name T625
Test name
Test status
Simulation time 14237281 ps
CPU time 0.58 seconds
Started Jul 03 06:00:31 PM PDT 24
Finished Jul 03 06:00:32 PM PDT 24
Peak memory 194424 kb
Host smart-3596de22-c9dd-4c1f-8a30-9185309d517d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100812109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3100812109
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.361503370
Short name T658
Test name
Test status
Simulation time 90655014 ps
CPU time 1.16 seconds
Started Jul 03 06:00:33 PM PDT 24
Finished Jul 03 06:00:35 PM PDT 24
Peak memory 198096 kb
Host smart-62b9069f-d932-4222-945d-cc29be20246b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361503370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.361503370
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2781896244
Short name T618
Test name
Test status
Simulation time 56206189 ps
CPU time 2.71 seconds
Started Jul 03 06:00:29 PM PDT 24
Finished Jul 03 06:00:32 PM PDT 24
Peak memory 199584 kb
Host smart-6ace777a-4604-423e-be9a-dce34d73b5b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781896244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2781896244
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.1256058413
Short name T148
Test name
Test status
Simulation time 244303236 ps
CPU time 3.77 seconds
Started Jul 03 06:00:36 PM PDT 24
Finished Jul 03 06:00:40 PM PDT 24
Peak memory 199548 kb
Host smart-343431e4-2cec-4cf4-932b-7301b55617fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256058413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.1256058413
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.700871779
Short name T559
Test name
Test status
Simulation time 130868985 ps
CPU time 2.21 seconds
Started Jul 03 06:00:36 PM PDT 24
Finished Jul 03 06:00:39 PM PDT 24
Peak memory 199680 kb
Host smart-612a9e4e-9329-4675-81c4-d0285b06e932
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700871779 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.700871779
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.432139347
Short name T573
Test name
Test status
Simulation time 214044095 ps
CPU time 0.98 seconds
Started Jul 03 06:00:30 PM PDT 24
Finished Jul 03 06:00:31 PM PDT 24
Peak memory 198748 kb
Host smart-afd0ab21-f941-4707-a4dc-d1cf2d57e52f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432139347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.432139347
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.58593348
Short name T597
Test name
Test status
Simulation time 54616676 ps
CPU time 0.61 seconds
Started Jul 03 06:00:33 PM PDT 24
Finished Jul 03 06:00:35 PM PDT 24
Peak memory 194568 kb
Host smart-65f9a88a-3917-4453-b080-1600df88a939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58593348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.58593348
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.4176378834
Short name T125
Test name
Test status
Simulation time 552555380 ps
CPU time 2.52 seconds
Started Jul 03 06:00:33 PM PDT 24
Finished Jul 03 06:00:36 PM PDT 24
Peak memory 199560 kb
Host smart-c2a87bc5-d8a5-4c17-80f1-073719334ccf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176378834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.4176378834
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2842509549
Short name T590
Test name
Test status
Simulation time 24896063 ps
CPU time 1.2 seconds
Started Jul 03 06:00:29 PM PDT 24
Finished Jul 03 06:00:31 PM PDT 24
Peak memory 199552 kb
Host smart-8ff66089-a482-4e91-a0d5-faf7e9ab28da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842509549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2842509549
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1883228735
Short name T629
Test name
Test status
Simulation time 106095084 ps
CPU time 2.02 seconds
Started Jul 03 06:00:31 PM PDT 24
Finished Jul 03 06:00:34 PM PDT 24
Peak memory 199536 kb
Host smart-3f74413c-25cc-4dd8-a4d5-d5da6848d742
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883228735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1883228735
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.222782795
Short name T569
Test name
Test status
Simulation time 122328919 ps
CPU time 1.81 seconds
Started Jul 03 06:00:35 PM PDT 24
Finished Jul 03 06:00:38 PM PDT 24
Peak memory 199672 kb
Host smart-6e346e03-95b2-47e0-9928-6cfa22ee5c23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222782795 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.222782795
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3182286803
Short name T574
Test name
Test status
Simulation time 54039738 ps
CPU time 0.94 seconds
Started Jul 03 06:00:33 PM PDT 24
Finished Jul 03 06:00:34 PM PDT 24
Peak memory 199404 kb
Host smart-e5994edc-6db0-4768-8e5f-316906028401
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182286803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3182286803
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3441053241
Short name T584
Test name
Test status
Simulation time 29960883 ps
CPU time 0.68 seconds
Started Jul 03 06:00:32 PM PDT 24
Finished Jul 03 06:00:33 PM PDT 24
Peak memory 194676 kb
Host smart-3919b4f4-f2be-4229-8251-279d7e7aa395
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441053241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3441053241
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1075935159
Short name T132
Test name
Test status
Simulation time 161473674 ps
CPU time 2.18 seconds
Started Jul 03 06:00:33 PM PDT 24
Finished Jul 03 06:00:36 PM PDT 24
Peak memory 199500 kb
Host smart-c256bcbe-7437-4291-a592-cbf1177733e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075935159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1075935159
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1263104636
Short name T553
Test name
Test status
Simulation time 159650552 ps
CPU time 3.44 seconds
Started Jul 03 06:00:31 PM PDT 24
Finished Jul 03 06:00:36 PM PDT 24
Peak memory 199528 kb
Host smart-f8173abe-b0b7-4da5-9778-3fa1cd909b1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263104636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1263104636
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1797709286
Short name T79
Test name
Test status
Simulation time 599751466 ps
CPU time 1.83 seconds
Started Jul 03 06:00:30 PM PDT 24
Finished Jul 03 06:00:33 PM PDT 24
Peak memory 199480 kb
Host smart-6b5d1b9d-0b45-4635-ba3b-616d87a1bf38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797709286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1797709286
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.826005506
Short name T588
Test name
Test status
Simulation time 1654288886 ps
CPU time 2.61 seconds
Started Jul 03 06:00:32 PM PDT 24
Finished Jul 03 06:00:36 PM PDT 24
Peak memory 199728 kb
Host smart-626d5350-aa42-4f00-9420-4d6cdfea282d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826005506 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.826005506
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2053560081
Short name T115
Test name
Test status
Simulation time 17512558 ps
CPU time 0.69 seconds
Started Jul 03 06:00:33 PM PDT 24
Finished Jul 03 06:00:34 PM PDT 24
Peak memory 198068 kb
Host smart-30e62d59-ea48-4d9e-ab9e-a32631807096
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053560081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2053560081
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1515996199
Short name T621
Test name
Test status
Simulation time 23302974 ps
CPU time 0.6 seconds
Started Jul 03 06:00:32 PM PDT 24
Finished Jul 03 06:00:33 PM PDT 24
Peak memory 194468 kb
Host smart-99900a6b-adcf-48df-97c9-02b11e10d5db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515996199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1515996199
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1474538110
Short name T589
Test name
Test status
Simulation time 87295674 ps
CPU time 1.68 seconds
Started Jul 03 06:00:36 PM PDT 24
Finished Jul 03 06:00:38 PM PDT 24
Peak memory 199544 kb
Host smart-b21cf43e-b9fe-4c5f-8bcd-c059712c8292
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474538110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1474538110
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3150436674
Short name T616
Test name
Test status
Simulation time 1052269105 ps
CPU time 2.64 seconds
Started Jul 03 06:00:32 PM PDT 24
Finished Jul 03 06:00:35 PM PDT 24
Peak memory 199520 kb
Host smart-90bc13e2-7951-409d-b3f1-6ee62024fba6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150436674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3150436674
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2350963191
Short name T142
Test name
Test status
Simulation time 328754073 ps
CPU time 4.46 seconds
Started Jul 03 06:00:37 PM PDT 24
Finished Jul 03 06:00:42 PM PDT 24
Peak memory 199536 kb
Host smart-2dc81bf0-f820-49cf-9133-753370dd095e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350963191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2350963191
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3328500567
Short name T608
Test name
Test status
Simulation time 35536674 ps
CPU time 1.32 seconds
Started Jul 03 06:00:34 PM PDT 24
Finished Jul 03 06:00:36 PM PDT 24
Peak memory 199528 kb
Host smart-a75dab60-7530-4c05-b6f4-d1315b7748b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328500567 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3328500567
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3799888694
Short name T580
Test name
Test status
Simulation time 58947315 ps
CPU time 0.81 seconds
Started Jul 03 06:00:34 PM PDT 24
Finished Jul 03 06:00:35 PM PDT 24
Peak memory 198524 kb
Host smart-73568fba-b5a4-42a9-a280-3e21e1487f14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799888694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3799888694
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3300281682
Short name T554
Test name
Test status
Simulation time 145041968 ps
CPU time 0.59 seconds
Started Jul 03 06:00:32 PM PDT 24
Finished Jul 03 06:00:33 PM PDT 24
Peak memory 194548 kb
Host smart-41c03ab2-8161-4367-9570-fea41773c9ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300281682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3300281682
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2509968020
Short name T127
Test name
Test status
Simulation time 108738906 ps
CPU time 1.13 seconds
Started Jul 03 06:00:31 PM PDT 24
Finished Jul 03 06:00:33 PM PDT 24
Peak memory 198096 kb
Host smart-2a67da1c-9d92-41d4-93db-d8e14f433f97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509968020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.2509968020
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3462187920
Short name T643
Test name
Test status
Simulation time 49761775 ps
CPU time 1.19 seconds
Started Jul 03 06:00:35 PM PDT 24
Finished Jul 03 06:00:37 PM PDT 24
Peak memory 199544 kb
Host smart-4516a77c-e795-43e8-bf5f-4e90cf6cb4bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462187920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3462187920
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.415981277
Short name T575
Test name
Test status
Simulation time 39890122 ps
CPU time 2.55 seconds
Started Jul 03 06:00:35 PM PDT 24
Finished Jul 03 06:00:38 PM PDT 24
Peak memory 207772 kb
Host smart-9573fe9e-bcea-45f7-b089-8f192944957e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415981277 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.415981277
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3916490284
Short name T594
Test name
Test status
Simulation time 92827793 ps
CPU time 0.69 seconds
Started Jul 03 06:00:33 PM PDT 24
Finished Jul 03 06:00:35 PM PDT 24
Peak memory 197516 kb
Host smart-c23044eb-16df-4d2d-8bf0-c2b894027d49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916490284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3916490284
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3488571005
Short name T609
Test name
Test status
Simulation time 47310562 ps
CPU time 0.61 seconds
Started Jul 03 06:00:34 PM PDT 24
Finished Jul 03 06:00:35 PM PDT 24
Peak memory 194568 kb
Host smart-a0d3ba1e-618a-4b3a-8d94-47e28321183e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488571005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3488571005
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2383334386
Short name T595
Test name
Test status
Simulation time 412583871 ps
CPU time 1.78 seconds
Started Jul 03 06:00:35 PM PDT 24
Finished Jul 03 06:00:37 PM PDT 24
Peak memory 199492 kb
Host smart-d9477d73-a775-4645-9974-1ca80062bf49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383334386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2383334386
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.966689831
Short name T617
Test name
Test status
Simulation time 318560939 ps
CPU time 3.09 seconds
Started Jul 03 06:00:30 PM PDT 24
Finished Jul 03 06:00:34 PM PDT 24
Peak memory 199600 kb
Host smart-e6023d2d-bb8f-461b-afa6-8f0206d87768
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966689831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.966689831
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.652728116
Short name T561
Test name
Test status
Simulation time 145365160 ps
CPU time 1.26 seconds
Started Jul 03 06:00:37 PM PDT 24
Finished Jul 03 06:00:38 PM PDT 24
Peak memory 199448 kb
Host smart-e896f9cb-152a-42c8-b380-a84e10eb3efa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652728116 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.652728116
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2930530474
Short name T118
Test name
Test status
Simulation time 13476951 ps
CPU time 0.69 seconds
Started Jul 03 06:00:36 PM PDT 24
Finished Jul 03 06:00:37 PM PDT 24
Peak memory 197692 kb
Host smart-80ed4e55-09e2-40a7-bde2-def52e58c7c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930530474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2930530474
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2129755495
Short name T647
Test name
Test status
Simulation time 126957083 ps
CPU time 0.61 seconds
Started Jul 03 06:00:36 PM PDT 24
Finished Jul 03 06:00:37 PM PDT 24
Peak memory 194568 kb
Host smart-afedd9bf-c46e-46ea-8b45-a3ae67649d88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129755495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2129755495
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.199333413
Short name T126
Test name
Test status
Simulation time 215957309 ps
CPU time 1.14 seconds
Started Jul 03 06:00:38 PM PDT 24
Finished Jul 03 06:00:39 PM PDT 24
Peak memory 198048 kb
Host smart-64d792d7-431d-48dc-9f78-281c08040adf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199333413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.199333413
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3712630690
Short name T539
Test name
Test status
Simulation time 98654535 ps
CPU time 2.34 seconds
Started Jul 03 06:00:34 PM PDT 24
Finished Jul 03 06:00:37 PM PDT 24
Peak memory 199532 kb
Host smart-06807595-328b-431a-b49b-8109e6ce40fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712630690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3712630690
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3962987820
Short name T146
Test name
Test status
Simulation time 181118914 ps
CPU time 3.05 seconds
Started Jul 03 06:00:34 PM PDT 24
Finished Jul 03 06:00:38 PM PDT 24
Peak memory 199528 kb
Host smart-768e2bdf-ac59-48c6-86d7-4d230e5de955
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962987820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3962987820
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.578440376
Short name T635
Test name
Test status
Simulation time 1959115111 ps
CPU time 2.39 seconds
Started Jul 03 06:00:38 PM PDT 24
Finished Jul 03 06:00:41 PM PDT 24
Peak memory 199644 kb
Host smart-a1d17706-2dab-477b-8b2a-bb5871db44d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578440376 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.578440376
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1837435181
Short name T549
Test name
Test status
Simulation time 22841944 ps
CPU time 0.83 seconds
Started Jul 03 06:00:35 PM PDT 24
Finished Jul 03 06:00:36 PM PDT 24
Peak memory 198808 kb
Host smart-0207a44c-6283-4edc-92e1-16d4722ee1d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837435181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1837435181
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2289673297
Short name T548
Test name
Test status
Simulation time 47756164 ps
CPU time 0.61 seconds
Started Jul 03 06:00:35 PM PDT 24
Finished Jul 03 06:00:36 PM PDT 24
Peak memory 194544 kb
Host smart-8dad090e-08a7-4224-8daf-0ba77733dd4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289673297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2289673297
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.2913187838
Short name T599
Test name
Test status
Simulation time 144677945 ps
CPU time 2.02 seconds
Started Jul 03 06:00:36 PM PDT 24
Finished Jul 03 06:00:39 PM PDT 24
Peak memory 199528 kb
Host smart-2b3e7b2b-bdba-4db5-a5b9-969060db014c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913187838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.2913187838
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2755215033
Short name T640
Test name
Test status
Simulation time 339331365 ps
CPU time 1.51 seconds
Started Jul 03 06:00:34 PM PDT 24
Finished Jul 03 06:00:37 PM PDT 24
Peak memory 199624 kb
Host smart-92684c66-7e20-4346-80ad-3d4515f9f8a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755215033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2755215033
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.268196834
Short name T145
Test name
Test status
Simulation time 360472911 ps
CPU time 3.19 seconds
Started Jul 03 06:00:35 PM PDT 24
Finished Jul 03 06:00:39 PM PDT 24
Peak memory 199520 kb
Host smart-b977498d-8e48-4e3e-bd6c-2a5a7d350677
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268196834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.268196834
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.869631390
Short name T121
Test name
Test status
Simulation time 321849330 ps
CPU time 3.27 seconds
Started Jul 03 06:00:15 PM PDT 24
Finished Jul 03 06:00:18 PM PDT 24
Peak memory 199528 kb
Host smart-839e324b-ca32-4d4e-a682-e2c4b6803ebf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869631390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.869631390
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.627938148
Short name T536
Test name
Test status
Simulation time 2925480768 ps
CPU time 9.86 seconds
Started Jul 03 06:00:13 PM PDT 24
Finished Jul 03 06:00:23 PM PDT 24
Peak memory 199688 kb
Host smart-22fde1d8-5785-4e29-a9c0-7f038a378246
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627938148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.627938148
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1818425035
Short name T110
Test name
Test status
Simulation time 43685324 ps
CPU time 0.75 seconds
Started Jul 03 06:00:12 PM PDT 24
Finished Jul 03 06:00:13 PM PDT 24
Peak memory 197972 kb
Host smart-3216924c-27c0-4574-83c7-c52a00b8b817
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818425035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1818425035
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.4019196410
Short name T541
Test name
Test status
Simulation time 35416421 ps
CPU time 1.08 seconds
Started Jul 03 06:00:14 PM PDT 24
Finished Jul 03 06:00:15 PM PDT 24
Peak memory 199444 kb
Host smart-ffa1ee4a-137a-48bf-a23f-db5ec3d06eee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019196410 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.4019196410
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1291432676
Short name T123
Test name
Test status
Simulation time 26931367 ps
CPU time 0.81 seconds
Started Jul 03 06:00:18 PM PDT 24
Finished Jul 03 06:00:19 PM PDT 24
Peak memory 199264 kb
Host smart-16690bca-2d53-4f34-b886-8d37908e7631
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291432676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1291432676
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2387313047
Short name T555
Test name
Test status
Simulation time 23255130 ps
CPU time 0.58 seconds
Started Jul 03 06:00:15 PM PDT 24
Finished Jul 03 06:00:16 PM PDT 24
Peak memory 194600 kb
Host smart-959a1cec-1197-4e13-9e10-3443c558a7ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387313047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2387313047
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3023077934
Short name T592
Test name
Test status
Simulation time 221839303 ps
CPU time 2.33 seconds
Started Jul 03 06:00:13 PM PDT 24
Finished Jul 03 06:00:16 PM PDT 24
Peak memory 199496 kb
Host smart-1aafc950-7b5b-4936-9282-2a9d16085568
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023077934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3023077934
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2096289440
Short name T572
Test name
Test status
Simulation time 105860279 ps
CPU time 1.94 seconds
Started Jul 03 06:00:13 PM PDT 24
Finished Jul 03 06:00:16 PM PDT 24
Peak memory 199548 kb
Host smart-ad523a0b-267d-4855-aee5-96f3458a9d22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096289440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2096289440
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.817726281
Short name T614
Test name
Test status
Simulation time 17602804 ps
CPU time 0.56 seconds
Started Jul 03 06:00:39 PM PDT 24
Finished Jul 03 06:00:40 PM PDT 24
Peak memory 194448 kb
Host smart-b440b35e-005f-4de6-a56d-75d691a66208
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817726281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.817726281
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.650480763
Short name T648
Test name
Test status
Simulation time 157635010 ps
CPU time 0.58 seconds
Started Jul 03 06:00:35 PM PDT 24
Finished Jul 03 06:00:37 PM PDT 24
Peak memory 194500 kb
Host smart-091bca5c-4c37-4c36-a797-721b6b1d07f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650480763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.650480763
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3899678584
Short name T603
Test name
Test status
Simulation time 50214400 ps
CPU time 0.63 seconds
Started Jul 03 06:00:37 PM PDT 24
Finished Jul 03 06:00:38 PM PDT 24
Peak memory 194600 kb
Host smart-c4b17647-2207-4c05-b2a7-73c4109a1021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899678584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3899678584
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1925025418
Short name T645
Test name
Test status
Simulation time 11813372 ps
CPU time 0.61 seconds
Started Jul 03 06:00:36 PM PDT 24
Finished Jul 03 06:00:38 PM PDT 24
Peak memory 194576 kb
Host smart-4f59921f-097a-4667-bd84-1f0e2ed60dcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925025418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1925025418
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1380055329
Short name T637
Test name
Test status
Simulation time 24154842 ps
CPU time 0.62 seconds
Started Jul 03 06:00:39 PM PDT 24
Finished Jul 03 06:00:40 PM PDT 24
Peak memory 194564 kb
Host smart-b5e8e983-675a-480d-a81e-49ef5e6d9052
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380055329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1380055329
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2456455571
Short name T540
Test name
Test status
Simulation time 44904616 ps
CPU time 0.6 seconds
Started Jul 03 06:00:39 PM PDT 24
Finished Jul 03 06:00:39 PM PDT 24
Peak memory 194520 kb
Host smart-0ab0d1f6-fba7-46c9-b12e-7e1ebe84779f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456455571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2456455571
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2227080540
Short name T646
Test name
Test status
Simulation time 39528874 ps
CPU time 0.59 seconds
Started Jul 03 06:00:38 PM PDT 24
Finished Jul 03 06:00:39 PM PDT 24
Peak memory 194504 kb
Host smart-3ad9ebf9-084e-4c96-ac63-c3c1471f16df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227080540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2227080540
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2834143752
Short name T610
Test name
Test status
Simulation time 133694883 ps
CPU time 0.6 seconds
Started Jul 03 06:00:39 PM PDT 24
Finished Jul 03 06:00:40 PM PDT 24
Peak memory 194632 kb
Host smart-d9de93c3-58f1-424c-ab89-d9abd6c51526
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834143752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2834143752
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1618420078
Short name T602
Test name
Test status
Simulation time 10921131 ps
CPU time 0.57 seconds
Started Jul 03 06:00:37 PM PDT 24
Finished Jul 03 06:00:38 PM PDT 24
Peak memory 194480 kb
Host smart-ec6b255a-fd1e-4818-8bef-e15e4f97f93d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618420078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1618420078
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.448863367
Short name T581
Test name
Test status
Simulation time 19476177 ps
CPU time 0.58 seconds
Started Jul 03 06:00:37 PM PDT 24
Finished Jul 03 06:00:38 PM PDT 24
Peak memory 194544 kb
Host smart-2cc99b06-1769-454f-9131-8d562af6c40e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448863367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.448863367
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1446362212
Short name T545
Test name
Test status
Simulation time 4265123760 ps
CPU time 6.15 seconds
Started Jul 03 06:00:16 PM PDT 24
Finished Jul 03 06:00:23 PM PDT 24
Peak memory 199592 kb
Host smart-eb32ec6a-af58-4037-ac3a-e4fb5d356289
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446362212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1446362212
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3355153498
Short name T638
Test name
Test status
Simulation time 2920244436 ps
CPU time 10.34 seconds
Started Jul 03 06:00:16 PM PDT 24
Finished Jul 03 06:00:27 PM PDT 24
Peak memory 199692 kb
Host smart-db9bd055-d2ff-4473-9c04-6a9feaa981bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355153498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3355153498
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.249720822
Short name T113
Test name
Test status
Simulation time 22743213 ps
CPU time 0.94 seconds
Started Jul 03 06:00:19 PM PDT 24
Finished Jul 03 06:00:21 PM PDT 24
Peak memory 199364 kb
Host smart-bb7b0565-839a-4da4-8cfb-2cc1e2da5743
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249720822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.249720822
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.663950969
Short name T642
Test name
Test status
Simulation time 243927757 ps
CPU time 1.78 seconds
Started Jul 03 06:00:24 PM PDT 24
Finished Jul 03 06:00:26 PM PDT 24
Peak memory 199592 kb
Host smart-6ca08ff6-934f-4063-9979-5eb0ad1fd5d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663950969 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.663950969
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2209607701
Short name T122
Test name
Test status
Simulation time 26451850 ps
CPU time 0.86 seconds
Started Jul 03 06:00:15 PM PDT 24
Finished Jul 03 06:00:17 PM PDT 24
Peak memory 198880 kb
Host smart-e80f0885-b4c7-4f57-8dfb-ed3345576b5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209607701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2209607701
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.713278209
Short name T564
Test name
Test status
Simulation time 14439250 ps
CPU time 0.58 seconds
Started Jul 03 06:00:16 PM PDT 24
Finished Jul 03 06:00:17 PM PDT 24
Peak memory 194492 kb
Host smart-54510c72-b4bf-4cb9-af5b-a31f68ca275a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713278209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.713278209
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.2771644333
Short name T606
Test name
Test status
Simulation time 111598493 ps
CPU time 1.99 seconds
Started Jul 03 06:00:15 PM PDT 24
Finished Jul 03 06:00:18 PM PDT 24
Peak memory 199504 kb
Host smart-1832efa2-193e-4f3a-b9ea-eac64c68c9eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771644333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.2771644333
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1162771056
Short name T556
Test name
Test status
Simulation time 128165857 ps
CPU time 2.61 seconds
Started Jul 03 06:00:14 PM PDT 24
Finished Jul 03 06:00:17 PM PDT 24
Peak memory 199512 kb
Host smart-7350e2f3-d3a9-4c68-ac56-8f70688cfb09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162771056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1162771056
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2974512335
Short name T151
Test name
Test status
Simulation time 158398868 ps
CPU time 1.76 seconds
Started Jul 03 06:00:16 PM PDT 24
Finished Jul 03 06:00:18 PM PDT 24
Peak memory 199504 kb
Host smart-b926e6f8-dcb1-4ba0-a6ce-b270cc11f644
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974512335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2974512335
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2735439963
Short name T577
Test name
Test status
Simulation time 108861662 ps
CPU time 0.64 seconds
Started Jul 03 06:00:39 PM PDT 24
Finished Jul 03 06:00:40 PM PDT 24
Peak memory 194544 kb
Host smart-8f15c313-31ca-48eb-8479-73f0d6f01b3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735439963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2735439963
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1675608886
Short name T585
Test name
Test status
Simulation time 30808451 ps
CPU time 0.61 seconds
Started Jul 03 06:00:38 PM PDT 24
Finished Jul 03 06:00:39 PM PDT 24
Peak memory 194668 kb
Host smart-30f498b8-d7b0-47ea-8261-9312393b08e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675608886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1675608886
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3097242324
Short name T653
Test name
Test status
Simulation time 24404282 ps
CPU time 0.65 seconds
Started Jul 03 06:00:45 PM PDT 24
Finished Jul 03 06:00:46 PM PDT 24
Peak memory 194572 kb
Host smart-e1dbe247-de46-4059-a1a3-e3aadd670dfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097242324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3097242324
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.206647412
Short name T546
Test name
Test status
Simulation time 79894133 ps
CPU time 0.62 seconds
Started Jul 03 06:00:40 PM PDT 24
Finished Jul 03 06:00:41 PM PDT 24
Peak memory 194464 kb
Host smart-87a92ce1-663a-4453-8ac5-98fb3271c52e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206647412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.206647412
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.780354316
Short name T571
Test name
Test status
Simulation time 14942052 ps
CPU time 0.63 seconds
Started Jul 03 06:00:46 PM PDT 24
Finished Jul 03 06:00:47 PM PDT 24
Peak memory 194600 kb
Host smart-d9453bd7-32e9-4e14-99f5-772755df91fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780354316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.780354316
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.487888093
Short name T611
Test name
Test status
Simulation time 13707527 ps
CPU time 0.62 seconds
Started Jul 03 06:00:43 PM PDT 24
Finished Jul 03 06:00:44 PM PDT 24
Peak memory 194588 kb
Host smart-c0bd3a16-f4b6-4b80-8636-dfaf0ee9ae95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487888093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.487888093
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3709220214
Short name T534
Test name
Test status
Simulation time 17916198 ps
CPU time 0.61 seconds
Started Jul 03 06:00:43 PM PDT 24
Finished Jul 03 06:00:44 PM PDT 24
Peak memory 194548 kb
Host smart-62910004-cb04-4471-8997-9396540bb9fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709220214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3709220214
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2523389367
Short name T641
Test name
Test status
Simulation time 16766740 ps
CPU time 0.6 seconds
Started Jul 03 06:00:46 PM PDT 24
Finished Jul 03 06:00:47 PM PDT 24
Peak memory 194520 kb
Host smart-c57abf38-0353-4c72-a57b-23cfeb2d2593
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523389367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2523389367
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2204746836
Short name T552
Test name
Test status
Simulation time 13220171 ps
CPU time 0.61 seconds
Started Jul 03 06:00:40 PM PDT 24
Finished Jul 03 06:00:41 PM PDT 24
Peak memory 194628 kb
Host smart-58e87900-bffc-448d-bcb5-39b62bbea3d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204746836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2204746836
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3261623315
Short name T563
Test name
Test status
Simulation time 17961558 ps
CPU time 0.6 seconds
Started Jul 03 06:00:44 PM PDT 24
Finished Jul 03 06:00:45 PM PDT 24
Peak memory 194576 kb
Host smart-2ab1ca82-7b79-420b-b72f-e7901645b6f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261623315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3261623315
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3039975901
Short name T632
Test name
Test status
Simulation time 2178037906 ps
CPU time 3.43 seconds
Started Jul 03 06:00:24 PM PDT 24
Finished Jul 03 06:00:28 PM PDT 24
Peak memory 199620 kb
Host smart-ca1127ad-86f4-4a2b-a7c2-b889f22854f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039975901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3039975901
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1173136295
Short name T117
Test name
Test status
Simulation time 385342218 ps
CPU time 13.62 seconds
Started Jul 03 06:00:24 PM PDT 24
Finished Jul 03 06:00:38 PM PDT 24
Peak memory 199536 kb
Host smart-ebe96962-c1a1-41a3-b2ff-2680df849ebc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173136295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1173136295
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2680074978
Short name T124
Test name
Test status
Simulation time 24144752 ps
CPU time 0.78 seconds
Started Jul 03 06:00:24 PM PDT 24
Finished Jul 03 06:00:25 PM PDT 24
Peak memory 197608 kb
Host smart-b56b1ed4-70cc-4f31-ba4c-f701d9d36f04
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680074978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2680074978
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3669386480
Short name T650
Test name
Test status
Simulation time 163258445 ps
CPU time 1.32 seconds
Started Jul 03 06:00:17 PM PDT 24
Finished Jul 03 06:00:19 PM PDT 24
Peak memory 199488 kb
Host smart-d95eea30-8fdf-481c-802d-2bec38cf9938
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669386480 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3669386480
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1883521913
Short name T582
Test name
Test status
Simulation time 128795252 ps
CPU time 0.72 seconds
Started Jul 03 06:00:24 PM PDT 24
Finished Jul 03 06:00:25 PM PDT 24
Peak memory 197824 kb
Host smart-f8189eac-4ee7-48de-a36e-e5f4d14fda8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883521913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1883521913
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.697094450
Short name T542
Test name
Test status
Simulation time 14309041 ps
CPU time 0.65 seconds
Started Jul 03 06:00:18 PM PDT 24
Finished Jul 03 06:00:19 PM PDT 24
Peak memory 194572 kb
Host smart-c12181eb-8012-493e-8165-e6d5669c5ec9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697094450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.697094450
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.34619199
Short name T128
Test name
Test status
Simulation time 224868745 ps
CPU time 1.11 seconds
Started Jul 03 06:00:16 PM PDT 24
Finished Jul 03 06:00:17 PM PDT 24
Peak memory 199408 kb
Host smart-612180af-7dc2-4c49-928e-fb5bfd903963
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34619199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_o
utstanding.34619199
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1412989241
Short name T623
Test name
Test status
Simulation time 136843604 ps
CPU time 1.77 seconds
Started Jul 03 06:00:16 PM PDT 24
Finished Jul 03 06:00:19 PM PDT 24
Peak memory 199608 kb
Host smart-486008a6-0ced-474b-97c8-e4400343cd49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412989241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1412989241
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2483451438
Short name T150
Test name
Test status
Simulation time 1282657049 ps
CPU time 1.82 seconds
Started Jul 03 06:00:17 PM PDT 24
Finished Jul 03 06:00:19 PM PDT 24
Peak memory 199544 kb
Host smart-528dfb11-ff84-408e-afeb-c60f39aecdc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483451438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2483451438
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3352194097
Short name T547
Test name
Test status
Simulation time 51090018 ps
CPU time 0.58 seconds
Started Jul 03 06:00:43 PM PDT 24
Finished Jul 03 06:00:45 PM PDT 24
Peak memory 194652 kb
Host smart-5500b04f-05fa-4346-8fc7-98730e7c38f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352194097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3352194097
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1633351666
Short name T558
Test name
Test status
Simulation time 32549352 ps
CPU time 0.66 seconds
Started Jul 03 06:00:41 PM PDT 24
Finished Jul 03 06:00:42 PM PDT 24
Peak memory 194580 kb
Host smart-109cd8eb-9a7a-4418-bfd3-457fca331f18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633351666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1633351666
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.809162883
Short name T615
Test name
Test status
Simulation time 24452971 ps
CPU time 0.58 seconds
Started Jul 03 06:00:43 PM PDT 24
Finished Jul 03 06:00:44 PM PDT 24
Peak memory 194512 kb
Host smart-2bedebaf-31d8-4675-9d9d-7d8e4db26691
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809162883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.809162883
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3177540764
Short name T551
Test name
Test status
Simulation time 56444206 ps
CPU time 0.63 seconds
Started Jul 03 06:00:49 PM PDT 24
Finished Jul 03 06:00:50 PM PDT 24
Peak memory 194528 kb
Host smart-c143f1a9-b36d-4ac8-b845-86e41a1ba385
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177540764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3177540764
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2630779375
Short name T550
Test name
Test status
Simulation time 18099698 ps
CPU time 0.6 seconds
Started Jul 03 06:00:45 PM PDT 24
Finished Jul 03 06:00:46 PM PDT 24
Peak memory 194548 kb
Host smart-038e99af-0d2f-4630-8638-5255133149f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630779375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2630779375
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3969583371
Short name T633
Test name
Test status
Simulation time 40238787 ps
CPU time 0.59 seconds
Started Jul 03 06:00:43 PM PDT 24
Finished Jul 03 06:00:44 PM PDT 24
Peak memory 194636 kb
Host smart-db892bfa-5ed2-4a5b-a3af-da03c225a458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969583371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3969583371
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3795471112
Short name T598
Test name
Test status
Simulation time 15436122 ps
CPU time 0.62 seconds
Started Jul 03 06:00:44 PM PDT 24
Finished Jul 03 06:00:45 PM PDT 24
Peak memory 194480 kb
Host smart-b2c45934-6f0d-408e-b2f2-5728d8760832
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795471112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3795471112
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.4266805045
Short name T628
Test name
Test status
Simulation time 13818632 ps
CPU time 0.59 seconds
Started Jul 03 06:00:44 PM PDT 24
Finished Jul 03 06:00:46 PM PDT 24
Peak memory 194476 kb
Host smart-734a180d-c4dc-4b38-92bd-251e77fec89e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266805045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.4266805045
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.481918012
Short name T607
Test name
Test status
Simulation time 53861910 ps
CPU time 0.58 seconds
Started Jul 03 06:00:44 PM PDT 24
Finished Jul 03 06:00:45 PM PDT 24
Peak memory 194588 kb
Host smart-251c7a0c-87c4-407e-8a1f-6f3efdbcf5ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481918012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.481918012
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3249157089
Short name T576
Test name
Test status
Simulation time 20048677 ps
CPU time 0.56 seconds
Started Jul 03 06:00:46 PM PDT 24
Finished Jul 03 06:00:47 PM PDT 24
Peak memory 194596 kb
Host smart-258fc2ca-0e0d-4b6c-8733-264cd9fe6cf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249157089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3249157089
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4089820187
Short name T652
Test name
Test status
Simulation time 713473944 ps
CPU time 2.43 seconds
Started Jul 03 06:00:34 PM PDT 24
Finished Jul 03 06:00:37 PM PDT 24
Peak memory 199544 kb
Host smart-8a7aba51-6b13-413c-b681-1d08a4ec1c4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089820187 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.4089820187
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.26926365
Short name T112
Test name
Test status
Simulation time 16789457 ps
CPU time 0.8 seconds
Started Jul 03 06:00:27 PM PDT 24
Finished Jul 03 06:00:28 PM PDT 24
Peak memory 199192 kb
Host smart-1a145e33-ae6b-44ad-a630-377ce1ee37f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26926365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.26926365
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1899749028
Short name T587
Test name
Test status
Simulation time 26179125 ps
CPU time 0.6 seconds
Started Jul 03 06:00:21 PM PDT 24
Finished Jul 03 06:00:22 PM PDT 24
Peak memory 194496 kb
Host smart-d485fd70-fef5-4b86-a99d-f501f69a09d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899749028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1899749028
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3666709572
Short name T659
Test name
Test status
Simulation time 176498671 ps
CPU time 2.15 seconds
Started Jul 03 06:00:18 PM PDT 24
Finished Jul 03 06:00:21 PM PDT 24
Peak memory 199512 kb
Host smart-6736a52b-2ce1-4656-bafd-5fc9615958f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666709572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3666709572
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.288979708
Short name T565
Test name
Test status
Simulation time 2490484403 ps
CPU time 2.47 seconds
Started Jul 03 06:00:18 PM PDT 24
Finished Jul 03 06:00:21 PM PDT 24
Peak memory 199664 kb
Host smart-614138e3-b701-4f74-9d8b-f18565a2b8e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288979708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.288979708
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3170123412
Short name T143
Test name
Test status
Simulation time 171500671 ps
CPU time 3.06 seconds
Started Jul 03 06:00:17 PM PDT 24
Finished Jul 03 06:00:21 PM PDT 24
Peak memory 199556 kb
Host smart-2cfd472e-6799-4d2b-9bb3-9dd8615ca88f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170123412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3170123412
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2862883615
Short name T557
Test name
Test status
Simulation time 59879217 ps
CPU time 1.69 seconds
Started Jul 03 06:00:34 PM PDT 24
Finished Jul 03 06:00:36 PM PDT 24
Peak memory 199592 kb
Host smart-59c95fd3-a896-4661-a199-907de79bd7fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862883615 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2862883615
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1121936691
Short name T111
Test name
Test status
Simulation time 21010850 ps
CPU time 0.7 seconds
Started Jul 03 06:00:31 PM PDT 24
Finished Jul 03 06:00:32 PM PDT 24
Peak memory 197432 kb
Host smart-156f75be-6045-4ede-b42b-2721534251f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121936691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1121936691
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2908829620
Short name T613
Test name
Test status
Simulation time 12624499 ps
CPU time 0.6 seconds
Started Jul 03 06:00:36 PM PDT 24
Finished Jul 03 06:00:38 PM PDT 24
Peak memory 194608 kb
Host smart-97858fd9-5ab3-4a70-8465-d2a5366fff59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908829620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2908829620
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1194099976
Short name T129
Test name
Test status
Simulation time 176898448 ps
CPU time 1.23 seconds
Started Jul 03 06:00:32 PM PDT 24
Finished Jul 03 06:00:34 PM PDT 24
Peak memory 199212 kb
Host smart-0174c45a-c8d5-4cf4-953a-92c3f7e4d9a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194099976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1194099976
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.1929150615
Short name T560
Test name
Test status
Simulation time 187735385 ps
CPU time 2.71 seconds
Started Jul 03 06:00:31 PM PDT 24
Finished Jul 03 06:00:35 PM PDT 24
Peak memory 199572 kb
Host smart-e3bf43fe-1083-424d-9b76-a00727eed3ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929150615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.1929150615
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1955460276
Short name T639
Test name
Test status
Simulation time 86625937 ps
CPU time 1.86 seconds
Started Jul 03 06:00:31 PM PDT 24
Finished Jul 03 06:00:33 PM PDT 24
Peak memory 199520 kb
Host smart-ad83af79-87fe-4371-9bab-35c04fc82280
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955460276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1955460276
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2789009072
Short name T644
Test name
Test status
Simulation time 58606848 ps
CPU time 3.63 seconds
Started Jul 03 06:00:26 PM PDT 24
Finished Jul 03 06:00:30 PM PDT 24
Peak memory 208116 kb
Host smart-02c84363-f531-4571-b8dc-26f1c55660b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789009072 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2789009072
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3119211242
Short name T630
Test name
Test status
Simulation time 104047665 ps
CPU time 0.85 seconds
Started Jul 03 06:00:31 PM PDT 24
Finished Jul 03 06:00:32 PM PDT 24
Peak memory 198784 kb
Host smart-3f5ebd8c-ed14-4512-a6fc-5175f8e8d0de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119211242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3119211242
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.4109535895
Short name T568
Test name
Test status
Simulation time 11800662 ps
CPU time 0.56 seconds
Started Jul 03 06:00:33 PM PDT 24
Finished Jul 03 06:00:34 PM PDT 24
Peak memory 194496 kb
Host smart-69fcc9e3-86b4-4134-ac55-88539037daa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109535895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.4109535895
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2254083720
Short name T131
Test name
Test status
Simulation time 256481460 ps
CPU time 2.34 seconds
Started Jul 03 06:00:30 PM PDT 24
Finished Jul 03 06:00:33 PM PDT 24
Peak memory 199488 kb
Host smart-da167011-d912-4380-8a31-ca5770b16d75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254083720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2254083720
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2038740168
Short name T636
Test name
Test status
Simulation time 211462022 ps
CPU time 3.68 seconds
Started Jul 03 06:00:32 PM PDT 24
Finished Jul 03 06:00:37 PM PDT 24
Peak memory 199504 kb
Host smart-eb41c988-c50b-4ea1-8f6c-b1bcebd6ad83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038740168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2038740168
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3343761087
Short name T80
Test name
Test status
Simulation time 250754887 ps
CPU time 4.01 seconds
Started Jul 03 06:00:32 PM PDT 24
Finished Jul 03 06:00:36 PM PDT 24
Peak memory 199536 kb
Host smart-53db7562-a417-451c-af46-05ff7c05543d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343761087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3343761087
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2848350187
Short name T562
Test name
Test status
Simulation time 29323100 ps
CPU time 1.9 seconds
Started Jul 03 06:00:22 PM PDT 24
Finished Jul 03 06:00:25 PM PDT 24
Peak memory 199680 kb
Host smart-062d4644-0014-468b-96bd-2fbd333f27ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848350187 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2848350187
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.36654452
Short name T116
Test name
Test status
Simulation time 35973093 ps
CPU time 0.93 seconds
Started Jul 03 06:00:31 PM PDT 24
Finished Jul 03 06:00:32 PM PDT 24
Peak memory 199432 kb
Host smart-4eae19d3-5a72-42e0-8208-ce40dad5a723
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36654452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.36654452
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.1833291035
Short name T538
Test name
Test status
Simulation time 11462801 ps
CPU time 0.6 seconds
Started Jul 03 06:00:30 PM PDT 24
Finished Jul 03 06:00:31 PM PDT 24
Peak memory 194520 kb
Host smart-a6f0e8e3-c9c6-4a84-9ab0-88d65d4ff451
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833291035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1833291035
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1724339846
Short name T579
Test name
Test status
Simulation time 66267063 ps
CPU time 1.17 seconds
Started Jul 03 06:00:31 PM PDT 24
Finished Jul 03 06:00:32 PM PDT 24
Peak memory 199424 kb
Host smart-df48d7f2-9604-49ff-bc35-90226d6036fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724339846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1724339846
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2757944779
Short name T605
Test name
Test status
Simulation time 98454219 ps
CPU time 2.75 seconds
Started Jul 03 06:00:24 PM PDT 24
Finished Jul 03 06:00:26 PM PDT 24
Peak memory 199500 kb
Host smart-8b3869a1-02f2-4d68-b1b3-0b8bc8aa2956
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757944779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2757944779
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2857288198
Short name T147
Test name
Test status
Simulation time 362246466 ps
CPU time 3.05 seconds
Started Jul 03 06:00:34 PM PDT 24
Finished Jul 03 06:00:38 PM PDT 24
Peak memory 199488 kb
Host smart-a43ead8d-c633-40ba-beee-a50a56cdaf0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857288198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2857288198
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1235887259
Short name T567
Test name
Test status
Simulation time 40473188 ps
CPU time 1.22 seconds
Started Jul 03 06:00:36 PM PDT 24
Finished Jul 03 06:00:38 PM PDT 24
Peak memory 199476 kb
Host smart-9a91a278-96b7-49bb-9560-5de6117051e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235887259 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1235887259
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1926693478
Short name T593
Test name
Test status
Simulation time 30904343 ps
CPU time 0.96 seconds
Started Jul 03 06:00:31 PM PDT 24
Finished Jul 03 06:00:33 PM PDT 24
Peak memory 199304 kb
Host smart-f285afce-9417-41a5-8e22-b3438db5242e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926693478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1926693478
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.471887642
Short name T543
Test name
Test status
Simulation time 80243461 ps
CPU time 0.6 seconds
Started Jul 03 06:00:32 PM PDT 24
Finished Jul 03 06:00:34 PM PDT 24
Peak memory 194504 kb
Host smart-74813fd7-8b91-462e-bf8e-74c9e96b6cc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471887642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.471887642
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3179678591
Short name T649
Test name
Test status
Simulation time 80021773 ps
CPU time 1.03 seconds
Started Jul 03 06:00:32 PM PDT 24
Finished Jul 03 06:00:34 PM PDT 24
Peak memory 198144 kb
Host smart-44fbd6f4-b7ce-4bc7-b6e7-22ee60d5336a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179678591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3179678591
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3139130302
Short name T566
Test name
Test status
Simulation time 71904782 ps
CPU time 1.94 seconds
Started Jul 03 06:00:30 PM PDT 24
Finished Jul 03 06:00:32 PM PDT 24
Peak memory 199544 kb
Host smart-b9207ee5-3a18-47b6-8048-0436de70f246
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139130302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3139130302
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.560479718
Short name T152
Test name
Test status
Simulation time 515440041 ps
CPU time 4.47 seconds
Started Jul 03 06:00:30 PM PDT 24
Finished Jul 03 06:00:35 PM PDT 24
Peak memory 199540 kb
Host smart-0c2bd2e4-57a4-47d4-b571-98d0edca3423
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560479718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.560479718
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.4148310411
Short name T380
Test name
Test status
Simulation time 33026142 ps
CPU time 0.56 seconds
Started Jul 03 07:19:30 PM PDT 24
Finished Jul 03 07:19:35 PM PDT 24
Peak memory 196856 kb
Host smart-7da4e8ab-a329-4bd5-bc7f-12fd93001deb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148310411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.4148310411
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2706065063
Short name T328
Test name
Test status
Simulation time 2274792645 ps
CPU time 47.96 seconds
Started Jul 03 07:19:28 PM PDT 24
Finished Jul 03 07:20:21 PM PDT 24
Peak memory 200696 kb
Host smart-a63e5b00-36b2-490b-81fd-e3a13fb31527
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2706065063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2706065063
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3524919727
Short name T168
Test name
Test status
Simulation time 1922296442 ps
CPU time 36.26 seconds
Started Jul 03 07:19:28 PM PDT 24
Finished Jul 03 07:20:09 PM PDT 24
Peak memory 200376 kb
Host smart-2eef8e77-e147-4136-b8c1-6008464c88f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524919727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3524919727
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.149749914
Short name T447
Test name
Test status
Simulation time 12612049058 ps
CPU time 952.83 seconds
Started Jul 03 07:19:26 PM PDT 24
Finished Jul 03 07:35:24 PM PDT 24
Peak memory 759568 kb
Host smart-fca82d71-301d-4533-bbdc-9da89db5f587
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=149749914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.149749914
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1301301263
Short name T161
Test name
Test status
Simulation time 3016775730 ps
CPU time 151.37 seconds
Started Jul 03 07:19:35 PM PDT 24
Finished Jul 03 07:22:10 PM PDT 24
Peak memory 200644 kb
Host smart-80f6f0d7-0db1-474a-a64b-10a5ac178605
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301301263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1301301263
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.2665389187
Short name T508
Test name
Test status
Simulation time 13348954404 ps
CPU time 188.07 seconds
Started Jul 03 07:19:28 PM PDT 24
Finished Jul 03 07:22:41 PM PDT 24
Peak memory 216832 kb
Host smart-77fbe554-79ec-4d88-9401-2594a9be7cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665389187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.2665389187
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.2162884340
Short name T301
Test name
Test status
Simulation time 2077708107 ps
CPU time 3.11 seconds
Started Jul 03 07:19:28 PM PDT 24
Finished Jul 03 07:19:37 PM PDT 24
Peak memory 200388 kb
Host smart-0e63180a-d85f-4f9c-8def-f1c36af0690a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162884340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2162884340
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3650051224
Short name T526
Test name
Test status
Simulation time 79361429409 ps
CPU time 2285.76 seconds
Started Jul 03 07:19:31 PM PDT 24
Finished Jul 03 07:57:41 PM PDT 24
Peak memory 800660 kb
Host smart-df1a0347-6f83-41bb-8429-dde3fe994317
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650051224 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3650051224
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.3797264601
Short name T24
Test name
Test status
Simulation time 348179361710 ps
CPU time 5697.21 seconds
Started Jul 03 07:19:31 PM PDT 24
Finished Jul 03 08:54:33 PM PDT 24
Peak memory 825648 kb
Host smart-a8b0867f-5418-469a-be00-092e59d080a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3797264601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.3797264601
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.1100065481
Short name T402
Test name
Test status
Simulation time 42457254439 ps
CPU time 69.98 seconds
Started Jul 03 07:19:31 PM PDT 24
Finished Jul 03 07:20:45 PM PDT 24
Peak memory 200508 kb
Host smart-84e87632-926c-461a-a1d4-57ce093480ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1100065481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.1100065481
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.2317544015
Short name T358
Test name
Test status
Simulation time 15041892803 ps
CPU time 57.08 seconds
Started Jul 03 07:19:31 PM PDT 24
Finished Jul 03 07:20:32 PM PDT 24
Peak memory 200432 kb
Host smart-31027d25-5b17-4998-941d-b0ec920d6784
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2317544015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.2317544015
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.3076270064
Short name T286
Test name
Test status
Simulation time 32720806190 ps
CPU time 99.06 seconds
Started Jul 03 07:19:32 PM PDT 24
Finished Jul 03 07:21:15 PM PDT 24
Peak memory 200484 kb
Host smart-911c4e71-6c0c-4328-bbf5-a9f45ea145cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3076270064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.3076270064
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.1260901564
Short name T479
Test name
Test status
Simulation time 9089006913 ps
CPU time 516.31 seconds
Started Jul 03 07:19:26 PM PDT 24
Finished Jul 03 07:28:08 PM PDT 24
Peak memory 200480 kb
Host smart-21f477de-bb7a-48c2-b7ef-90b68c377899
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1260901564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.1260901564
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.317356933
Short name T269
Test name
Test status
Simulation time 36836516208 ps
CPU time 1890.45 seconds
Started Jul 03 07:19:28 PM PDT 24
Finished Jul 03 07:51:04 PM PDT 24
Peak memory 208900 kb
Host smart-fa42f2ab-80af-48aa-8b47-3f8917d39e63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=317356933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.317356933
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.2525272968
Short name T517
Test name
Test status
Simulation time 367802413861 ps
CPU time 2668.03 seconds
Started Jul 03 07:19:34 PM PDT 24
Finished Jul 03 08:04:06 PM PDT 24
Peak memory 216012 kb
Host smart-212e8f5e-2b06-4f97-9247-d2f6a89893ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2525272968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.2525272968
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1181228627
Short name T387
Test name
Test status
Simulation time 8612955046 ps
CPU time 47.26 seconds
Started Jul 03 07:19:29 PM PDT 24
Finished Jul 03 07:20:21 PM PDT 24
Peak memory 200644 kb
Host smart-6e1710b4-6704-467e-821c-c810f6ac64d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181228627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1181228627
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.401029068
Short name T444
Test name
Test status
Simulation time 31796568 ps
CPU time 0.57 seconds
Started Jul 03 07:19:31 PM PDT 24
Finished Jul 03 07:19:36 PM PDT 24
Peak memory 196216 kb
Host smart-3d27ca5f-7182-4c1e-99f4-dc3837893e80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401029068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.401029068
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.440010878
Short name T324
Test name
Test status
Simulation time 4683865153 ps
CPU time 53.41 seconds
Started Jul 03 07:19:32 PM PDT 24
Finished Jul 03 07:20:30 PM PDT 24
Peak memory 200468 kb
Host smart-410af985-4919-4f8d-a789-362f0301db69
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=440010878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.440010878
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3777323381
Short name T322
Test name
Test status
Simulation time 7885676100 ps
CPU time 68.14 seconds
Started Jul 03 07:19:32 PM PDT 24
Finished Jul 03 07:20:44 PM PDT 24
Peak memory 200440 kb
Host smart-2d049140-fa4b-42e8-9f97-9194bcc77b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777323381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3777323381
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1985177151
Short name T418
Test name
Test status
Simulation time 1540369157 ps
CPU time 96.16 seconds
Started Jul 03 07:19:33 PM PDT 24
Finished Jul 03 07:21:13 PM PDT 24
Peak memory 409600 kb
Host smart-2d29eb8d-5922-4a04-b677-8dc2b4d65434
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1985177151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1985177151
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.524278803
Short name T341
Test name
Test status
Simulation time 3902388312 ps
CPU time 30.67 seconds
Started Jul 03 07:19:41 PM PDT 24
Finished Jul 03 07:20:16 PM PDT 24
Peak memory 200388 kb
Host smart-57ff551e-5650-4280-bd57-e260966bcc62
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524278803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.524278803
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3139354879
Short name T5
Test name
Test status
Simulation time 3998399585 ps
CPU time 59.7 seconds
Started Jul 03 07:19:38 PM PDT 24
Finished Jul 03 07:20:40 PM PDT 24
Peak memory 200428 kb
Host smart-3f42be65-202e-4f78-99a5-9f6349e02a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139354879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3139354879
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3253286686
Short name T69
Test name
Test status
Simulation time 37067333 ps
CPU time 0.89 seconds
Started Jul 03 07:19:38 PM PDT 24
Finished Jul 03 07:19:42 PM PDT 24
Peak memory 218364 kb
Host smart-35d49709-56c6-47fa-a4a7-27a2b76ba6c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253286686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3253286686
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1390534131
Short name T197
Test name
Test status
Simulation time 81656903 ps
CPU time 3.92 seconds
Started Jul 03 07:19:31 PM PDT 24
Finished Jul 03 07:19:39 PM PDT 24
Peak memory 200400 kb
Host smart-ae847ddf-ef3e-4cb9-8a7f-b1e5ca375296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390534131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1390534131
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1464426180
Short name T491
Test name
Test status
Simulation time 522243226165 ps
CPU time 827.1 seconds
Started Jul 03 07:19:32 PM PDT 24
Finished Jul 03 07:33:23 PM PDT 24
Peak memory 216892 kb
Host smart-85939508-29c3-45a8-939f-3bd9e1fb6fa8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464426180 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1464426180
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.2084806848
Short name T82
Test name
Test status
Simulation time 55330397721 ps
CPU time 2259.72 seconds
Started Jul 03 07:19:38 PM PDT 24
Finished Jul 03 07:57:21 PM PDT 24
Peak memory 769584 kb
Host smart-f59826bb-4f5c-4a9d-8538-d4ed24521e99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2084806848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.2084806848
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.4190148829
Short name T18
Test name
Test status
Simulation time 8211866571 ps
CPU time 40.15 seconds
Started Jul 03 07:19:35 PM PDT 24
Finished Jul 03 07:20:18 PM PDT 24
Peak memory 200440 kb
Host smart-e04c7372-a716-4dee-9e9e-522665bdc3e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4190148829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.4190148829
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.427751225
Short name T437
Test name
Test status
Simulation time 8662534238 ps
CPU time 105.29 seconds
Started Jul 03 07:19:35 PM PDT 24
Finished Jul 03 07:21:23 PM PDT 24
Peak memory 200396 kb
Host smart-e07fdfe8-adaf-4bce-9e22-71b05376f909
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=427751225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.427751225
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.87113704
Short name T201
Test name
Test status
Simulation time 78787206899 ps
CPU time 131.95 seconds
Started Jul 03 07:19:30 PM PDT 24
Finished Jul 03 07:21:47 PM PDT 24
Peak memory 200424 kb
Host smart-54c78c97-9f4b-479a-9fc4-9353a06bbc2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=87113704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.87113704
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1706989613
Short name T515
Test name
Test status
Simulation time 407839284438 ps
CPU time 564.94 seconds
Started Jul 03 07:19:34 PM PDT 24
Finished Jul 03 07:29:02 PM PDT 24
Peak memory 200480 kb
Host smart-e317d242-84c4-4379-904b-72c8a66c1328
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1706989613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1706989613
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.2471666227
Short name T193
Test name
Test status
Simulation time 73071137829 ps
CPU time 2116.24 seconds
Started Jul 03 07:19:32 PM PDT 24
Finished Jul 03 07:54:53 PM PDT 24
Peak memory 216524 kb
Host smart-e8c4d749-cafc-47d6-92cb-ca9b87328d5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2471666227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.2471666227
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.309937265
Short name T493
Test name
Test status
Simulation time 40714095758 ps
CPU time 2324.39 seconds
Started Jul 03 07:19:35 PM PDT 24
Finished Jul 03 07:58:24 PM PDT 24
Peak memory 216176 kb
Host smart-658599d5-06e0-45b7-a395-c9d40bbf7e4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=309937265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.309937265
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1701356590
Short name T72
Test name
Test status
Simulation time 27588101863 ps
CPU time 130.1 seconds
Started Jul 03 07:19:38 PM PDT 24
Finished Jul 03 07:21:51 PM PDT 24
Peak memory 200432 kb
Host smart-16623279-d698-4ad7-b2f4-db2787561898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701356590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1701356590
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.787478659
Short name T401
Test name
Test status
Simulation time 28574850 ps
CPU time 0.57 seconds
Started Jul 03 07:19:50 PM PDT 24
Finished Jul 03 07:19:52 PM PDT 24
Peak memory 195216 kb
Host smart-e8cadade-b3e1-4180-87b3-ca3d51337338
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787478659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.787478659
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2059862225
Short name T274
Test name
Test status
Simulation time 2024071938 ps
CPU time 60.53 seconds
Started Jul 03 07:19:51 PM PDT 24
Finished Jul 03 07:20:54 PM PDT 24
Peak memory 200360 kb
Host smart-4e82df77-14d7-43b4-adaf-01941a90bb39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2059862225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2059862225
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.746969662
Short name T355
Test name
Test status
Simulation time 6733367783 ps
CPU time 29.28 seconds
Started Jul 03 07:19:51 PM PDT 24
Finished Jul 03 07:20:23 PM PDT 24
Peak memory 200384 kb
Host smart-e636b8dc-0b6b-4eda-8098-093c362046e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746969662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.746969662
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3699139882
Short name T225
Test name
Test status
Simulation time 31767260 ps
CPU time 1.07 seconds
Started Jul 03 07:19:51 PM PDT 24
Finished Jul 03 07:19:55 PM PDT 24
Peak memory 200404 kb
Host smart-fe1dc33a-637c-4fe4-9959-1cc3d0bb6485
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3699139882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3699139882
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3674272025
Short name T472
Test name
Test status
Simulation time 2040254261 ps
CPU time 110.44 seconds
Started Jul 03 07:19:51 PM PDT 24
Finished Jul 03 07:21:44 PM PDT 24
Peak memory 200396 kb
Host smart-d887813c-bb23-4487-a143-c80d85ef0fcc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674272025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3674272025
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.4187247875
Short name T245
Test name
Test status
Simulation time 836501653 ps
CPU time 43.46 seconds
Started Jul 03 07:19:51 PM PDT 24
Finished Jul 03 07:20:38 PM PDT 24
Peak memory 200428 kb
Host smart-e3082db9-9a2c-417a-a548-3d31ef87c1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187247875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.4187247875
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.43833338
Short name T212
Test name
Test status
Simulation time 314504693 ps
CPU time 1.86 seconds
Started Jul 03 07:19:52 PM PDT 24
Finished Jul 03 07:19:57 PM PDT 24
Peak memory 200316 kb
Host smart-d7d35789-b6af-4c7a-b2d3-d4b728329e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43833338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.43833338
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.2396491395
Short name T25
Test name
Test status
Simulation time 82823573682 ps
CPU time 1967.51 seconds
Started Jul 03 07:19:54 PM PDT 24
Finished Jul 03 07:52:45 PM PDT 24
Peak memory 753916 kb
Host smart-db66327b-dff9-4de9-82f0-0dff5e044f06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396491395 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2396491395
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2481501740
Short name T385
Test name
Test status
Simulation time 2649799610 ps
CPU time 32.33 seconds
Started Jul 03 07:19:49 PM PDT 24
Finished Jul 03 07:20:24 PM PDT 24
Peak memory 200476 kb
Host smart-9f3b993d-a3be-42b2-b0ed-895f44649e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481501740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2481501740
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2040024459
Short name T9
Test name
Test status
Simulation time 1617811400 ps
CPU time 93.33 seconds
Started Jul 03 07:19:51 PM PDT 24
Finished Jul 03 07:21:27 PM PDT 24
Peak memory 200364 kb
Host smart-b0327ffb-0480-4061-a700-5b45426b0c02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2040024459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2040024459
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2642234790
Short name T259
Test name
Test status
Simulation time 125315470 ps
CPU time 1.67 seconds
Started Jul 03 07:19:52 PM PDT 24
Finished Jul 03 07:19:57 PM PDT 24
Peak memory 200260 kb
Host smart-3359fdb9-c5b1-4ca2-8d80-69a777f5cbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642234790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2642234790
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1706619614
Short name T317
Test name
Test status
Simulation time 35942030158 ps
CPU time 321.13 seconds
Started Jul 03 07:19:50 PM PDT 24
Finished Jul 03 07:25:14 PM PDT 24
Peak memory 632632 kb
Host smart-0c53abdd-7b2a-4a85-85d0-4f17cdc2949a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1706619614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1706619614
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.299687651
Short name T50
Test name
Test status
Simulation time 2347582027 ps
CPU time 120.25 seconds
Started Jul 03 07:19:52 PM PDT 24
Finished Jul 03 07:21:55 PM PDT 24
Peak memory 200384 kb
Host smart-3f1969ab-47b8-4840-935e-83a92fd25840
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299687651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.299687651
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3825136947
Short name T263
Test name
Test status
Simulation time 3189933669 ps
CPU time 33.83 seconds
Started Jul 03 07:19:52 PM PDT 24
Finished Jul 03 07:20:28 PM PDT 24
Peak memory 200428 kb
Host smart-b846e96c-ae45-465d-b874-d74c0a9db23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825136947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3825136947
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1897357830
Short name T273
Test name
Test status
Simulation time 1404894402 ps
CPU time 12.42 seconds
Started Jul 03 07:19:54 PM PDT 24
Finished Jul 03 07:20:09 PM PDT 24
Peak memory 200144 kb
Host smart-6d40b3f9-2e16-4066-96cd-5bc19ec66734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897357830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1897357830
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2072363436
Short name T441
Test name
Test status
Simulation time 94738731099 ps
CPU time 2470.17 seconds
Started Jul 03 07:19:53 PM PDT 24
Finished Jul 03 08:01:07 PM PDT 24
Peak memory 734532 kb
Host smart-ba3e4b75-0d39-4f35-a88a-57ce01f678f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072363436 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2072363436
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2701006346
Short name T353
Test name
Test status
Simulation time 1041200692 ps
CPU time 27.21 seconds
Started Jul 03 07:19:52 PM PDT 24
Finished Jul 03 07:20:22 PM PDT 24
Peak memory 200420 kb
Host smart-6c88b8d2-bae9-4edc-a8cf-898bb7fb133c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701006346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2701006346
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.273863885
Short name T446
Test name
Test status
Simulation time 45808808 ps
CPU time 0.6 seconds
Started Jul 03 07:19:54 PM PDT 24
Finished Jul 03 07:19:57 PM PDT 24
Peak memory 195168 kb
Host smart-f5db8563-901b-49df-8b72-834a00b3e2aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273863885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.273863885
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3023365135
Short name T474
Test name
Test status
Simulation time 1139691066 ps
CPU time 67.74 seconds
Started Jul 03 07:19:58 PM PDT 24
Finished Jul 03 07:21:09 PM PDT 24
Peak memory 200376 kb
Host smart-7cb4169e-c047-457b-a919-a1d9acaa419a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3023365135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3023365135
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.4048150891
Short name T250
Test name
Test status
Simulation time 2755836497 ps
CPU time 18.53 seconds
Started Jul 03 07:19:57 PM PDT 24
Finished Jul 03 07:20:19 PM PDT 24
Peak memory 200388 kb
Host smart-38b1c670-ca84-4d3c-b312-2a0b2321a463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048150891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.4048150891
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.396361537
Short name T248
Test name
Test status
Simulation time 16127135985 ps
CPU time 495.22 seconds
Started Jul 03 07:19:56 PM PDT 24
Finished Jul 03 07:28:15 PM PDT 24
Peak memory 684732 kb
Host smart-62a54930-a66c-49b5-82ef-86ba75f924f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=396361537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.396361537
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2116654841
Short name T354
Test name
Test status
Simulation time 1519488840 ps
CPU time 21.82 seconds
Started Jul 03 07:19:55 PM PDT 24
Finished Jul 03 07:20:20 PM PDT 24
Peak memory 200216 kb
Host smart-c9247201-289e-49dd-b5eb-457204166229
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116654841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2116654841
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.4064104325
Short name T533
Test name
Test status
Simulation time 22944997022 ps
CPU time 90.26 seconds
Started Jul 03 07:19:56 PM PDT 24
Finished Jul 03 07:21:30 PM PDT 24
Peak memory 200456 kb
Host smart-2074f746-96f2-4f2f-9554-3d613a1260b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064104325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.4064104325
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.1438648701
Short name T208
Test name
Test status
Simulation time 875782380 ps
CPU time 14.79 seconds
Started Jul 03 07:19:48 PM PDT 24
Finished Jul 03 07:20:06 PM PDT 24
Peak memory 200316 kb
Host smart-809a89db-f67e-46ab-9879-ae74d9095606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438648701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.1438648701
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3812284519
Short name T507
Test name
Test status
Simulation time 1390228817 ps
CPU time 80.28 seconds
Started Jul 03 07:19:57 PM PDT 24
Finished Jul 03 07:21:20 PM PDT 24
Peak memory 200308 kb
Host smart-ac1501be-42d6-4f62-87ab-4add0a25e6e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812284519 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3812284519
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.885825218
Short name T179
Test name
Test status
Simulation time 70594872 ps
CPU time 1.33 seconds
Started Jul 03 07:19:55 PM PDT 24
Finished Jul 03 07:20:00 PM PDT 24
Peak memory 200436 kb
Host smart-73aa1383-a7c3-4ff7-9f14-4aa8f8435469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885825218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.885825218
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1122022002
Short name T308
Test name
Test status
Simulation time 88858702 ps
CPU time 0.58 seconds
Started Jul 03 07:19:57 PM PDT 24
Finished Jul 03 07:20:01 PM PDT 24
Peak memory 195040 kb
Host smart-fda18706-4ad1-4cd5-bbb2-b92c12732d9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122022002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1122022002
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2446728333
Short name T61
Test name
Test status
Simulation time 6463052844 ps
CPU time 66.37 seconds
Started Jul 03 07:20:01 PM PDT 24
Finished Jul 03 07:21:11 PM PDT 24
Peak memory 200436 kb
Host smart-e20492c0-f7a2-4c08-ac69-c5f63ed38c29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2446728333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2446728333
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.3107211222
Short name T510
Test name
Test status
Simulation time 685946055 ps
CPU time 14.42 seconds
Started Jul 03 07:19:55 PM PDT 24
Finished Jul 03 07:20:12 PM PDT 24
Peak memory 200324 kb
Host smart-6482b5f7-76c9-4b3b-8d03-f8a79254e6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107211222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.3107211222
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2152906162
Short name T298
Test name
Test status
Simulation time 29551466566 ps
CPU time 1800.39 seconds
Started Jul 03 07:20:01 PM PDT 24
Finished Jul 03 07:50:05 PM PDT 24
Peak memory 785804 kb
Host smart-f58eb6b3-397f-4262-96bf-5906f8bde443
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2152906162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2152906162
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2057952336
Short name T175
Test name
Test status
Simulation time 12269133617 ps
CPU time 193.51 seconds
Started Jul 03 07:19:56 PM PDT 24
Finished Jul 03 07:23:13 PM PDT 24
Peak memory 200400 kb
Host smart-bbb76646-1bff-482b-a56d-f9597ff8def4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057952336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2057952336
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.3265704793
Short name T375
Test name
Test status
Simulation time 4050987924 ps
CPU time 96.66 seconds
Started Jul 03 07:19:56 PM PDT 24
Finished Jul 03 07:21:35 PM PDT 24
Peak memory 216760 kb
Host smart-93a01459-39a8-466d-8e7f-8ad2b10b6eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265704793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3265704793
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3182913111
Short name T204
Test name
Test status
Simulation time 1078648619 ps
CPU time 4.64 seconds
Started Jul 03 07:19:54 PM PDT 24
Finished Jul 03 07:20:02 PM PDT 24
Peak memory 200332 kb
Host smart-81558bf4-c463-4217-b000-7485ce43197c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182913111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3182913111
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3994023595
Short name T260
Test name
Test status
Simulation time 39956030737 ps
CPU time 169.42 seconds
Started Jul 03 07:19:54 PM PDT 24
Finished Jul 03 07:22:46 PM PDT 24
Peak memory 199696 kb
Host smart-3f3c9195-4c79-47a4-8f08-76fb3f1508e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994023595 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3994023595
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.128401305
Short name T104
Test name
Test status
Simulation time 18643821714 ps
CPU time 122.4 seconds
Started Jul 03 07:19:54 PM PDT 24
Finished Jul 03 07:21:59 PM PDT 24
Peak memory 200424 kb
Host smart-bacac841-3a45-4e35-821b-1733346b4ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128401305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.128401305
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2911432816
Short name T351
Test name
Test status
Simulation time 156095112 ps
CPU time 0.61 seconds
Started Jul 03 07:19:58 PM PDT 24
Finished Jul 03 07:20:02 PM PDT 24
Peak memory 196896 kb
Host smart-55834aa4-f245-4d09-9826-b478dd809361
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911432816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2911432816
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3938821882
Short name T29
Test name
Test status
Simulation time 6937285229 ps
CPU time 64.46 seconds
Started Jul 03 07:19:56 PM PDT 24
Finished Jul 03 07:21:03 PM PDT 24
Peak memory 200500 kb
Host smart-6b828fa3-9bc0-487e-9af0-0119e280eaea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3938821882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3938821882
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3614219653
Short name T86
Test name
Test status
Simulation time 4205741785 ps
CPU time 199.82 seconds
Started Jul 03 07:19:56 PM PDT 24
Finished Jul 03 07:23:19 PM PDT 24
Peak memory 640108 kb
Host smart-132c3a54-62eb-4195-bcf1-5dc484825451
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3614219653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3614219653
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.827639456
Short name T49
Test name
Test status
Simulation time 529208475 ps
CPU time 7.18 seconds
Started Jul 03 07:19:56 PM PDT 24
Finished Jul 03 07:20:07 PM PDT 24
Peak memory 200144 kb
Host smart-8c5288b0-79ed-43a8-ad25-2b07b754d42c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827639456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.827639456
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1927826566
Short name T530
Test name
Test status
Simulation time 23952855316 ps
CPU time 165.52 seconds
Started Jul 03 07:19:56 PM PDT 24
Finished Jul 03 07:22:44 PM PDT 24
Peak memory 216796 kb
Host smart-a12589e6-d55a-4598-bfd3-2e3fbe4b11c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927826566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1927826566
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3549801458
Short name T463
Test name
Test status
Simulation time 880270185 ps
CPU time 9.56 seconds
Started Jul 03 07:19:55 PM PDT 24
Finished Jul 03 07:20:08 PM PDT 24
Peak memory 200344 kb
Host smart-6f5f559c-cfeb-4f69-853b-03c4b1f0bd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549801458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3549801458
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.787904455
Short name T477
Test name
Test status
Simulation time 31349679725 ps
CPU time 414.66 seconds
Started Jul 03 07:19:56 PM PDT 24
Finished Jul 03 07:26:54 PM PDT 24
Peak memory 200460 kb
Host smart-7bbb7e34-5a82-42ea-be8a-2f88a8de62b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787904455 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.787904455
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2217827526
Short name T222
Test name
Test status
Simulation time 6305988439 ps
CPU time 55.17 seconds
Started Jul 03 07:19:56 PM PDT 24
Finished Jul 03 07:20:54 PM PDT 24
Peak memory 200408 kb
Host smart-fd635064-00a7-4dee-82b2-1e4ebe2f7b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217827526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2217827526
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3569290372
Short name T52
Test name
Test status
Simulation time 12563944 ps
CPU time 0.65 seconds
Started Jul 03 07:20:03 PM PDT 24
Finished Jul 03 07:20:07 PM PDT 24
Peak memory 196476 kb
Host smart-869d77e2-6381-4b41-9e27-1e6ba9dda4e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569290372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3569290372
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.16548162
Short name T38
Test name
Test status
Simulation time 6891990528 ps
CPU time 89.48 seconds
Started Jul 03 07:19:59 PM PDT 24
Finished Jul 03 07:21:32 PM PDT 24
Peak memory 200420 kb
Host smart-8ffdd3a6-48d4-4b94-b6eb-d379bfa1d179
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16548162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.16548162
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1325938785
Short name T336
Test name
Test status
Simulation time 2087988893 ps
CPU time 55.8 seconds
Started Jul 03 07:19:58 PM PDT 24
Finished Jul 03 07:20:57 PM PDT 24
Peak memory 200388 kb
Host smart-7090c76a-5aaf-47a9-ad6e-f4d58dc280c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325938785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1325938785
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2001955228
Short name T369
Test name
Test status
Simulation time 2357109892 ps
CPU time 457.85 seconds
Started Jul 03 07:20:00 PM PDT 24
Finished Jul 03 07:27:41 PM PDT 24
Peak memory 708836 kb
Host smart-6eae1c7a-dd3f-4987-9047-ef93e5cc4878
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2001955228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2001955228
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1583195289
Short name T436
Test name
Test status
Simulation time 13012126764 ps
CPU time 177.87 seconds
Started Jul 03 07:20:03 PM PDT 24
Finished Jul 03 07:23:04 PM PDT 24
Peak memory 200392 kb
Host smart-d412f628-4e8f-472c-8429-b76c5331ed9e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583195289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1583195289
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.1662823534
Short name T371
Test name
Test status
Simulation time 2614730063 ps
CPU time 16.54 seconds
Started Jul 03 07:20:03 PM PDT 24
Finished Jul 03 07:20:23 PM PDT 24
Peak memory 200300 kb
Host smart-d764dab7-4153-43f4-b95d-429e143599f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662823534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.1662823534
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.781295002
Short name T267
Test name
Test status
Simulation time 176031573 ps
CPU time 6.04 seconds
Started Jul 03 07:19:59 PM PDT 24
Finished Jul 03 07:20:09 PM PDT 24
Peak memory 200388 kb
Host smart-bd7d0953-d629-4a18-b748-de4bdff65d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781295002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.781295002
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3299550262
Short name T218
Test name
Test status
Simulation time 7165666742 ps
CPU time 92.39 seconds
Started Jul 03 07:20:04 PM PDT 24
Finished Jul 03 07:21:39 PM PDT 24
Peak memory 200432 kb
Host smart-dc3caff6-9e2b-421e-ae24-95c9b8c5c950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299550262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3299550262
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2353805261
Short name T503
Test name
Test status
Simulation time 53976879 ps
CPU time 0.61 seconds
Started Jul 03 07:20:00 PM PDT 24
Finished Jul 03 07:20:04 PM PDT 24
Peak memory 196864 kb
Host smart-435bd368-3da5-4c04-b637-35e1472a596a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353805261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2353805261
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2060943310
Short name T498
Test name
Test status
Simulation time 2854730508 ps
CPU time 85.48 seconds
Started Jul 03 07:20:01 PM PDT 24
Finished Jul 03 07:21:30 PM PDT 24
Peak memory 200484 kb
Host smart-0aaa8059-74a1-44a4-af23-35bdd796ebd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2060943310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2060943310
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.4180873881
Short name T331
Test name
Test status
Simulation time 16927329386 ps
CPU time 58.64 seconds
Started Jul 03 07:19:59 PM PDT 24
Finished Jul 03 07:21:01 PM PDT 24
Peak memory 200520 kb
Host smart-e1d2ce60-cf3c-4019-9fec-5c64aa2e9b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180873881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.4180873881
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.1635028713
Short name T398
Test name
Test status
Simulation time 16522399099 ps
CPU time 715.26 seconds
Started Jul 03 07:19:59 PM PDT 24
Finished Jul 03 07:31:58 PM PDT 24
Peak memory 686060 kb
Host smart-d727512d-8510-460f-8d62-38a1fab36f02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1635028713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1635028713
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.381048924
Short name T297
Test name
Test status
Simulation time 13637345196 ps
CPU time 187.59 seconds
Started Jul 03 07:19:59 PM PDT 24
Finished Jul 03 07:23:10 PM PDT 24
Peak memory 200484 kb
Host smart-bde3a2e4-3caf-4761-b33e-d64e2dda44ca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381048924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.381048924
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2641099123
Short name T100
Test name
Test status
Simulation time 10558595370 ps
CPU time 192.73 seconds
Started Jul 03 07:20:04 PM PDT 24
Finished Jul 03 07:23:20 PM PDT 24
Peak memory 216804 kb
Host smart-dccaa407-ff17-475a-8a33-86790dbe7e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641099123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2641099123
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.4130451803
Short name T37
Test name
Test status
Simulation time 1453331034 ps
CPU time 4.96 seconds
Started Jul 03 07:20:00 PM PDT 24
Finished Jul 03 07:20:08 PM PDT 24
Peak memory 200316 kb
Host smart-cda483de-5fb1-4c72-9941-8311f0c3332e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130451803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.4130451803
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.388869028
Short name T160
Test name
Test status
Simulation time 111000157293 ps
CPU time 3843.75 seconds
Started Jul 03 07:20:00 PM PDT 24
Finished Jul 03 08:24:08 PM PDT 24
Peak memory 781180 kb
Host smart-5b6ee708-df04-438c-ab33-0f1bc0209623
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388869028 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.388869028
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3160732037
Short name T170
Test name
Test status
Simulation time 3536584285 ps
CPU time 16.38 seconds
Started Jul 03 07:20:01 PM PDT 24
Finished Jul 03 07:20:21 PM PDT 24
Peak memory 200364 kb
Host smart-c3fa2d32-9ad5-4bed-a4e7-f68713853693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160732037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3160732037
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3714643470
Short name T66
Test name
Test status
Simulation time 16070968 ps
CPU time 0.59 seconds
Started Jul 03 07:20:00 PM PDT 24
Finished Jul 03 07:20:04 PM PDT 24
Peak memory 195856 kb
Host smart-ffddaca3-0012-43ac-934d-18099db72195
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714643470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3714643470
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3899511002
Short name T167
Test name
Test status
Simulation time 59641593 ps
CPU time 2.68 seconds
Started Jul 03 07:20:05 PM PDT 24
Finished Jul 03 07:20:12 PM PDT 24
Peak memory 200264 kb
Host smart-2b93f363-6060-4638-ba6e-150a6da669ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3899511002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3899511002
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2770954280
Short name T75
Test name
Test status
Simulation time 3104998895 ps
CPU time 14.06 seconds
Started Jul 03 07:19:59 PM PDT 24
Finished Jul 03 07:20:17 PM PDT 24
Peak memory 200428 kb
Host smart-e39a72bb-d0d7-4858-a7fe-eca53d5989b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770954280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2770954280
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.522905816
Short name T448
Test name
Test status
Simulation time 51389645 ps
CPU time 1.59 seconds
Started Jul 03 07:20:03 PM PDT 24
Finished Jul 03 07:20:07 PM PDT 24
Peak memory 215956 kb
Host smart-51ba1b9a-1c54-4415-9740-77edffacd239
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=522905816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.522905816
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.4009508973
Short name T96
Test name
Test status
Simulation time 11713465432 ps
CPU time 174.42 seconds
Started Jul 03 07:20:01 PM PDT 24
Finished Jul 03 07:22:59 PM PDT 24
Peak memory 200384 kb
Host smart-686aecab-170e-4d61-9799-84d1dc3f2582
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009508973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.4009508973
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3167966328
Short name T340
Test name
Test status
Simulation time 13372700478 ps
CPU time 47.62 seconds
Started Jul 03 07:19:59 PM PDT 24
Finished Jul 03 07:20:50 PM PDT 24
Peak memory 200372 kb
Host smart-7488cf4f-c9f9-41b9-beb0-e50b5f4ed17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167966328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3167966328
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3158912592
Short name T247
Test name
Test status
Simulation time 721530424 ps
CPU time 9.49 seconds
Started Jul 03 07:19:59 PM PDT 24
Finished Jul 03 07:20:12 PM PDT 24
Peak memory 200428 kb
Host smart-85e16ab3-d0ce-468d-ab10-f8ef48592701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158912592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3158912592
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3276131292
Short name T105
Test name
Test status
Simulation time 94463152964 ps
CPU time 1210.97 seconds
Started Jul 03 07:20:03 PM PDT 24
Finished Jul 03 07:40:17 PM PDT 24
Peak memory 437640 kb
Host smart-e97d868c-b7f8-4fab-8e86-e5d97c3d5901
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276131292 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3276131292
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.790708746
Short name T162
Test name
Test status
Simulation time 8815578680 ps
CPU time 34.25 seconds
Started Jul 03 07:20:00 PM PDT 24
Finished Jul 03 07:20:38 PM PDT 24
Peak memory 200396 kb
Host smart-b41c4a7f-9ac0-44e8-9064-a0b4b9b9e0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790708746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.790708746
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3436550258
Short name T482
Test name
Test status
Simulation time 18607417 ps
CPU time 0.59 seconds
Started Jul 03 07:20:05 PM PDT 24
Finished Jul 03 07:20:09 PM PDT 24
Peak memory 195256 kb
Host smart-ed055655-eace-4cf1-8114-1d0951c1b61f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436550258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3436550258
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1811575980
Short name T73
Test name
Test status
Simulation time 5355125392 ps
CPU time 74.69 seconds
Started Jul 03 07:19:59 PM PDT 24
Finished Jul 03 07:21:17 PM PDT 24
Peak memory 200428 kb
Host smart-3b39aa1c-0cc2-4ab3-863f-e494adfe1c8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1811575980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1811575980
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1985463523
Short name T275
Test name
Test status
Simulation time 4324147666 ps
CPU time 24.26 seconds
Started Jul 03 07:20:02 PM PDT 24
Finished Jul 03 07:20:29 PM PDT 24
Peak memory 200428 kb
Host smart-09e816ca-c7f8-4474-8720-ebcd6290cad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985463523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1985463523
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1232564756
Short name T216
Test name
Test status
Simulation time 4638803053 ps
CPU time 209.19 seconds
Started Jul 03 07:20:04 PM PDT 24
Finished Jul 03 07:23:36 PM PDT 24
Peak memory 629180 kb
Host smart-a6611696-6b98-44b7-8782-00ea944dfd3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1232564756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1232564756
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.434746058
Short name T303
Test name
Test status
Simulation time 26141649239 ps
CPU time 132.74 seconds
Started Jul 03 07:20:09 PM PDT 24
Finished Jul 03 07:22:25 PM PDT 24
Peak memory 200408 kb
Host smart-57d4cc51-d1ba-49e6-84d8-5e03595cf798
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434746058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.434746058
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2227388836
Short name T394
Test name
Test status
Simulation time 281763443 ps
CPU time 4.39 seconds
Started Jul 03 07:19:59 PM PDT 24
Finished Jul 03 07:20:07 PM PDT 24
Peak memory 200364 kb
Host smart-9527c791-6e8f-4441-9495-3583196efdf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227388836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2227388836
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3432442820
Short name T39
Test name
Test status
Simulation time 315920177 ps
CPU time 11.61 seconds
Started Jul 03 07:20:03 PM PDT 24
Finished Jul 03 07:20:18 PM PDT 24
Peak memory 200056 kb
Host smart-993c5953-5799-4b8e-bf08-9431bb4dc456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432442820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3432442820
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.4283734999
Short name T428
Test name
Test status
Simulation time 22608338439 ps
CPU time 91.31 seconds
Started Jul 03 07:20:05 PM PDT 24
Finished Jul 03 07:21:40 PM PDT 24
Peak memory 200392 kb
Host smart-eaeb65cb-4d68-4c49-851f-6feb4b2dd1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283734999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.4283734999
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1934430080
Short name T415
Test name
Test status
Simulation time 37092988 ps
CPU time 0.58 seconds
Started Jul 03 07:20:05 PM PDT 24
Finished Jul 03 07:20:09 PM PDT 24
Peak memory 195816 kb
Host smart-0703ddb3-4856-40de-bf13-2a24539f4326
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934430080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1934430080
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3863741142
Short name T494
Test name
Test status
Simulation time 796135353 ps
CPU time 45.87 seconds
Started Jul 03 07:20:06 PM PDT 24
Finished Jul 03 07:20:56 PM PDT 24
Peak memory 200340 kb
Host smart-e1f30a02-1811-492e-9c8a-66dab8735c1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3863741142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3863741142
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.123593964
Short name T452
Test name
Test status
Simulation time 960709058 ps
CPU time 6.97 seconds
Started Jul 03 07:20:06 PM PDT 24
Finished Jul 03 07:20:17 PM PDT 24
Peak memory 200220 kb
Host smart-e624f167-2980-46b8-83a1-c4ff7dda6f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123593964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.123593964
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2056328924
Short name T89
Test name
Test status
Simulation time 1024934243 ps
CPU time 24.04 seconds
Started Jul 03 07:20:04 PM PDT 24
Finished Jul 03 07:20:32 PM PDT 24
Peak memory 227744 kb
Host smart-2e50b17a-136f-4198-97ce-ffc06e745a9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2056328924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2056328924
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3238372282
Short name T166
Test name
Test status
Simulation time 25912018682 ps
CPU time 172.45 seconds
Started Jul 03 07:20:04 PM PDT 24
Finished Jul 03 07:23:00 PM PDT 24
Peak memory 200376 kb
Host smart-fc7d0059-e7df-4eb1-87b8-22cee7bf104f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238372282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3238372282
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.4211943216
Short name T211
Test name
Test status
Simulation time 9592228372 ps
CPU time 173.98 seconds
Started Jul 03 07:20:07 PM PDT 24
Finished Jul 03 07:23:04 PM PDT 24
Peak memory 200436 kb
Host smart-7aa5e640-bc7d-456b-a750-b9b581d64155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211943216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.4211943216
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2986242152
Short name T163
Test name
Test status
Simulation time 114402837 ps
CPU time 5.93 seconds
Started Jul 03 07:20:08 PM PDT 24
Finished Jul 03 07:20:18 PM PDT 24
Peak memory 200400 kb
Host smart-7243a07d-dbd0-4a3f-8a8f-e87a11f20a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986242152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2986242152
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.741910825
Short name T11
Test name
Test status
Simulation time 25911264262 ps
CPU time 3567.23 seconds
Started Jul 03 07:20:11 PM PDT 24
Finished Jul 03 08:19:43 PM PDT 24
Peak memory 768540 kb
Host smart-6fb2a8ef-ddb1-4881-9183-556289090b6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741910825 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.741910825
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.725382188
Short name T460
Test name
Test status
Simulation time 5158751423 ps
CPU time 45.67 seconds
Started Jul 03 07:20:04 PM PDT 24
Finished Jul 03 07:20:53 PM PDT 24
Peak memory 200412 kb
Host smart-d51eaa54-c118-4e53-93ba-5919565ca8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725382188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.725382188
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2438263637
Short name T422
Test name
Test status
Simulation time 47078478 ps
CPU time 0.57 seconds
Started Jul 03 07:19:47 PM PDT 24
Finished Jul 03 07:19:51 PM PDT 24
Peak memory 195852 kb
Host smart-72a36932-9d57-4b6b-b65c-b21ba13fb219
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438263637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2438263637
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.98506721
Short name T395
Test name
Test status
Simulation time 12236996003 ps
CPU time 50.71 seconds
Started Jul 03 07:19:35 PM PDT 24
Finished Jul 03 07:20:29 PM PDT 24
Peak memory 200480 kb
Host smart-a14eca28-72a8-424b-b99b-bfd2431ace24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=98506721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.98506721
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2295208892
Short name T283
Test name
Test status
Simulation time 1417544869 ps
CPU time 40.46 seconds
Started Jul 03 07:19:33 PM PDT 24
Finished Jul 03 07:20:17 PM PDT 24
Peak memory 200348 kb
Host smart-0d34fa01-a2c2-4048-a27a-83a85cffa118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295208892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2295208892
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.827475571
Short name T205
Test name
Test status
Simulation time 18248936107 ps
CPU time 952.96 seconds
Started Jul 03 07:19:36 PM PDT 24
Finished Jul 03 07:35:32 PM PDT 24
Peak memory 719488 kb
Host smart-f62527b1-ea4c-4df3-98cb-5a571f408f51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=827475571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.827475571
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3118580114
Short name T209
Test name
Test status
Simulation time 4019017857 ps
CPU time 217.93 seconds
Started Jul 03 07:19:34 PM PDT 24
Finished Jul 03 07:23:15 PM PDT 24
Peak memory 200408 kb
Host smart-a909fc9c-84f9-4d76-adca-03f449d7c155
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118580114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3118580114
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.1737775964
Short name T256
Test name
Test status
Simulation time 101895185103 ps
CPU time 115.55 seconds
Started Jul 03 07:19:33 PM PDT 24
Finished Jul 03 07:21:33 PM PDT 24
Peak memory 208600 kb
Host smart-f484f728-9882-4a94-aa0d-2b30909207aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737775964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1737775964
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.627825885
Short name T71
Test name
Test status
Simulation time 159491613 ps
CPU time 1.02 seconds
Started Jul 03 07:19:36 PM PDT 24
Finished Jul 03 07:19:40 PM PDT 24
Peak memory 219516 kb
Host smart-da5a9f3e-9faa-4a8a-8ac1-9afa0b73be74
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627825885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.627825885
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3669112241
Short name T461
Test name
Test status
Simulation time 643362328 ps
CPU time 8.16 seconds
Started Jul 03 07:19:35 PM PDT 24
Finished Jul 03 07:19:46 PM PDT 24
Peak memory 200332 kb
Host smart-aa0ac9b1-4323-4f90-91bf-0fd607c71387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669112241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3669112241
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3521752783
Short name T188
Test name
Test status
Simulation time 63287491376 ps
CPU time 562.35 seconds
Started Jul 03 07:19:39 PM PDT 24
Finished Jul 03 07:29:05 PM PDT 24
Peak memory 200540 kb
Host smart-d11c8712-c15f-4bd0-9a86-03bad930f46f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521752783 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3521752783
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.3930583959
Short name T84
Test name
Test status
Simulation time 50914576500 ps
CPU time 3528.65 seconds
Started Jul 03 07:19:38 PM PDT 24
Finished Jul 03 08:18:30 PM PDT 24
Peak memory 787272 kb
Host smart-18d4a18a-b643-4a92-afa0-21e45239411a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3930583959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.3930583959
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.1802968880
Short name T421
Test name
Test status
Simulation time 27635419988 ps
CPU time 77.15 seconds
Started Jul 03 07:19:40 PM PDT 24
Finished Jul 03 07:21:00 PM PDT 24
Peak memory 200396 kb
Host smart-7f80cb33-2cb0-4112-8d25-3766bae0117c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1802968880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.1802968880
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.1902487796
Short name T196
Test name
Test status
Simulation time 24854970462 ps
CPU time 89.38 seconds
Started Jul 03 07:19:33 PM PDT 24
Finished Jul 03 07:21:07 PM PDT 24
Peak memory 200440 kb
Host smart-592d746e-25cb-4744-8b06-5642715f4437
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1902487796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.1902487796
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.3399197631
Short name T338
Test name
Test status
Simulation time 4840009310 ps
CPU time 75.26 seconds
Started Jul 03 07:19:39 PM PDT 24
Finished Jul 03 07:20:58 PM PDT 24
Peak memory 200396 kb
Host smart-25a7b96b-d2f1-494e-9714-200dd62aaff5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3399197631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.3399197631
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.3975207893
Short name T502
Test name
Test status
Simulation time 333064885929 ps
CPU time 616.3 seconds
Started Jul 03 07:19:32 PM PDT 24
Finished Jul 03 07:29:53 PM PDT 24
Peak memory 200432 kb
Host smart-0a7134aa-6151-4d09-af02-38c3d0f94172
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3975207893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3975207893
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.2933503518
Short name T372
Test name
Test status
Simulation time 560095014540 ps
CPU time 2389.12 seconds
Started Jul 03 07:19:35 PM PDT 24
Finished Jul 03 07:59:29 PM PDT 24
Peak memory 216600 kb
Host smart-8c0c5c4d-f849-4fdc-adad-1e1c0cb1a125
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2933503518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.2933503518
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.4258068275
Short name T236
Test name
Test status
Simulation time 137592690408 ps
CPU time 2614.96 seconds
Started Jul 03 07:19:45 PM PDT 24
Finished Jul 03 08:03:24 PM PDT 24
Peak memory 215964 kb
Host smart-b864deb9-8b09-45f2-b496-50c0e2967887
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4258068275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.4258068275
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2141544601
Short name T509
Test name
Test status
Simulation time 3616162766 ps
CPU time 43.96 seconds
Started Jul 03 07:19:33 PM PDT 24
Finished Jul 03 07:20:20 PM PDT 24
Peak memory 200528 kb
Host smart-6d8d12d0-b75e-41c2-94f5-e3dc13274e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141544601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2141544601
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1513232577
Short name T480
Test name
Test status
Simulation time 13790672 ps
CPU time 0.59 seconds
Started Jul 03 07:20:09 PM PDT 24
Finished Jul 03 07:20:13 PM PDT 24
Peak memory 196876 kb
Host smart-70f552a2-5035-4bb3-b741-7f149c6430e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513232577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1513232577
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.4260975652
Short name T383
Test name
Test status
Simulation time 142764360 ps
CPU time 7.64 seconds
Started Jul 03 07:20:04 PM PDT 24
Finished Jul 03 07:20:14 PM PDT 24
Peak memory 200384 kb
Host smart-bf1e099d-f6b7-40c2-98a0-311b88aa125e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4260975652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.4260975652
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3686630690
Short name T290
Test name
Test status
Simulation time 3467866228 ps
CPU time 63.51 seconds
Started Jul 03 07:20:04 PM PDT 24
Finished Jul 03 07:21:11 PM PDT 24
Peak memory 208588 kb
Host smart-0018003d-a366-44a5-bc65-39e9faddb5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686630690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3686630690
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1003096261
Short name T234
Test name
Test status
Simulation time 10954330708 ps
CPU time 543.46 seconds
Started Jul 03 07:20:12 PM PDT 24
Finished Jul 03 07:29:20 PM PDT 24
Peak memory 714500 kb
Host smart-854ee45c-a81b-4f2a-9b5c-0702d555c266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1003096261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1003096261
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3576877724
Short name T244
Test name
Test status
Simulation time 3490431378 ps
CPU time 59.97 seconds
Started Jul 03 07:20:10 PM PDT 24
Finished Jul 03 07:21:14 PM PDT 24
Peak memory 200308 kb
Host smart-322f6e04-b747-47c9-a346-b79391a32cb2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576877724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3576877724
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2998685457
Short name T296
Test name
Test status
Simulation time 59789925868 ps
CPU time 190.88 seconds
Started Jul 03 07:20:06 PM PDT 24
Finished Jul 03 07:23:21 PM PDT 24
Peak memory 200664 kb
Host smart-4082125e-1b8d-4051-a8ec-8c52e05ea1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998685457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2998685457
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3141088978
Short name T487
Test name
Test status
Simulation time 467920691 ps
CPU time 3.43 seconds
Started Jul 03 07:20:06 PM PDT 24
Finished Jul 03 07:20:13 PM PDT 24
Peak memory 200340 kb
Host smart-778f572e-c82a-462c-8c70-441ef83a4526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141088978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3141088978
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.4052247673
Short name T320
Test name
Test status
Simulation time 27824326422 ps
CPU time 40.64 seconds
Started Jul 03 07:20:04 PM PDT 24
Finished Jul 03 07:20:48 PM PDT 24
Peak memory 208652 kb
Host smart-783d13f3-c4cb-494b-9793-2cfcc4bfa4e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052247673 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.4052247673
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3856767442
Short name T522
Test name
Test status
Simulation time 3956479442 ps
CPU time 51.52 seconds
Started Jul 03 07:20:10 PM PDT 24
Finished Jul 03 07:21:06 PM PDT 24
Peak memory 200428 kb
Host smart-0da5e7a0-5e4f-4618-b922-da7147506cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856767442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3856767442
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.3678200431
Short name T173
Test name
Test status
Simulation time 15257905 ps
CPU time 0.62 seconds
Started Jul 03 07:20:07 PM PDT 24
Finished Jul 03 07:20:11 PM PDT 24
Peak memory 196084 kb
Host smart-cfe236f4-ae6a-474f-9031-ca5e0edcd100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678200431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.3678200431
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.556403957
Short name T368
Test name
Test status
Simulation time 2178718244 ps
CPU time 126.17 seconds
Started Jul 03 07:20:05 PM PDT 24
Finished Jul 03 07:22:15 PM PDT 24
Peak memory 200464 kb
Host smart-faeb608c-3eff-434b-b5cf-2ba36aaa69e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=556403957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.556403957
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3614798170
Short name T471
Test name
Test status
Simulation time 3444647576 ps
CPU time 50.88 seconds
Started Jul 03 07:20:08 PM PDT 24
Finished Jul 03 07:21:02 PM PDT 24
Peak memory 200388 kb
Host smart-7b4bcb91-eca5-468f-ab40-d2057d998b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614798170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3614798170
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.954327913
Short name T427
Test name
Test status
Simulation time 9766221105 ps
CPU time 445.19 seconds
Started Jul 03 07:20:05 PM PDT 24
Finished Jul 03 07:27:34 PM PDT 24
Peak memory 691728 kb
Host smart-6c175e9b-16ed-4186-ad68-7b1e7e27233c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=954327913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.954327913
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1472004942
Short name T63
Test name
Test status
Simulation time 10686967629 ps
CPU time 143.04 seconds
Started Jul 03 07:20:09 PM PDT 24
Finished Jul 03 07:22:36 PM PDT 24
Peak memory 200392 kb
Host smart-aaf797c9-101d-4652-83b4-e2f9db3419ad
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472004942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1472004942
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1935766421
Short name T198
Test name
Test status
Simulation time 2442117294 ps
CPU time 141.26 seconds
Started Jul 03 07:20:09 PM PDT 24
Finished Jul 03 07:22:34 PM PDT 24
Peak memory 200384 kb
Host smart-4089f955-a2ee-4cff-b76d-9328893981d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935766421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1935766421
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1353660592
Short name T16
Test name
Test status
Simulation time 1642712265 ps
CPU time 7.29 seconds
Started Jul 03 07:20:03 PM PDT 24
Finished Jul 03 07:20:13 PM PDT 24
Peak memory 200404 kb
Host smart-0bfcb449-f81e-4633-89e4-9f15f76fb700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353660592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1353660592
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2238111352
Short name T438
Test name
Test status
Simulation time 5313586123 ps
CPU time 543.78 seconds
Started Jul 03 07:20:05 PM PDT 24
Finished Jul 03 07:29:13 PM PDT 24
Peak memory 671256 kb
Host smart-ef2313bf-e462-4fae-ae79-a2886cc8f675
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238111352 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2238111352
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.712082791
Short name T270
Test name
Test status
Simulation time 7622544366 ps
CPU time 130.38 seconds
Started Jul 03 07:20:07 PM PDT 24
Finished Jul 03 07:22:21 PM PDT 24
Peak memory 200448 kb
Host smart-fb3e3ecc-bd83-4fb0-8ec1-1c9872108735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712082791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.712082791
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3507778596
Short name T363
Test name
Test status
Simulation time 13799671 ps
CPU time 0.62 seconds
Started Jul 03 07:20:12 PM PDT 24
Finished Jul 03 07:20:16 PM PDT 24
Peak memory 196216 kb
Host smart-8731f9b4-426f-412d-bbbc-e8d62bad38e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507778596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3507778596
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1643835145
Short name T30
Test name
Test status
Simulation time 1095237074 ps
CPU time 62.28 seconds
Started Jul 03 07:20:09 PM PDT 24
Finished Jul 03 07:21:15 PM PDT 24
Peak memory 200400 kb
Host smart-354493a5-b6d0-40d2-9e89-1d1aab7da057
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1643835145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1643835145
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.3641199006
Short name T171
Test name
Test status
Simulation time 798672340 ps
CPU time 5.74 seconds
Started Jul 03 07:20:06 PM PDT 24
Finished Jul 03 07:20:15 PM PDT 24
Peak memory 200388 kb
Host smart-6877da36-c688-4131-b911-975f8be4f7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641199006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3641199006
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.198412286
Short name T492
Test name
Test status
Simulation time 2731745570 ps
CPU time 86.39 seconds
Started Jul 03 07:20:07 PM PDT 24
Finished Jul 03 07:21:37 PM PDT 24
Peak memory 455244 kb
Host smart-f7881955-e6af-49e3-b7a4-e1aa6d780639
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=198412286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.198412286
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3386107535
Short name T465
Test name
Test status
Simulation time 2259664753 ps
CPU time 88.07 seconds
Started Jul 03 07:20:07 PM PDT 24
Finished Jul 03 07:21:39 PM PDT 24
Peak memory 200412 kb
Host smart-a61788eb-3771-4650-bb9a-bbaa2349aa9b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386107535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3386107535
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.4030900047
Short name T450
Test name
Test status
Simulation time 286820510 ps
CPU time 3.65 seconds
Started Jul 03 07:20:05 PM PDT 24
Finished Jul 03 07:20:13 PM PDT 24
Peak memory 200328 kb
Host smart-812af42e-3ef2-44ba-b03b-38c9595ed337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030900047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.4030900047
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3511381736
Short name T483
Test name
Test status
Simulation time 1233378356 ps
CPU time 16.85 seconds
Started Jul 03 07:20:08 PM PDT 24
Finished Jul 03 07:20:29 PM PDT 24
Peak memory 200424 kb
Host smart-754cdba2-eaaa-4574-b5d2-c68b52e64e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511381736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3511381736
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2304380798
Short name T327
Test name
Test status
Simulation time 165381722161 ps
CPU time 1290.66 seconds
Started Jul 03 07:20:09 PM PDT 24
Finished Jul 03 07:41:44 PM PDT 24
Peak memory 750880 kb
Host smart-ea4df4ef-d842-4370-8c6d-be0071319229
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304380798 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2304380798
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.4244260177
Short name T287
Test name
Test status
Simulation time 6749281949 ps
CPU time 116.94 seconds
Started Jul 03 07:20:09 PM PDT 24
Finished Jul 03 07:22:10 PM PDT 24
Peak memory 200448 kb
Host smart-c2a39422-4f00-4abb-9d5d-186f3be1d3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244260177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.4244260177
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1374789345
Short name T257
Test name
Test status
Simulation time 43902212 ps
CPU time 0.61 seconds
Started Jul 03 07:20:11 PM PDT 24
Finished Jul 03 07:20:16 PM PDT 24
Peak memory 195136 kb
Host smart-9535d227-e53b-4ebc-b68b-41f212051190
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374789345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1374789345
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1192805057
Short name T278
Test name
Test status
Simulation time 1642900527 ps
CPU time 96.32 seconds
Started Jul 03 07:20:09 PM PDT 24
Finished Jul 03 07:21:49 PM PDT 24
Peak memory 200340 kb
Host smart-53b9b309-62e1-450c-ac3c-7e9acc994c03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1192805057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1192805057
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2365894416
Short name T134
Test name
Test status
Simulation time 3020038331 ps
CPU time 49.24 seconds
Started Jul 03 07:20:08 PM PDT 24
Finished Jul 03 07:21:01 PM PDT 24
Peak memory 200444 kb
Host smart-a609ea60-6aa7-4372-af49-5455f0c1c3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365894416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2365894416
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.578147343
Short name T194
Test name
Test status
Simulation time 6649034294 ps
CPU time 275.9 seconds
Started Jul 03 07:20:10 PM PDT 24
Finished Jul 03 07:24:50 PM PDT 24
Peak memory 596912 kb
Host smart-db886722-27bc-47fb-a29c-f5b573411b60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=578147343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.578147343
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3617890115
Short name T32
Test name
Test status
Simulation time 53378791382 ps
CPU time 141.64 seconds
Started Jul 03 07:20:18 PM PDT 24
Finished Jul 03 07:22:41 PM PDT 24
Peak memory 200448 kb
Host smart-b5af5614-fc95-4aee-81af-6badead68ad7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617890115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3617890115
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2517715161
Short name T255
Test name
Test status
Simulation time 2170148630 ps
CPU time 118.14 seconds
Started Jul 03 07:20:10 PM PDT 24
Finished Jul 03 07:22:12 PM PDT 24
Peak memory 200456 kb
Host smart-082e7711-ddb8-44c4-b6e1-3ea157f719a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517715161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2517715161
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1113007956
Short name T443
Test name
Test status
Simulation time 108346750 ps
CPU time 1.82 seconds
Started Jul 03 07:20:08 PM PDT 24
Finished Jul 03 07:20:14 PM PDT 24
Peak memory 200412 kb
Host smart-4ab9160a-7540-41b3-9535-b44132ac8cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113007956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1113007956
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.2222440753
Short name T518
Test name
Test status
Simulation time 57140577935 ps
CPU time 816.43 seconds
Started Jul 03 07:20:13 PM PDT 24
Finished Jul 03 07:33:53 PM PDT 24
Peak memory 233184 kb
Host smart-92257c18-6388-4ea6-ac33-6ad2102947bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222440753 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2222440753
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3923440849
Short name T109
Test name
Test status
Simulation time 49049488823 ps
CPU time 164.6 seconds
Started Jul 03 07:20:14 PM PDT 24
Finished Jul 03 07:23:02 PM PDT 24
Peak memory 200416 kb
Host smart-2528ecc1-b031-418d-80bc-78965ffc05cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923440849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3923440849
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.1689695626
Short name T65
Test name
Test status
Simulation time 13671868 ps
CPU time 0.61 seconds
Started Jul 03 07:20:10 PM PDT 24
Finished Jul 03 07:20:15 PM PDT 24
Peak memory 196188 kb
Host smart-e09cc497-8b21-4cda-bc3a-e996f0adee0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689695626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1689695626
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.677225284
Short name T454
Test name
Test status
Simulation time 190034124 ps
CPU time 11.85 seconds
Started Jul 03 07:20:14 PM PDT 24
Finished Jul 03 07:20:29 PM PDT 24
Peak memory 200280 kb
Host smart-a0506ce8-65b2-41ab-9426-245bf0c16084
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=677225284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.677225284
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1350048321
Short name T174
Test name
Test status
Simulation time 622360622 ps
CPU time 8.91 seconds
Started Jul 03 07:20:11 PM PDT 24
Finished Jul 03 07:20:24 PM PDT 24
Peak memory 200408 kb
Host smart-f8cb6958-d57a-4fa1-9996-f307cf63c6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350048321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1350048321
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3994366729
Short name T485
Test name
Test status
Simulation time 3187478510 ps
CPU time 515.32 seconds
Started Jul 03 07:20:11 PM PDT 24
Finished Jul 03 07:28:51 PM PDT 24
Peak memory 657988 kb
Host smart-522e4b11-b294-4757-9018-78f86150a914
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3994366729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3994366729
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2093752332
Short name T519
Test name
Test status
Simulation time 8782873784 ps
CPU time 144.36 seconds
Started Jul 03 07:20:08 PM PDT 24
Finished Jul 03 07:22:36 PM PDT 24
Peak memory 200648 kb
Host smart-82d2740c-1537-4f08-bc3d-1806a996e25a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093752332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2093752332
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.4252447472
Short name T325
Test name
Test status
Simulation time 136464587667 ps
CPU time 198.97 seconds
Started Jul 03 07:20:14 PM PDT 24
Finished Jul 03 07:23:36 PM PDT 24
Peak memory 200448 kb
Host smart-b7f7f86f-da68-4134-afa7-0c9986301781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252447472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.4252447472
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2795225448
Short name T223
Test name
Test status
Simulation time 470207913 ps
CPU time 11.31 seconds
Started Jul 03 07:20:12 PM PDT 24
Finished Jul 03 07:20:27 PM PDT 24
Peak memory 200440 kb
Host smart-7bcd0d9b-5868-439a-94bf-37f98c8d663e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795225448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2795225448
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2994427757
Short name T93
Test name
Test status
Simulation time 123379607695 ps
CPU time 3765.71 seconds
Started Jul 03 07:20:10 PM PDT 24
Finished Jul 03 08:23:00 PM PDT 24
Peak memory 821532 kb
Host smart-ed857f85-db1c-40e8-91d9-ea03922ddd5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994427757 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2994427757
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2565539760
Short name T76
Test name
Test status
Simulation time 4697911087 ps
CPU time 59.3 seconds
Started Jul 03 07:20:10 PM PDT 24
Finished Jul 03 07:21:13 PM PDT 24
Peak memory 200404 kb
Host smart-5cdce3ac-de12-4ba0-9091-5a082ccdbc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565539760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2565539760
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2330851815
Short name T495
Test name
Test status
Simulation time 111240094 ps
CPU time 0.59 seconds
Started Jul 03 07:20:10 PM PDT 24
Finished Jul 03 07:20:14 PM PDT 24
Peak memory 196192 kb
Host smart-20d6f08b-a161-4755-9aa6-2bb8aca1b690
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330851815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2330851815
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.4190377176
Short name T403
Test name
Test status
Simulation time 1620420807 ps
CPU time 10.36 seconds
Started Jul 03 07:20:08 PM PDT 24
Finished Jul 03 07:20:22 PM PDT 24
Peak memory 200292 kb
Host smart-1ddfc8e0-0e3b-4e41-a30c-3c96ebe179c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4190377176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.4190377176
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.66638190
Short name T220
Test name
Test status
Simulation time 9322891985 ps
CPU time 40.67 seconds
Started Jul 03 07:20:10 PM PDT 24
Finished Jul 03 07:20:54 PM PDT 24
Peak memory 200404 kb
Host smart-8340e245-6f2d-49f2-8a6a-116408be58b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66638190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.66638190
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.313749758
Short name T392
Test name
Test status
Simulation time 1677218746 ps
CPU time 81.18 seconds
Started Jul 03 07:20:17 PM PDT 24
Finished Jul 03 07:21:40 PM PDT 24
Peak memory 446976 kb
Host smart-82fb74d4-f3b7-429b-8fd6-5466f2ec5f8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=313749758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.313749758
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.398439551
Short name T326
Test name
Test status
Simulation time 5316587908 ps
CPU time 91.87 seconds
Started Jul 03 07:20:10 PM PDT 24
Finished Jul 03 07:21:46 PM PDT 24
Peak memory 200444 kb
Host smart-835dedd4-8687-4a10-ba74-547622730516
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398439551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.398439551
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1873473577
Short name T334
Test name
Test status
Simulation time 4743206910 ps
CPU time 70.57 seconds
Started Jul 03 07:20:13 PM PDT 24
Finished Jul 03 07:21:27 PM PDT 24
Peak memory 200408 kb
Host smart-bb2aa2a9-6174-4008-964f-c183bdc25cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873473577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1873473577
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1350643605
Short name T413
Test name
Test status
Simulation time 296800403 ps
CPU time 13.58 seconds
Started Jul 03 07:20:11 PM PDT 24
Finished Jul 03 07:20:28 PM PDT 24
Peak memory 200372 kb
Host smart-f8cff5c4-cb4a-4055-a50f-90a0400c1b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350643605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1350643605
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2225099859
Short name T315
Test name
Test status
Simulation time 90945597304 ps
CPU time 1698.07 seconds
Started Jul 03 07:20:12 PM PDT 24
Finished Jul 03 07:48:34 PM PDT 24
Peak memory 689488 kb
Host smart-0b39e225-2224-46c8-bc28-9c438569b765
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225099859 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2225099859
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2136331215
Short name T374
Test name
Test status
Simulation time 1074545613 ps
CPU time 57.67 seconds
Started Jul 03 07:20:18 PM PDT 24
Finished Jul 03 07:21:17 PM PDT 24
Peak memory 200380 kb
Host smart-62012895-c75e-43ab-afb6-fda2145d23e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136331215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2136331215
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.936838696
Short name T206
Test name
Test status
Simulation time 15939645 ps
CPU time 0.58 seconds
Started Jul 03 07:20:10 PM PDT 24
Finished Jul 03 07:20:15 PM PDT 24
Peak memory 196224 kb
Host smart-e9ca4fcc-9961-42a7-8f69-d3e32d5c29d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936838696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.936838696
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.819415614
Short name T276
Test name
Test status
Simulation time 12971644379 ps
CPU time 86.94 seconds
Started Jul 03 07:20:11 PM PDT 24
Finished Jul 03 07:21:42 PM PDT 24
Peak memory 200672 kb
Host smart-7f016565-4769-46dd-a3df-43867fa3cb50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=819415614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.819415614
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.4218795065
Short name T343
Test name
Test status
Simulation time 2703630389 ps
CPU time 6.46 seconds
Started Jul 03 07:20:11 PM PDT 24
Finished Jul 03 07:20:22 PM PDT 24
Peak memory 200476 kb
Host smart-56675206-eba9-4bfa-b764-bb5d32336aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218795065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.4218795065
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3710345030
Short name T59
Test name
Test status
Simulation time 14351011005 ps
CPU time 735.22 seconds
Started Jul 03 07:20:12 PM PDT 24
Finished Jul 03 07:32:32 PM PDT 24
Peak memory 687756 kb
Host smart-25bb1d38-608a-4e26-8761-5d9d2aeda094
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3710345030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3710345030
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.360588630
Short name T88
Test name
Test status
Simulation time 10564657512 ps
CPU time 131.14 seconds
Started Jul 03 07:20:10 PM PDT 24
Finished Jul 03 07:22:26 PM PDT 24
Peak memory 200280 kb
Host smart-36a9cb5d-1799-4f9a-ad2a-5a6b1cd6dc54
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360588630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.360588630
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.767430900
Short name T35
Test name
Test status
Simulation time 516609570 ps
CPU time 30.06 seconds
Started Jul 03 07:20:18 PM PDT 24
Finished Jul 03 07:20:50 PM PDT 24
Peak memory 200380 kb
Host smart-99b750dd-b00f-40cd-bf10-5212c17fa8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767430900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.767430900
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2947182853
Short name T426
Test name
Test status
Simulation time 2081696594 ps
CPU time 7.27 seconds
Started Jul 03 07:20:10 PM PDT 24
Finished Jul 03 07:20:21 PM PDT 24
Peak memory 200368 kb
Host smart-81d5449a-bed4-4ab2-8778-42bdbc39c5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947182853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2947182853
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.1743679668
Short name T46
Test name
Test status
Simulation time 140557484655 ps
CPU time 368.73 seconds
Started Jul 03 07:20:12 PM PDT 24
Finished Jul 03 07:26:25 PM PDT 24
Peak memory 216856 kb
Host smart-dc4cce54-c962-47c5-a647-6961f23e7a1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743679668 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.1743679668
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3170864720
Short name T106
Test name
Test status
Simulation time 10216259662 ps
CPU time 112.21 seconds
Started Jul 03 07:20:10 PM PDT 24
Finished Jul 03 07:22:06 PM PDT 24
Peak memory 200460 kb
Host smart-8ff84905-a82a-4534-bcbd-dede5c5c1395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170864720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3170864720
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.4169009026
Short name T388
Test name
Test status
Simulation time 50522250 ps
CPU time 0.6 seconds
Started Jul 03 07:20:16 PM PDT 24
Finished Jul 03 07:20:19 PM PDT 24
Peak memory 196184 kb
Host smart-9a9c7fb3-bf62-4cef-8ae0-4b4f70cc91cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169009026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.4169009026
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3737401429
Short name T484
Test name
Test status
Simulation time 1434125575 ps
CPU time 79.09 seconds
Started Jul 03 07:20:15 PM PDT 24
Finished Jul 03 07:21:37 PM PDT 24
Peak memory 200412 kb
Host smart-085433c5-01bf-4f28-81dd-6c5e4268c1ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3737401429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3737401429
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3809753760
Short name T42
Test name
Test status
Simulation time 22364988291 ps
CPU time 62.51 seconds
Started Jul 03 07:20:20 PM PDT 24
Finished Jul 03 07:21:23 PM PDT 24
Peak memory 200496 kb
Host smart-ec6c77ad-9fec-4c72-9264-efbf1e777a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809753760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3809753760
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3426815076
Short name T432
Test name
Test status
Simulation time 5209283373 ps
CPU time 978.57 seconds
Started Jul 03 07:20:15 PM PDT 24
Finished Jul 03 07:36:37 PM PDT 24
Peak memory 744416 kb
Host smart-145b0e1b-94a5-4205-a854-b203bd7860ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3426815076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3426815076
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3397790922
Short name T386
Test name
Test status
Simulation time 2122813175 ps
CPU time 110.42 seconds
Started Jul 03 07:20:15 PM PDT 24
Finished Jul 03 07:22:09 PM PDT 24
Peak memory 200356 kb
Host smart-749e33b3-3074-4c38-af75-44070f101546
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397790922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3397790922
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2918696627
Short name T74
Test name
Test status
Simulation time 569891520 ps
CPU time 31.53 seconds
Started Jul 03 07:20:14 PM PDT 24
Finished Jul 03 07:20:49 PM PDT 24
Peak memory 200456 kb
Host smart-4d360aeb-a04a-4e35-91c6-e7a97d5785e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918696627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2918696627
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.4243299178
Short name T513
Test name
Test status
Simulation time 1644754708 ps
CPU time 11.75 seconds
Started Jul 03 07:20:13 PM PDT 24
Finished Jul 03 07:20:29 PM PDT 24
Peak memory 200432 kb
Host smart-71cfa45a-2fa7-471b-9fe2-68d78d84a4ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243299178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.4243299178
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.1288107111
Short name T10
Test name
Test status
Simulation time 6855126279 ps
CPU time 443.3 seconds
Started Jul 03 07:20:17 PM PDT 24
Finished Jul 03 07:27:43 PM PDT 24
Peak memory 556232 kb
Host smart-56c7272e-fa9b-4ce1-bee8-09d9428e9832
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288107111 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1288107111
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.538566154
Short name T429
Test name
Test status
Simulation time 12881643023 ps
CPU time 134.81 seconds
Started Jul 03 07:20:16 PM PDT 24
Finished Jul 03 07:22:33 PM PDT 24
Peak memory 200552 kb
Host smart-f5b65d27-0421-4f0c-9790-282f4294a229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538566154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.538566154
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.4189337251
Short name T252
Test name
Test status
Simulation time 12799718 ps
CPU time 0.59 seconds
Started Jul 03 07:20:21 PM PDT 24
Finished Jul 03 07:20:23 PM PDT 24
Peak memory 195876 kb
Host smart-ac871f3a-1803-4b3d-8f7c-da2a7f7412bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189337251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.4189337251
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3812794640
Short name T58
Test name
Test status
Simulation time 2034168295 ps
CPU time 47 seconds
Started Jul 03 07:20:16 PM PDT 24
Finished Jul 03 07:21:05 PM PDT 24
Peak memory 200360 kb
Host smart-5552a2fa-eea2-4cfc-a661-90204e31e669
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3812794640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3812794640
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.458280681
Short name T523
Test name
Test status
Simulation time 4044050214 ps
CPU time 54.6 seconds
Started Jul 03 07:20:23 PM PDT 24
Finished Jul 03 07:21:19 PM PDT 24
Peak memory 200368 kb
Host smart-79a93b5a-2323-4519-bd30-fbf1961d5247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458280681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.458280681
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1027636898
Short name T393
Test name
Test status
Simulation time 2194330524 ps
CPU time 191.11 seconds
Started Jul 03 07:20:17 PM PDT 24
Finished Jul 03 07:23:30 PM PDT 24
Peak memory 619184 kb
Host smart-ce0fa8e3-3e74-4a92-a095-ac347c0b6605
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1027636898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1027636898
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.682831754
Short name T505
Test name
Test status
Simulation time 9170190071 ps
CPU time 55.21 seconds
Started Jul 03 07:20:20 PM PDT 24
Finished Jul 03 07:21:16 PM PDT 24
Peak memory 200420 kb
Host smart-620b52f9-38ce-401f-9347-af56407f1030
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682831754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.682831754
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.728410513
Short name T243
Test name
Test status
Simulation time 18095594176 ps
CPU time 77.66 seconds
Started Jul 03 07:20:16 PM PDT 24
Finished Jul 03 07:21:36 PM PDT 24
Peak memory 200444 kb
Host smart-efa03eac-f00b-45bb-8324-931fbfaf3a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728410513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.728410513
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.79740989
Short name T490
Test name
Test status
Simulation time 416925193 ps
CPU time 5.02 seconds
Started Jul 03 07:20:16 PM PDT 24
Finished Jul 03 07:20:23 PM PDT 24
Peak memory 200400 kb
Host smart-9a9c9c3c-ed66-4b37-bd3e-72b987c7f3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79740989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.79740989
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.874305493
Short name T94
Test name
Test status
Simulation time 450333673460 ps
CPU time 2482.52 seconds
Started Jul 03 07:20:20 PM PDT 24
Finished Jul 03 08:01:44 PM PDT 24
Peak memory 751580 kb
Host smart-fc297566-4976-483b-838f-04790783933b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874305493 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.874305493
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.263091591
Short name T497
Test name
Test status
Simulation time 598650126 ps
CPU time 33.12 seconds
Started Jul 03 07:20:22 PM PDT 24
Finished Jul 03 07:20:56 PM PDT 24
Peak memory 200336 kb
Host smart-861a217c-d627-4bc5-9ac6-0c1cb55e4c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263091591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.263091591
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1322083555
Short name T475
Test name
Test status
Simulation time 14638862 ps
CPU time 0.6 seconds
Started Jul 03 07:20:25 PM PDT 24
Finished Jul 03 07:20:27 PM PDT 24
Peak memory 196908 kb
Host smart-dd1edc61-23a7-46b6-b72b-e106ee2e08d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322083555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1322083555
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3297364180
Short name T293
Test name
Test status
Simulation time 1527510678 ps
CPU time 83.44 seconds
Started Jul 03 07:20:22 PM PDT 24
Finished Jul 03 07:21:47 PM PDT 24
Peak memory 200344 kb
Host smart-f0574522-a384-4174-8efd-3e8437973aea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3297364180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3297364180
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2883828514
Short name T227
Test name
Test status
Simulation time 24820836337 ps
CPU time 76.59 seconds
Started Jul 03 07:20:20 PM PDT 24
Finished Jul 03 07:21:38 PM PDT 24
Peak memory 200516 kb
Host smart-c114dcbc-ef82-42d5-a7c3-0a6dbbabcba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883828514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2883828514
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.332063093
Short name T506
Test name
Test status
Simulation time 4108846484 ps
CPU time 831.27 seconds
Started Jul 03 07:20:22 PM PDT 24
Finished Jul 03 07:34:15 PM PDT 24
Peak memory 720948 kb
Host smart-44f160d2-3079-4364-9f4f-6e55f4ed7d51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=332063093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.332063093
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1820615025
Short name T305
Test name
Test status
Simulation time 49705980423 ps
CPU time 193.24 seconds
Started Jul 03 07:20:22 PM PDT 24
Finished Jul 03 07:23:37 PM PDT 24
Peak memory 200412 kb
Host smart-b7b9c4ed-d78e-459c-a8ef-63648b7fa78d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820615025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1820615025
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1700836939
Short name T453
Test name
Test status
Simulation time 2280904972 ps
CPU time 37.52 seconds
Started Jul 03 07:20:21 PM PDT 24
Finished Jul 03 07:20:59 PM PDT 24
Peak memory 200432 kb
Host smart-b307e45d-fa26-4c35-b382-0cd56fb335e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700836939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1700836939
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2900718846
Short name T213
Test name
Test status
Simulation time 458949575 ps
CPU time 7.55 seconds
Started Jul 03 07:20:22 PM PDT 24
Finished Jul 03 07:20:31 PM PDT 24
Peak memory 200364 kb
Host smart-30f61df2-f92d-4fa2-8a3d-f6f2d741f7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900718846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2900718846
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2196105823
Short name T408
Test name
Test status
Simulation time 9407818000 ps
CPU time 1187.38 seconds
Started Jul 03 07:20:26 PM PDT 24
Finished Jul 03 07:40:15 PM PDT 24
Peak memory 777420 kb
Host smart-509e831a-1c37-4089-ad3e-696703f2cee2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196105823 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2196105823
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3908545657
Short name T215
Test name
Test status
Simulation time 19363237028 ps
CPU time 130.18 seconds
Started Jul 03 07:20:27 PM PDT 24
Finished Jul 03 07:22:38 PM PDT 24
Peak memory 200432 kb
Host smart-0be3b272-c1f0-451b-9c64-3413d534b5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908545657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3908545657
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.196299190
Short name T356
Test name
Test status
Simulation time 14351711 ps
CPU time 0.58 seconds
Started Jul 03 07:19:39 PM PDT 24
Finished Jul 03 07:19:43 PM PDT 24
Peak memory 195268 kb
Host smart-a0650c7d-3e8a-4e6f-a79d-6f66a399b034
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196299190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.196299190
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3382560959
Short name T528
Test name
Test status
Simulation time 6583616481 ps
CPU time 99.9 seconds
Started Jul 03 07:19:39 PM PDT 24
Finished Jul 03 07:21:22 PM PDT 24
Peak memory 200524 kb
Host smart-b42b8028-23ad-4d37-aa65-de7b6fc48f3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3382560959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3382560959
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.1809633131
Short name T435
Test name
Test status
Simulation time 3340743642 ps
CPU time 11.38 seconds
Started Jul 03 07:19:39 PM PDT 24
Finished Jul 03 07:19:53 PM PDT 24
Peak memory 200476 kb
Host smart-b73a474c-8522-4c47-8266-c2a0afa4bf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809633131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.1809633131
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.4272679928
Short name T527
Test name
Test status
Simulation time 590487323 ps
CPU time 92.29 seconds
Started Jul 03 07:19:41 PM PDT 24
Finished Jul 03 07:21:17 PM PDT 24
Peak memory 417748 kb
Host smart-27ae6499-6288-456b-9644-ce1f44cae305
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4272679928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.4272679928
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3729859771
Short name T182
Test name
Test status
Simulation time 7093340905 ps
CPU time 61.2 seconds
Started Jul 03 07:19:35 PM PDT 24
Finished Jul 03 07:20:40 PM PDT 24
Peak memory 200312 kb
Host smart-0aaf342a-5112-4317-896d-1d52292c0281
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729859771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3729859771
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.33212516
Short name T330
Test name
Test status
Simulation time 1186723974 ps
CPU time 8.17 seconds
Started Jul 03 07:19:39 PM PDT 24
Finished Jul 03 07:19:50 PM PDT 24
Peak memory 200356 kb
Host smart-7cf5e63e-51a7-4c7d-81cc-0bba1e2a8479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33212516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.33212516
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.25423907
Short name T68
Test name
Test status
Simulation time 74372051 ps
CPU time 0.88 seconds
Started Jul 03 07:19:42 PM PDT 24
Finished Jul 03 07:19:46 PM PDT 24
Peak memory 218332 kb
Host smart-ff8d26cf-7996-4c6f-83d8-bdec24fcd6f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25423907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.25423907
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3325174135
Short name T312
Test name
Test status
Simulation time 525522388 ps
CPU time 2.07 seconds
Started Jul 03 07:19:37 PM PDT 24
Finished Jul 03 07:19:42 PM PDT 24
Peak memory 200268 kb
Host smart-e37a204d-da44-4397-a34c-febf9fd6e417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325174135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3325174135
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.1497148667
Short name T8
Test name
Test status
Simulation time 19342748424 ps
CPU time 711.19 seconds
Started Jul 03 07:19:39 PM PDT 24
Finished Jul 03 07:31:33 PM PDT 24
Peak memory 541432 kb
Host smart-2f1a2548-29ee-4ce7-803e-492750844446
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1497148667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.1497148667
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.4130734327
Short name T40
Test name
Test status
Simulation time 2752776914 ps
CPU time 43.31 seconds
Started Jul 03 07:19:47 PM PDT 24
Finished Jul 03 07:20:33 PM PDT 24
Peak memory 200452 kb
Host smart-e0fc99c5-f628-4fea-bc9a-4a9ef15897df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4130734327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.4130734327
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.2046887728
Short name T229
Test name
Test status
Simulation time 27086167408 ps
CPU time 107.6 seconds
Started Jul 03 07:19:36 PM PDT 24
Finished Jul 03 07:21:27 PM PDT 24
Peak memory 200484 kb
Host smart-fe9800f1-72cf-42b2-b51a-6bf3d79221f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2046887728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.2046887728
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.2030849546
Short name T294
Test name
Test status
Simulation time 6967742484 ps
CPU time 88.45 seconds
Started Jul 03 07:19:37 PM PDT 24
Finished Jul 03 07:21:08 PM PDT 24
Peak memory 200420 kb
Host smart-5aae9ea9-0685-4884-b172-d20f5af8b820
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2030849546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.2030849546
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.3731204810
Short name T139
Test name
Test status
Simulation time 204762791322 ps
CPU time 651.57 seconds
Started Jul 03 07:19:41 PM PDT 24
Finished Jul 03 07:30:37 PM PDT 24
Peak memory 200444 kb
Host smart-eb413d95-1e69-4917-87cf-b6741ad5ba81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3731204810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.3731204810
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.2488603056
Short name T500
Test name
Test status
Simulation time 197275982054 ps
CPU time 2503.24 seconds
Started Jul 03 07:19:35 PM PDT 24
Finished Jul 03 08:01:22 PM PDT 24
Peak memory 215832 kb
Host smart-35fd43b4-9776-42ee-a43b-4b414105fd75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2488603056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.2488603056
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2436731996
Short name T344
Test name
Test status
Simulation time 152353464505 ps
CPU time 2470.79 seconds
Started Jul 03 07:19:47 PM PDT 24
Finished Jul 03 08:01:02 PM PDT 24
Peak memory 215972 kb
Host smart-a9456ee9-b6a5-40c2-b260-0f5dbbe3f7a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2436731996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2436731996
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3285670252
Short name T48
Test name
Test status
Simulation time 2330258171 ps
CPU time 57.41 seconds
Started Jul 03 07:19:40 PM PDT 24
Finished Jul 03 07:20:41 PM PDT 24
Peak memory 200428 kb
Host smart-dd789e34-a8af-45de-b7a6-cfdf8d20eb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285670252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3285670252
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1214372970
Short name T499
Test name
Test status
Simulation time 14256651 ps
CPU time 0.61 seconds
Started Jul 03 07:20:28 PM PDT 24
Finished Jul 03 07:20:29 PM PDT 24
Peak memory 196192 kb
Host smart-8515d962-2060-4afd-ac88-88e832ef00db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214372970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1214372970
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.4111550343
Short name T214
Test name
Test status
Simulation time 9931902257 ps
CPU time 92.27 seconds
Started Jul 03 07:20:29 PM PDT 24
Finished Jul 03 07:22:02 PM PDT 24
Peak memory 200412 kb
Host smart-ab5cb9bb-0e6d-4547-8a85-d970c15fdbdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4111550343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.4111550343
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1679129000
Short name T365
Test name
Test status
Simulation time 2058907729 ps
CPU time 38.88 seconds
Started Jul 03 07:20:26 PM PDT 24
Finished Jul 03 07:21:06 PM PDT 24
Peak memory 200376 kb
Host smart-f42a3828-ea75-41d9-af06-1fd155b5b3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679129000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1679129000
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3917657711
Short name T399
Test name
Test status
Simulation time 943613834 ps
CPU time 155.78 seconds
Started Jul 03 07:20:28 PM PDT 24
Finished Jul 03 07:23:05 PM PDT 24
Peak memory 437976 kb
Host smart-bd1463ab-0a77-450c-a6de-905578100245
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3917657711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3917657711
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.2295957004
Short name T306
Test name
Test status
Simulation time 23736552334 ps
CPU time 144.91 seconds
Started Jul 03 07:20:25 PM PDT 24
Finished Jul 03 07:22:52 PM PDT 24
Peak memory 200460 kb
Host smart-e0faca89-e72d-464f-bebc-3eb745003aa9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295957004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2295957004
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1467022981
Short name T382
Test name
Test status
Simulation time 20143952847 ps
CPU time 129.22 seconds
Started Jul 03 07:20:26 PM PDT 24
Finished Jul 03 07:22:36 PM PDT 24
Peak memory 200408 kb
Host smart-8aa209cf-a47a-4516-8c38-3d4459e4aa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467022981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1467022981
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3895555
Short name T183
Test name
Test status
Simulation time 3514166892 ps
CPU time 11.35 seconds
Started Jul 03 07:20:26 PM PDT 24
Finished Jul 03 07:20:39 PM PDT 24
Peak memory 200500 kb
Host smart-54100788-bd50-4129-8e22-fd9237a51800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3895555
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1606237972
Short name T384
Test name
Test status
Simulation time 213728030860 ps
CPU time 1622.47 seconds
Started Jul 03 07:20:25 PM PDT 24
Finished Jul 03 07:47:30 PM PDT 24
Peak memory 629628 kb
Host smart-909b85a0-bf7d-4ea0-835f-37d51587f845
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606237972 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1606237972
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2650010940
Short name T516
Test name
Test status
Simulation time 7386957387 ps
CPU time 72.22 seconds
Started Jul 03 07:20:29 PM PDT 24
Finished Jul 03 07:21:43 PM PDT 24
Peak memory 200392 kb
Host smart-6ce4fc78-3020-426b-8ae2-fff64c4a9a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650010940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2650010940
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2872944614
Short name T451
Test name
Test status
Simulation time 17503778 ps
CPU time 0.61 seconds
Started Jul 03 07:20:36 PM PDT 24
Finished Jul 03 07:20:38 PM PDT 24
Peak memory 196172 kb
Host smart-3cd7f956-b6a9-4bdd-a9e5-e4ebca1c348b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872944614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2872944614
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2029725635
Short name T251
Test name
Test status
Simulation time 1267920997 ps
CPU time 71.61 seconds
Started Jul 03 07:20:36 PM PDT 24
Finished Jul 03 07:21:48 PM PDT 24
Peak memory 200368 kb
Host smart-63a285b9-b934-4de5-95f0-d5f283cd6df7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2029725635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2029725635
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3868927582
Short name T239
Test name
Test status
Simulation time 9469120554 ps
CPU time 34.49 seconds
Started Jul 03 07:20:33 PM PDT 24
Finished Jul 03 07:21:08 PM PDT 24
Peak memory 200468 kb
Host smart-df619310-3d6e-45d6-8e8a-092ee535f0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868927582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3868927582
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2547720815
Short name T440
Test name
Test status
Simulation time 7090587313 ps
CPU time 595.7 seconds
Started Jul 03 07:20:36 PM PDT 24
Finished Jul 03 07:30:32 PM PDT 24
Peak memory 629692 kb
Host smart-40e642e7-42ac-4fd5-b76d-11ddbd0b66e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2547720815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2547720815
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.4149894051
Short name T319
Test name
Test status
Simulation time 1092111843 ps
CPU time 15.07 seconds
Started Jul 03 07:20:34 PM PDT 24
Finished Jul 03 07:20:50 PM PDT 24
Peak memory 200204 kb
Host smart-29c02365-7fe1-432e-aa2d-eac0f4c17621
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149894051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.4149894051
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3919632437
Short name T55
Test name
Test status
Simulation time 8282316267 ps
CPU time 104.33 seconds
Started Jul 03 07:20:29 PM PDT 24
Finished Jul 03 07:22:15 PM PDT 24
Peak memory 200472 kb
Host smart-63d7b77a-3013-4beb-ab00-fd855dd81d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919632437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3919632437
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2639805215
Short name T87
Test name
Test status
Simulation time 31383296 ps
CPU time 1.57 seconds
Started Jul 03 07:20:29 PM PDT 24
Finished Jul 03 07:20:32 PM PDT 24
Peak memory 200400 kb
Host smart-18a0ad70-97ff-4c45-8768-bf27c9b19fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639805215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2639805215
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1735755079
Short name T51
Test name
Test status
Simulation time 30254903556 ps
CPU time 1309.11 seconds
Started Jul 03 07:20:33 PM PDT 24
Finished Jul 03 07:42:23 PM PDT 24
Peak memory 686972 kb
Host smart-45c300c5-90f7-405a-af55-5888392c84e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735755079 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1735755079
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2270566828
Short name T511
Test name
Test status
Simulation time 1424738486 ps
CPU time 26.72 seconds
Started Jul 03 07:20:34 PM PDT 24
Finished Jul 03 07:21:01 PM PDT 24
Peak memory 200336 kb
Host smart-ad6aba07-b549-4862-9ac3-fe55ab671936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270566828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2270566828
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1573387469
Short name T266
Test name
Test status
Simulation time 13232626 ps
CPU time 0.64 seconds
Started Jul 03 07:20:35 PM PDT 24
Finished Jul 03 07:20:36 PM PDT 24
Peak memory 195248 kb
Host smart-9684b538-543b-4499-98a0-059daff13fbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573387469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1573387469
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.57433084
Short name T397
Test name
Test status
Simulation time 4664761407 ps
CPU time 64.15 seconds
Started Jul 03 07:20:36 PM PDT 24
Finished Jul 03 07:21:41 PM PDT 24
Peak memory 200412 kb
Host smart-62e90ebb-af35-4b5c-99f1-9467d89f1149
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=57433084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.57433084
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.4187668615
Short name T159
Test name
Test status
Simulation time 4905999036 ps
CPU time 67.33 seconds
Started Jul 03 07:20:36 PM PDT 24
Finished Jul 03 07:21:44 PM PDT 24
Peak memory 200424 kb
Host smart-8d764485-e450-485d-96d2-81e6e1da7add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187668615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.4187668615
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.4221578114
Short name T133
Test name
Test status
Simulation time 32725749693 ps
CPU time 1389.37 seconds
Started Jul 03 07:20:41 PM PDT 24
Finished Jul 03 07:43:52 PM PDT 24
Peak memory 772548 kb
Host smart-1b178418-b0a6-4a2b-b926-c585339c44da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4221578114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.4221578114
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1417791900
Short name T285
Test name
Test status
Simulation time 39312882351 ps
CPU time 140.87 seconds
Started Jul 03 07:20:32 PM PDT 24
Finished Jul 03 07:22:54 PM PDT 24
Peak memory 200420 kb
Host smart-2897a664-e163-40fc-b8f6-c7c2c64731d9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417791900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1417791900
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1052990330
Short name T457
Test name
Test status
Simulation time 9887591711 ps
CPU time 132.04 seconds
Started Jul 03 07:20:34 PM PDT 24
Finished Jul 03 07:22:47 PM PDT 24
Peak memory 200452 kb
Host smart-b4cb43cd-525d-4c21-a2f2-1e92e824e3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052990330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1052990330
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.4219820661
Short name T329
Test name
Test status
Simulation time 1082536194 ps
CPU time 4.01 seconds
Started Jul 03 07:20:34 PM PDT 24
Finished Jul 03 07:20:39 PM PDT 24
Peak memory 200392 kb
Host smart-05a6f8a2-27be-4dd6-a65a-85d413e23572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219820661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.4219820661
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.3896989065
Short name T525
Test name
Test status
Simulation time 39277670204 ps
CPU time 1164.84 seconds
Started Jul 03 07:20:41 PM PDT 24
Finished Jul 03 07:40:07 PM PDT 24
Peak memory 765312 kb
Host smart-3d46fec2-760c-4da6-a134-8cd036a8a412
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896989065 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3896989065
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.2078651149
Short name T224
Test name
Test status
Simulation time 10342674139 ps
CPU time 66.8 seconds
Started Jul 03 07:20:41 PM PDT 24
Finished Jul 03 07:21:49 PM PDT 24
Peak memory 200424 kb
Host smart-14f7a99d-6add-4f70-8ab3-32dd004f814c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078651149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2078651149
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.3407586314
Short name T458
Test name
Test status
Simulation time 41414791 ps
CPU time 0.58 seconds
Started Jul 03 07:20:44 PM PDT 24
Finished Jul 03 07:20:47 PM PDT 24
Peak memory 196116 kb
Host smart-133896f6-9680-4566-b09d-cff6fa6c4bf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407586314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3407586314
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.4252354959
Short name T434
Test name
Test status
Simulation time 1101329396 ps
CPU time 65.52 seconds
Started Jul 03 07:20:44 PM PDT 24
Finished Jul 03 07:21:52 PM PDT 24
Peak memory 200408 kb
Host smart-869cab2e-192d-4c55-898f-59b60c4ce4c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4252354959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.4252354959
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3862596640
Short name T154
Test name
Test status
Simulation time 328608869 ps
CPU time 17.99 seconds
Started Jul 03 07:20:40 PM PDT 24
Finished Jul 03 07:20:58 PM PDT 24
Peak memory 200416 kb
Host smart-7692db66-03eb-4e6a-af11-f5ca4a06a488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862596640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3862596640
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1445063267
Short name T36
Test name
Test status
Simulation time 19482149226 ps
CPU time 881.32 seconds
Started Jul 03 07:20:45 PM PDT 24
Finished Jul 03 07:35:28 PM PDT 24
Peak memory 726604 kb
Host smart-ac7cf5a6-717e-417c-b691-c96ec9f4759c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1445063267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1445063267
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1420406011
Short name T165
Test name
Test status
Simulation time 3980193414 ps
CPU time 68.33 seconds
Started Jul 03 07:20:39 PM PDT 24
Finished Jul 03 07:21:48 PM PDT 24
Peak memory 200280 kb
Host smart-929a2e92-9d1f-48dd-bc3e-b18a02a04a21
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420406011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1420406011
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1641375598
Short name T292
Test name
Test status
Simulation time 4330449005 ps
CPU time 55.68 seconds
Started Jul 03 07:20:37 PM PDT 24
Finished Jul 03 07:21:34 PM PDT 24
Peak memory 208852 kb
Host smart-95d9c630-8e87-461f-9df6-63ead55d185b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641375598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1641375598
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.960950276
Short name T504
Test name
Test status
Simulation time 260667678 ps
CPU time 12.3 seconds
Started Jul 03 07:20:39 PM PDT 24
Finished Jul 03 07:20:53 PM PDT 24
Peak memory 200376 kb
Host smart-9d43220b-e422-4d16-baf8-11b5366c7c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960950276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.960950276
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3498551455
Short name T464
Test name
Test status
Simulation time 29463553178 ps
CPU time 5558.44 seconds
Started Jul 03 07:20:44 PM PDT 24
Finished Jul 03 08:53:26 PM PDT 24
Peak memory 912344 kb
Host smart-db89b47a-c022-4616-a8f1-1971bc2a45bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498551455 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3498551455
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1194690049
Short name T332
Test name
Test status
Simulation time 184520769543 ps
CPU time 152.88 seconds
Started Jul 03 07:20:44 PM PDT 24
Finished Jul 03 07:23:19 PM PDT 24
Peak memory 200416 kb
Host smart-d4f0c3a5-2f03-468d-a280-1a87a3dec207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194690049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1194690049
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.67942453
Short name T439
Test name
Test status
Simulation time 18162546 ps
CPU time 0.57 seconds
Started Jul 03 07:20:45 PM PDT 24
Finished Jul 03 07:20:48 PM PDT 24
Peak memory 195188 kb
Host smart-32781f89-5d2f-49ee-9137-c6e64d30e2d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67942453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.67942453
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3563644725
Short name T43
Test name
Test status
Simulation time 613025853 ps
CPU time 35.05 seconds
Started Jul 03 07:20:36 PM PDT 24
Finished Jul 03 07:21:13 PM PDT 24
Peak memory 200376 kb
Host smart-fe6781dd-6c90-440a-9978-1f86a994a4e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3563644725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3563644725
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1082115768
Short name T337
Test name
Test status
Simulation time 2472658887 ps
CPU time 67.6 seconds
Started Jul 03 07:20:37 PM PDT 24
Finished Jul 03 07:21:46 PM PDT 24
Peak memory 200432 kb
Host smart-2f76d8d9-09d5-4016-8a38-087cb323b532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082115768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1082115768
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3396069472
Short name T14
Test name
Test status
Simulation time 7168050777 ps
CPU time 1521.72 seconds
Started Jul 03 07:20:44 PM PDT 24
Finished Jul 03 07:46:09 PM PDT 24
Peak memory 748520 kb
Host smart-6cf8f9f6-b241-4144-8fbf-7123e83569ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3396069472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3396069472
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1328598802
Short name T468
Test name
Test status
Simulation time 26239558871 ps
CPU time 163.16 seconds
Started Jul 03 07:20:44 PM PDT 24
Finished Jul 03 07:23:28 PM PDT 24
Peak memory 200480 kb
Host smart-83cd8629-48b8-49f6-a754-f037100ea682
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328598802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1328598802
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.36939570
Short name T210
Test name
Test status
Simulation time 531770334 ps
CPU time 7.4 seconds
Started Jul 03 07:20:44 PM PDT 24
Finished Jul 03 07:20:54 PM PDT 24
Peak memory 200368 kb
Host smart-e88f81f4-337f-429b-8318-380df79b4904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36939570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.36939570
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3299925164
Short name T302
Test name
Test status
Simulation time 1107134989 ps
CPU time 12.4 seconds
Started Jul 03 07:20:39 PM PDT 24
Finished Jul 03 07:20:52 PM PDT 24
Peak memory 200516 kb
Host smart-2568e5d7-7434-4a0e-b3c5-aa2f716621b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299925164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3299925164
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1894664522
Short name T180
Test name
Test status
Simulation time 60411679618 ps
CPU time 1752.3 seconds
Started Jul 03 07:20:44 PM PDT 24
Finished Jul 03 07:49:58 PM PDT 24
Peak memory 724328 kb
Host smart-cc089b6a-6769-482e-83b5-833e60da4018
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894664522 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1894664522
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.4270483183
Short name T107
Test name
Test status
Simulation time 8969277296 ps
CPU time 79.12 seconds
Started Jul 03 07:20:49 PM PDT 24
Finished Jul 03 07:22:10 PM PDT 24
Peak memory 200504 kb
Host smart-7534712e-ccc2-4c60-b45e-8f1bef55b315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270483183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.4270483183
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2927835650
Short name T64
Test name
Test status
Simulation time 15460031 ps
CPU time 0.63 seconds
Started Jul 03 07:20:45 PM PDT 24
Finished Jul 03 07:20:48 PM PDT 24
Peak memory 196156 kb
Host smart-6dbbe77d-882f-44be-aa4d-4cc41fc8f1c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927835650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2927835650
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3780441716
Short name T424
Test name
Test status
Simulation time 1671319438 ps
CPU time 23.67 seconds
Started Jul 03 07:20:48 PM PDT 24
Finished Jul 03 07:21:13 PM PDT 24
Peak memory 200276 kb
Host smart-a2650fb6-6851-4a86-8e65-3fbd0522ad27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3780441716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3780441716
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.405370246
Short name T456
Test name
Test status
Simulation time 861875722 ps
CPU time 47.89 seconds
Started Jul 03 07:20:48 PM PDT 24
Finished Jul 03 07:21:38 PM PDT 24
Peak memory 200368 kb
Host smart-2c818a68-9f4d-4167-90d0-5c88acb75ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405370246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.405370246
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1664577803
Short name T288
Test name
Test status
Simulation time 43619375336 ps
CPU time 1350.76 seconds
Started Jul 03 07:20:45 PM PDT 24
Finished Jul 03 07:43:19 PM PDT 24
Peak memory 771360 kb
Host smart-7d1d3bff-2630-439f-9606-cb6e7a239847
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1664577803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1664577803
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.519147370
Short name T77
Test name
Test status
Simulation time 1375746687 ps
CPU time 63.07 seconds
Started Jul 03 07:20:45 PM PDT 24
Finished Jul 03 07:21:50 PM PDT 24
Peak memory 200408 kb
Host smart-d3cb09a2-ab6d-4d9f-a6e0-09723c9cb6e2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519147370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.519147370
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1365264929
Short name T237
Test name
Test status
Simulation time 22317302748 ps
CPU time 79.1 seconds
Started Jul 03 07:20:43 PM PDT 24
Finished Jul 03 07:22:03 PM PDT 24
Peak memory 200416 kb
Host smart-448a8bb5-8dfa-4e6a-814b-b2dd2a227312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365264929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1365264929
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.548568520
Short name T486
Test name
Test status
Simulation time 2908569613 ps
CPU time 12.76 seconds
Started Jul 03 07:20:48 PM PDT 24
Finished Jul 03 07:21:02 PM PDT 24
Peak memory 200344 kb
Host smart-b0481411-2782-4524-bc01-639a1f2a9606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548568520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.548568520
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2138696276
Short name T310
Test name
Test status
Simulation time 13314167175 ps
CPU time 175.42 seconds
Started Jul 03 07:20:44 PM PDT 24
Finished Jul 03 07:23:41 PM PDT 24
Peak memory 200352 kb
Host smart-42a72484-19b6-4eef-98a0-7d6946608850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138696276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2138696276
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.2642822282
Short name T246
Test name
Test status
Simulation time 13221401 ps
CPU time 0.61 seconds
Started Jul 03 07:20:51 PM PDT 24
Finished Jul 03 07:20:54 PM PDT 24
Peak memory 196852 kb
Host smart-33690548-1c97-46e2-90ff-4b6b89d56ff0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642822282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.2642822282
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.609535834
Short name T184
Test name
Test status
Simulation time 1503823706 ps
CPU time 46.1 seconds
Started Jul 03 07:20:53 PM PDT 24
Finished Jul 03 07:21:40 PM PDT 24
Peak memory 200408 kb
Host smart-138c0db8-5331-42fb-8d42-0957975d76fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=609535834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.609535834
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2258245815
Short name T455
Test name
Test status
Simulation time 169174518 ps
CPU time 2.61 seconds
Started Jul 03 07:20:50 PM PDT 24
Finished Jul 03 07:20:55 PM PDT 24
Peak memory 200176 kb
Host smart-b8972ba2-2bac-41e1-9895-ef177abe9b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258245815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2258245815
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2448217543
Short name T476
Test name
Test status
Simulation time 14652432033 ps
CPU time 449.86 seconds
Started Jul 03 07:20:53 PM PDT 24
Finished Jul 03 07:28:24 PM PDT 24
Peak memory 496332 kb
Host smart-05963be5-f275-4d2d-b6fc-09e617ec6a2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2448217543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2448217543
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1057853096
Short name T240
Test name
Test status
Simulation time 17390334276 ps
CPU time 71.39 seconds
Started Jul 03 07:20:57 PM PDT 24
Finished Jul 03 07:22:10 PM PDT 24
Peak memory 200364 kb
Host smart-bf8895ad-0733-4b1b-bbfc-408f23656da5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057853096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1057853096
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2648267664
Short name T235
Test name
Test status
Simulation time 56424357 ps
CPU time 2.93 seconds
Started Jul 03 07:20:49 PM PDT 24
Finished Jul 03 07:20:54 PM PDT 24
Peak memory 200328 kb
Host smart-6ea86b3b-8876-4a57-9ef9-7f664b447aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648267664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2648267664
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2056554124
Short name T138
Test name
Test status
Simulation time 88672036 ps
CPU time 3.93 seconds
Started Jul 03 07:20:45 PM PDT 24
Finished Jul 03 07:20:51 PM PDT 24
Peak memory 200368 kb
Host smart-dc0d4838-2f51-4e93-bbf5-521a0a58eaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056554124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2056554124
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1330533542
Short name T178
Test name
Test status
Simulation time 87545212777 ps
CPU time 405.06 seconds
Started Jul 03 07:20:51 PM PDT 24
Finished Jul 03 07:27:38 PM PDT 24
Peak memory 216816 kb
Host smart-cf67418d-d319-49f4-8af2-4d61ed6343a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330533542 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1330533542
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2878951084
Short name T407
Test name
Test status
Simulation time 724713250 ps
CPU time 4.86 seconds
Started Jul 03 07:20:51 PM PDT 24
Finished Jul 03 07:20:58 PM PDT 24
Peak memory 200380 kb
Host smart-47981dcd-af18-40c3-851d-57a23715a848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878951084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2878951084
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2385076794
Short name T176
Test name
Test status
Simulation time 34053281 ps
CPU time 0.54 seconds
Started Jul 03 07:20:49 PM PDT 24
Finished Jul 03 07:20:52 PM PDT 24
Peak memory 196212 kb
Host smart-a0cdd4ef-5cfb-4ad7-8907-08f9b83f5844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385076794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2385076794
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3354398171
Short name T231
Test name
Test status
Simulation time 1158607950 ps
CPU time 56.8 seconds
Started Jul 03 07:20:50 PM PDT 24
Finished Jul 03 07:21:50 PM PDT 24
Peak memory 200344 kb
Host smart-2afa7d9b-1c2e-49d1-955e-fd0af37c6cc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3354398171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3354398171
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1774515716
Short name T187
Test name
Test status
Simulation time 25147375059 ps
CPU time 41.92 seconds
Started Jul 03 07:20:57 PM PDT 24
Finished Jul 03 07:21:40 PM PDT 24
Peak memory 200436 kb
Host smart-ac4b58d1-8f5f-42ac-b182-239163d222ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774515716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1774515716
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1083330530
Short name T268
Test name
Test status
Simulation time 1311206037 ps
CPU time 270.05 seconds
Started Jul 03 07:20:49 PM PDT 24
Finished Jul 03 07:25:22 PM PDT 24
Peak memory 635152 kb
Host smart-159f95ef-0a5b-4473-9a85-50ea390806e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1083330530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1083330530
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.497030925
Short name T459
Test name
Test status
Simulation time 2374202230 ps
CPU time 65.68 seconds
Started Jul 03 07:20:50 PM PDT 24
Finished Jul 03 07:21:58 PM PDT 24
Peak memory 200420 kb
Host smart-26c69faa-c4fc-4e2d-8698-382cefc95ccc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497030925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.497030925
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.4074595666
Short name T396
Test name
Test status
Simulation time 1233193756 ps
CPU time 22.39 seconds
Started Jul 03 07:20:49 PM PDT 24
Finished Jul 03 07:21:14 PM PDT 24
Peak memory 200344 kb
Host smart-825b5636-4a48-4187-be3f-33b7ce859a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074595666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.4074595666
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.104513322
Short name T431
Test name
Test status
Simulation time 629274321 ps
CPU time 9.61 seconds
Started Jul 03 07:20:50 PM PDT 24
Finished Jul 03 07:21:02 PM PDT 24
Peak memory 200384 kb
Host smart-5ceedf2e-7168-4d8d-8abd-c4eee63bb2c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104513322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.104513322
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.4043874830
Short name T99
Test name
Test status
Simulation time 126380371457 ps
CPU time 1313.94 seconds
Started Jul 03 07:20:51 PM PDT 24
Finished Jul 03 07:42:47 PM PDT 24
Peak memory 691896 kb
Host smart-af03b8cf-ede8-4568-bd1a-f26fcf33ab04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043874830 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.4043874830
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2817878598
Short name T137
Test name
Test status
Simulation time 3208266073 ps
CPU time 24.97 seconds
Started Jul 03 07:20:57 PM PDT 24
Finished Jul 03 07:21:23 PM PDT 24
Peak memory 200460 kb
Host smart-5fa7bc35-13c4-44bb-a7d3-50471a97979f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817878598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2817878598
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.170861015
Short name T521
Test name
Test status
Simulation time 26724595 ps
CPU time 0.58 seconds
Started Jul 03 07:20:55 PM PDT 24
Finished Jul 03 07:20:57 PM PDT 24
Peak memory 196224 kb
Host smart-dc527e46-9dac-4bad-ae40-aeae46ab3254
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170861015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.170861015
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3159309490
Short name T414
Test name
Test status
Simulation time 3859561621 ps
CPU time 44.77 seconds
Started Jul 03 07:20:56 PM PDT 24
Finished Jul 03 07:21:42 PM PDT 24
Peak memory 200352 kb
Host smart-8025bbc0-d2e0-48ff-986d-e20fb11b78f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3159309490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3159309490
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.646827153
Short name T233
Test name
Test status
Simulation time 691809195 ps
CPU time 20.11 seconds
Started Jul 03 07:20:55 PM PDT 24
Finished Jul 03 07:21:16 PM PDT 24
Peak memory 200476 kb
Host smart-95dfd292-0b0d-4913-958e-f11ff3923b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646827153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.646827153
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.1478625819
Short name T307
Test name
Test status
Simulation time 2522484801 ps
CPU time 409.63 seconds
Started Jul 03 07:20:54 PM PDT 24
Finished Jul 03 07:27:45 PM PDT 24
Peak memory 675756 kb
Host smart-7fdc0691-4382-485d-9830-47d209be77c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1478625819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.1478625819
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.62861844
Short name T378
Test name
Test status
Simulation time 18938841838 ps
CPU time 28.53 seconds
Started Jul 03 07:20:55 PM PDT 24
Finished Jul 03 07:21:25 PM PDT 24
Peak memory 200472 kb
Host smart-45fbca4a-263c-4f12-b78e-45da4493353d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62861844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.62861844
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2251297830
Short name T54
Test name
Test status
Simulation time 18719974052 ps
CPU time 166.58 seconds
Started Jul 03 07:20:49 PM PDT 24
Finished Jul 03 07:23:38 PM PDT 24
Peak memory 200488 kb
Host smart-19caca40-355a-47a9-88a2-7ade42cd00a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251297830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2251297830
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.4122591158
Short name T366
Test name
Test status
Simulation time 671578192 ps
CPU time 10.05 seconds
Started Jul 03 07:20:57 PM PDT 24
Finished Jul 03 07:21:08 PM PDT 24
Peak memory 200396 kb
Host smart-b655c6ed-ec47-4b07-9d9a-7e692eb2f5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122591158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.4122591158
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.385651377
Short name T31
Test name
Test status
Simulation time 67477859373 ps
CPU time 242.85 seconds
Started Jul 03 07:20:53 PM PDT 24
Finished Jul 03 07:24:58 PM PDT 24
Peak memory 200448 kb
Host smart-4938da07-cc56-47c2-8d63-b772d255b329
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385651377 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.385651377
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2954823692
Short name T202
Test name
Test status
Simulation time 10603373811 ps
CPU time 65.15 seconds
Started Jul 03 07:20:54 PM PDT 24
Finished Jul 03 07:22:01 PM PDT 24
Peak memory 200432 kb
Host smart-a6683af8-6c58-4e88-b000-e09f71759c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954823692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2954823692
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.986726235
Short name T241
Test name
Test status
Simulation time 27339212 ps
CPU time 0.6 seconds
Started Jul 03 07:20:55 PM PDT 24
Finished Jul 03 07:20:57 PM PDT 24
Peak memory 195840 kb
Host smart-623df8f7-995a-4bb3-b169-9bc3d26a1b3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986726235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.986726235
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3630486030
Short name T291
Test name
Test status
Simulation time 4328186940 ps
CPU time 59.98 seconds
Started Jul 03 07:20:54 PM PDT 24
Finished Jul 03 07:21:56 PM PDT 24
Peak memory 200440 kb
Host smart-fafc7ccf-4a68-44a0-9650-ae7baad0557f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3630486030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3630486030
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2106559603
Short name T190
Test name
Test status
Simulation time 1409802907 ps
CPU time 59.05 seconds
Started Jul 03 07:20:55 PM PDT 24
Finished Jul 03 07:21:56 PM PDT 24
Peak memory 336792 kb
Host smart-4d86f79b-5df5-4447-aeea-50b9b2996725
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2106559603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2106559603
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3092395540
Short name T62
Test name
Test status
Simulation time 2186912700 ps
CPU time 112.71 seconds
Started Jul 03 07:20:56 PM PDT 24
Finished Jul 03 07:22:50 PM PDT 24
Peak memory 200376 kb
Host smart-61f54f52-e222-42b8-96d4-a3392a907e5a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092395540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3092395540
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1534086606
Short name T53
Test name
Test status
Simulation time 4284957377 ps
CPU time 5.74 seconds
Started Jul 03 07:20:56 PM PDT 24
Finished Jul 03 07:21:03 PM PDT 24
Peak memory 200328 kb
Host smart-3b5d1222-e4d2-4ada-9865-071002a4f8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534086606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1534086606
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1820087294
Short name T379
Test name
Test status
Simulation time 1882870393 ps
CPU time 13.03 seconds
Started Jul 03 07:20:54 PM PDT 24
Finished Jul 03 07:21:09 PM PDT 24
Peak memory 200384 kb
Host smart-dc3af1f6-73ab-4f65-b95f-b8fab3a13ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820087294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1820087294
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3490876675
Short name T92
Test name
Test status
Simulation time 1038759532001 ps
CPU time 988.7 seconds
Started Jul 03 07:20:55 PM PDT 24
Finished Jul 03 07:37:25 PM PDT 24
Peak memory 658200 kb
Host smart-f038c247-a979-4a29-a8be-c3c9df4f0a20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490876675 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3490876675
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2405468682
Short name T41
Test name
Test status
Simulation time 1867058172 ps
CPU time 24.17 seconds
Started Jul 03 07:20:57 PM PDT 24
Finished Jul 03 07:21:22 PM PDT 24
Peak memory 200356 kb
Host smart-8f5d937d-d328-4dc1-a89c-f6f979f18f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405468682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2405468682
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1456291807
Short name T265
Test name
Test status
Simulation time 12622074 ps
CPU time 0.62 seconds
Started Jul 03 07:19:40 PM PDT 24
Finished Jul 03 07:19:44 PM PDT 24
Peak memory 196220 kb
Host smart-c7326b36-d2d3-450d-b407-a2a312e94490
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456291807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1456291807
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2056797938
Short name T47
Test name
Test status
Simulation time 6855172893 ps
CPU time 99.76 seconds
Started Jul 03 07:19:36 PM PDT 24
Finished Jul 03 07:21:19 PM PDT 24
Peak memory 200424 kb
Host smart-5021f986-14f8-4131-8d9d-f38ebed6dea5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2056797938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2056797938
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.629692432
Short name T21
Test name
Test status
Simulation time 5848888041 ps
CPU time 50.54 seconds
Started Jul 03 07:19:38 PM PDT 24
Finished Jul 03 07:20:32 PM PDT 24
Peak memory 200516 kb
Host smart-7fc36b56-eb85-4dd4-b6cf-68d4624dbb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629692432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.629692432
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1567589914
Short name T164
Test name
Test status
Simulation time 433667990 ps
CPU time 57.93 seconds
Started Jul 03 07:19:35 PM PDT 24
Finished Jul 03 07:20:36 PM PDT 24
Peak memory 336216 kb
Host smart-698b4269-31db-462a-9772-7adf0c825f9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1567589914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1567589914
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1177202237
Short name T277
Test name
Test status
Simulation time 11183864622 ps
CPU time 155.36 seconds
Started Jul 03 07:19:37 PM PDT 24
Finished Jul 03 07:22:15 PM PDT 24
Peak memory 200476 kb
Host smart-5795af9e-613e-483f-bd15-0435bd9f8a5b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177202237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1177202237
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2156900266
Short name T97
Test name
Test status
Simulation time 3430832133 ps
CPU time 107.13 seconds
Started Jul 03 07:19:47 PM PDT 24
Finished Jul 03 07:21:37 PM PDT 24
Peak memory 200404 kb
Host smart-8b4faab0-316a-42b6-a9f8-3ffd88475374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156900266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2156900266
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1587329000
Short name T70
Test name
Test status
Simulation time 143448895 ps
CPU time 0.83 seconds
Started Jul 03 07:19:49 PM PDT 24
Finished Jul 03 07:19:52 PM PDT 24
Peak memory 218508 kb
Host smart-25273555-daaf-4652-a37b-5ec1bdab9c9b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587329000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1587329000
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1278923052
Short name T449
Test name
Test status
Simulation time 399019074 ps
CPU time 7.13 seconds
Started Jul 03 07:19:34 PM PDT 24
Finished Jul 03 07:19:45 PM PDT 24
Peak memory 200380 kb
Host smart-b722558c-5609-4a9f-97af-351eee51d85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278923052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1278923052
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1756876308
Short name T91
Test name
Test status
Simulation time 126390667598 ps
CPU time 833.91 seconds
Started Jul 03 07:19:42 PM PDT 24
Finished Jul 03 07:33:40 PM PDT 24
Peak memory 200416 kb
Host smart-5807066e-3996-4d3d-9c88-b7b6f4de6826
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756876308 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1756876308
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.2188694105
Short name T357
Test name
Test status
Simulation time 3307051004 ps
CPU time 69.47 seconds
Started Jul 03 07:19:43 PM PDT 24
Finished Jul 03 07:20:57 PM PDT 24
Peak memory 200396 kb
Host smart-881b4e12-d52e-4bef-a674-424b87312d50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2188694105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.2188694105
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.1310721463
Short name T242
Test name
Test status
Simulation time 9757531415 ps
CPU time 62.94 seconds
Started Jul 03 07:19:43 PM PDT 24
Finished Jul 03 07:20:50 PM PDT 24
Peak memory 200420 kb
Host smart-3dcb3732-55ce-44e7-85da-63cd8512ff36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1310721463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.1310721463
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.3487376629
Short name T44
Test name
Test status
Simulation time 2876184285 ps
CPU time 117.9 seconds
Started Jul 03 07:19:42 PM PDT 24
Finished Jul 03 07:21:44 PM PDT 24
Peak memory 200560 kb
Host smart-b470522a-f392-496b-bc38-589b977ccb40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3487376629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.3487376629
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.1110377144
Short name T370
Test name
Test status
Simulation time 11251611401 ps
CPU time 662.56 seconds
Started Jul 03 07:19:42 PM PDT 24
Finished Jul 03 07:30:49 PM PDT 24
Peak memory 200432 kb
Host smart-53848320-71f4-4779-b2a4-e3668bb3f8b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1110377144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.1110377144
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.315966817
Short name T335
Test name
Test status
Simulation time 405957858255 ps
CPU time 2696.99 seconds
Started Jul 03 07:19:41 PM PDT 24
Finished Jul 03 08:04:42 PM PDT 24
Peak memory 215904 kb
Host smart-4c6a6204-d306-4278-aab6-093d1c900e47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=315966817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.315966817
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.1957597201
Short name T2
Test name
Test status
Simulation time 272996257289 ps
CPU time 2605.8 seconds
Started Jul 03 07:19:46 PM PDT 24
Finished Jul 03 08:03:16 PM PDT 24
Peak memory 216004 kb
Host smart-b69f3d04-2513-4337-85ad-e88c109cd271
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1957597201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1957597201
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.598327578
Short name T289
Test name
Test status
Simulation time 13973287559 ps
CPU time 86.62 seconds
Started Jul 03 07:19:41 PM PDT 24
Finished Jul 03 07:21:12 PM PDT 24
Peak memory 200424 kb
Host smart-c3e9a77f-d7b9-4fc8-9a8b-2a4ce727bb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598327578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.598327578
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2063132057
Short name T279
Test name
Test status
Simulation time 65910203 ps
CPU time 0.61 seconds
Started Jul 03 07:21:04 PM PDT 24
Finished Jul 03 07:21:06 PM PDT 24
Peak memory 196232 kb
Host smart-2083799d-6f32-4d80-949f-3fe074eb88b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063132057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2063132057
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.676165617
Short name T26
Test name
Test status
Simulation time 3409299021 ps
CPU time 51.87 seconds
Started Jul 03 07:20:54 PM PDT 24
Finished Jul 03 07:21:47 PM PDT 24
Peak memory 200476 kb
Host smart-3dd48f1a-17fa-457a-8e8e-33307214ea09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=676165617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.676165617
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2417786437
Short name T56
Test name
Test status
Simulation time 814218475 ps
CPU time 39.98 seconds
Started Jul 03 07:21:02 PM PDT 24
Finished Jul 03 07:21:43 PM PDT 24
Peak memory 200396 kb
Host smart-ae87e3fd-b73c-494e-9f9c-c1695e723ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417786437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2417786437
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1542101884
Short name T377
Test name
Test status
Simulation time 5059228460 ps
CPU time 1072.43 seconds
Started Jul 03 07:20:55 PM PDT 24
Finished Jul 03 07:38:49 PM PDT 24
Peak memory 767372 kb
Host smart-f2c3117c-9ec3-4dd1-b4fb-ad1c5a8375f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1542101884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1542101884
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1298140406
Short name T34
Test name
Test status
Simulation time 2935741864 ps
CPU time 53.3 seconds
Started Jul 03 07:21:03 PM PDT 24
Finished Jul 03 07:21:57 PM PDT 24
Peak memory 200372 kb
Host smart-ec9c5c76-763d-4b25-821b-cb3bfe2ba77d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298140406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1298140406
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3094331960
Short name T469
Test name
Test status
Simulation time 2491743397 ps
CPU time 148.28 seconds
Started Jul 03 07:20:55 PM PDT 24
Finished Jul 03 07:23:25 PM PDT 24
Peak memory 200420 kb
Host smart-4df52837-1555-4545-a2d5-a5fa14c06898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094331960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3094331960
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.3493480970
Short name T103
Test name
Test status
Simulation time 264991933 ps
CPU time 2.23 seconds
Started Jul 03 07:20:55 PM PDT 24
Finished Jul 03 07:20:58 PM PDT 24
Peak memory 200388 kb
Host smart-53ac51f0-b0da-4355-b6fb-f8d1c1cd7a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493480970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3493480970
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.64028248
Short name T425
Test name
Test status
Simulation time 10287354036 ps
CPU time 119.17 seconds
Started Jul 03 07:21:00 PM PDT 24
Finished Jul 03 07:23:00 PM PDT 24
Peak memory 200440 kb
Host smart-32aa36e1-e265-430d-b841-8f09abbac316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64028248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.64028248
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3558277265
Short name T192
Test name
Test status
Simulation time 15462800 ps
CPU time 0.6 seconds
Started Jul 03 07:21:03 PM PDT 24
Finished Jul 03 07:21:05 PM PDT 24
Peak memory 196908 kb
Host smart-37482ec8-7985-4cb8-9558-1326d86757c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558277265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3558277265
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2868173587
Short name T272
Test name
Test status
Simulation time 2410464126 ps
CPU time 33.65 seconds
Started Jul 03 07:21:02 PM PDT 24
Finished Jul 03 07:21:37 PM PDT 24
Peak memory 200492 kb
Host smart-61d489ae-14ed-4d1c-959f-4f1e1a2cbd89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2868173587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2868173587
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3161657920
Short name T17
Test name
Test status
Simulation time 219654988 ps
CPU time 4.58 seconds
Started Jul 03 07:21:01 PM PDT 24
Finished Jul 03 07:21:08 PM PDT 24
Peak memory 200364 kb
Host smart-689d94c1-f928-445b-9d93-7bdfadd5d53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161657920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3161657920
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2438453735
Short name T419
Test name
Test status
Simulation time 1183100972 ps
CPU time 118.37 seconds
Started Jul 03 07:21:02 PM PDT 24
Finished Jul 03 07:23:01 PM PDT 24
Peak memory 568380 kb
Host smart-c520d72f-6dd2-4a27-910b-ce75d8d31ae8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2438453735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2438453735
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3524649184
Short name T98
Test name
Test status
Simulation time 13069653181 ps
CPU time 13.54 seconds
Started Jul 03 07:21:04 PM PDT 24
Finished Jul 03 07:21:19 PM PDT 24
Peak memory 200476 kb
Host smart-b855c36e-c099-4fc9-9541-c5624c11f5b7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524649184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3524649184
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.394433115
Short name T411
Test name
Test status
Simulation time 23124956416 ps
CPU time 101.83 seconds
Started Jul 03 07:21:01 PM PDT 24
Finished Jul 03 07:22:44 PM PDT 24
Peak memory 200432 kb
Host smart-b9c9368f-acb5-48f9-9193-0218ed0cab2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394433115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.394433115
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3932020201
Short name T309
Test name
Test status
Simulation time 1229457369 ps
CPU time 13.59 seconds
Started Jul 03 07:21:02 PM PDT 24
Finished Jul 03 07:21:17 PM PDT 24
Peak memory 200368 kb
Host smart-39a247c9-37dd-4788-960f-8cab83175577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932020201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3932020201
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.963899952
Short name T156
Test name
Test status
Simulation time 21997653235 ps
CPU time 1264.19 seconds
Started Jul 03 07:21:00 PM PDT 24
Finished Jul 03 07:42:06 PM PDT 24
Peak memory 677216 kb
Host smart-25ebd1d4-91a8-4c88-84f3-28ce6240e106
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963899952 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.963899952
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2834173546
Short name T462
Test name
Test status
Simulation time 8582831149 ps
CPU time 77.42 seconds
Started Jul 03 07:21:02 PM PDT 24
Finished Jul 03 07:22:21 PM PDT 24
Peak memory 200392 kb
Host smart-bb82e616-fb16-43e9-ac9b-1afc5f4b2009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834173546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2834173546
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.4283167753
Short name T420
Test name
Test status
Simulation time 18979553 ps
CPU time 0.57 seconds
Started Jul 03 07:21:09 PM PDT 24
Finished Jul 03 07:21:11 PM PDT 24
Peak memory 195128 kb
Host smart-930e87e2-c9e0-41fd-8755-9c02b3ddc2be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283167753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.4283167753
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2997999251
Short name T20
Test name
Test status
Simulation time 286596873 ps
CPU time 16.54 seconds
Started Jul 03 07:21:12 PM PDT 24
Finished Jul 03 07:21:30 PM PDT 24
Peak memory 200364 kb
Host smart-cefe6f4a-c1ce-4c93-9ce6-1801921ad986
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2997999251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2997999251
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2189084795
Short name T4
Test name
Test status
Simulation time 2206659375 ps
CPU time 20.45 seconds
Started Jul 03 07:21:11 PM PDT 24
Finished Jul 03 07:21:32 PM PDT 24
Peak memory 200456 kb
Host smart-ffcafcfe-9a2d-4948-8a53-1a7d52822fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189084795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2189084795
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2553560647
Short name T271
Test name
Test status
Simulation time 24803794727 ps
CPU time 1338.39 seconds
Started Jul 03 07:21:08 PM PDT 24
Finished Jul 03 07:43:28 PM PDT 24
Peak memory 762844 kb
Host smart-d8613ef1-2f78-455e-9d0a-842d3622178b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2553560647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2553560647
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.4145054864
Short name T417
Test name
Test status
Simulation time 2049108810 ps
CPU time 120.36 seconds
Started Jul 03 07:21:08 PM PDT 24
Finished Jul 03 07:23:10 PM PDT 24
Peak memory 200356 kb
Host smart-35d88015-28f7-4522-8660-7520a2b013eb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145054864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.4145054864
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.3178615317
Short name T60
Test name
Test status
Simulation time 1708914844 ps
CPU time 98.72 seconds
Started Jul 03 07:21:08 PM PDT 24
Finished Jul 03 07:22:48 PM PDT 24
Peak memory 200384 kb
Host smart-ebf42b85-3591-4c0b-aa37-99e766f9efb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178615317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.3178615317
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.133014810
Short name T531
Test name
Test status
Simulation time 736041684 ps
CPU time 9.36 seconds
Started Jul 03 07:21:02 PM PDT 24
Finished Jul 03 07:21:13 PM PDT 24
Peak memory 200404 kb
Host smart-d821f97a-8d30-4f3b-aec8-9744cb0bba86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133014810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.133014810
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1737519888
Short name T512
Test name
Test status
Simulation time 7006173530 ps
CPU time 107.24 seconds
Started Jul 03 07:21:11 PM PDT 24
Finished Jul 03 07:22:59 PM PDT 24
Peak memory 200504 kb
Host smart-6ce0b209-941e-45bc-9860-d8974801f53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737519888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1737519888
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2122317451
Short name T489
Test name
Test status
Simulation time 30141548 ps
CPU time 0.59 seconds
Started Jul 03 07:21:13 PM PDT 24
Finished Jul 03 07:21:15 PM PDT 24
Peak memory 195980 kb
Host smart-466cefdc-8d02-4914-a22e-2ea302796ee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122317451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2122317451
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1267532840
Short name T19
Test name
Test status
Simulation time 571820971 ps
CPU time 16.47 seconds
Started Jul 03 07:21:08 PM PDT 24
Finished Jul 03 07:21:26 PM PDT 24
Peak memory 200380 kb
Host smart-96f12126-4f11-4135-87fc-03074a3a65f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1267532840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1267532840
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2029915383
Short name T314
Test name
Test status
Simulation time 5814476543 ps
CPU time 15.83 seconds
Started Jul 03 07:21:09 PM PDT 24
Finished Jul 03 07:21:26 PM PDT 24
Peak memory 200420 kb
Host smart-30642beb-342d-46f3-aaa9-7e181f63f5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029915383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2029915383
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.3053423676
Short name T254
Test name
Test status
Simulation time 12011223213 ps
CPU time 530.75 seconds
Started Jul 03 07:21:09 PM PDT 24
Finished Jul 03 07:30:01 PM PDT 24
Peak memory 658972 kb
Host smart-1a84e7c1-0b42-4bc1-9a33-a08d1a641b7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3053423676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3053423676
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.641132633
Short name T219
Test name
Test status
Simulation time 26007955123 ps
CPU time 121.01 seconds
Started Jul 03 07:21:10 PM PDT 24
Finished Jul 03 07:23:12 PM PDT 24
Peak memory 200472 kb
Host smart-cf5a8614-3c33-4030-ad42-57bfe5d7dd1c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641132633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.641132633
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2590034787
Short name T323
Test name
Test status
Simulation time 11227636024 ps
CPU time 47.22 seconds
Started Jul 03 07:21:07 PM PDT 24
Finished Jul 03 07:21:55 PM PDT 24
Peak memory 200468 kb
Host smart-9a424a00-4e93-4ca0-95e9-5a1541f0cdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590034787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2590034787
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3245888176
Short name T313
Test name
Test status
Simulation time 108648970 ps
CPU time 4.75 seconds
Started Jul 03 07:21:07 PM PDT 24
Finished Jul 03 07:21:13 PM PDT 24
Peak memory 200376 kb
Host smart-9254cb6a-19d1-44e7-8f17-3d155fe5a884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245888176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3245888176
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.610035842
Short name T232
Test name
Test status
Simulation time 27240659596 ps
CPU time 125.53 seconds
Started Jul 03 07:21:11 PM PDT 24
Finished Jul 03 07:23:18 PM PDT 24
Peak memory 208628 kb
Host smart-3c65befd-7442-480a-a255-3478d1b4f940
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610035842 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.610035842
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2371817875
Short name T442
Test name
Test status
Simulation time 3790549131 ps
CPU time 45.84 seconds
Started Jul 03 07:21:09 PM PDT 24
Finished Jul 03 07:21:56 PM PDT 24
Peak memory 200404 kb
Host smart-23aadb1b-4fc7-4887-ad24-78d05d2de580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371817875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2371817875
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.322139085
Short name T390
Test name
Test status
Simulation time 35724183 ps
CPU time 0.55 seconds
Started Jul 03 07:21:13 PM PDT 24
Finished Jul 03 07:21:15 PM PDT 24
Peak memory 195188 kb
Host smart-43e85464-3e83-4b0f-b67e-9019d6d40f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322139085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.322139085
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.877562506
Short name T501
Test name
Test status
Simulation time 6751847261 ps
CPU time 24.19 seconds
Started Jul 03 07:21:12 PM PDT 24
Finished Jul 03 07:21:38 PM PDT 24
Peak memory 200492 kb
Host smart-5362cab8-298c-41da-94f7-c0740b8ab4be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=877562506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.877562506
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3788804546
Short name T352
Test name
Test status
Simulation time 2874828840 ps
CPU time 19.22 seconds
Started Jul 03 07:21:13 PM PDT 24
Finished Jul 03 07:21:34 PM PDT 24
Peak memory 200424 kb
Host smart-d1862629-2fee-4f4f-8449-b7c0bdf8e7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788804546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3788804546
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3658330439
Short name T135
Test name
Test status
Simulation time 12178251525 ps
CPU time 522.13 seconds
Started Jul 03 07:21:16 PM PDT 24
Finished Jul 03 07:30:00 PM PDT 24
Peak memory 708164 kb
Host smart-3fcee86b-baca-4bd6-9c3b-a889fd94836e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3658330439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3658330439
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3874767558
Short name T347
Test name
Test status
Simulation time 4076930122 ps
CPU time 105.47 seconds
Started Jul 03 07:21:14 PM PDT 24
Finished Jul 03 07:23:02 PM PDT 24
Peak memory 200408 kb
Host smart-22e27ffb-411d-416b-9d63-f0c51e451fb9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874767558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3874767558
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1172693423
Short name T467
Test name
Test status
Simulation time 40259076883 ps
CPU time 187.2 seconds
Started Jul 03 07:21:13 PM PDT 24
Finished Jul 03 07:24:22 PM PDT 24
Peak memory 200444 kb
Host smart-71ffa782-9740-4e1e-8423-0c168cfd3a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172693423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1172693423
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.4293342064
Short name T478
Test name
Test status
Simulation time 1356216468 ps
CPU time 11.23 seconds
Started Jul 03 07:21:13 PM PDT 24
Finished Jul 03 07:21:27 PM PDT 24
Peak memory 200352 kb
Host smart-9cede11f-ab84-4ce4-b158-c26f018903c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293342064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.4293342064
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2080738369
Short name T95
Test name
Test status
Simulation time 21424216642 ps
CPU time 254.5 seconds
Started Jul 03 07:21:13 PM PDT 24
Finished Jul 03 07:25:29 PM PDT 24
Peak memory 200428 kb
Host smart-84aa8761-6ebc-4473-8156-41da18609a83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080738369 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2080738369
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1993684960
Short name T207
Test name
Test status
Simulation time 24880501022 ps
CPU time 115.12 seconds
Started Jul 03 07:21:13 PM PDT 24
Finished Jul 03 07:23:10 PM PDT 24
Peak memory 200524 kb
Host smart-a23ed6eb-44e6-440d-90ab-bb91cf6dd8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993684960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1993684960
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.3203616386
Short name T181
Test name
Test status
Simulation time 35436395 ps
CPU time 0.56 seconds
Started Jul 03 07:21:19 PM PDT 24
Finished Jul 03 07:21:22 PM PDT 24
Peak memory 195208 kb
Host smart-494e1b33-ff1e-4289-9745-b481e7b44793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203616386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.3203616386
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1138913510
Short name T318
Test name
Test status
Simulation time 792013241 ps
CPU time 9.83 seconds
Started Jul 03 07:21:13 PM PDT 24
Finished Jul 03 07:21:24 PM PDT 24
Peak memory 200424 kb
Host smart-2547231a-ae88-4595-8427-099b26b86632
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1138913510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1138913510
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3116613446
Short name T136
Test name
Test status
Simulation time 1579075178 ps
CPU time 6.3 seconds
Started Jul 03 07:21:14 PM PDT 24
Finished Jul 03 07:21:22 PM PDT 24
Peak memory 200296 kb
Host smart-10a6ae44-0f50-4ad4-8905-9db5ca67f8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116613446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3116613446
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.361359223
Short name T280
Test name
Test status
Simulation time 6219731688 ps
CPU time 1095.44 seconds
Started Jul 03 07:21:16 PM PDT 24
Finished Jul 03 07:39:34 PM PDT 24
Peak memory 749536 kb
Host smart-1dd4ec34-7a93-449a-9d88-10a829d53a59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=361359223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.361359223
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1342781755
Short name T389
Test name
Test status
Simulation time 1841969787 ps
CPU time 102.89 seconds
Started Jul 03 07:21:18 PM PDT 24
Finished Jul 03 07:23:04 PM PDT 24
Peak memory 200420 kb
Host smart-a17c7eb7-d329-4283-9202-57d61d227fac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342781755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1342781755
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1404142805
Short name T284
Test name
Test status
Simulation time 7614183880 ps
CPU time 115.91 seconds
Started Jul 03 07:21:14 PM PDT 24
Finished Jul 03 07:23:12 PM PDT 24
Peak memory 208616 kb
Host smart-4703eb7a-5b41-4ec4-af3b-bc3f67dce7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404142805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1404142805
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.246482076
Short name T200
Test name
Test status
Simulation time 239060294 ps
CPU time 5.58 seconds
Started Jul 03 07:21:13 PM PDT 24
Finished Jul 03 07:21:21 PM PDT 24
Peak memory 200344 kb
Host smart-bb27bac5-5d26-453a-8203-d449a7155644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246482076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.246482076
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.4218670667
Short name T33
Test name
Test status
Simulation time 10264469338 ps
CPU time 1809.07 seconds
Started Jul 03 07:21:18 PM PDT 24
Finished Jul 03 07:51:30 PM PDT 24
Peak memory 763972 kb
Host smart-14c82634-0d12-470a-ae70-31b969e93d66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218670667 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.4218670667
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1455290996
Short name T85
Test name
Test status
Simulation time 327557694 ps
CPU time 17.34 seconds
Started Jul 03 07:21:20 PM PDT 24
Finished Jul 03 07:21:40 PM PDT 24
Peak memory 200336 kb
Host smart-42a748ee-35f4-4dc2-a67f-13d39347bbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455290996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1455290996
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3752517480
Short name T199
Test name
Test status
Simulation time 47079833 ps
CPU time 0.6 seconds
Started Jul 03 07:21:26 PM PDT 24
Finished Jul 03 07:21:28 PM PDT 24
Peak memory 196284 kb
Host smart-15996bfb-9c5f-4ba5-8ec6-7820b884b8db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752517480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3752517480
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3989838863
Short name T15
Test name
Test status
Simulation time 3683913310 ps
CPU time 46.89 seconds
Started Jul 03 07:21:25 PM PDT 24
Finished Jul 03 07:22:13 PM PDT 24
Peak memory 200452 kb
Host smart-d9e93cad-c5cc-4094-9d07-996a80bcabf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3989838863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3989838863
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.220146632
Short name T157
Test name
Test status
Simulation time 2655068385 ps
CPU time 76.87 seconds
Started Jul 03 07:21:24 PM PDT 24
Finished Jul 03 07:22:43 PM PDT 24
Peak memory 200420 kb
Host smart-41a5d58e-fce1-44d5-8c00-19a13be72ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220146632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.220146632
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.4097795769
Short name T264
Test name
Test status
Simulation time 11487877646 ps
CPU time 657.81 seconds
Started Jul 03 07:21:25 PM PDT 24
Finished Jul 03 07:32:24 PM PDT 24
Peak memory 627588 kb
Host smart-2d9b2481-0236-4e6d-8f99-88d2d151771a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4097795769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.4097795769
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2004734621
Short name T169
Test name
Test status
Simulation time 12984121116 ps
CPU time 187.12 seconds
Started Jul 03 07:21:27 PM PDT 24
Finished Jul 03 07:24:35 PM PDT 24
Peak memory 200476 kb
Host smart-556e369e-2266-48ae-ba76-8571a1385bb7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004734621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2004734621
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2724465533
Short name T299
Test name
Test status
Simulation time 1006379227 ps
CPU time 56.56 seconds
Started Jul 03 07:21:18 PM PDT 24
Finished Jul 03 07:22:17 PM PDT 24
Peak memory 200324 kb
Host smart-6d98e152-4999-4609-878e-7ee4512a3594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724465533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2724465533
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1053175166
Short name T342
Test name
Test status
Simulation time 431226933 ps
CPU time 10.63 seconds
Started Jul 03 07:21:18 PM PDT 24
Finished Jul 03 07:21:32 PM PDT 24
Peak memory 200372 kb
Host smart-2c8cb6dc-ea62-4387-bb86-816ec4954e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053175166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1053175166
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1376854390
Short name T349
Test name
Test status
Simulation time 323265970165 ps
CPU time 2514.37 seconds
Started Jul 03 07:21:25 PM PDT 24
Finished Jul 03 08:03:21 PM PDT 24
Peak memory 697064 kb
Host smart-0146bb74-7df6-458e-8956-1f5c7fdbf5a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376854390 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1376854390
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.320202578
Short name T345
Test name
Test status
Simulation time 32475648703 ps
CPU time 104.68 seconds
Started Jul 03 07:21:31 PM PDT 24
Finished Jul 03 07:23:18 PM PDT 24
Peak memory 200396 kb
Host smart-ad75c23e-c42c-441c-ba78-67164372ee5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320202578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.320202578
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.231285888
Short name T238
Test name
Test status
Simulation time 23051987 ps
CPU time 0.58 seconds
Started Jul 03 07:21:32 PM PDT 24
Finished Jul 03 07:21:35 PM PDT 24
Peak memory 196900 kb
Host smart-f8ea203b-2639-41a7-ae1d-53b250cdbed2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231285888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.231285888
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2597367454
Short name T226
Test name
Test status
Simulation time 1155313134 ps
CPU time 61.95 seconds
Started Jul 03 07:21:34 PM PDT 24
Finished Jul 03 07:22:38 PM PDT 24
Peak memory 200376 kb
Host smart-c14efd6c-cd3a-4d3c-b3e6-a79c4d83142f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2597367454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2597367454
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.36630581
Short name T153
Test name
Test status
Simulation time 1694548347 ps
CPU time 48 seconds
Started Jul 03 07:21:32 PM PDT 24
Finished Jul 03 07:22:22 PM PDT 24
Peak memory 200368 kb
Host smart-83bf8de3-fff3-4894-82d1-05f9af3d363f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36630581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.36630581
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3506173990
Short name T445
Test name
Test status
Simulation time 2649586102 ps
CPU time 550.42 seconds
Started Jul 03 07:21:31 PM PDT 24
Finished Jul 03 07:30:44 PM PDT 24
Peak memory 676648 kb
Host smart-d6a73837-3c9f-44e4-a215-f6e363722164
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3506173990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3506173990
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.224270006
Short name T333
Test name
Test status
Simulation time 17267387779 ps
CPU time 69.96 seconds
Started Jul 03 07:21:32 PM PDT 24
Finished Jul 03 07:22:44 PM PDT 24
Peak memory 200436 kb
Host smart-f8bbcc0b-8c4e-43ea-9a32-5283737db9c4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224270006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.224270006
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.430444843
Short name T258
Test name
Test status
Simulation time 14046036377 ps
CPU time 167.82 seconds
Started Jul 03 07:21:34 PM PDT 24
Finished Jul 03 07:24:24 PM PDT 24
Peak memory 208624 kb
Host smart-221a5907-9122-4d5a-8c55-c87a00657a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430444843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.430444843
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3206323033
Short name T350
Test name
Test status
Simulation time 274324557 ps
CPU time 4.29 seconds
Started Jul 03 07:21:34 PM PDT 24
Finished Jul 03 07:21:40 PM PDT 24
Peak memory 200384 kb
Host smart-9a0ea58c-bb6d-447d-a041-2be6399f20fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206323033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3206323033
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.753640381
Short name T45
Test name
Test status
Simulation time 185442797722 ps
CPU time 1155.55 seconds
Started Jul 03 07:21:33 PM PDT 24
Finished Jul 03 07:40:51 PM PDT 24
Peak memory 208616 kb
Host smart-0435c5b5-36ef-42f5-885a-02ee13e39bcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753640381 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.753640381
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3222437692
Short name T261
Test name
Test status
Simulation time 8903411283 ps
CPU time 60.6 seconds
Started Jul 03 07:21:29 PM PDT 24
Finished Jul 03 07:22:30 PM PDT 24
Peak memory 200396 kb
Host smart-c5753ae0-ec73-4a10-83f6-30a45e44be3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222437692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3222437692
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.2759258629
Short name T295
Test name
Test status
Simulation time 23514207 ps
CPU time 0.6 seconds
Started Jul 03 07:21:34 PM PDT 24
Finished Jul 03 07:21:37 PM PDT 24
Peak memory 196872 kb
Host smart-c7b1344e-dcb9-4d98-a0dc-a23db4ae8142
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759258629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2759258629
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.4228577504
Short name T496
Test name
Test status
Simulation time 3100669499 ps
CPU time 43.69 seconds
Started Jul 03 07:21:31 PM PDT 24
Finished Jul 03 07:22:16 PM PDT 24
Peak memory 200556 kb
Host smart-f7bc55c7-bdcd-4ddd-b1f3-b0eaca67b3f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4228577504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.4228577504
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1250689643
Short name T262
Test name
Test status
Simulation time 8240703077 ps
CPU time 55.41 seconds
Started Jul 03 07:21:35 PM PDT 24
Finished Jul 03 07:22:32 PM PDT 24
Peak memory 200448 kb
Host smart-c0f8328f-5616-4027-b5aa-00d6c4940490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250689643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1250689643
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1896271584
Short name T177
Test name
Test status
Simulation time 2102869700 ps
CPU time 223.27 seconds
Started Jul 03 07:21:33 PM PDT 24
Finished Jul 03 07:25:19 PM PDT 24
Peak memory 599184 kb
Host smart-d5dbb8f0-350b-42db-95d9-516e2c461ce2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1896271584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1896271584
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.67291310
Short name T102
Test name
Test status
Simulation time 18124349183 ps
CPU time 104.63 seconds
Started Jul 03 07:21:35 PM PDT 24
Finished Jul 03 07:23:21 PM PDT 24
Peak memory 200332 kb
Host smart-8519c0cd-ce8d-45a1-affd-f09b23594e3f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67291310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.67291310
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2677493571
Short name T524
Test name
Test status
Simulation time 6139516045 ps
CPU time 87.92 seconds
Started Jul 03 07:21:31 PM PDT 24
Finished Jul 03 07:23:01 PM PDT 24
Peak memory 216740 kb
Host smart-b2edc59e-b7d6-409a-a2f1-62ccfb3654ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677493571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2677493571
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1809911594
Short name T221
Test name
Test status
Simulation time 1394082394 ps
CPU time 6.65 seconds
Started Jul 03 07:21:35 PM PDT 24
Finished Jul 03 07:21:44 PM PDT 24
Peak memory 200420 kb
Host smart-3a0c476c-b044-4b4b-af73-647ed5f028d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809911594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1809911594
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.879049784
Short name T195
Test name
Test status
Simulation time 62770490896 ps
CPU time 1613.44 seconds
Started Jul 03 07:21:34 PM PDT 24
Finished Jul 03 07:48:30 PM PDT 24
Peak memory 728392 kb
Host smart-c21b0c03-4be3-4b4d-b4b3-3fab1736db9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879049784 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.879049784
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2874949655
Short name T249
Test name
Test status
Simulation time 4504906634 ps
CPU time 112.66 seconds
Started Jul 03 07:21:32 PM PDT 24
Finished Jul 03 07:23:27 PM PDT 24
Peak memory 200380 kb
Host smart-38830758-e893-497c-b8ee-b5878cf95b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874949655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2874949655
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2553819879
Short name T362
Test name
Test status
Simulation time 15343041 ps
CPU time 0.63 seconds
Started Jul 03 07:21:36 PM PDT 24
Finished Jul 03 07:21:38 PM PDT 24
Peak memory 196236 kb
Host smart-0a3e7c9d-3236-43a4-acae-42212f3acc13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553819879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2553819879
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.3793489245
Short name T185
Test name
Test status
Simulation time 1362666923 ps
CPU time 37.7 seconds
Started Jul 03 07:21:32 PM PDT 24
Finished Jul 03 07:22:12 PM PDT 24
Peak memory 200356 kb
Host smart-c275fde7-ab6a-428e-b88a-bb1d9ff7d42e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3793489245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3793489245
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3110545323
Short name T360
Test name
Test status
Simulation time 703559885 ps
CPU time 37.22 seconds
Started Jul 03 07:21:39 PM PDT 24
Finished Jul 03 07:22:18 PM PDT 24
Peak memory 200504 kb
Host smart-b4305eff-49de-4446-a35a-b3e171a41146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110545323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3110545323
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3264296959
Short name T300
Test name
Test status
Simulation time 1318143377 ps
CPU time 228.68 seconds
Started Jul 03 07:21:34 PM PDT 24
Finished Jul 03 07:25:25 PM PDT 24
Peak memory 477276 kb
Host smart-f0aa6936-1f24-431f-9fdb-7594563a8978
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3264296959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3264296959
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.154989815
Short name T304
Test name
Test status
Simulation time 15340899913 ps
CPU time 93.42 seconds
Started Jul 03 07:21:40 PM PDT 24
Finished Jul 03 07:23:15 PM PDT 24
Peak memory 200376 kb
Host smart-91c87bf4-8c84-418f-8b91-1b56f1053451
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154989815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.154989815
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2801621072
Short name T346
Test name
Test status
Simulation time 1872335194 ps
CPU time 100.93 seconds
Started Jul 03 07:21:33 PM PDT 24
Finished Jul 03 07:23:16 PM PDT 24
Peak memory 200372 kb
Host smart-fc6bbfdd-477f-46a2-b27c-a488db100a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801621072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2801621072
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1534783567
Short name T364
Test name
Test status
Simulation time 580994392 ps
CPU time 11.52 seconds
Started Jul 03 07:21:31 PM PDT 24
Finished Jul 03 07:21:44 PM PDT 24
Peak memory 200368 kb
Host smart-3d5094a2-c7f3-4d9d-81bb-82b613917634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534783567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1534783567
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1738337273
Short name T359
Test name
Test status
Simulation time 9892170402 ps
CPU time 552.78 seconds
Started Jul 03 07:21:43 PM PDT 24
Finished Jul 03 07:30:58 PM PDT 24
Peak memory 344040 kb
Host smart-31e761f2-e137-441f-866a-5615dba311e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738337273 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1738337273
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3536143305
Short name T412
Test name
Test status
Simulation time 24518145556 ps
CPU time 153.43 seconds
Started Jul 03 07:21:34 PM PDT 24
Finished Jul 03 07:24:10 PM PDT 24
Peak memory 200432 kb
Host smart-06b98ea9-a29e-4fe8-bb67-eecca111fc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536143305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3536143305
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3473295418
Short name T189
Test name
Test status
Simulation time 35981653 ps
CPU time 0.6 seconds
Started Jul 03 07:19:43 PM PDT 24
Finished Jul 03 07:19:47 PM PDT 24
Peak memory 196852 kb
Host smart-ebf2597c-a072-4e80-ad82-185cc57876cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473295418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3473295418
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1048905840
Short name T473
Test name
Test status
Simulation time 1373834696 ps
CPU time 80.16 seconds
Started Jul 03 07:19:44 PM PDT 24
Finished Jul 03 07:21:08 PM PDT 24
Peak memory 200352 kb
Host smart-fdb8def4-71e2-4bec-9877-ba94a494c598
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1048905840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1048905840
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1356186064
Short name T520
Test name
Test status
Simulation time 1178783367 ps
CPU time 47.33 seconds
Started Jul 03 07:19:42 PM PDT 24
Finished Jul 03 07:20:33 PM PDT 24
Peak memory 200456 kb
Host smart-fd3f13e1-1029-49f1-b257-fde1d7002656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356186064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1356186064
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3194998104
Short name T409
Test name
Test status
Simulation time 5313447583 ps
CPU time 266.72 seconds
Started Jul 03 07:19:41 PM PDT 24
Finished Jul 03 07:24:12 PM PDT 24
Peak memory 647696 kb
Host smart-04c8dcc5-3247-4caa-9c0f-4ed7391d5c26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3194998104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3194998104
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3973812899
Short name T532
Test name
Test status
Simulation time 2466958215 ps
CPU time 5.24 seconds
Started Jul 03 07:19:41 PM PDT 24
Finished Jul 03 07:19:51 PM PDT 24
Peak memory 200280 kb
Host smart-7a52d9b1-c344-4d06-9731-f56f297d3b98
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973812899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3973812899
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3062400997
Short name T172
Test name
Test status
Simulation time 5636885887 ps
CPU time 72.02 seconds
Started Jul 03 07:19:42 PM PDT 24
Finished Jul 03 07:20:58 PM PDT 24
Peak memory 200432 kb
Host smart-fd6a4817-a913-44ee-9661-19e209c7aac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062400997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3062400997
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3021587463
Short name T228
Test name
Test status
Simulation time 259485041 ps
CPU time 11.13 seconds
Started Jul 03 07:19:41 PM PDT 24
Finished Jul 03 07:19:56 PM PDT 24
Peak memory 200400 kb
Host smart-aa12c8a7-ae30-49d6-8bbd-79e8e6353b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021587463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3021587463
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1221159176
Short name T316
Test name
Test status
Simulation time 58571972004 ps
CPU time 1312.96 seconds
Started Jul 03 07:19:41 PM PDT 24
Finished Jul 03 07:41:38 PM PDT 24
Peak memory 718252 kb
Host smart-60e9b76e-af55-42d8-9c32-9083cce86c6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221159176 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1221159176
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2347971318
Short name T101
Test name
Test status
Simulation time 10194555267 ps
CPU time 88.69 seconds
Started Jul 03 07:19:39 PM PDT 24
Finished Jul 03 07:21:11 PM PDT 24
Peak memory 200452 kb
Host smart-2db398f6-b149-4e26-b679-b67d64afddef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347971318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2347971318
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2456160350
Short name T361
Test name
Test status
Simulation time 13610806 ps
CPU time 0.6 seconds
Started Jul 03 07:19:41 PM PDT 24
Finished Jul 03 07:19:45 PM PDT 24
Peak memory 196204 kb
Host smart-c5a86e22-cc16-4479-a4e4-5b86179c562e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456160350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2456160350
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.279458345
Short name T529
Test name
Test status
Simulation time 602250552 ps
CPU time 24.78 seconds
Started Jul 03 07:19:44 PM PDT 24
Finished Jul 03 07:20:13 PM PDT 24
Peak memory 200356 kb
Host smart-37d5e9f5-e9ab-4fd5-82e9-ccde7742dc01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=279458345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.279458345
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1906326016
Short name T158
Test name
Test status
Simulation time 7456200849 ps
CPU time 30.35 seconds
Started Jul 03 07:19:43 PM PDT 24
Finished Jul 03 07:20:17 PM PDT 24
Peak memory 200412 kb
Host smart-cd3abc9a-86bc-4a32-9e83-05ed23160b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906326016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1906326016
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2642535539
Short name T191
Test name
Test status
Simulation time 16458451 ps
CPU time 0.69 seconds
Started Jul 03 07:19:40 PM PDT 24
Finished Jul 03 07:19:45 PM PDT 24
Peak memory 200072 kb
Host smart-55593b2e-cf1b-4bf3-a491-206d4fff5221
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2642535539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2642535539
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.4071212636
Short name T311
Test name
Test status
Simulation time 20907472134 ps
CPU time 293.86 seconds
Started Jul 03 07:19:42 PM PDT 24
Finished Jul 03 07:24:40 PM PDT 24
Peak memory 200412 kb
Host smart-fcc7f1dc-76a5-46fd-8430-5b43f7e64ad7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071212636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.4071212636
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.2717748669
Short name T423
Test name
Test status
Simulation time 37903787925 ps
CPU time 217.53 seconds
Started Jul 03 07:19:42 PM PDT 24
Finished Jul 03 07:23:23 PM PDT 24
Peak memory 216784 kb
Host smart-ac2d5a32-e97f-40e9-8d69-9bcf512a0f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717748669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2717748669
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1905349034
Short name T430
Test name
Test status
Simulation time 326229786 ps
CPU time 4.71 seconds
Started Jul 03 07:19:42 PM PDT 24
Finished Jul 03 07:19:51 PM PDT 24
Peak memory 200372 kb
Host smart-74cfbd70-f502-423d-8cb5-36a1605035b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905349034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1905349034
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1446932976
Short name T282
Test name
Test status
Simulation time 10799797365 ps
CPU time 198.05 seconds
Started Jul 03 07:19:40 PM PDT 24
Finished Jul 03 07:23:02 PM PDT 24
Peak memory 208688 kb
Host smart-d4298b6a-a8c5-43b0-9f48-f5399915fbc4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446932976 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1446932976
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1831539248
Short name T281
Test name
Test status
Simulation time 8703694669 ps
CPU time 39.12 seconds
Started Jul 03 07:19:44 PM PDT 24
Finished Jul 03 07:20:26 PM PDT 24
Peak memory 200420 kb
Host smart-3b0fe07a-600f-40be-aec0-4273bd381482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831539248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1831539248
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.4004195936
Short name T367
Test name
Test status
Simulation time 14827544 ps
CPU time 0.56 seconds
Started Jul 03 07:19:46 PM PDT 24
Finished Jul 03 07:19:50 PM PDT 24
Peak memory 195204 kb
Host smart-55a3c1e5-9d83-44df-b882-9d962cce9c39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004195936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.4004195936
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.178604206
Short name T488
Test name
Test status
Simulation time 2658146039 ps
CPU time 47.36 seconds
Started Jul 03 07:19:45 PM PDT 24
Finished Jul 03 07:20:35 PM PDT 24
Peak memory 200408 kb
Host smart-8d497b44-2eb1-4c02-9941-3fbe8074e39c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=178604206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.178604206
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1106442715
Short name T155
Test name
Test status
Simulation time 976208884 ps
CPU time 50.46 seconds
Started Jul 03 07:19:44 PM PDT 24
Finished Jul 03 07:20:38 PM PDT 24
Peak memory 200520 kb
Host smart-c073471d-e25c-4ff2-bbd9-ac0097b859dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106442715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1106442715
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1051027179
Short name T405
Test name
Test status
Simulation time 4309584438 ps
CPU time 132.72 seconds
Started Jul 03 07:19:46 PM PDT 24
Finished Jul 03 07:22:02 PM PDT 24
Peak memory 340224 kb
Host smart-9816ecf0-8811-4c80-85dd-82e8f67b62b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1051027179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1051027179
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2712358310
Short name T406
Test name
Test status
Simulation time 7311487707 ps
CPU time 123.75 seconds
Started Jul 03 07:19:48 PM PDT 24
Finished Jul 03 07:21:54 PM PDT 24
Peak memory 200424 kb
Host smart-beb7c49c-4499-4a31-a307-728739f137ca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712358310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2712358310
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.243007271
Short name T466
Test name
Test status
Simulation time 4325230512 ps
CPU time 83.94 seconds
Started Jul 03 07:19:42 PM PDT 24
Finished Jul 03 07:21:10 PM PDT 24
Peak memory 200480 kb
Host smart-31cc8de2-0dcb-4716-959c-db0215dbb0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243007271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.243007271
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1547858059
Short name T410
Test name
Test status
Simulation time 571302601 ps
CPU time 7.53 seconds
Started Jul 03 07:19:39 PM PDT 24
Finished Jul 03 07:19:49 PM PDT 24
Peak memory 200416 kb
Host smart-fe2ae457-8005-4abd-bbcc-fb236b7a6f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547858059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1547858059
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.1234963734
Short name T7
Test name
Test status
Simulation time 21709394991 ps
CPU time 164.44 seconds
Started Jul 03 07:19:46 PM PDT 24
Finished Jul 03 07:22:34 PM PDT 24
Peak memory 208648 kb
Host smart-f7c4ee27-748c-45dc-a9cd-d755f3d0f511
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1234963734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.1234963734
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2688190297
Short name T376
Test name
Test status
Simulation time 21170809218 ps
CPU time 97.56 seconds
Started Jul 03 07:19:45 PM PDT 24
Finished Jul 03 07:21:26 PM PDT 24
Peak memory 200476 kb
Host smart-7b77365e-741f-4e8e-a5d8-2455540939a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688190297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2688190297
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.279159478
Short name T404
Test name
Test status
Simulation time 22791545 ps
CPU time 0.6 seconds
Started Jul 03 07:19:47 PM PDT 24
Finished Jul 03 07:19:50 PM PDT 24
Peak memory 196152 kb
Host smart-5391fd83-8a06-43d0-897e-d8368b4313dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279159478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.279159478
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1368422081
Short name T481
Test name
Test status
Simulation time 2150031767 ps
CPU time 63.33 seconds
Started Jul 03 07:19:45 PM PDT 24
Finished Jul 03 07:20:52 PM PDT 24
Peak memory 200352 kb
Host smart-69ee7dd1-ce9d-4824-9746-8d02a4dc0b25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1368422081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1368422081
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.810461991
Short name T339
Test name
Test status
Simulation time 14980707839 ps
CPU time 58.81 seconds
Started Jul 03 07:19:44 PM PDT 24
Finished Jul 03 07:20:47 PM PDT 24
Peak memory 200444 kb
Host smart-b0b59a08-a2db-4045-affc-167e37f126f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810461991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.810461991
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.712446348
Short name T391
Test name
Test status
Simulation time 10640715653 ps
CPU time 462.68 seconds
Started Jul 03 07:19:43 PM PDT 24
Finished Jul 03 07:27:30 PM PDT 24
Peak memory 653744 kb
Host smart-96be6452-5756-4abb-bcd6-f8e9a8045ec7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=712446348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.712446348
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3082160539
Short name T373
Test name
Test status
Simulation time 7538254432 ps
CPU time 124.94 seconds
Started Jul 03 07:19:46 PM PDT 24
Finished Jul 03 07:21:54 PM PDT 24
Peak memory 200456 kb
Host smart-b74c6e20-3137-422d-8b31-45cadd7e5856
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082160539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3082160539
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.882476460
Short name T186
Test name
Test status
Simulation time 1504823637 ps
CPU time 82.7 seconds
Started Jul 03 07:19:47 PM PDT 24
Finished Jul 03 07:21:13 PM PDT 24
Peak memory 200380 kb
Host smart-b0ce09d3-53c1-447d-9679-d2e9ded6613c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882476460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.882476460
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3563944370
Short name T381
Test name
Test status
Simulation time 7151450910 ps
CPU time 14.55 seconds
Started Jul 03 07:19:45 PM PDT 24
Finished Jul 03 07:20:03 PM PDT 24
Peak memory 200388 kb
Host smart-88d20d29-ade3-4f35-ad89-dcce0bd7aa85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563944370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3563944370
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.360675031
Short name T90
Test name
Test status
Simulation time 224119006514 ps
CPU time 5646.51 seconds
Started Jul 03 07:19:47 PM PDT 24
Finished Jul 03 08:53:57 PM PDT 24
Peak memory 834684 kb
Host smart-4e12c8e6-ae03-422a-ae38-0614f4dda0d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360675031 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.360675031
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.4184710732
Short name T83
Test name
Test status
Simulation time 192450648824 ps
CPU time 4882.13 seconds
Started Jul 03 07:19:45 PM PDT 24
Finished Jul 03 08:41:11 PM PDT 24
Peak memory 790392 kb
Host smart-c2676769-cf43-4252-9725-488261c48350
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4184710732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.4184710732
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.774964604
Short name T217
Test name
Test status
Simulation time 16328272029 ps
CPU time 76.98 seconds
Started Jul 03 07:19:48 PM PDT 24
Finished Jul 03 07:21:08 PM PDT 24
Peak memory 200412 kb
Host smart-bf36f12a-074e-4cc7-871d-b0b073b746bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774964604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.774964604
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3423251684
Short name T348
Test name
Test status
Simulation time 24098251 ps
CPU time 0.58 seconds
Started Jul 03 07:19:52 PM PDT 24
Finished Jul 03 07:19:55 PM PDT 24
Peak memory 196208 kb
Host smart-2345a7e8-dc8a-4b2f-93b6-f0c133e149d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423251684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3423251684
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.538878741
Short name T416
Test name
Test status
Simulation time 2630068328 ps
CPU time 61.23 seconds
Started Jul 03 07:19:47 PM PDT 24
Finished Jul 03 07:20:51 PM PDT 24
Peak memory 200448 kb
Host smart-8a58d52b-6ac0-4d65-a311-7546ce0f7a55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=538878741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.538878741
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.48837645
Short name T230
Test name
Test status
Simulation time 1993158035 ps
CPU time 13.84 seconds
Started Jul 03 07:19:46 PM PDT 24
Finished Jul 03 07:20:03 PM PDT 24
Peak memory 200452 kb
Host smart-57b49faa-a92e-479c-b11f-f1fda377c5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48837645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.48837645
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1213274953
Short name T514
Test name
Test status
Simulation time 22722038691 ps
CPU time 1059.84 seconds
Started Jul 03 07:19:45 PM PDT 24
Finished Jul 03 07:37:28 PM PDT 24
Peak memory 776872 kb
Host smart-0cc9232c-4745-40eb-9ce8-1d6679ae5fbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1213274953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1213274953
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2143540481
Short name T78
Test name
Test status
Simulation time 27131601701 ps
CPU time 216.28 seconds
Started Jul 03 07:19:45 PM PDT 24
Finished Jul 03 07:23:25 PM PDT 24
Peak memory 200344 kb
Host smart-1d464789-ab3a-4273-886c-009ee92b266a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143540481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2143540481
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2504060611
Short name T321
Test name
Test status
Simulation time 6718270016 ps
CPU time 69.61 seconds
Started Jul 03 07:19:47 PM PDT 24
Finished Jul 03 07:21:00 PM PDT 24
Peak memory 200480 kb
Host smart-6ec9fb51-affe-41cf-99a0-5d23c0118d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504060611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2504060611
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2582562050
Short name T253
Test name
Test status
Simulation time 902421016 ps
CPU time 5.57 seconds
Started Jul 03 07:19:45 PM PDT 24
Finished Jul 03 07:19:54 PM PDT 24
Peak memory 200316 kb
Host smart-1ba6a190-fe49-4d6f-84c6-17ef3e1dd8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582562050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2582562050
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2879489722
Short name T470
Test name
Test status
Simulation time 91771982297 ps
CPU time 2322.86 seconds
Started Jul 03 07:19:51 PM PDT 24
Finished Jul 03 07:58:37 PM PDT 24
Peak memory 740308 kb
Host smart-3a39c77c-2928-4b81-9e68-7243df7a28d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879489722 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2879489722
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.3064756806
Short name T13
Test name
Test status
Simulation time 359810672277 ps
CPU time 1844.76 seconds
Started Jul 03 07:19:54 PM PDT 24
Finished Jul 03 07:50:42 PM PDT 24
Peak memory 703104 kb
Host smart-e6cb7744-8d9d-4a80-8681-4adffa54500a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3064756806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.3064756806
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3928949358
Short name T433
Test name
Test status
Simulation time 4150303709 ps
CPU time 99.94 seconds
Started Jul 03 07:19:51 PM PDT 24
Finished Jul 03 07:21:34 PM PDT 24
Peak memory 200376 kb
Host smart-b6b8c3c6-d7b2-4e46-9736-4970ce59b89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928949358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3928949358
Directory /workspace/9.hmac_wipe_secret/latest
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