Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17670430	1			T1	47219		T2	19872		T3	1301
all_values[1]	17670430	1			T1	47219		T2	19872		T3	1301
all_values[2]	17670430	1			T1	47219		T2	19872		T3	1301

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

269055

1

T2

1367

T3

106

T4

298

auto[1]

52742235

1

T1

141657

T2

58249

T3

3797

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45073922

1

T1

125833

T2

53054

T3

3330

auto[1]

7937368

1

T1

15824

T2

6562

T3

573

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	74546	1			T4	298		T15	50		T5	1029
all_values[0]	auto[0]	auto[1]	361	1			T15	2		T5	3		T20	17
all_values[0]	auto[1]	auto[0]	17576266	1			T1	47194		T2	19844		T3	1284
all_values[0]	auto[1]	auto[1]	19257	1			T1	25		T2	28		T3	17
all_values[1]	auto[0]	auto[0]	107554	1			T2	1367		T3	53		T5	2
all_values[1]	auto[0]	auto[1]	196	1			T5	2		T20	3		T44	4
all_values[1]	auto[1]	auto[0]	17562368	1			T1	47219		T2	18505		T3	1248
all_values[1]	auto[1]	auto[1]	312	1			T5	2		T18	2		T20	6
all_values[2]	auto[0]	auto[0]	38431	1			T3	17		T15	52		T5	7
all_values[2]	auto[0]	auto[1]	47967	1			T3	36		T5	19		T20	50
all_values[2]	auto[1]	auto[0]	9714757	1			T1	31420		T2	13338		T3	728
all_values[2]	auto[1]	auto[1]	7869275	1			T1	15799		T2	6534		T3	520