Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

124168

1

T2

62

T3

32

T4

42

auto[1]

125314

1

T1

56

T2

24

T3

18

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	92600	1			T1	12		T2	36		T4	28
len_1026_2046	5395	1			T4	3		T14	16		T15	6
len_514_1022	3713	1			T2	3		T14	79		T15	1
len_2_510	4531	1			T3	2		T14	39		T15	10
len_2056	149	1			T3	1		T15	4		T6	3
len_2048	510	1			T4	1		T14	2		T18	4
len_2040	169	1			T15	2		T44	16		T19	2
len_1032	172	1			T3	2		T20	1		T44	24
len_1024	1731	1			T4	1		T14	1		T15	7
len_1016	167	1			T3	6		T15	1		T5	1
len_520	153	1			T3	6		T5	2		T25	1
len_512	338	1			T3	1		T14	1		T5	2
len_504	399	1			T3	5		T25	1		T20	2
len_8	1077	1			T1	15		T5	2		T25	1
len_0	13638	1			T1	1		T2	4		T3	2

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

97

1

T41

2

T42

2

T65

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	48739	1			T2	24		T4	17		T14	163
auto[0]	len_1026_2046	2713	1			T4	3		T14	11		T15	3
auto[0]	len_514_1022	2497	1			T2	3		T14	72		T15	1
auto[0]	len_2_510	2380	1			T3	1		T14	17		T15	8
auto[0]	len_2056	79	1			T15	3		T126	3		T127	1
auto[0]	len_2048	298	1			T14	2		T18	3		T44	4
auto[0]	len_2040	80	1			T15	1		T44	9		T19	2
auto[0]	len_1032	84	1			T3	1		T44	5		T41	1
auto[0]	len_1024	234	1			T4	1		T14	1		T15	3
auto[0]	len_1016	93	1			T3	5		T20	4		T44	6
auto[0]	len_520	83	1			T3	3		T5	2		T25	1
auto[0]	len_512	205	1			T14	1		T18	1		T25	1
auto[0]	len_504	96	1			T3	4		T25	1		T20	2
auto[0]	len_8	26	1			T25	1		T63	2		T71	1
auto[0]	len_0	4478	1			T2	4		T3	2		T14	136
auto[1]	len_2050_plus	43861	1			T1	12		T2	12		T4	11
auto[1]	len_1026_2046	2682	1			T14	5		T15	3		T5	1
auto[1]	len_514_1022	1216	1			T14	7		T5	2		T18	2
auto[1]	len_2_510	2151	1			T3	1		T14	22		T15	2
auto[1]	len_2056	70	1			T3	1		T15	1		T6	3
auto[1]	len_2048	212	1			T4	1		T18	1		T20	2
auto[1]	len_2040	89	1			T15	1		T44	7		T88	3
auto[1]	len_1032	88	1			T3	1		T20	1		T44	19
auto[1]	len_1024	1497	1			T15	4		T44	5		T43	1
auto[1]	len_1016	74	1			T3	1		T15	1		T5	1
auto[1]	len_520	70	1			T3	3		T20	3		T44	2
auto[1]	len_512	133	1			T3	1		T5	2		T18	1
auto[1]	len_504	303	1			T3	1		T44	4		T6	243
auto[1]	len_8	1051	1			T1	15		T5	2		T20	30
auto[1]	len_0	9160	1			T1	1		T4	1		T14	68

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

49

1

T65

1

T128

1

T129

1

auto[1]

len_upper

48

1

T41

2

T42

2

T71

2