Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4439670 1 T1 9503 T2 4784 T3 423
auto[1] 2826011 1 T1 13876 T2 5131 T3 245


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2755642 1 T1 6096 T2 6079 T3 270
auto[1] 4510039 1 T1 17283 T2 3836 T3 398


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3227432 1 T2 5666 T3 357 T4 28
auto[1] 4038249 1 T1 23379 T2 4249 T3 311


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4498673 1 T1 9414 T2 5820 T3 380
auto[1] 2767008 1 T1 13965 T2 4095 T3 288


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 6569738 1 T1 20138 T2 8498 T3 657
fifo_depth[1] 116492 1 T1 479 T2 240 T3 5
fifo_depth[2] 91016 1 T1 489 T2 227 T3 4
fifo_depth[3] 71077 1 T1 488 T2 214 T3 2
fifo_depth[4] 62776 1 T1 470 T2 195 T14 8
fifo_depth[5] 48432 1 T1 448 T2 204 T14 4
fifo_depth[6] 39824 1 T1 346 T2 130 T4 1
fifo_depth[7] 26790 1 T1 266 T2 94 T4 1


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 695943 1 T1 3241 T2 1417 T3 11
auto[1] 6569738 1 T1 20138 T2 8498 T3 657


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7254631 1 T1 23379 T2 9915 T3 668
auto[1] 11050 1 T18 807 T21 153 T24 4


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 39857 1 T2 237 T4 1 T14 20
auto[0] auto[0] auto[0] auto[0] auto[1] 30406 1 T2 109 T3 1 T4 2
auto[0] auto[0] auto[0] auto[1] auto[0] 31854 1 T2 200 T4 3 T14 5
auto[0] auto[0] auto[0] auto[1] auto[1] 24916 1 T2 58 T4 1 T15 8
auto[0] auto[0] auto[1] auto[0] auto[0] 188759 1 T2 104 T3 1 T4 3
auto[0] auto[0] auto[1] auto[0] auto[1] 27429 1 T2 111 T4 1 T15 7
auto[0] auto[0] auto[1] auto[1] auto[0] 40212 1 T2 97 T14 14 T15 6
auto[0] auto[0] auto[1] auto[1] auto[1] 29016 1 T2 153 T4 1 T18 143
auto[0] auto[1] auto[0] auto[0] auto[0] 33580 1 T1 473 T5 14 T18 1474
auto[0] auto[1] auto[0] auto[0] auto[1] 28574 1 T1 79 T5 62 T18 1281
auto[0] auto[1] auto[0] auto[1] auto[0] 36203 1 T1 489 T2 192 T15 26
auto[0] auto[1] auto[0] auto[1] auto[1] 40151 1 T2 105 T3 3 T4 1
auto[0] auto[1] auto[1] auto[0] auto[0] 46824 1 T2 51 T14 5 T15 12
auto[0] auto[1] auto[1] auto[0] auto[1] 40685 1 T1 1283 T3 2 T4 1
auto[0] auto[1] auto[1] auto[1] auto[0] 26347 1 T3 4 T4 1 T15 9
auto[0] auto[1] auto[1] auto[1] auto[1] 31130 1 T1 917 T5 50 T20 240
auto[1] auto[0] auto[0] auto[0] auto[0] 156232 1 T2 698 T3 47 T4 4
auto[1] auto[0] auto[0] auto[0] auto[1] 170372 1 T2 1191 T3 44 T4 2
auto[1] auto[0] auto[0] auto[1] auto[0] 162720 1 T2 1141 T3 52 T4 3
auto[1] auto[0] auto[0] auto[1] auto[1] 165733 1 T2 126 T3 62 T4 1
auto[1] auto[0] auto[1] auto[0] auto[0] 1653920 1 T2 376 T3 88 T4 1
auto[1] auto[0] auto[1] auto[0] auto[1] 165073 1 T2 391 T3 37 T4 2
auto[1] auto[0] auto[1] auto[1] auto[0] 169732 1 T2 356 T3 16 T4 2
auto[1] auto[0] auto[1] auto[1] auto[1] 171201 1 T2 318 T3 9 T4 1
auto[1] auto[1] auto[0] auto[0] auto[0] 447097 1 T1 2610 T2 255 T4 2
auto[1] auto[1] auto[0] auto[0] auto[1] 424477 1 T1 132 T2 817 T3 48
auto[1] auto[1] auto[0] auto[1] auto[0] 500571 1 T1 1643 T2 648 T4 4
auto[1] auto[1] auto[0] auto[1] auto[1] 462899 1 T1 670 T2 302 T3 13
auto[1] auto[1] auto[1] auto[0] auto[0] 516783 1 T1 1664 T2 427 T3 86
auto[1] auto[1] auto[1] auto[0] auto[1] 469602 1 T1 3262 T2 17 T3 69
auto[1] auto[1] auto[1] auto[1] auto[0] 447982 1 T1 2535 T2 1038 T3 86
auto[1] auto[1] auto[1] auto[1] auto[1] 485344 1 T1 7622 T2 397 T4 2


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 194968 1 T2 935 T3 47 T4 5
auto[0] auto[0] auto[0] auto[0] auto[1] 199752 1 T2 1300 T3 45 T4 4
auto[0] auto[0] auto[0] auto[1] auto[0] 193933 1 T2 1341 T3 52 T4 6
auto[0] auto[0] auto[0] auto[1] auto[1] 189977 1 T2 184 T3 62 T4 2
auto[0] auto[0] auto[1] auto[0] auto[0] 1841584 1 T2 480 T3 89 T4 4
auto[0] auto[0] auto[1] auto[0] auto[1] 191969 1 T2 502 T3 37 T4 3
auto[0] auto[0] auto[1] auto[1] auto[0] 208777 1 T2 453 T3 16 T4 2
auto[0] auto[0] auto[1] auto[1] auto[1] 199635 1 T2 471 T3 9 T4 2
auto[0] auto[1] auto[0] auto[0] auto[0] 480266 1 T1 3083 T2 255 T4 2
auto[0] auto[1] auto[0] auto[0] auto[1] 452396 1 T1 211 T2 817 T3 48
auto[0] auto[1] auto[0] auto[1] auto[0] 536446 1 T1 2132 T2 840 T4 4
auto[0] auto[1] auto[0] auto[1] auto[1] 502028 1 T1 670 T2 407 T3 16
auto[0] auto[1] auto[1] auto[0] auto[0] 563255 1 T1 1664 T2 478 T3 86
auto[0] auto[1] auto[1] auto[0] auto[1] 509938 1 T1 4545 T2 17 T3 71
auto[0] auto[1] auto[1] auto[1] auto[0] 473655 1 T1 2535 T2 1038 T3 90
auto[0] auto[1] auto[1] auto[1] auto[1] 516052 1 T1 8539 T2 397 T4 2
auto[1] auto[0] auto[0] auto[0] auto[0] 1121 1 T21 1 T37 47 T52 1
auto[1] auto[0] auto[0] auto[0] auto[1] 1026 1 T21 7 T37 72 T52 1
auto[1] auto[0] auto[0] auto[1] auto[0] 641 1 T18 145 T6 7 T79 1
auto[1] auto[0] auto[0] auto[1] auto[1] 672 1 T21 1 T52 6 T41 16
auto[1] auto[0] auto[1] auto[0] auto[0] 1095 1 T18 6 T41 42 T6 12
auto[1] auto[0] auto[1] auto[0] auto[1] 533 1 T18 42 T41 3 T6 4
auto[1] auto[0] auto[1] auto[1] auto[0] 1167 1 T18 44 T52 3 T130 92
auto[1] auto[0] auto[1] auto[1] auto[1] 582 1 T21 7 T37 1 T41 28
auto[1] auto[1] auto[0] auto[0] auto[0] 411 1 T18 110 T41 24 T6 1
auto[1] auto[1] auto[0] auto[0] auto[1] 655 1 T18 94 T21 3 T24 4
auto[1] auto[1] auto[0] auto[1] auto[0] 328 1 T41 9 T131 19 T132 11
auto[1] auto[1] auto[0] auto[1] auto[1] 1022 1 T18 366 T41 119 T131 8
auto[1] auto[1] auto[1] auto[0] auto[0] 352 1 T41 5 T131 8 T133 3
auto[1] auto[1] auto[1] auto[0] auto[1] 349 1 T37 16 T41 69 T6 9
auto[1] auto[1] auto[1] auto[1] auto[0] 674 1 T21 134 T133 4 T134 6
auto[1] auto[1] auto[1] auto[1] auto[1] 422 1 T41 6 T79 3 T131 36


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 156232 1 T2 698 T3 47 T4 4
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 170372 1 T2 1191 T3 44 T4 2
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 162720 1 T2 1141 T3 52 T4 3
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 165733 1 T2 126 T3 62 T4 1
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1653920 1 T2 376 T3 88 T4 1
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 165073 1 T2 391 T3 37 T4 2
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 169732 1 T2 356 T3 16 T4 2
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 171201 1 T2 318 T3 9 T4 1
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 447097 1 T1 2610 T2 255 T4 2
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 424477 1 T1 132 T2 817 T3 48
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 500571 1 T1 1643 T2 648 T4 4
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 462899 1 T1 670 T2 302 T3 13
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 516783 1 T1 1664 T2 427 T3 86
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 469602 1 T1 3262 T2 17 T3 69
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 447982 1 T1 2535 T2 1038 T3 86
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 485344 1 T1 7622 T2 397 T4 2
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 3180 1 T2 41 T14 6 T20 68
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 3423 1 T2 15 T3 1 T4 1
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 3210 1 T2 27 T4 1 T14 2
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 3064 1 T2 15 T4 1 T15 2
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 48327 1 T2 16 T5 15 T18 2
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 2925 1 T2 17 T5 22 T20 35
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 3267 1 T2 20 T14 4 T18 75
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 3329 1 T2 30 T18 4 T20 19
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 5289 1 T1 66 T5 8 T20 81
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 4565 1 T1 14 T5 43 T20 61
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 6008 1 T1 63 T2 39 T15 2
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 5822 1 T2 14 T3 1 T15 1
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 8254 1 T2 6 T15 4 T5 1
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 5947 1 T1 194 T3 2 T5 39
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 4294 1 T3 1 T5 4 T20 16
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 5588 1 T1 142 T5 24 T20 131
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 2521 1 T2 35 T14 5 T20 29
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 2462 1 T2 14 T4 1 T14 5
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 2535 1 T2 35 T15 1 T5 5
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 2428 1 T2 13 T15 1 T5 16
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 37552 1 T2 19 T3 1 T5 4
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 2466 1 T2 15 T15 2 T5 8
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 2309 1 T2 11 T14 2 T5 1
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 2948 1 T2 27 T20 7 T21 34
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 4317 1 T1 68 T5 2 T18 2
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 3361 1 T1 12 T5 14 T18 3
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 4347 1 T1 76 T2 35 T15 6
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 4696 1 T2 18 T3 1 T15 5
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 6171 1 T2 5 T14 5 T15 1
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 4696 1 T1 190 T14 2 T5 18
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 3430 1 T3 2 T4 1 T15 2
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 4777 1 T1 143 T5 14 T20 73
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 1849 1 T2 30 T14 4 T20 3
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 1757 1 T2 17 T5 5 T20 13
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 1822 1 T2 25 T5 1 T18 18
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 1811 1 T2 12 T15 1 T5 4
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 28864 1 T2 21 T5 3 T18 2
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 1464 1 T2 22 T15 1 T5 3
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 1899 1 T2 12 T14 2 T18 81
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 2222 1 T2 36 T4 1 T18 7
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 3645 1 T1 68 T5 2 T20 15
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 2799 1 T1 15 T5 5 T20 6
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 3547 1 T1 69 T2 18 T15 4
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 3973 1 T2 14 T3 1 T15 2
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 4706 1 T2 7 T15 2 T18 1
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 3935 1 T1 200 T5 11 T36 24
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 2881 1 T3 1 T15 1 T20 1
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 3903 1 T1 136 T5 10 T20 26
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2160 1 T2 34 T14 3 T21 31
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 1840 1 T2 19 T5 1 T20 3
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 2035 1 T2 31 T14 2 T18 19
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 1962 1 T2 7 T36 5 T21 2
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 21149 1 T2 13 T18 2 T25 2813
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 1756 1 T2 10 T15 1 T5 1
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 1921 1 T2 15 T14 3 T15 1
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 2494 1 T2 21 T18 28 T21 28
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 3251 1 T1 71 T5 2 T20 4
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 2645 1 T1 11 T20 3 T21 6
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 3255 1 T1 67 T2 29 T15 2
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 3829 1 T2 13 T15 2 T20 2
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 4236 1 T2 3 T15 1 T18 2
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 3767 1 T1 192 T5 5 T36 14
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 2690 1 T15 2 T21 29 T44 5
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 3786 1 T1 129 T5 2 T20 10
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 1373 1 T2 32 T14 1 T21 15
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 1360 1 T2 16 T20 1 T21 56
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1439 1 T2 33 T14 1 T18 16
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 1436 1 T2 5 T15 1 T36 9
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 14929 1 T2 17 T18 4 T25 2131
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 1002 1 T2 13 T36 17 T44 15
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1613 1 T2 13 T14 2 T15 1
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 1876 1 T2 20 T18 4 T21 10
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 2870 1 T1 68 T20 1 T21 61
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 2241 1 T1 13 T21 6 T44 1
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 2837 1 T1 76 T2 29 T15 2
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 3222 1 T2 18 T15 2 T20 2
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 3580 1 T2 8 T15 1 T18 2
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 3260 1 T1 183 T5 1 T36 17
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 2331 1 T15 2 T21 19 T52 1
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 3063 1 T1 108 T21 64 T44 1
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1561 1 T2 25 T14 1 T21 25
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1245 1 T2 9 T21 43 T52 2
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1425 1 T2 17 T15 1 T18 18
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1354 1 T2 5 T15 1 T36 5
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 10723 1 T2 9 T4 1 T18 6
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1141 1 T2 13 T15 1 T36 9
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1389 1 T2 8 T15 1 T18 3
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1668 1 T2 12 T21 26 T37 6
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 2205 1 T1 54 T21 42 T44 5
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 1777 1 T1 8 T21 7 T24 2
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 2193 1 T1 48 T2 15 T15 4
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 2869 1 T2 9 T15 4 T44 7
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3212 1 T2 8 T18 2 T21 52
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 2641 1 T1 131 T36 7 T21 50
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 1937 1 T15 1 T21 14 T52 16
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 2484 1 T1 105 T21 47 T41 99
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 904 1 T2 17 T4 1 T21 7
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 939 1 T2 6 T21 44 T37 1
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 1106 1 T2 11 T15 2 T18 18
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 888 1 T2 1 T36 3 T52 79
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 6727 1 T2 6 T18 2 T25 954
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 695 1 T2 14 T15 1 T18 1
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 1111 1 T2 8 T14 1 T15 2
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 1134 1 T2 4 T18 4 T21 4
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 1555 1 T1 39 T21 29 T44 5
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 1173 1 T1 2 T18 9 T21 6
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 1671 1 T1 39 T2 9 T15 2
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 1847 1 T2 11 T15 2 T44 6
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2303 1 T2 7 T15 1 T18 2
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 1826 1 T1 103 T36 4 T21 21
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 1410 1 T15 1 T21 6 T44 1
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 1501 1 T1 83 T21 25 T41 55

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