Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17670430	1			T1	47219		T2	19872		T3	1301
all_pins[1]	17670430	1			T1	47219		T2	19872		T3	1301
all_pins[2]	17670430	1			T1	47219		T2	19872		T3	1301

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	45121662	1			T1	125831		T2	53053		T3	3366
values[0x1]	7889628	1			T1	15826		T2	6563		T3	537
transitions[0x0=>0x1]	7889455	1			T1	15826		T2	6563		T3	537
transitions[0x1=>0x0]	7889472	1			T1	15826		T2	6563		T3	537

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17650405	1			T1	47192		T2	19843		T3	1284
all_pins[0]	values[0x1]	20025	1			T1	27		T2	29		T3	17
all_pins[0]	transitions[0x0=>0x1]	19944	1			T1	27		T2	29		T3	17
all_pins[0]	transitions[0x1=>0x0]	7869211	1			T1	15799		T2	6534		T3	520
all_pins[1]	values[0x0]	17670102	1			T1	47219		T2	19872		T3	1301
all_pins[1]	values[0x1]	328	1			T5	2		T18	3		T20	6
all_pins[1]	transitions[0x0=>0x1]	282	1			T5	2		T18	3		T20	6
all_pins[1]	transitions[0x1=>0x0]	19979	1			T1	27		T2	29		T3	17
all_pins[2]	values[0x0]	9801155	1			T1	31420		T2	13338		T3	781
all_pins[2]	values[0x1]	7869275	1			T1	15799		T2	6534		T3	520
all_pins[2]	transitions[0x0=>0x1]	7869229	1			T1	15799		T2	6534		T3	520
all_pins[2]	transitions[0x1=>0x0]	282	1			T5	1		T18	3		T20	5