Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 919 1 T5 7 T20 27 T44 10
all_values[1] 919 1 T5 7 T20 27 T44 10
all_values[2] 919 1 T5 7 T20 27 T44 10


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1435 1 T5 10 T20 41 T44 19
auto[1] 1322 1 T5 11 T20 40 T44 11


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 975 1 T5 4 T20 31 T44 4
auto[1] 1782 1 T5 17 T20 50 T44 26


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1554 1 T5 9 T20 46 T44 10
auto[1] 1203 1 T5 12 T20 35 T44 20


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 186 1 T5 2 T20 1 T41 1
all_values[0] auto[0] auto[0] auto[1] 89 1 T20 4 T44 2 T41 2
all_values[0] auto[0] auto[1] auto[0] 166 1 T5 1 T20 6 T41 7
all_values[0] auto[0] auto[1] auto[1] 90 1 T5 1 T20 2 T44 1
all_values[0] auto[1] auto[0] auto[1] 196 1 T5 3 T20 8 T44 7
all_values[0] auto[1] auto[1] auto[1] 192 1 T20 6 T41 1 T6 4
all_values[1] auto[0] auto[0] auto[0] 149 1 T20 4 T44 1 T41 2
all_values[1] auto[0] auto[0] auto[1] 114 1 T5 1 T20 3 T44 1
all_values[1] auto[0] auto[1] auto[0] 137 1 T5 1 T20 8 T41 1
all_values[1] auto[0] auto[1] auto[1] 113 1 T5 1 T20 3 T44 1
all_values[1] auto[1] auto[0] auto[1] 201 1 T5 1 T20 5 T44 5
all_values[1] auto[1] auto[1] auto[1] 205 1 T5 3 T20 4 T44 2
all_values[2] auto[0] auto[0] auto[0] 190 1 T20 5 T44 3 T41 4
all_values[2] auto[0] auto[0] auto[1] 86 1 T5 1 T20 2 T6 3
all_values[2] auto[0] auto[1] auto[0] 147 1 T20 7 T6 4 T71 6
all_values[2] auto[0] auto[1] auto[1] 87 1 T5 1 T20 1 T44 1
all_values[2] auto[1] auto[0] auto[1] 224 1 T5 2 T20 9 T41 3
all_values[2] auto[1] auto[1] auto[1] 185 1 T5 3 T20 3 T44 6


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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