Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4212	1			T1	6		T2	8		T3	5
sha2_none	4140	1			T1	6		T2	8		T3	7
sha2_512	7393	1			T1	12		T2	8		T3	3
sha2_384	7232	1			T1	6		T2	12		T3	8
sha2_256	6219	1			T1	8		T2	10		T3	7

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18445

1

T1

21

T2

22

T3

19

auto[1]

11137

1

T1

19

T2

24

T3

13

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11128

1

T1

21

T2

25

T3

12

auto[1]

18454

1

T1

19

T2

21

T3

20

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

15311

1

T1

40

T2

19

T3

12

disabled

14271

1

T2

27

T3

20

T4

29

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4582	1			T1	4		T2	8		T3	6
key_none	7696	1			T1	5		T2	10		T3	3
key_1024	4341	1			T1	7		T2	9		T3	3
key_512	3787	1			T1	6		T2	5		T3	3
key_384	3259	1			T1	6		T2	5		T3	9
key_256	2974	1			T1	7		T2	4		T3	5
key_128	2858	1			T1	5		T2	5		T3	3

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18509

1

T1

18

T2

26

T3

17

auto[1]

11073

1

T1

22

T2

20

T3

15

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

29377

1

T1

40

T2

46

T3

32

disabled

205

1

T20

5

T44

2

T45

3

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1577

1

T1

4

T2

4

T4

3

enabled

auto[0]

auto[0]

auto[1]

1544

1

T1

6

T2

2

T3

1

enabled

auto[0]

auto[1]

auto[0]

1583

1

T1

5

T2

3

T4

4

enabled

auto[0]

auto[1]

auto[1]

1628

1

T1

6

T2

1

T3

1

enabled

auto[1]

auto[0]

auto[0]

4230

1

T1

6

T2

3

T3

3

enabled

auto[1]

auto[0]

auto[1]

1567

1

T1

5

T2

1

T3

3

enabled

auto[1]

auto[1]

auto[0]

1629

1

T1

3

T2

4

T3

4

enabled

auto[1]

auto[1]

auto[1]

1553

1

T1

5

T2

1

T4

2

disabled

auto[0]

auto[0]

auto[0]

1202

1

T2

3

T3

1

T4

5

disabled

auto[0]

auto[0]

auto[1]

1195

1

T2

4

T3

3

T4

4

disabled

auto[0]

auto[1]

auto[0]

1189

1

T2

4

T3

3

T4

7

disabled

auto[0]

auto[1]

auto[1]

1210

1

T2

4

T3

3

T4

2

disabled

auto[1]

auto[0]

auto[0]

5953

1

T2

2

T3

5

T4

4

disabled

auto[1]

auto[0]

auto[1]

1177

1

T2

3

T3

3

T4

3

disabled

auto[1]

auto[1]

auto[0]

1146

1

T2

3

T3

1

T4

2

disabled

auto[1]

auto[1]

auto[1]

1199

1

T2

4

T3

1

T4

2

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

15241

1

T1

40

T2

19

T3

12

enabled

disabled

70

1

T20

1

T45

1

T41

7

disabled

disabled

135

1

T20

4

T44

2

T45

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

14136

1

T2

27

T3

20

T4

29

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1136	1			T2	1		T3	2		T4	3
key_invalid	sha2_none	821	1			T1	1		T2	1		T3	1
key_invalid	sha2_512	824	1			T2	1		T3	1		T14	1
key_invalid	sha2_384	828	1			T1	1		T2	4		T4	1
key_invalid	sha2_256	859	1			T1	1		T2	1		T3	1
key_none	sha2_invalid	492	1			T2	3		T3	1		T4	1
key_none	sha2_none	555	1			T1	2		T2	3		T3	1
key_none	sha2_512	2487	1			T15	4		T5	1		T20	8
key_none	sha2_384	2537	1			T1	1		T2	3		T3	1
key_none	sha2_256	1588	1			T1	1		T2	1		T4	1
key_1024	sha2_invalid	529	1			T1	1		T4	4		T14	3
key_1024	sha2_none	575	1			T1	1		T2	3		T14	2
key_1024	sha2_512	1722	1			T1	2		T2	2		T4	1
key_1024	sha2_384	904	1			T1	1		T2	1		T3	2
key_512	sha2_invalid	498	1			T1	2		T2	2		T14	3
key_512	sha2_none	562	1			T1	1		T4	1		T15	4
key_512	sha2_512	621	1			T1	3		T2	1		T4	1
key_512	sha2_384	1204	1			T3	2		T4	3		T15	3
key_512	sha2_256	859	1			T2	2		T3	1		T4	1
key_384	sha2_invalid	500	1			T1	1		T2	1		T3	2
key_384	sha2_none	506	1			T1	1		T2	1		T3	2
key_384	sha2_512	581	1			T1	2		T2	1		T3	1
key_384	sha2_384	586	1			T1	1		T2	1		T3	1
key_384	sha2_256	1035	1			T1	1		T2	1		T3	2
key_256	sha2_invalid	492	1			T1	1		T4	1		T5	5
key_256	sha2_none	565	1			T3	1		T15	1		T5	3
key_256	sha2_512	588	1			T1	2		T2	1		T3	1
key_256	sha2_384	572	1			T1	1		T2	2		T3	1
key_256	sha2_256	713	1			T1	3		T2	1		T3	2
key_128	sha2_invalid	538	1			T1	1		T2	1		T4	1
key_128	sha2_none	544	1			T3	2		T4	2		T15	1
key_128	sha2_512	560	1			T1	3		T2	2		T4	1
key_128	sha2_384	584	1			T1	1		T2	1		T3	1
key_128	sha2_256	588	1			T2	1		T4	1		T14	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

561

1

T1

2

T2

3

T3

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1136	1			T2	1		T3	2		T4	3
key_invalid	sha2_none	821	1			T1	1		T2	1		T3	1
key_invalid	sha2_512	824	1			T2	1		T3	1		T14	1
key_invalid	sha2_384	828	1			T1	1		T2	4		T4	1
key_invalid	sha2_256	859	1			T1	1		T2	1		T3	1
key_none	sha2_invalid	492	1			T2	3		T3	1		T4	1
key_none	sha2_none	555	1			T1	2		T2	3		T3	1
key_none	sha2_512	2487	1			T15	4		T5	1		T20	8
key_none	sha2_384	2537	1			T1	1		T2	3		T3	1
key_none	sha2_256	1588	1			T1	1		T2	1		T4	1
key_1024	sha2_invalid	529	1			T1	1		T4	4		T14	3
key_1024	sha2_none	575	1			T1	1		T2	3		T14	2
key_1024	sha2_512	1722	1			T1	2		T2	2		T4	1
key_1024	sha2_384	904	1			T1	1		T2	1		T3	2
key_1024	sha2_256	561	1			T1	2		T2	3		T3	1
key_512	sha2_invalid	498	1			T1	2		T2	2		T14	3
key_512	sha2_none	562	1			T1	1		T4	1		T15	4
key_512	sha2_512	621	1			T1	3		T2	1		T4	1
key_512	sha2_384	1204	1			T3	2		T4	3		T15	3
key_512	sha2_256	859	1			T2	2		T3	1		T4	1
key_384	sha2_invalid	500	1			T1	1		T2	1		T3	2
key_384	sha2_none	506	1			T1	1		T2	1		T3	2
key_384	sha2_512	581	1			T1	2		T2	1		T3	1
key_384	sha2_384	586	1			T1	1		T2	1		T3	1
key_384	sha2_256	1035	1			T1	1		T2	1		T3	2
key_256	sha2_invalid	492	1			T1	1		T4	1		T5	5
key_256	sha2_none	565	1			T3	1		T15	1		T5	3
key_256	sha2_512	588	1			T1	2		T2	1		T3	1
key_256	sha2_384	572	1			T1	1		T2	2		T3	1
key_256	sha2_256	713	1			T1	3		T2	1		T3	2
key_128	sha2_invalid	538	1			T1	1		T2	1		T4	1
key_128	sha2_none	544	1			T3	2		T4	2		T15	1
key_128	sha2_512	560	1			T1	3		T2	2		T4	1
key_128	sha2_384	584	1			T1	1		T2	1		T3	1
key_128	sha2_256	588	1			T2	1		T4	1		T14	1