Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.58 95.95 94.24 100.00 87.18 92.33 99.49 99.85


Total test records in report: 660
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html
T107 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2190884946 Jul 04 05:21:45 PM PDT 24 Jul 04 05:21:47 PM PDT 24 101216923 ps
T535 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1841214830 Jul 04 05:21:57 PM PDT 24 Jul 04 05:22:02 PM PDT 24 156944188 ps
T536 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1593460784 Jul 04 05:22:04 PM PDT 24 Jul 04 05:22:06 PM PDT 24 159390635 ps
T537 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1576457061 Jul 04 05:21:50 PM PDT 24 Jul 04 05:21:53 PM PDT 24 69707256 ps
T108 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2486898899 Jul 04 05:22:06 PM PDT 24 Jul 04 05:22:08 PM PDT 24 582154451 ps
T57 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1725354942 Jul 04 05:21:53 PM PDT 24 Jul 04 05:21:57 PM PDT 24 220486273 ps
T94 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.833864508 Jul 04 05:21:48 PM PDT 24 Jul 04 05:21:54 PM PDT 24 452721198 ps
T58 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1713676279 Jul 04 05:21:50 PM PDT 24 Jul 04 05:21:54 PM PDT 24 236131778 ps
T538 /workspace/coverage/cover_reg_top/47.hmac_intr_test.406059871 Jul 04 05:22:15 PM PDT 24 Jul 04 05:22:16 PM PDT 24 23085365 ps
T95 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2689610630 Jul 04 05:22:06 PM PDT 24 Jul 04 05:22:07 PM PDT 24 111120151 ps
T539 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1997162292 Jul 04 05:22:03 PM PDT 24 Jul 04 05:22:05 PM PDT 24 27015377 ps
T540 /workspace/coverage/cover_reg_top/14.hmac_intr_test.165595151 Jul 04 05:22:03 PM PDT 24 Jul 04 05:22:04 PM PDT 24 39467848 ps
T541 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3526310955 Jul 04 05:22:05 PM PDT 24 Jul 04 05:22:08 PM PDT 24 92214232 ps
T109 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.4079876028 Jul 04 05:21:50 PM PDT 24 Jul 04 05:21:52 PM PDT 24 208078065 ps
T542 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3610631728 Jul 04 05:22:15 PM PDT 24 Jul 04 05:22:16 PM PDT 24 40347717 ps
T96 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3078239031 Jul 04 05:21:43 PM PDT 24 Jul 04 05:21:44 PM PDT 24 23708582 ps
T543 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1571105682 Jul 04 05:22:00 PM PDT 24 Jul 04 05:22:02 PM PDT 24 261804628 ps
T59 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3527550839 Jul 04 05:22:05 PM PDT 24 Jul 04 05:22:10 PM PDT 24 930305025 ps
T544 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.4221821852 Jul 04 05:21:43 PM PDT 24 Jul 04 05:21:54 PM PDT 24 741270431 ps
T545 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1509834343 Jul 04 05:22:04 PM PDT 24 Jul 04 05:22:06 PM PDT 24 227032447 ps
T125 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.475134619 Jul 04 05:21:43 PM PDT 24 Jul 04 05:21:46 PM PDT 24 194808578 ps
T546 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2507687118 Jul 04 05:22:13 PM PDT 24 Jul 04 05:22:14 PM PDT 24 42911085 ps
T547 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3592338772 Jul 04 05:21:41 PM PDT 24 Jul 04 05:21:44 PM PDT 24 230034854 ps
T548 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.10165100 Jul 04 05:21:57 PM PDT 24 Jul 04 05:21:59 PM PDT 24 187295984 ps
T549 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2210022375 Jul 04 05:22:06 PM PDT 24 Jul 04 05:22:10 PM PDT 24 498626474 ps
T117 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1824633094 Jul 04 05:21:59 PM PDT 24 Jul 04 05:22:02 PM PDT 24 329729143 ps
T550 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2082234063 Jul 04 05:22:06 PM PDT 24 Jul 04 05:22:07 PM PDT 24 25447827 ps
T551 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.337793919 Jul 04 05:22:05 PM PDT 24 Jul 04 05:22:06 PM PDT 24 62276374 ps
T97 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3863966266 Jul 04 05:22:03 PM PDT 24 Jul 04 05:22:04 PM PDT 24 12371060 ps
T552 /workspace/coverage/cover_reg_top/30.hmac_intr_test.442799372 Jul 04 05:22:12 PM PDT 24 Jul 04 05:22:13 PM PDT 24 22790426 ps
T553 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1892596417 Jul 04 05:21:50 PM PDT 24 Jul 04 05:21:51 PM PDT 24 108028976 ps
T110 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1098846639 Jul 04 05:21:48 PM PDT 24 Jul 04 05:21:49 PM PDT 24 223544593 ps
T111 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2301786120 Jul 04 05:22:07 PM PDT 24 Jul 04 05:22:09 PM PDT 24 163307893 ps
T118 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.4083157783 Jul 04 05:22:07 PM PDT 24 Jul 04 05:22:12 PM PDT 24 538048644 ps
T115 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.853069863 Jul 04 05:21:56 PM PDT 24 Jul 04 05:22:00 PM PDT 24 662035120 ps
T554 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1832924466 Jul 04 05:22:06 PM PDT 24 Jul 04 05:22:07 PM PDT 24 13002493 ps
T555 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3840260424 Jul 04 05:21:52 PM PDT 24 Jul 04 05:21:56 PM PDT 24 205385655 ps
T119 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.495364224 Jul 04 05:22:04 PM PDT 24 Jul 04 05:22:08 PM PDT 24 218296765 ps
T556 /workspace/coverage/cover_reg_top/40.hmac_intr_test.766991043 Jul 04 05:22:16 PM PDT 24 Jul 04 05:22:17 PM PDT 24 35441241 ps
T98 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.181645197 Jul 04 05:21:51 PM PDT 24 Jul 04 05:21:57 PM PDT 24 2956774033 ps
T99 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.586868943 Jul 04 05:21:45 PM PDT 24 Jul 04 05:21:46 PM PDT 24 56368471 ps
T557 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.824786387 Jul 04 05:22:04 PM PDT 24 Jul 04 05:22:09 PM PDT 24 116321646 ps
T112 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1972973806 Jul 04 05:21:55 PM PDT 24 Jul 04 05:21:56 PM PDT 24 124430555 ps
T120 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.996174237 Jul 04 05:21:44 PM PDT 24 Jul 04 05:21:48 PM PDT 24 282284768 ps
T124 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3833853851 Jul 04 05:21:44 PM PDT 24 Jul 04 05:21:48 PM PDT 24 1438158244 ps
T113 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3634555072 Jul 04 05:22:06 PM PDT 24 Jul 04 05:22:09 PM PDT 24 271594834 ps
T558 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.395479278 Jul 04 05:21:50 PM PDT 24 Jul 04 05:21:51 PM PDT 24 119550115 ps
T559 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3168559161 Jul 04 05:21:54 PM PDT 24 Jul 04 05:21:55 PM PDT 24 37938591 ps
T560 /workspace/coverage/cover_reg_top/34.hmac_intr_test.677860924 Jul 04 05:22:13 PM PDT 24 Jul 04 05:22:14 PM PDT 24 29696604 ps
T561 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1312032770 Jul 04 05:22:15 PM PDT 24 Jul 04 05:22:16 PM PDT 24 46068115 ps
T100 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3215004664 Jul 04 05:21:42 PM PDT 24 Jul 04 05:21:45 PM PDT 24 113959034 ps
T121 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1429812135 Jul 04 05:21:56 PM PDT 24 Jul 04 05:22:00 PM PDT 24 2198601675 ps
T562 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.370456738 Jul 04 05:21:42 PM PDT 24 Jul 04 05:21:45 PM PDT 24 76599793 ps
T122 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2837990264 Jul 04 05:22:07 PM PDT 24 Jul 04 05:22:12 PM PDT 24 583025092 ps
T563 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3900815272 Jul 04 05:22:07 PM PDT 24 Jul 04 05:22:11 PM PDT 24 55002270 ps
T564 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.268551229 Jul 04 05:21:42 PM PDT 24 Jul 04 05:21:57 PM PDT 24 1056753789 ps
T565 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1372481838 Jul 04 05:21:43 PM PDT 24 Jul 04 05:21:45 PM PDT 24 96753576 ps
T566 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3820737761 Jul 04 05:21:50 PM PDT 24 Jul 04 05:21:53 PM PDT 24 98447746 ps
T567 /workspace/coverage/cover_reg_top/20.hmac_intr_test.3290802637 Jul 04 05:22:03 PM PDT 24 Jul 04 05:22:04 PM PDT 24 59979741 ps
T101 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3227951106 Jul 04 05:21:42 PM PDT 24 Jul 04 05:21:56 PM PDT 24 1799768118 ps
T102 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1219476745 Jul 04 05:21:42 PM PDT 24 Jul 04 05:21:43 PM PDT 24 44508225 ps
T116 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1415001445 Jul 04 05:21:51 PM PDT 24 Jul 04 05:21:56 PM PDT 24 1154481289 ps
T103 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2277795979 Jul 04 05:21:49 PM PDT 24 Jul 04 05:21:50 PM PDT 24 31088869 ps
T568 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3679721180 Jul 04 05:21:55 PM PDT 24 Jul 04 05:21:57 PM PDT 24 225204151 ps
T569 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1728879130 Jul 04 05:21:41 PM PDT 24 Jul 04 05:21:42 PM PDT 24 33562654 ps
T570 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1220026137 Jul 04 05:22:14 PM PDT 24 Jul 04 05:22:15 PM PDT 24 55613584 ps
T571 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3431191422 Jul 04 05:21:43 PM PDT 24 Jul 04 05:21:45 PM PDT 24 43278962 ps
T104 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2389595864 Jul 04 05:21:43 PM PDT 24 Jul 04 05:21:44 PM PDT 24 12003609 ps
T572 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2557164171 Jul 04 05:22:15 PM PDT 24 Jul 04 05:22:16 PM PDT 24 58220617 ps
T573 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2982453813 Jul 04 05:22:16 PM PDT 24 Jul 04 05:22:17 PM PDT 24 17580290 ps
T574 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3862579891 Jul 04 05:21:57 PM PDT 24 Jul 04 05:21:57 PM PDT 24 41302054 ps
T575 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3922053161 Jul 04 05:21:41 PM PDT 24 Jul 04 05:21:45 PM PDT 24 286629130 ps
T576 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3156693364 Jul 04 05:22:07 PM PDT 24 Jul 04 05:22:08 PM PDT 24 15036452 ps
T105 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3579769900 Jul 04 05:22:05 PM PDT 24 Jul 04 05:22:06 PM PDT 24 23459706 ps
T577 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1791164700 Jul 04 05:22:14 PM PDT 24 Jul 04 05:22:15 PM PDT 24 25471630 ps
T578 /workspace/coverage/cover_reg_top/26.hmac_intr_test.2649965613 Jul 04 05:22:12 PM PDT 24 Jul 04 05:22:13 PM PDT 24 13969626 ps
T579 /workspace/coverage/cover_reg_top/39.hmac_intr_test.804682269 Jul 04 05:22:12 PM PDT 24 Jul 04 05:22:13 PM PDT 24 35063301 ps
T580 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.799735030 Jul 04 05:21:58 PM PDT 24 Jul 04 05:22:00 PM PDT 24 228979194 ps
T581 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1837532985 Jul 04 05:21:51 PM PDT 24 Jul 04 05:21:53 PM PDT 24 406821228 ps
T106 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1507866662 Jul 04 05:21:56 PM PDT 24 Jul 04 05:21:57 PM PDT 24 46924404 ps
T582 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2324088287 Jul 04 05:21:57 PM PDT 24 Jul 04 05:21:59 PM PDT 24 43905154 ps
T583 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1040884173 Jul 04 05:21:42 PM PDT 24 Jul 04 05:21:43 PM PDT 24 37455340 ps
T584 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.390407379 Jul 04 05:22:01 PM PDT 24 Jul 04 05:22:02 PM PDT 24 16515362 ps
T585 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3408336424 Jul 04 05:21:56 PM PDT 24 Jul 04 05:21:58 PM PDT 24 64128154 ps
T586 /workspace/coverage/cover_reg_top/23.hmac_intr_test.158809547 Jul 04 05:22:14 PM PDT 24 Jul 04 05:22:15 PM PDT 24 30520692 ps
T587 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2480129551 Jul 04 05:22:05 PM PDT 24 Jul 04 05:22:07 PM PDT 24 48827934 ps
T588 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1946740729 Jul 04 05:21:55 PM PDT 24 Jul 04 05:22:00 PM PDT 24 227440890 ps
T589 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2192236875 Jul 04 05:21:39 PM PDT 24 Jul 04 05:21:41 PM PDT 24 1103268744 ps
T590 /workspace/coverage/cover_reg_top/17.hmac_intr_test.203249587 Jul 04 05:22:03 PM PDT 24 Jul 04 05:22:04 PM PDT 24 12739034 ps
T591 /workspace/coverage/cover_reg_top/18.hmac_intr_test.352502270 Jul 04 05:22:03 PM PDT 24 Jul 04 05:22:03 PM PDT 24 16329374 ps
T592 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3650241860 Jul 04 05:21:59 PM PDT 24 Jul 04 05:22:00 PM PDT 24 22903393 ps
T593 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1756915074 Jul 04 05:21:52 PM PDT 24 Jul 04 05:21:54 PM PDT 24 63374015 ps
T594 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2285759441 Jul 04 05:22:14 PM PDT 24 Jul 04 05:22:15 PM PDT 24 21637934 ps
T595 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3733487012 Jul 04 05:22:11 PM PDT 24 Jul 04 05:22:12 PM PDT 24 16814521 ps
T596 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1880789502 Jul 04 05:21:43 PM PDT 24 Jul 04 05:21:44 PM PDT 24 25644441 ps
T597 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2557466432 Jul 04 05:21:56 PM PDT 24 Jul 04 05:21:58 PM PDT 24 139493613 ps
T598 /workspace/coverage/cover_reg_top/10.hmac_intr_test.3765584220 Jul 04 05:21:59 PM PDT 24 Jul 04 05:22:00 PM PDT 24 40072814 ps
T123 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1908276201 Jul 04 05:21:39 PM PDT 24 Jul 04 05:21:43 PM PDT 24 726833313 ps
T599 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1004364657 Jul 04 05:21:42 PM PDT 24 Jul 04 05:21:44 PM PDT 24 15396787 ps
T600 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3941725219 Jul 04 05:22:04 PM PDT 24 Jul 04 05:22:06 PM PDT 24 103235415 ps
T601 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2609099638 Jul 04 05:21:50 PM PDT 24 Jul 04 05:21:51 PM PDT 24 35849802 ps
T602 /workspace/coverage/cover_reg_top/46.hmac_intr_test.32472312 Jul 04 05:22:14 PM PDT 24 Jul 04 05:22:15 PM PDT 24 93630459 ps
T603 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.964983630 Jul 04 05:21:56 PM PDT 24 Jul 04 05:21:58 PM PDT 24 44052017 ps
T604 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2025219176 Jul 04 05:22:04 PM PDT 24 Jul 04 05:22:06 PM PDT 24 64828567 ps
T605 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.587123602 Jul 04 05:21:43 PM PDT 24 Jul 04 05:33:41 PM PDT 24 261326296102 ps
T606 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3320810750 Jul 04 05:21:44 PM PDT 24 Jul 04 05:21:47 PM PDT 24 181385548 ps
T607 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2977403843 Jul 04 05:21:56 PM PDT 24 Jul 04 05:21:57 PM PDT 24 40048709 ps
T608 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2268777809 Jul 04 05:21:36 PM PDT 24 Jul 04 05:21:38 PM PDT 24 110390824 ps
T609 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3867715737 Jul 04 05:21:50 PM PDT 24 Jul 04 05:21:53 PM PDT 24 107714099 ps
T610 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2023394181 Jul 04 05:22:13 PM PDT 24 Jul 04 05:22:14 PM PDT 24 16774837 ps
T611 /workspace/coverage/cover_reg_top/19.hmac_intr_test.3105265724 Jul 04 05:22:04 PM PDT 24 Jul 04 05:22:04 PM PDT 24 10784965 ps
T612 /workspace/coverage/cover_reg_top/33.hmac_intr_test.793711755 Jul 04 05:22:12 PM PDT 24 Jul 04 05:22:13 PM PDT 24 18550612 ps
T613 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3465533137 Jul 04 05:21:57 PM PDT 24 Jul 04 05:21:58 PM PDT 24 53706268 ps
T614 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3809747752 Jul 04 05:22:05 PM PDT 24 Jul 04 05:22:07 PM PDT 24 170877938 ps
T615 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.890350920 Jul 04 05:21:56 PM PDT 24 Jul 04 05:21:58 PM PDT 24 85605955 ps
T616 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2899352599 Jul 04 05:21:49 PM PDT 24 Jul 04 05:21:50 PM PDT 24 36109758 ps
T617 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2789772346 Jul 04 05:22:04 PM PDT 24 Jul 04 05:22:07 PM PDT 24 47912666 ps
T618 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2832201345 Jul 04 05:21:42 PM PDT 24 Jul 04 05:21:44 PM PDT 24 40334935 ps
T619 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3160144728 Jul 04 05:22:16 PM PDT 24 Jul 04 05:22:17 PM PDT 24 12834933 ps
T620 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3024273504 Jul 04 05:22:05 PM PDT 24 Jul 04 05:22:06 PM PDT 24 15154100 ps
T621 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4123405391 Jul 04 05:22:06 PM PDT 24 Jul 04 05:22:07 PM PDT 24 80085214 ps
T622 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.85254647 Jul 04 05:21:41 PM PDT 24 Jul 04 05:21:51 PM PDT 24 412635909 ps
T623 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3185981540 Jul 04 05:21:49 PM PDT 24 Jul 04 05:21:51 PM PDT 24 169951407 ps
T624 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2923499409 Jul 04 05:22:04 PM PDT 24 Jul 04 05:22:05 PM PDT 24 15591289 ps
T625 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1304465781 Jul 04 05:21:56 PM PDT 24 Jul 04 05:26:39 PM PDT 24 109507241696 ps
T626 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1279387356 Jul 04 05:22:02 PM PDT 24 Jul 04 05:22:04 PM PDT 24 98059229 ps
T627 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3797634094 Jul 04 05:21:54 PM PDT 24 Jul 04 05:21:55 PM PDT 24 16562467 ps
T628 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1118462584 Jul 04 05:22:06 PM PDT 24 Jul 04 05:22:07 PM PDT 24 20615209 ps
T629 /workspace/coverage/cover_reg_top/9.hmac_intr_test.865242347 Jul 04 05:21:57 PM PDT 24 Jul 04 05:21:58 PM PDT 24 14754819 ps
T630 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.316169866 Jul 04 05:21:56 PM PDT 24 Jul 04 05:21:57 PM PDT 24 30214519 ps
T631 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3434169022 Jul 04 05:21:58 PM PDT 24 Jul 04 05:22:00 PM PDT 24 190250118 ps
T632 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1452547482 Jul 04 05:21:56 PM PDT 24 Jul 04 05:21:57 PM PDT 24 98304860 ps
T633 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2631426890 Jul 04 05:21:42 PM PDT 24 Jul 04 05:21:44 PM PDT 24 20932762 ps
T634 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1626246514 Jul 04 05:22:05 PM PDT 24 Jul 04 05:22:06 PM PDT 24 66512190 ps
T635 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3137876178 Jul 04 05:22:04 PM PDT 24 Jul 04 05:22:06 PM PDT 24 53336219 ps
T636 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2547478464 Jul 04 05:21:50 PM PDT 24 Jul 04 05:21:52 PM PDT 24 1103229346 ps
T637 /workspace/coverage/cover_reg_top/2.hmac_intr_test.3364522002 Jul 04 05:21:46 PM PDT 24 Jul 04 05:21:46 PM PDT 24 14223477 ps
T638 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1114290006 Jul 04 05:22:10 PM PDT 24 Jul 04 05:22:11 PM PDT 24 10975119 ps
T639 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4217118219 Jul 04 05:21:46 PM PDT 24 Jul 04 05:21:49 PM PDT 24 63011152 ps
T640 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3283275492 Jul 04 05:22:00 PM PDT 24 Jul 04 05:22:01 PM PDT 24 21041811 ps
T641 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1519070492 Jul 04 05:22:14 PM PDT 24 Jul 04 05:22:15 PM PDT 24 29809155 ps
T642 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2093161932 Jul 04 05:21:44 PM PDT 24 Jul 04 05:21:46 PM PDT 24 424652123 ps
T643 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2874613226 Jul 04 05:22:12 PM PDT 24 Jul 04 05:22:13 PM PDT 24 45821154 ps
T644 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.306841592 Jul 04 05:22:07 PM PDT 24 Jul 04 05:22:09 PM PDT 24 100373274 ps
T645 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.818933788 Jul 04 05:21:51 PM PDT 24 Jul 04 05:21:55 PM PDT 24 51861018 ps
T646 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1899019897 Jul 04 05:21:44 PM PDT 24 Jul 04 05:21:46 PM PDT 24 28721439 ps
T647 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3858403493 Jul 04 05:22:12 PM PDT 24 Jul 04 05:22:13 PM PDT 24 17116735 ps
T648 /workspace/coverage/cover_reg_top/24.hmac_intr_test.118498004 Jul 04 05:22:14 PM PDT 24 Jul 04 05:22:15 PM PDT 24 15380082 ps
T649 /workspace/coverage/cover_reg_top/7.hmac_intr_test.4209591619 Jul 04 05:21:55 PM PDT 24 Jul 04 05:21:56 PM PDT 24 11820739 ps
T650 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3387667344 Jul 04 05:22:05 PM PDT 24 Jul 04 05:22:07 PM PDT 24 182995223 ps
T651 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.14868867 Jul 04 05:21:40 PM PDT 24 Jul 04 05:21:43 PM PDT 24 341273901 ps
T652 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3438344364 Jul 04 05:21:59 PM PDT 24 Jul 04 05:22:02 PM PDT 24 111435075 ps
T653 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1988258547 Jul 04 05:22:00 PM PDT 24 Jul 04 05:22:05 PM PDT 24 548800267 ps
T654 /workspace/coverage/cover_reg_top/31.hmac_intr_test.425735469 Jul 04 05:22:13 PM PDT 24 Jul 04 05:22:14 PM PDT 24 13414365 ps
T655 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3774944181 Jul 04 05:22:04 PM PDT 24 Jul 04 05:22:05 PM PDT 24 28688663 ps
T656 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4050738252 Jul 04 05:21:49 PM PDT 24 Jul 04 05:21:51 PM PDT 24 138348807 ps
T657 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2049442111 Jul 04 05:22:06 PM PDT 24 Jul 04 05:22:07 PM PDT 24 20436178 ps
T658 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2380736834 Jul 04 05:21:42 PM PDT 24 Jul 04 05:21:45 PM PDT 24 32811822 ps
T659 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2785625265 Jul 04 05:21:41 PM PDT 24 Jul 04 05:21:42 PM PDT 24 22371796 ps
T660 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3943063102 Jul 04 05:22:03 PM PDT 24 Jul 04 05:22:07 PM PDT 24 460546710 ps

Test location /workspace/coverage/default/40.hmac_back_pressure.4221127428
Short name T4
Test name
Test status
Simulation time 5489401704 ps
CPU time 76.38 seconds
Started Jul 04 05:23:56 PM PDT 24
Finished Jul 04 05:25:12 PM PDT 24
Peak memory 208588 kb
Host smart-16aa8440-0141-4608-a113-7dd408229884
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4221127428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.4221127428
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.1315347743
Short name T6
Test name
Test status
Simulation time 28076987367 ps
CPU time 2354.41 seconds
Started Jul 04 05:22:32 PM PDT 24
Finished Jul 04 06:01:46 PM PDT 24
Peak memory 731140 kb
Host smart-73b71c27-4598-43f3-b001-d660f1bd0901
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1315347743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.1315347743
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1829549858
Short name T44
Test name
Test status
Simulation time 102783388745 ps
CPU time 1161.49 seconds
Started Jul 04 05:23:44 PM PDT 24
Finished Jul 04 05:43:06 PM PDT 24
Peak memory 680036 kb
Host smart-506c6e9d-e5aa-4448-aef8-875d0161bdb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829549858 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1829549858
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.4168511141
Short name T22
Test name
Test status
Simulation time 16836539305 ps
CPU time 1533.24 seconds
Started Jul 04 05:22:23 PM PDT 24
Finished Jul 04 05:47:57 PM PDT 24
Peak memory 745096 kb
Host smart-681c43bc-2b9f-4dc3-9cb2-7cd4e0c81070
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4168511141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.4168511141
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1725354942
Short name T57
Test name
Test status
Simulation time 220486273 ps
CPU time 4.33 seconds
Started Jul 04 05:21:53 PM PDT 24
Finished Jul 04 05:21:57 PM PDT 24
Peak memory 200284 kb
Host smart-3e3c69f1-dbfb-47ea-830f-6b0bf708bd11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725354942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1725354942
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1512772901
Short name T41
Test name
Test status
Simulation time 19907004657 ps
CPU time 1207.83 seconds
Started Jul 04 05:22:30 PM PDT 24
Finished Jul 04 05:42:38 PM PDT 24
Peak memory 651748 kb
Host smart-9c2dc25a-da0c-4e68-b97f-177249993287
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512772901 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1512772901
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3409155439
Short name T47
Test name
Test status
Simulation time 229259574 ps
CPU time 0.96 seconds
Started Jul 04 05:22:18 PM PDT 24
Finished Jul 04 05:22:20 PM PDT 24
Peak memory 218292 kb
Host smart-d00dc432-586e-4e57-b0ba-50f60a14981b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409155439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3409155439
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.3072224420
Short name T23
Test name
Test status
Simulation time 58487070928 ps
CPU time 1807.29 seconds
Started Jul 04 05:22:15 PM PDT 24
Finished Jul 04 05:52:23 PM PDT 24
Peak memory 744392 kb
Host smart-aa2473de-eadf-4ea6-9ac5-7af782ff034f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3072224420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.3072224420
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3863966266
Short name T97
Test name
Test status
Simulation time 12371060 ps
CPU time 0.69 seconds
Started Jul 04 05:22:03 PM PDT 24
Finished Jul 04 05:22:04 PM PDT 24
Peak memory 198036 kb
Host smart-a39c784f-7d76-46a0-a3bc-5e6df142714b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863966266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3863966266
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2384052987
Short name T9
Test name
Test status
Simulation time 1624556241 ps
CPU time 64.25 seconds
Started Jul 04 05:22:43 PM PDT 24
Finished Jul 04 05:23:48 PM PDT 24
Peak memory 200344 kb
Host smart-3c5ef83b-f57f-47ff-9a2f-45ba24b1bcbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2384052987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2384052987
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_stress_all.4215896954
Short name T71
Test name
Test status
Simulation time 451828098463 ps
CPU time 1636.7 seconds
Started Jul 04 05:22:45 PM PDT 24
Finished Jul 04 05:50:02 PM PDT 24
Peak memory 699812 kb
Host smart-9207721b-c9a5-444d-821d-612369be1131
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215896954 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.4215896954
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2535406989
Short name T2
Test name
Test status
Simulation time 7628886682 ps
CPU time 96.09 seconds
Started Jul 04 05:23:38 PM PDT 24
Finished Jul 04 05:25:14 PM PDT 24
Peak memory 200336 kb
Host smart-8da30f9e-eb61-4c2c-b5c9-fc2a76bb0efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535406989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2535406989
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.996174237
Short name T120
Test name
Test status
Simulation time 282284768 ps
CPU time 4.36 seconds
Started Jul 04 05:21:44 PM PDT 24
Finished Jul 04 05:21:48 PM PDT 24
Peak memory 200256 kb
Host smart-554a953a-491c-44f8-81d6-8831518b6ecd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996174237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.996174237
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2396478269
Short name T151
Test name
Test status
Simulation time 22139317 ps
CPU time 0.57 seconds
Started Jul 04 05:22:18 PM PDT 24
Finished Jul 04 05:22:19 PM PDT 24
Peak memory 195164 kb
Host smart-bfb237b2-d1a0-4203-9f2c-f8f1dccc8b11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396478269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2396478269
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1396685902
Short name T21
Test name
Test status
Simulation time 22538238924 ps
CPU time 495.92 seconds
Started Jul 04 05:22:44 PM PDT 24
Finished Jul 04 05:31:01 PM PDT 24
Peak memory 416252 kb
Host smart-dc0468b1-9b63-4800-bac1-dbf978029287
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396685902 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1396685902
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.3721211772
Short name T13
Test name
Test status
Simulation time 229981409098 ps
CPU time 3512.5 seconds
Started Jul 04 05:22:26 PM PDT 24
Finished Jul 04 06:20:59 PM PDT 24
Peak memory 782136 kb
Host smart-91ef71e5-5498-4d36-837f-f4911468eb6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3721211772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.3721211772
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.951386550
Short name T39
Test name
Test status
Simulation time 2788674062 ps
CPU time 36.38 seconds
Started Jul 04 05:22:14 PM PDT 24
Finished Jul 04 05:22:50 PM PDT 24
Peak memory 200324 kb
Host smart-86dbad2c-41a7-4f1b-93c8-df2811a1c45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951386550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.951386550
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3320810750
Short name T606
Test name
Test status
Simulation time 181385548 ps
CPU time 3.16 seconds
Started Jul 04 05:21:44 PM PDT 24
Finished Jul 04 05:21:47 PM PDT 24
Peak memory 200220 kb
Host smart-c8b1f595-5107-424e-8496-5e437ab57806
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320810750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3320810750
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.85254647
Short name T622
Test name
Test status
Simulation time 412635909 ps
CPU time 9.59 seconds
Started Jul 04 05:21:41 PM PDT 24
Finished Jul 04 05:21:51 PM PDT 24
Peak memory 200240 kb
Host smart-c50a1765-6817-474e-97d5-3a3015da87e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85254647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.85254647
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3078239031
Short name T96
Test name
Test status
Simulation time 23708582 ps
CPU time 0.94 seconds
Started Jul 04 05:21:43 PM PDT 24
Finished Jul 04 05:21:44 PM PDT 24
Peak memory 200148 kb
Host smart-053f8aef-9585-4515-9728-50f45ef2ffd4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078239031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3078239031
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2192236875
Short name T589
Test name
Test status
Simulation time 1103268744 ps
CPU time 1.71 seconds
Started Jul 04 05:21:39 PM PDT 24
Finished Jul 04 05:21:41 PM PDT 24
Peak memory 200264 kb
Host smart-fc911b85-bf1c-4973-8cca-004263e34f9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192236875 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2192236875
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2389595864
Short name T104
Test name
Test status
Simulation time 12003609 ps
CPU time 0.67 seconds
Started Jul 04 05:21:43 PM PDT 24
Finished Jul 04 05:21:44 PM PDT 24
Peak memory 198040 kb
Host smart-21f30058-fac7-4abf-8de8-fa272912782a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389595864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2389595864
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2785625265
Short name T659
Test name
Test status
Simulation time 22371796 ps
CPU time 0.57 seconds
Started Jul 04 05:21:41 PM PDT 24
Finished Jul 04 05:21:42 PM PDT 24
Peak memory 195136 kb
Host smart-3358ee77-0d82-487d-be0a-febde30a0892
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785625265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2785625265
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2093161932
Short name T642
Test name
Test status
Simulation time 424652123 ps
CPU time 1.81 seconds
Started Jul 04 05:21:44 PM PDT 24
Finished Jul 04 05:21:46 PM PDT 24
Peak memory 200096 kb
Host smart-9f6e7828-8e04-4f03-937d-469f0981a843
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093161932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2093161932
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2268777809
Short name T608
Test name
Test status
Simulation time 110390824 ps
CPU time 1.57 seconds
Started Jul 04 05:21:36 PM PDT 24
Finished Jul 04 05:21:38 PM PDT 24
Peak memory 200252 kb
Host smart-9e5320bc-52d7-43e7-bb11-74100e47ec2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268777809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2268777809
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1908276201
Short name T123
Test name
Test status
Simulation time 726833313 ps
CPU time 4.38 seconds
Started Jul 04 05:21:39 PM PDT 24
Finished Jul 04 05:21:43 PM PDT 24
Peak memory 200256 kb
Host smart-18a38dc9-6a45-4086-8bce-adac61584a69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908276201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1908276201
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3215004664
Short name T100
Test name
Test status
Simulation time 113959034 ps
CPU time 3.12 seconds
Started Jul 04 05:21:42 PM PDT 24
Finished Jul 04 05:21:45 PM PDT 24
Peak memory 200076 kb
Host smart-22f018a9-c788-4004-8e35-a05af70eaa6c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215004664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3215004664
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.4221821852
Short name T544
Test name
Test status
Simulation time 741270431 ps
CPU time 10.82 seconds
Started Jul 04 05:21:43 PM PDT 24
Finished Jul 04 05:21:54 PM PDT 24
Peak memory 199316 kb
Host smart-01109789-7a8b-4374-8a78-12be9772a3c8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221821852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.4221821852
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1219476745
Short name T102
Test name
Test status
Simulation time 44508225 ps
CPU time 0.74 seconds
Started Jul 04 05:21:42 PM PDT 24
Finished Jul 04 05:21:43 PM PDT 24
Peak memory 198456 kb
Host smart-b6746132-699f-418a-8bf0-9392b0d31032
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219476745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1219476745
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.14868867
Short name T651
Test name
Test status
Simulation time 341273901 ps
CPU time 2.35 seconds
Started Jul 04 05:21:40 PM PDT 24
Finished Jul 04 05:21:43 PM PDT 24
Peak memory 200372 kb
Host smart-0629f0f5-1f61-48cb-afc8-6b0f18f410df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14868867 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.14868867
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1040884173
Short name T583
Test name
Test status
Simulation time 37455340 ps
CPU time 0.88 seconds
Started Jul 04 05:21:42 PM PDT 24
Finished Jul 04 05:21:43 PM PDT 24
Peak memory 200020 kb
Host smart-59479dc6-09a6-463e-b20b-c89df3760a92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040884173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1040884173
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1004364657
Short name T599
Test name
Test status
Simulation time 15396787 ps
CPU time 0.59 seconds
Started Jul 04 05:21:42 PM PDT 24
Finished Jul 04 05:21:44 PM PDT 24
Peak memory 195264 kb
Host smart-48a41027-cf57-40ea-8423-0bebfaa89003
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004364657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1004364657
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.1372481838
Short name T565
Test name
Test status
Simulation time 96753576 ps
CPU time 1.7 seconds
Started Jul 04 05:21:43 PM PDT 24
Finished Jul 04 05:21:45 PM PDT 24
Peak memory 200544 kb
Host smart-9d2fb9fe-f031-4459-aa52-e4491d60ac14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372481838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.1372481838
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1899019897
Short name T646
Test name
Test status
Simulation time 28721439 ps
CPU time 1.38 seconds
Started Jul 04 05:21:44 PM PDT 24
Finished Jul 04 05:21:46 PM PDT 24
Peak memory 200276 kb
Host smart-a29c4e1f-ee0b-45a0-b7a1-f8db373af72e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899019897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1899019897
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3833853851
Short name T124
Test name
Test status
Simulation time 1438158244 ps
CPU time 4 seconds
Started Jul 04 05:21:44 PM PDT 24
Finished Jul 04 05:21:48 PM PDT 24
Peak memory 200316 kb
Host smart-1caf48bf-7a9f-447e-b9a5-96313579befe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833853851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3833853851
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2324088287
Short name T582
Test name
Test status
Simulation time 43905154 ps
CPU time 1.43 seconds
Started Jul 04 05:21:57 PM PDT 24
Finished Jul 04 05:21:59 PM PDT 24
Peak memory 200300 kb
Host smart-9718237a-6730-46cb-b9a1-2be6b94c8e71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324088287 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2324088287
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.316169866
Short name T630
Test name
Test status
Simulation time 30214519 ps
CPU time 0.9 seconds
Started Jul 04 05:21:56 PM PDT 24
Finished Jul 04 05:21:57 PM PDT 24
Peak memory 199900 kb
Host smart-fc720ce4-4772-4751-a4a4-c0e1b9f8d4da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316169866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.316169866
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3765584220
Short name T598
Test name
Test status
Simulation time 40072814 ps
CPU time 0.58 seconds
Started Jul 04 05:21:59 PM PDT 24
Finished Jul 04 05:22:00 PM PDT 24
Peak memory 195252 kb
Host smart-7a16cccd-6ff8-45e0-a556-edede37cff3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765584220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3765584220
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3434169022
Short name T631
Test name
Test status
Simulation time 190250118 ps
CPU time 2.25 seconds
Started Jul 04 05:21:58 PM PDT 24
Finished Jul 04 05:22:00 PM PDT 24
Peak memory 200172 kb
Host smart-614b2974-8577-4748-813a-229e8c74f1fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434169022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3434169022
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.890350920
Short name T615
Test name
Test status
Simulation time 85605955 ps
CPU time 1.79 seconds
Started Jul 04 05:21:56 PM PDT 24
Finished Jul 04 05:21:58 PM PDT 24
Peak memory 200200 kb
Host smart-d0adbf9e-7406-4d18-a3cc-b9ca61e66534
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890350920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.890350920
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.10165100
Short name T548
Test name
Test status
Simulation time 187295984 ps
CPU time 1.69 seconds
Started Jul 04 05:21:57 PM PDT 24
Finished Jul 04 05:21:59 PM PDT 24
Peak memory 200316 kb
Host smart-f02fe403-64e6-4d78-8db3-60c9eaaa427b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10165100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.10165100
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2977403843
Short name T607
Test name
Test status
Simulation time 40048709 ps
CPU time 1.32 seconds
Started Jul 04 05:21:56 PM PDT 24
Finished Jul 04 05:21:57 PM PDT 24
Peak memory 200324 kb
Host smart-07fee19c-d5c9-4e34-92b7-73e2aff8feab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977403843 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.2977403843
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1452547482
Short name T632
Test name
Test status
Simulation time 98304860 ps
CPU time 0.68 seconds
Started Jul 04 05:21:56 PM PDT 24
Finished Jul 04 05:21:57 PM PDT 24
Peak memory 198136 kb
Host smart-784b581d-dfd9-4254-8038-2438203a50cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452547482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1452547482
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2503826625
Short name T532
Test name
Test status
Simulation time 73179757 ps
CPU time 0.57 seconds
Started Jul 04 05:21:59 PM PDT 24
Finished Jul 04 05:22:00 PM PDT 24
Peak memory 195096 kb
Host smart-98d32ac3-0490-44b2-8ff1-7c389248e5ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503826625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2503826625
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2557466432
Short name T597
Test name
Test status
Simulation time 139493613 ps
CPU time 1.2 seconds
Started Jul 04 05:21:56 PM PDT 24
Finished Jul 04 05:21:58 PM PDT 24
Peak memory 200232 kb
Host smart-ed0799e9-abc2-47d4-9715-878908d0cd5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557466432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2557466432
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3438344364
Short name T652
Test name
Test status
Simulation time 111435075 ps
CPU time 2.67 seconds
Started Jul 04 05:21:59 PM PDT 24
Finished Jul 04 05:22:02 PM PDT 24
Peak memory 200236 kb
Host smart-382caf5b-dc32-4033-8cda-a85f8101c658
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438344364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3438344364
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1824633094
Short name T117
Test name
Test status
Simulation time 329729143 ps
CPU time 2.88 seconds
Started Jul 04 05:21:59 PM PDT 24
Finished Jul 04 05:22:02 PM PDT 24
Peak memory 200284 kb
Host smart-f346e1b8-0c5b-4184-91c4-1c6299a2da97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824633094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1824633094
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1304465781
Short name T625
Test name
Test status
Simulation time 109507241696 ps
CPU time 282.33 seconds
Started Jul 04 05:21:56 PM PDT 24
Finished Jul 04 05:26:39 PM PDT 24
Peak memory 216732 kb
Host smart-79054d17-c281-479d-ad8c-04d347b17e29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304465781 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1304465781
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.964983630
Short name T603
Test name
Test status
Simulation time 44052017 ps
CPU time 0.84 seconds
Started Jul 04 05:21:56 PM PDT 24
Finished Jul 04 05:21:58 PM PDT 24
Peak memory 200064 kb
Host smart-7ac1fddc-70d7-43f9-a00d-f41b45f4b7eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964983630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.964983630
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3650241860
Short name T592
Test name
Test status
Simulation time 22903393 ps
CPU time 0.6 seconds
Started Jul 04 05:21:59 PM PDT 24
Finished Jul 04 05:22:00 PM PDT 24
Peak memory 195072 kb
Host smart-ba184d95-f6ff-48c6-8a5d-fd207dd48755
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650241860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3650241860
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3283275492
Short name T640
Test name
Test status
Simulation time 21041811 ps
CPU time 1.17 seconds
Started Jul 04 05:22:00 PM PDT 24
Finished Jul 04 05:22:01 PM PDT 24
Peak memory 198792 kb
Host smart-165fb21a-2a3e-455e-9a2b-a95d86dc6533
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283275492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3283275492
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3408336424
Short name T585
Test name
Test status
Simulation time 64128154 ps
CPU time 1.8 seconds
Started Jul 04 05:21:56 PM PDT 24
Finished Jul 04 05:21:58 PM PDT 24
Peak memory 200268 kb
Host smart-6005978b-3678-4238-893c-d07143f501ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408336424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3408336424
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.853069863
Short name T115
Test name
Test status
Simulation time 662035120 ps
CPU time 4.09 seconds
Started Jul 04 05:21:56 PM PDT 24
Finished Jul 04 05:22:00 PM PDT 24
Peak memory 200240 kb
Host smart-cf1ca7f2-3a84-4392-92de-3a0c247b705d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853069863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.853069863
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1509834343
Short name T545
Test name
Test status
Simulation time 227032447 ps
CPU time 1.09 seconds
Started Jul 04 05:22:04 PM PDT 24
Finished Jul 04 05:22:06 PM PDT 24
Peak memory 200108 kb
Host smart-f2b1ea14-b8d0-4ed5-9d7c-0f00b7cebbcf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509834343 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1509834343
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3579769900
Short name T105
Test name
Test status
Simulation time 23459706 ps
CPU time 0.83 seconds
Started Jul 04 05:22:05 PM PDT 24
Finished Jul 04 05:22:06 PM PDT 24
Peak memory 199464 kb
Host smart-790d49ba-7074-4eb4-acb1-ba6c865cc74b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579769900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3579769900
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1626246514
Short name T634
Test name
Test status
Simulation time 66512190 ps
CPU time 0.61 seconds
Started Jul 04 05:22:05 PM PDT 24
Finished Jul 04 05:22:06 PM PDT 24
Peak memory 195164 kb
Host smart-1a4758ac-4774-40f3-851a-6cfe6d6c22b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626246514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1626246514
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2301786120
Short name T111
Test name
Test status
Simulation time 163307893 ps
CPU time 2.1 seconds
Started Jul 04 05:22:07 PM PDT 24
Finished Jul 04 05:22:09 PM PDT 24
Peak memory 200280 kb
Host smart-0970a1b8-5f8d-41d7-8d6d-d5e634caad5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301786120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2301786120
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.1571105682
Short name T543
Test name
Test status
Simulation time 261804628 ps
CPU time 1.89 seconds
Started Jul 04 05:22:00 PM PDT 24
Finished Jul 04 05:22:02 PM PDT 24
Peak memory 200276 kb
Host smart-3b78b84e-6f96-4a4e-bee4-104fe9d40b4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571105682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.1571105682
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1988258547
Short name T653
Test name
Test status
Simulation time 548800267 ps
CPU time 4.69 seconds
Started Jul 04 05:22:00 PM PDT 24
Finished Jul 04 05:22:05 PM PDT 24
Peak memory 200252 kb
Host smart-cc1477ad-52f4-4d15-a542-36629abc8dc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988258547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1988258547
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3526310955
Short name T541
Test name
Test status
Simulation time 92214232 ps
CPU time 2.8 seconds
Started Jul 04 05:22:05 PM PDT 24
Finished Jul 04 05:22:08 PM PDT 24
Peak memory 200292 kb
Host smart-53d6187e-3505-419b-9a04-457a79357610
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526310955 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.3526310955
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.165595151
Short name T540
Test name
Test status
Simulation time 39467848 ps
CPU time 0.59 seconds
Started Jul 04 05:22:03 PM PDT 24
Finished Jul 04 05:22:04 PM PDT 24
Peak memory 195208 kb
Host smart-651e4e5d-99ef-4570-a207-d2fd86736d74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165595151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.165595151
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3941725219
Short name T600
Test name
Test status
Simulation time 103235415 ps
CPU time 1.09 seconds
Started Jul 04 05:22:04 PM PDT 24
Finished Jul 04 05:22:06 PM PDT 24
Peak memory 200204 kb
Host smart-67ec298b-c705-416a-9e72-0e87e17edd40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941725219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3941725219
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2210022375
Short name T549
Test name
Test status
Simulation time 498626474 ps
CPU time 4.28 seconds
Started Jul 04 05:22:06 PM PDT 24
Finished Jul 04 05:22:10 PM PDT 24
Peak memory 200308 kb
Host smart-f32d5fc6-b2eb-41a6-93f5-8ef090f054bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210022375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2210022375
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3527550839
Short name T59
Test name
Test status
Simulation time 930305025 ps
CPU time 4.38 seconds
Started Jul 04 05:22:05 PM PDT 24
Finished Jul 04 05:22:10 PM PDT 24
Peak memory 200220 kb
Host smart-9beb8f03-f33d-4e6d-9b3a-fba1607a012e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527550839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3527550839
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1811360284
Short name T530
Test name
Test status
Simulation time 344403128 ps
CPU time 2.48 seconds
Started Jul 04 05:22:04 PM PDT 24
Finished Jul 04 05:22:07 PM PDT 24
Peak memory 200308 kb
Host smart-a2f2e25d-7f50-43e6-8155-d94b6548a8f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811360284 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1811360284
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2049442111
Short name T657
Test name
Test status
Simulation time 20436178 ps
CPU time 0.7 seconds
Started Jul 04 05:22:06 PM PDT 24
Finished Jul 04 05:22:07 PM PDT 24
Peak memory 198448 kb
Host smart-bd6b9f73-dbeb-4146-b06c-f3b2e4c3fcb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049442111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2049442111
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1832924466
Short name T554
Test name
Test status
Simulation time 13002493 ps
CPU time 0.6 seconds
Started Jul 04 05:22:06 PM PDT 24
Finished Jul 04 05:22:07 PM PDT 24
Peak memory 195228 kb
Host smart-ab1e10a6-9780-461c-8a82-67dcef92af47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832924466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1832924466
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2486898899
Short name T108
Test name
Test status
Simulation time 582154451 ps
CPU time 1.79 seconds
Started Jul 04 05:22:06 PM PDT 24
Finished Jul 04 05:22:08 PM PDT 24
Peak memory 200264 kb
Host smart-7c5d61b2-95cc-41bf-ab40-99363a2f83c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486898899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2486898899
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3809747752
Short name T614
Test name
Test status
Simulation time 170877938 ps
CPU time 2.02 seconds
Started Jul 04 05:22:05 PM PDT 24
Finished Jul 04 05:22:07 PM PDT 24
Peak memory 200276 kb
Host smart-382a4d55-461d-4eca-865a-0bba34dae6f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809747752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3809747752
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2837990264
Short name T122
Test name
Test status
Simulation time 583025092 ps
CPU time 4.75 seconds
Started Jul 04 05:22:07 PM PDT 24
Finished Jul 04 05:22:12 PM PDT 24
Peak memory 200336 kb
Host smart-5230d2c5-2b18-4cae-a1fb-0eab10ad5996
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837990264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2837990264
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3900815272
Short name T563
Test name
Test status
Simulation time 55002270 ps
CPU time 3.44 seconds
Started Jul 04 05:22:07 PM PDT 24
Finished Jul 04 05:22:11 PM PDT 24
Peak memory 208544 kb
Host smart-4c79bae3-932a-4f86-b2e0-bc91c02e83d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900815272 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3900815272
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1118462584
Short name T628
Test name
Test status
Simulation time 20615209 ps
CPU time 0.7 seconds
Started Jul 04 05:22:06 PM PDT 24
Finished Jul 04 05:22:07 PM PDT 24
Peak memory 198076 kb
Host smart-5d36a856-2ac9-4e24-a269-c07f78d50efd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118462584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1118462584
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2923499409
Short name T624
Test name
Test status
Simulation time 15591289 ps
CPU time 0.6 seconds
Started Jul 04 05:22:04 PM PDT 24
Finished Jul 04 05:22:05 PM PDT 24
Peak memory 195144 kb
Host smart-da2dc272-c10f-4a92-ace5-dcdaab93f41a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923499409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2923499409
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2025219176
Short name T604
Test name
Test status
Simulation time 64828567 ps
CPU time 1.57 seconds
Started Jul 04 05:22:04 PM PDT 24
Finished Jul 04 05:22:06 PM PDT 24
Peak memory 200268 kb
Host smart-8a6190a5-37a4-468e-8247-52929ab75f92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025219176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.2025219176
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2082234063
Short name T550
Test name
Test status
Simulation time 25447827 ps
CPU time 1.42 seconds
Started Jul 04 05:22:06 PM PDT 24
Finished Jul 04 05:22:07 PM PDT 24
Peak memory 200268 kb
Host smart-3e367a8b-216b-4cfd-b148-4fa22a9d7e5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082234063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2082234063
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.495364224
Short name T119
Test name
Test status
Simulation time 218296765 ps
CPU time 4.27 seconds
Started Jul 04 05:22:04 PM PDT 24
Finished Jul 04 05:22:08 PM PDT 24
Peak memory 200308 kb
Host smart-02d61f0f-5eab-45e2-8f1f-2db65b34784d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495364224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.495364224
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1997162292
Short name T539
Test name
Test status
Simulation time 27015377 ps
CPU time 1.61 seconds
Started Jul 04 05:22:03 PM PDT 24
Finished Jul 04 05:22:05 PM PDT 24
Peak memory 200324 kb
Host smart-7e28a6fd-41ad-45aa-8d4b-fda6a639b9f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997162292 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1997162292
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.2689610630
Short name T95
Test name
Test status
Simulation time 111120151 ps
CPU time 0.92 seconds
Started Jul 04 05:22:06 PM PDT 24
Finished Jul 04 05:22:07 PM PDT 24
Peak memory 199732 kb
Host smart-b2d72884-d369-43ae-982b-57d77ee8cec5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689610630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.2689610630
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.203249587
Short name T590
Test name
Test status
Simulation time 12739034 ps
CPU time 0.64 seconds
Started Jul 04 05:22:03 PM PDT 24
Finished Jul 04 05:22:04 PM PDT 24
Peak memory 195200 kb
Host smart-018a7c6a-c501-4c06-98d5-49bb65504a61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203249587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.203249587
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.4123405391
Short name T621
Test name
Test status
Simulation time 80085214 ps
CPU time 1.2 seconds
Started Jul 04 05:22:06 PM PDT 24
Finished Jul 04 05:22:07 PM PDT 24
Peak memory 198908 kb
Host smart-36b60dea-5da3-42d2-a4ec-bf8637a367d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123405391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.4123405391
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2480129551
Short name T587
Test name
Test status
Simulation time 48827934 ps
CPU time 1.38 seconds
Started Jul 04 05:22:05 PM PDT 24
Finished Jul 04 05:22:07 PM PDT 24
Peak memory 200252 kb
Host smart-b91dee84-2b37-4226-a76b-1fcf1bf84f7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480129551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2480129551
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.4083157783
Short name T118
Test name
Test status
Simulation time 538048644 ps
CPU time 4.25 seconds
Started Jul 04 05:22:07 PM PDT 24
Finished Jul 04 05:22:12 PM PDT 24
Peak memory 200260 kb
Host smart-65d9ce39-3221-4071-8627-7ef856e47ee9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083157783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.4083157783
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3137876178
Short name T635
Test name
Test status
Simulation time 53336219 ps
CPU time 1.79 seconds
Started Jul 04 05:22:04 PM PDT 24
Finished Jul 04 05:22:06 PM PDT 24
Peak memory 200368 kb
Host smart-3b143b4d-059b-4ce0-8444-e5300167c4a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137876178 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3137876178
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3387667344
Short name T650
Test name
Test status
Simulation time 182995223 ps
CPU time 0.77 seconds
Started Jul 04 05:22:05 PM PDT 24
Finished Jul 04 05:22:07 PM PDT 24
Peak memory 199360 kb
Host smart-80fe79c8-3051-4d8e-80ef-cbd16643a390
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387667344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3387667344
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.352502270
Short name T591
Test name
Test status
Simulation time 16329374 ps
CPU time 0.61 seconds
Started Jul 04 05:22:03 PM PDT 24
Finished Jul 04 05:22:03 PM PDT 24
Peak memory 195148 kb
Host smart-8d81f87a-e6ef-47b2-b61f-4f9fa3240d59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352502270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.352502270
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2789772346
Short name T617
Test name
Test status
Simulation time 47912666 ps
CPU time 2.12 seconds
Started Jul 04 05:22:04 PM PDT 24
Finished Jul 04 05:22:07 PM PDT 24
Peak memory 200240 kb
Host smart-8578d529-ab4e-4a7b-8855-9ea804f55c5b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789772346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2789772346
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.306841592
Short name T644
Test name
Test status
Simulation time 100373274 ps
CPU time 1.56 seconds
Started Jul 04 05:22:07 PM PDT 24
Finished Jul 04 05:22:09 PM PDT 24
Peak memory 200336 kb
Host smart-7da2e973-65aa-4f35-a982-b1968962aba8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306841592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.306841592
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3943063102
Short name T660
Test name
Test status
Simulation time 460546710 ps
CPU time 4 seconds
Started Jul 04 05:22:03 PM PDT 24
Finished Jul 04 05:22:07 PM PDT 24
Peak memory 200248 kb
Host smart-5d77f49a-1afb-4bbb-bf0d-8a0c542c539e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943063102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3943063102
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1593460784
Short name T536
Test name
Test status
Simulation time 159390635 ps
CPU time 1.24 seconds
Started Jul 04 05:22:04 PM PDT 24
Finished Jul 04 05:22:06 PM PDT 24
Peak memory 200272 kb
Host smart-e1e0aeb8-9d60-4e1f-83a9-48d15c13d3e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593460784 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1593460784
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3774944181
Short name T655
Test name
Test status
Simulation time 28688663 ps
CPU time 0.67 seconds
Started Jul 04 05:22:04 PM PDT 24
Finished Jul 04 05:22:05 PM PDT 24
Peak memory 198044 kb
Host smart-f7828cf7-1367-46ac-b29c-8f43059fed84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774944181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3774944181
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3105265724
Short name T611
Test name
Test status
Simulation time 10784965 ps
CPU time 0.57 seconds
Started Jul 04 05:22:04 PM PDT 24
Finished Jul 04 05:22:04 PM PDT 24
Peak memory 195184 kb
Host smart-c5d3bd8d-8ba8-473d-82d9-2d9f27584557
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105265724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3105265724
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3634555072
Short name T113
Test name
Test status
Simulation time 271594834 ps
CPU time 2.21 seconds
Started Jul 04 05:22:06 PM PDT 24
Finished Jul 04 05:22:09 PM PDT 24
Peak memory 200320 kb
Host smart-b4246660-c736-4468-9d6f-73fe26cda113
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634555072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3634555072
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.337793919
Short name T551
Test name
Test status
Simulation time 62276374 ps
CPU time 1.59 seconds
Started Jul 04 05:22:05 PM PDT 24
Finished Jul 04 05:22:06 PM PDT 24
Peak memory 200284 kb
Host smart-a58a5830-2293-4d09-94c4-988149d2c3a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337793919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.337793919
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.824786387
Short name T557
Test name
Test status
Simulation time 116321646 ps
CPU time 3.95 seconds
Started Jul 04 05:22:04 PM PDT 24
Finished Jul 04 05:22:09 PM PDT 24
Peak memory 200252 kb
Host smart-cc7085ae-bd7d-4608-a158-a1f7a3fd143a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824786387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.824786387
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4217118219
Short name T639
Test name
Test status
Simulation time 63011152 ps
CPU time 3.18 seconds
Started Jul 04 05:21:46 PM PDT 24
Finished Jul 04 05:21:49 PM PDT 24
Peak memory 200228 kb
Host smart-7e7cf0cb-1ce1-4716-9f52-b6d818b128ac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217118219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.4217118219
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3227951106
Short name T101
Test name
Test status
Simulation time 1799768118 ps
CPU time 14.51 seconds
Started Jul 04 05:21:42 PM PDT 24
Finished Jul 04 05:21:56 PM PDT 24
Peak memory 200296 kb
Host smart-9b26fba5-331c-4f19-9d72-df592568587c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227951106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3227951106
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2832201345
Short name T618
Test name
Test status
Simulation time 40334935 ps
CPU time 0.73 seconds
Started Jul 04 05:21:42 PM PDT 24
Finished Jul 04 05:21:44 PM PDT 24
Peak memory 198196 kb
Host smart-86ae3b00-0b3d-4450-a026-a2464b4440f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832201345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2832201345
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.587123602
Short name T605
Test name
Test status
Simulation time 261326296102 ps
CPU time 717.06 seconds
Started Jul 04 05:21:43 PM PDT 24
Finished Jul 04 05:33:41 PM PDT 24
Peak memory 216700 kb
Host smart-21286190-ccb3-494c-8df2-93d4744f5324
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587123602 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.587123602
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.586868943
Short name T99
Test name
Test status
Simulation time 56368471 ps
CPU time 0.87 seconds
Started Jul 04 05:21:45 PM PDT 24
Finished Jul 04 05:21:46 PM PDT 24
Peak memory 199752 kb
Host smart-36d2b401-191a-4a4c-84f8-bdc58898024a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586868943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.586868943
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3364522002
Short name T637
Test name
Test status
Simulation time 14223477 ps
CPU time 0.62 seconds
Started Jul 04 05:21:46 PM PDT 24
Finished Jul 04 05:21:46 PM PDT 24
Peak memory 195172 kb
Host smart-9c45319a-ab1b-454d-8cc6-c9de99b55f71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364522002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3364522002
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2190884946
Short name T107
Test name
Test status
Simulation time 101216923 ps
CPU time 1.65 seconds
Started Jul 04 05:21:45 PM PDT 24
Finished Jul 04 05:21:47 PM PDT 24
Peak memory 200264 kb
Host smart-483e5220-cf5e-41fa-9542-2a504ffda4ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190884946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2190884946
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3922053161
Short name T575
Test name
Test status
Simulation time 286629130 ps
CPU time 3.18 seconds
Started Jul 04 05:21:41 PM PDT 24
Finished Jul 04 05:21:45 PM PDT 24
Peak memory 200312 kb
Host smart-2ac23b75-c88b-43da-9a58-b23dc0b87e76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922053161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3922053161
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3290802637
Short name T567
Test name
Test status
Simulation time 59979741 ps
CPU time 0.55 seconds
Started Jul 04 05:22:03 PM PDT 24
Finished Jul 04 05:22:04 PM PDT 24
Peak memory 195156 kb
Host smart-08ded6a2-a6ca-4ecb-9d24-9a203f0e6eaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290802637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3290802637
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3024273504
Short name T620
Test name
Test status
Simulation time 15154100 ps
CPU time 0.56 seconds
Started Jul 04 05:22:05 PM PDT 24
Finished Jul 04 05:22:06 PM PDT 24
Peak memory 195136 kb
Host smart-67c72649-cf29-4692-a721-a807d1586059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024273504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3024273504
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3156693364
Short name T576
Test name
Test status
Simulation time 15036452 ps
CPU time 0.6 seconds
Started Jul 04 05:22:07 PM PDT 24
Finished Jul 04 05:22:08 PM PDT 24
Peak memory 195292 kb
Host smart-aeba98c2-cbc7-4a47-b941-916a68ca49af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156693364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3156693364
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.158809547
Short name T586
Test name
Test status
Simulation time 30520692 ps
CPU time 0.63 seconds
Started Jul 04 05:22:14 PM PDT 24
Finished Jul 04 05:22:15 PM PDT 24
Peak memory 195164 kb
Host smart-15f79e8b-07fb-4e86-a945-f25be86cfeb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158809547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.158809547
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.118498004
Short name T648
Test name
Test status
Simulation time 15380082 ps
CPU time 0.6 seconds
Started Jul 04 05:22:14 PM PDT 24
Finished Jul 04 05:22:15 PM PDT 24
Peak memory 195172 kb
Host smart-cc9b6208-fcba-4865-b3a5-153edab0a50d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118498004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.118498004
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1791164700
Short name T577
Test name
Test status
Simulation time 25471630 ps
CPU time 0.57 seconds
Started Jul 04 05:22:14 PM PDT 24
Finished Jul 04 05:22:15 PM PDT 24
Peak memory 195144 kb
Host smart-ca29c47e-61ce-48fc-92fe-69a004f6888a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791164700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1791164700
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.2649965613
Short name T578
Test name
Test status
Simulation time 13969626 ps
CPU time 0.58 seconds
Started Jul 04 05:22:12 PM PDT 24
Finished Jul 04 05:22:13 PM PDT 24
Peak memory 195208 kb
Host smart-cfbd90e7-a036-4db8-9836-554df023c43e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649965613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.2649965613
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2023394181
Short name T610
Test name
Test status
Simulation time 16774837 ps
CPU time 0.62 seconds
Started Jul 04 05:22:13 PM PDT 24
Finished Jul 04 05:22:14 PM PDT 24
Peak memory 195224 kb
Host smart-6665a783-3688-4b94-bf11-d95e1afbdb9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023394181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2023394181
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1114290006
Short name T638
Test name
Test status
Simulation time 10975119 ps
CPU time 0.56 seconds
Started Jul 04 05:22:10 PM PDT 24
Finished Jul 04 05:22:11 PM PDT 24
Peak memory 195136 kb
Host smart-f3356e76-cbbd-4cbd-a333-88f82c374d38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114290006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1114290006
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3858403493
Short name T647
Test name
Test status
Simulation time 17116735 ps
CPU time 0.61 seconds
Started Jul 04 05:22:12 PM PDT 24
Finished Jul 04 05:22:13 PM PDT 24
Peak memory 195236 kb
Host smart-8840929f-6b9c-4660-b003-481b36deb2ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858403493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3858403493
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3592338772
Short name T547
Test name
Test status
Simulation time 230034854 ps
CPU time 3.13 seconds
Started Jul 04 05:21:41 PM PDT 24
Finished Jul 04 05:21:44 PM PDT 24
Peak memory 200228 kb
Host smart-4ea805f1-3f2f-48eb-819b-ae9e20d3587b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592338772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3592338772
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.268551229
Short name T564
Test name
Test status
Simulation time 1056753789 ps
CPU time 15.39 seconds
Started Jul 04 05:21:42 PM PDT 24
Finished Jul 04 05:21:57 PM PDT 24
Peak memory 200252 kb
Host smart-8844f454-aa57-4fdb-baab-1b8891baa670
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268551229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.268551229
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1728879130
Short name T569
Test name
Test status
Simulation time 33562654 ps
CPU time 1.02 seconds
Started Jul 04 05:21:41 PM PDT 24
Finished Jul 04 05:21:42 PM PDT 24
Peak memory 199824 kb
Host smart-0c6c907b-44f1-4215-9471-a5aa5efb0356
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728879130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1728879130
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.370456738
Short name T562
Test name
Test status
Simulation time 76599793 ps
CPU time 1.75 seconds
Started Jul 04 05:21:42 PM PDT 24
Finished Jul 04 05:21:45 PM PDT 24
Peak memory 200304 kb
Host smart-1cac9957-f5f3-4c17-a44e-77dc1c9df4c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370456738 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.370456738
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2631426890
Short name T633
Test name
Test status
Simulation time 20932762 ps
CPU time 0.68 seconds
Started Jul 04 05:21:42 PM PDT 24
Finished Jul 04 05:21:44 PM PDT 24
Peak memory 197936 kb
Host smart-bf0acc28-0db6-4877-b2fd-551438b8bb33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631426890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2631426890
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1880789502
Short name T596
Test name
Test status
Simulation time 25644441 ps
CPU time 0.62 seconds
Started Jul 04 05:21:43 PM PDT 24
Finished Jul 04 05:21:44 PM PDT 24
Peak memory 195200 kb
Host smart-46e79c34-44d2-4155-837d-73cf7bf5aefb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880789502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1880789502
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3431191422
Short name T571
Test name
Test status
Simulation time 43278962 ps
CPU time 1.12 seconds
Started Jul 04 05:21:43 PM PDT 24
Finished Jul 04 05:21:45 PM PDT 24
Peak memory 200056 kb
Host smart-7b134b8c-e559-437a-a44a-78bb87e93704
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431191422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3431191422
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.2380736834
Short name T658
Test name
Test status
Simulation time 32811822 ps
CPU time 1.67 seconds
Started Jul 04 05:21:42 PM PDT 24
Finished Jul 04 05:21:45 PM PDT 24
Peak memory 200244 kb
Host smart-38052354-31fc-41d9-9cfb-353302b77410
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380736834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.2380736834
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.475134619
Short name T125
Test name
Test status
Simulation time 194808578 ps
CPU time 2.9 seconds
Started Jul 04 05:21:43 PM PDT 24
Finished Jul 04 05:21:46 PM PDT 24
Peak memory 200236 kb
Host smart-27128714-25c5-4c19-83aa-8fe0dd587616
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475134619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.475134619
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.442799372
Short name T552
Test name
Test status
Simulation time 22790426 ps
CPU time 0.58 seconds
Started Jul 04 05:22:12 PM PDT 24
Finished Jul 04 05:22:13 PM PDT 24
Peak memory 195236 kb
Host smart-fc3f3787-cc71-40ab-a06e-60b9df5599e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442799372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.442799372
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.425735469
Short name T654
Test name
Test status
Simulation time 13414365 ps
CPU time 0.6 seconds
Started Jul 04 05:22:13 PM PDT 24
Finished Jul 04 05:22:14 PM PDT 24
Peak memory 195116 kb
Host smart-879c85fb-9f32-49c3-aada-761308891d9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425735469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.425735469
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1519070492
Short name T641
Test name
Test status
Simulation time 29809155 ps
CPU time 0.62 seconds
Started Jul 04 05:22:14 PM PDT 24
Finished Jul 04 05:22:15 PM PDT 24
Peak memory 195216 kb
Host smart-4e6cd40e-85ff-4b9b-a2f8-fc19b680e2c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519070492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1519070492
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.793711755
Short name T612
Test name
Test status
Simulation time 18550612 ps
CPU time 0.57 seconds
Started Jul 04 05:22:12 PM PDT 24
Finished Jul 04 05:22:13 PM PDT 24
Peak memory 195100 kb
Host smart-5555c920-28b5-4559-8d65-5b66cc3a1e00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793711755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.793711755
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.677860924
Short name T560
Test name
Test status
Simulation time 29696604 ps
CPU time 0.62 seconds
Started Jul 04 05:22:13 PM PDT 24
Finished Jul 04 05:22:14 PM PDT 24
Peak memory 195176 kb
Host smart-ffe98fe9-419b-40eb-a206-12f890bf4677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677860924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.677860924
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2721070786
Short name T531
Test name
Test status
Simulation time 20503051 ps
CPU time 0.58 seconds
Started Jul 04 05:22:16 PM PDT 24
Finished Jul 04 05:22:16 PM PDT 24
Peak memory 195144 kb
Host smart-af30ebb5-7da3-40be-9d0f-906e77784984
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721070786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2721070786
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3610631728
Short name T542
Test name
Test status
Simulation time 40347717 ps
CPU time 0.6 seconds
Started Jul 04 05:22:15 PM PDT 24
Finished Jul 04 05:22:16 PM PDT 24
Peak memory 195196 kb
Host smart-e30e25ea-5fce-46b9-ae0f-28222fcb28f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610631728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3610631728
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1312032770
Short name T561
Test name
Test status
Simulation time 46068115 ps
CPU time 0.65 seconds
Started Jul 04 05:22:15 PM PDT 24
Finished Jul 04 05:22:16 PM PDT 24
Peak memory 195144 kb
Host smart-c8a94939-53e9-47fd-a852-796ec505c0d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312032770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1312032770
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3160144728
Short name T619
Test name
Test status
Simulation time 12834933 ps
CPU time 0.63 seconds
Started Jul 04 05:22:16 PM PDT 24
Finished Jul 04 05:22:17 PM PDT 24
Peak memory 195232 kb
Host smart-d7d1f5e1-8d93-4ec0-821a-a2ee1f811d53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160144728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3160144728
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.804682269
Short name T579
Test name
Test status
Simulation time 35063301 ps
CPU time 0.59 seconds
Started Jul 04 05:22:12 PM PDT 24
Finished Jul 04 05:22:13 PM PDT 24
Peak memory 195136 kb
Host smart-abd743a0-5f2e-4c68-bdd7-9a28027efc56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804682269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.804682269
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.181645197
Short name T98
Test name
Test status
Simulation time 2956774033 ps
CPU time 6.19 seconds
Started Jul 04 05:21:51 PM PDT 24
Finished Jul 04 05:21:57 PM PDT 24
Peak memory 200296 kb
Host smart-8c54cc28-b31b-4cba-b259-0a70b838d127
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181645197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.181645197
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.833864508
Short name T94
Test name
Test status
Simulation time 452721198 ps
CPU time 5.32 seconds
Started Jul 04 05:21:48 PM PDT 24
Finished Jul 04 05:21:54 PM PDT 24
Peak memory 199288 kb
Host smart-ffdb3506-6f24-46ea-8db2-61ebea824815
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833864508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.833864508
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.395479278
Short name T558
Test name
Test status
Simulation time 119550115 ps
CPU time 1.03 seconds
Started Jul 04 05:21:50 PM PDT 24
Finished Jul 04 05:21:51 PM PDT 24
Peak memory 200052 kb
Host smart-ad8152e6-d87b-49b5-8002-d26e457676b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395479278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.395479278
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.818933788
Short name T645
Test name
Test status
Simulation time 51861018 ps
CPU time 3.49 seconds
Started Jul 04 05:21:51 PM PDT 24
Finished Jul 04 05:21:55 PM PDT 24
Peak memory 208500 kb
Host smart-d780ff27-a623-44b2-9f86-9abeef60de96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818933788 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.818933788
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3797634094
Short name T627
Test name
Test status
Simulation time 16562467 ps
CPU time 0.74 seconds
Started Jul 04 05:21:54 PM PDT 24
Finished Jul 04 05:21:55 PM PDT 24
Peak memory 198000 kb
Host smart-cd1e95ba-f070-4611-b4aa-ebbb7c78175b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797634094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3797634094
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2609099638
Short name T601
Test name
Test status
Simulation time 35849802 ps
CPU time 0.62 seconds
Started Jul 04 05:21:50 PM PDT 24
Finished Jul 04 05:21:51 PM PDT 24
Peak memory 195180 kb
Host smart-12069f19-c1a5-4176-9df7-ee2433904f3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609099638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2609099638
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1837532985
Short name T581
Test name
Test status
Simulation time 406821228 ps
CPU time 1.81 seconds
Started Jul 04 05:21:51 PM PDT 24
Finished Jul 04 05:21:53 PM PDT 24
Peak memory 200236 kb
Host smart-c10962b8-9568-4617-bd0d-59537ed99542
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837532985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1837532985
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3867715737
Short name T609
Test name
Test status
Simulation time 107714099 ps
CPU time 2.54 seconds
Started Jul 04 05:21:50 PM PDT 24
Finished Jul 04 05:21:53 PM PDT 24
Peak memory 200312 kb
Host smart-921b8937-a510-450a-95d5-e59f21222260
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867715737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3867715737
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1946740729
Short name T588
Test name
Test status
Simulation time 227440890 ps
CPU time 4.34 seconds
Started Jul 04 05:21:55 PM PDT 24
Finished Jul 04 05:22:00 PM PDT 24
Peak memory 200268 kb
Host smart-8ca7105b-f2aa-417e-ad55-c667cb8eb6d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946740729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1946740729
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.766991043
Short name T556
Test name
Test status
Simulation time 35441241 ps
CPU time 0.59 seconds
Started Jul 04 05:22:16 PM PDT 24
Finished Jul 04 05:22:17 PM PDT 24
Peak memory 195100 kb
Host smart-14a4623c-960c-4f5d-a785-df1bfb5e9818
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766991043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.766991043
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1220026137
Short name T570
Test name
Test status
Simulation time 55613584 ps
CPU time 0.63 seconds
Started Jul 04 05:22:14 PM PDT 24
Finished Jul 04 05:22:15 PM PDT 24
Peak memory 195220 kb
Host smart-febbd84c-4605-480f-900c-bcf8de4b996b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220026137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1220026137
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2285759441
Short name T594
Test name
Test status
Simulation time 21637934 ps
CPU time 0.61 seconds
Started Jul 04 05:22:14 PM PDT 24
Finished Jul 04 05:22:15 PM PDT 24
Peak memory 195196 kb
Host smart-c59200c3-feef-4c6d-95cc-f09ec8a92a9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285759441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2285759441
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2507687118
Short name T546
Test name
Test status
Simulation time 42911085 ps
CPU time 0.66 seconds
Started Jul 04 05:22:13 PM PDT 24
Finished Jul 04 05:22:14 PM PDT 24
Peak memory 195276 kb
Host smart-7ffbf0b3-c5bb-43b7-ac8b-c227b06e485b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507687118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2507687118
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2557164171
Short name T572
Test name
Test status
Simulation time 58220617 ps
CPU time 0.62 seconds
Started Jul 04 05:22:15 PM PDT 24
Finished Jul 04 05:22:16 PM PDT 24
Peak memory 195152 kb
Host smart-cc47dacc-8070-41cf-be8e-d1098ef92c4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557164171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2557164171
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2874613226
Short name T643
Test name
Test status
Simulation time 45821154 ps
CPU time 0.59 seconds
Started Jul 04 05:22:12 PM PDT 24
Finished Jul 04 05:22:13 PM PDT 24
Peak memory 195208 kb
Host smart-64d1f8d7-4133-4f4c-863f-5c16b4a1abda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874613226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2874613226
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.32472312
Short name T602
Test name
Test status
Simulation time 93630459 ps
CPU time 0.63 seconds
Started Jul 04 05:22:14 PM PDT 24
Finished Jul 04 05:22:15 PM PDT 24
Peak memory 195156 kb
Host smart-71ef81d3-9923-4b6e-97a4-5610182edc00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32472312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.32472312
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.406059871
Short name T538
Test name
Test status
Simulation time 23085365 ps
CPU time 0.58 seconds
Started Jul 04 05:22:15 PM PDT 24
Finished Jul 04 05:22:16 PM PDT 24
Peak memory 195264 kb
Host smart-2de72b7e-93d9-43a2-8380-46aebba2ef04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406059871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.406059871
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3733487012
Short name T595
Test name
Test status
Simulation time 16814521 ps
CPU time 0.65 seconds
Started Jul 04 05:22:11 PM PDT 24
Finished Jul 04 05:22:12 PM PDT 24
Peak memory 195160 kb
Host smart-23e7a33c-e87f-4fec-a52d-13efd648f68c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733487012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3733487012
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2982453813
Short name T573
Test name
Test status
Simulation time 17580290 ps
CPU time 0.65 seconds
Started Jul 04 05:22:16 PM PDT 24
Finished Jul 04 05:22:17 PM PDT 24
Peak memory 195220 kb
Host smart-ea1439ae-3da8-4bb0-9461-06252bed4770
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982453813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2982453813
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4050738252
Short name T656
Test name
Test status
Simulation time 138348807 ps
CPU time 1.82 seconds
Started Jul 04 05:21:49 PM PDT 24
Finished Jul 04 05:21:51 PM PDT 24
Peak memory 200284 kb
Host smart-f3c130a2-311c-4278-b0df-16ae56c695cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050738252 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.4050738252
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2277795979
Short name T103
Test name
Test status
Simulation time 31088869 ps
CPU time 0.93 seconds
Started Jul 04 05:21:49 PM PDT 24
Finished Jul 04 05:21:50 PM PDT 24
Peak memory 200112 kb
Host smart-aaf8788b-32b0-470b-a224-351dfd420a45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277795979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2277795979
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3168559161
Short name T559
Test name
Test status
Simulation time 37938591 ps
CPU time 0.59 seconds
Started Jul 04 05:21:54 PM PDT 24
Finished Jul 04 05:21:55 PM PDT 24
Peak memory 195172 kb
Host smart-1c9c26db-288c-47a9-91c1-79deee9d4aa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168559161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3168559161
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1972973806
Short name T112
Test name
Test status
Simulation time 124430555 ps
CPU time 1.04 seconds
Started Jul 04 05:21:55 PM PDT 24
Finished Jul 04 05:21:56 PM PDT 24
Peak memory 198840 kb
Host smart-77afb181-7371-4235-80cf-286361e6b488
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972973806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1972973806
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1576457061
Short name T537
Test name
Test status
Simulation time 69707256 ps
CPU time 3.51 seconds
Started Jul 04 05:21:50 PM PDT 24
Finished Jul 04 05:21:53 PM PDT 24
Peak memory 200264 kb
Host smart-08416be9-69ff-4675-945b-d056b96ebf5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576457061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1576457061
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3820737761
Short name T566
Test name
Test status
Simulation time 98447746 ps
CPU time 2.01 seconds
Started Jul 04 05:21:50 PM PDT 24
Finished Jul 04 05:21:53 PM PDT 24
Peak memory 200232 kb
Host smart-c49e59f3-1aaf-4bc7-9115-faf0dc14d49c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820737761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3820737761
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1756915074
Short name T593
Test name
Test status
Simulation time 63374015 ps
CPU time 1.14 seconds
Started Jul 04 05:21:52 PM PDT 24
Finished Jul 04 05:21:54 PM PDT 24
Peak memory 200072 kb
Host smart-2947ebcd-2cfb-4030-a65e-d85f23dc7a93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756915074 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1756915074
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1892596417
Short name T553
Test name
Test status
Simulation time 108028976 ps
CPU time 0.83 seconds
Started Jul 04 05:21:50 PM PDT 24
Finished Jul 04 05:21:51 PM PDT 24
Peak memory 200080 kb
Host smart-8f3ab678-19c0-4630-afe6-762e6956668e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892596417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1892596417
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2601448083
Short name T533
Test name
Test status
Simulation time 19788997 ps
CPU time 0.61 seconds
Started Jul 04 05:21:54 PM PDT 24
Finished Jul 04 05:21:54 PM PDT 24
Peak memory 195260 kb
Host smart-64ede7a3-fc99-4476-9483-5c3a7a13f3a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601448083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2601448083
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1098846639
Short name T110
Test name
Test status
Simulation time 223544593 ps
CPU time 1.2 seconds
Started Jul 04 05:21:48 PM PDT 24
Finished Jul 04 05:21:49 PM PDT 24
Peak memory 200252 kb
Host smart-abd26dd4-9b74-4f43-8c30-fc01a94fa66c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098846639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1098846639
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3840260424
Short name T555
Test name
Test status
Simulation time 205385655 ps
CPU time 2.69 seconds
Started Jul 04 05:21:52 PM PDT 24
Finished Jul 04 05:21:56 PM PDT 24
Peak memory 200324 kb
Host smart-ab13b903-a4ab-4a61-90a9-e530b9920487
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840260424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3840260424
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2547478464
Short name T636
Test name
Test status
Simulation time 1103229346 ps
CPU time 1.76 seconds
Started Jul 04 05:21:50 PM PDT 24
Finished Jul 04 05:21:52 PM PDT 24
Peak memory 200300 kb
Host smart-2d70d4b1-e5d5-42df-877c-ab43d33538cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547478464 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2547478464
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2899352599
Short name T616
Test name
Test status
Simulation time 36109758 ps
CPU time 0.82 seconds
Started Jul 04 05:21:49 PM PDT 24
Finished Jul 04 05:21:50 PM PDT 24
Peak memory 200080 kb
Host smart-365bd1e4-3aa5-4b73-ab70-3feca1a2eada
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899352599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2899352599
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.4209591619
Short name T649
Test name
Test status
Simulation time 11820739 ps
CPU time 0.59 seconds
Started Jul 04 05:21:55 PM PDT 24
Finished Jul 04 05:21:56 PM PDT 24
Peak memory 195200 kb
Host smart-7fbe9a43-d273-40d5-919c-65921da51c7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209591619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.4209591619
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.4079876028
Short name T109
Test name
Test status
Simulation time 208078065 ps
CPU time 1.82 seconds
Started Jul 04 05:21:50 PM PDT 24
Finished Jul 04 05:21:52 PM PDT 24
Peak memory 200104 kb
Host smart-008d78f6-f80e-4097-b664-898d9e14272e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079876028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.4079876028
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3679721180
Short name T568
Test name
Test status
Simulation time 225204151 ps
CPU time 2.55 seconds
Started Jul 04 05:21:55 PM PDT 24
Finished Jul 04 05:21:57 PM PDT 24
Peak memory 200348 kb
Host smart-1c049437-1376-4289-be09-b0094399c69a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679721180 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3679721180
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1713676279
Short name T58
Test name
Test status
Simulation time 236131778 ps
CPU time 4.17 seconds
Started Jul 04 05:21:50 PM PDT 24
Finished Jul 04 05:21:54 PM PDT 24
Peak memory 200280 kb
Host smart-1ac8a180-5536-47b1-ae18-881e0ead5b21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713676279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1713676279
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.799735030
Short name T580
Test name
Test status
Simulation time 228979194 ps
CPU time 1.82 seconds
Started Jul 04 05:21:58 PM PDT 24
Finished Jul 04 05:22:00 PM PDT 24
Peak memory 200340 kb
Host smart-2e1caadf-8ab7-42a8-b936-bb58fefe9979
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799735030 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.799735030
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.390407379
Short name T584
Test name
Test status
Simulation time 16515362 ps
CPU time 0.98 seconds
Started Jul 04 05:22:01 PM PDT 24
Finished Jul 04 05:22:02 PM PDT 24
Peak memory 199916 kb
Host smart-e06f1cf8-485c-45b1-b278-973e758f1fbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390407379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.390407379
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3862579891
Short name T574
Test name
Test status
Simulation time 41302054 ps
CPU time 0.63 seconds
Started Jul 04 05:21:57 PM PDT 24
Finished Jul 04 05:21:57 PM PDT 24
Peak memory 195212 kb
Host smart-bc11c55e-0229-478d-a86a-af27d54e965b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862579891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3862579891
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3465533137
Short name T613
Test name
Test status
Simulation time 53706268 ps
CPU time 1.21 seconds
Started Jul 04 05:21:57 PM PDT 24
Finished Jul 04 05:21:58 PM PDT 24
Peak memory 200052 kb
Host smart-8cacb06f-e6d3-4154-b249-283f78808b7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465533137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3465533137
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3185981540
Short name T623
Test name
Test status
Simulation time 169951407 ps
CPU time 2.01 seconds
Started Jul 04 05:21:49 PM PDT 24
Finished Jul 04 05:21:51 PM PDT 24
Peak memory 200256 kb
Host smart-6dca0352-afac-402e-a7be-e741656bbd19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185981540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3185981540
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1415001445
Short name T116
Test name
Test status
Simulation time 1154481289 ps
CPU time 4.63 seconds
Started Jul 04 05:21:51 PM PDT 24
Finished Jul 04 05:21:56 PM PDT 24
Peak memory 200244 kb
Host smart-0b2a7316-aa5a-499d-8a13-4542764e1361
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415001445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1415001445
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2898680136
Short name T534
Test name
Test status
Simulation time 72056123 ps
CPU time 1.51 seconds
Started Jul 04 05:22:01 PM PDT 24
Finished Jul 04 05:22:02 PM PDT 24
Peak memory 200228 kb
Host smart-9a1dbbaa-6528-4490-8b85-9a5a636b1578
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898680136 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2898680136
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1507866662
Short name T106
Test name
Test status
Simulation time 46924404 ps
CPU time 0.81 seconds
Started Jul 04 05:21:56 PM PDT 24
Finished Jul 04 05:21:57 PM PDT 24
Peak memory 199528 kb
Host smart-182c2fda-c2cb-4f10-a335-f5999767185c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507866662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1507866662
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.865242347
Short name T629
Test name
Test status
Simulation time 14754819 ps
CPU time 0.62 seconds
Started Jul 04 05:21:57 PM PDT 24
Finished Jul 04 05:21:58 PM PDT 24
Peak memory 195264 kb
Host smart-91c5d804-7095-4034-8dc2-0d00e8eb13d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865242347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.865242347
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1279387356
Short name T626
Test name
Test status
Simulation time 98059229 ps
CPU time 2.22 seconds
Started Jul 04 05:22:02 PM PDT 24
Finished Jul 04 05:22:04 PM PDT 24
Peak memory 200324 kb
Host smart-ac7ffc3a-d386-44a3-9b0a-b01285934180
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279387356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1279387356
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1841214830
Short name T535
Test name
Test status
Simulation time 156944188 ps
CPU time 4.19 seconds
Started Jul 04 05:21:57 PM PDT 24
Finished Jul 04 05:22:02 PM PDT 24
Peak memory 200304 kb
Host smart-be4d902f-605f-46e9-a114-b4bbb612ec75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841214830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1841214830
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1429812135
Short name T121
Test name
Test status
Simulation time 2198601675 ps
CPU time 4.48 seconds
Started Jul 04 05:21:56 PM PDT 24
Finished Jul 04 05:22:00 PM PDT 24
Peak memory 200300 kb
Host smart-f4927686-9204-4643-b248-65e48e76f2f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429812135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1429812135
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.1820808079
Short name T268
Test name
Test status
Simulation time 1188965282 ps
CPU time 35.43 seconds
Started Jul 04 05:22:19 PM PDT 24
Finished Jul 04 05:22:55 PM PDT 24
Peak memory 200320 kb
Host smart-17c6829e-cac9-4d41-8c2d-1da103b77f0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1820808079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1820808079
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2188064214
Short name T515
Test name
Test status
Simulation time 2888680885 ps
CPU time 516.63 seconds
Started Jul 04 05:22:20 PM PDT 24
Finished Jul 04 05:30:57 PM PDT 24
Peak memory 631500 kb
Host smart-b2583538-20d3-494a-82f3-73523179c5de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2188064214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2188064214
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.505572589
Short name T425
Test name
Test status
Simulation time 26851168288 ps
CPU time 168.03 seconds
Started Jul 04 05:22:16 PM PDT 24
Finished Jul 04 05:25:04 PM PDT 24
Peak memory 200324 kb
Host smart-c2b3c349-a8b6-4e19-a28b-036d29a8e3cc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505572589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.505572589
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.2912375952
Short name T355
Test name
Test status
Simulation time 5784199526 ps
CPU time 101.09 seconds
Started Jul 04 05:22:15 PM PDT 24
Finished Jul 04 05:23:56 PM PDT 24
Peak memory 200348 kb
Host smart-0e1a5841-c40d-4ac9-99ce-4a360338412b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912375952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.2912375952
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2857892481
Short name T50
Test name
Test status
Simulation time 86770290 ps
CPU time 1.04 seconds
Started Jul 04 05:22:15 PM PDT 24
Finished Jul 04 05:22:16 PM PDT 24
Peak memory 219392 kb
Host smart-00cf6ed1-55f9-493d-8def-5b9c8561d6b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857892481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2857892481
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.3896925559
Short name T341
Test name
Test status
Simulation time 457808741 ps
CPU time 7.71 seconds
Started Jul 04 05:22:15 PM PDT 24
Finished Jul 04 05:22:23 PM PDT 24
Peak memory 200308 kb
Host smart-8b6bb967-fd1c-4292-9eaa-80b5f6e9043b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896925559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3896925559
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3516881055
Short name T326
Test name
Test status
Simulation time 11879999511 ps
CPU time 537.47 seconds
Started Jul 04 05:22:15 PM PDT 24
Finished Jul 04 05:31:13 PM PDT 24
Peak memory 688204 kb
Host smart-11506350-7325-468f-8af3-2400d95c8380
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516881055 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3516881055
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.2312794368
Short name T166
Test name
Test status
Simulation time 2391383822 ps
CPU time 45.91 seconds
Started Jul 04 05:22:14 PM PDT 24
Finished Jul 04 05:23:00 PM PDT 24
Peak memory 200352 kb
Host smart-5661326c-4cd3-41d6-b0b9-9a70884593f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2312794368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.2312794368
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.2417711235
Short name T398
Test name
Test status
Simulation time 3612903237 ps
CPU time 61.45 seconds
Started Jul 04 05:22:17 PM PDT 24
Finished Jul 04 05:23:18 PM PDT 24
Peak memory 200356 kb
Host smart-4b839226-f906-4133-b541-539aefd02751
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2417711235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.2417711235
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.2116383111
Short name T509
Test name
Test status
Simulation time 2108175892 ps
CPU time 71.11 seconds
Started Jul 04 05:22:13 PM PDT 24
Finished Jul 04 05:23:24 PM PDT 24
Peak memory 200284 kb
Host smart-adfbbd91-b46d-43ba-a865-2547fe704c54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2116383111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.2116383111
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.19916699
Short name T336
Test name
Test status
Simulation time 10548097805 ps
CPU time 522.11 seconds
Started Jul 04 05:22:14 PM PDT 24
Finished Jul 04 05:30:57 PM PDT 24
Peak memory 200408 kb
Host smart-48b656de-7acb-4dd1-bf1a-25082eb9be3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=19916699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.19916699
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.3814671763
Short name T409
Test name
Test status
Simulation time 196658153026 ps
CPU time 2524.92 seconds
Started Jul 04 05:22:20 PM PDT 24
Finished Jul 04 06:04:25 PM PDT 24
Peak memory 215896 kb
Host smart-ff4c813e-4422-4c24-9972-0d847f8b91d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3814671763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.3814671763
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.3762748511
Short name T63
Test name
Test status
Simulation time 503994550414 ps
CPU time 2197.86 seconds
Started Jul 04 05:22:15 PM PDT 24
Finished Jul 04 05:58:54 PM PDT 24
Peak memory 215900 kb
Host smart-dc1afad2-7387-49fc-b8ef-6bde48058e32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3762748511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.3762748511
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.373509095
Short name T93
Test name
Test status
Simulation time 1947124043 ps
CPU time 96.2 seconds
Started Jul 04 05:22:13 PM PDT 24
Finished Jul 04 05:23:49 PM PDT 24
Peak memory 200268 kb
Host smart-5b9ffabf-7e71-4e56-8759-66cd63b68782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373509095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.373509095
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.208694182
Short name T517
Test name
Test status
Simulation time 12536836 ps
CPU time 0.61 seconds
Started Jul 04 05:22:18 PM PDT 24
Finished Jul 04 05:22:19 PM PDT 24
Peak memory 196188 kb
Host smart-7a8b738c-f3e3-480e-9248-103ae392aa38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208694182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.208694182
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3343831078
Short name T177
Test name
Test status
Simulation time 551241945 ps
CPU time 29.98 seconds
Started Jul 04 05:22:19 PM PDT 24
Finished Jul 04 05:22:49 PM PDT 24
Peak memory 200156 kb
Host smart-c0188dbb-8302-4188-be41-e70e1f02f912
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3343831078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3343831078
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1149820224
Short name T382
Test name
Test status
Simulation time 13781389388 ps
CPU time 44.81 seconds
Started Jul 04 05:22:14 PM PDT 24
Finished Jul 04 05:22:59 PM PDT 24
Peak memory 200388 kb
Host smart-e36ff2c0-91b4-413b-8bc2-e42326106fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149820224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1149820224
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3474008707
Short name T30
Test name
Test status
Simulation time 5880200115 ps
CPU time 957.65 seconds
Started Jul 04 05:22:14 PM PDT 24
Finished Jul 04 05:38:12 PM PDT 24
Peak memory 692792 kb
Host smart-2a39e493-04b5-4387-bffd-0df88bd2585a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3474008707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3474008707
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.4227940301
Short name T516
Test name
Test status
Simulation time 281275951 ps
CPU time 4.96 seconds
Started Jul 04 05:22:14 PM PDT 24
Finished Jul 04 05:22:19 PM PDT 24
Peak memory 200228 kb
Host smart-a108543b-3928-4a21-bedb-8ff4fe013584
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227940301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.4227940301
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.444097831
Short name T42
Test name
Test status
Simulation time 3994698644 ps
CPU time 228.16 seconds
Started Jul 04 05:22:14 PM PDT 24
Finished Jul 04 05:26:02 PM PDT 24
Peak memory 216728 kb
Host smart-bbc8f949-e534-4f4c-ab2f-598a647429e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444097831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.444097831
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.3539293852
Short name T493
Test name
Test status
Simulation time 825218283 ps
CPU time 13.43 seconds
Started Jul 04 05:22:14 PM PDT 24
Finished Jul 04 05:22:28 PM PDT 24
Peak memory 200288 kb
Host smart-9f9b3d81-7707-4b8e-a0a1-f43cb3c228d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539293852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3539293852
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.4096838847
Short name T236
Test name
Test status
Simulation time 8308438677 ps
CPU time 458.49 seconds
Started Jul 04 05:22:19 PM PDT 24
Finished Jul 04 05:29:58 PM PDT 24
Peak memory 216772 kb
Host smart-e342ad73-6043-4820-9f68-56b1668bdefd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096838847 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.4096838847
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.726862065
Short name T7
Test name
Test status
Simulation time 139310499096 ps
CPU time 1537.43 seconds
Started Jul 04 05:22:19 PM PDT 24
Finished Jul 04 05:47:57 PM PDT 24
Peak memory 697936 kb
Host smart-702a3fe7-bb46-4052-a8b5-655f4285db8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=726862065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.726862065
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.1693565521
Short name T441
Test name
Test status
Simulation time 3523811417 ps
CPU time 71.67 seconds
Started Jul 04 05:22:13 PM PDT 24
Finished Jul 04 05:23:25 PM PDT 24
Peak memory 200336 kb
Host smart-1cd70c4a-24ee-40d9-b56b-e722b7318651
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1693565521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.1693565521
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.1793839270
Short name T372
Test name
Test status
Simulation time 17811293779 ps
CPU time 65.8 seconds
Started Jul 04 05:22:15 PM PDT 24
Finished Jul 04 05:23:21 PM PDT 24
Peak memory 200344 kb
Host smart-6ad1e268-e320-4b1e-a13d-512335f8128a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1793839270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.1793839270
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.88521695
Short name T345
Test name
Test status
Simulation time 7702888372 ps
CPU time 117.87 seconds
Started Jul 04 05:22:15 PM PDT 24
Finished Jul 04 05:24:14 PM PDT 24
Peak memory 200356 kb
Host smart-5d0c06e3-bfce-4e86-b8c8-68c674597eb8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=88521695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.88521695
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.3782705775
Short name T314
Test name
Test status
Simulation time 22470021681 ps
CPU time 617.74 seconds
Started Jul 04 05:22:19 PM PDT 24
Finished Jul 04 05:32:37 PM PDT 24
Peak memory 200300 kb
Host smart-485561fd-8475-42c6-9401-c0de5a76d285
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3782705775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.3782705775
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.3124048744
Short name T424
Test name
Test status
Simulation time 199767141317 ps
CPU time 2190.77 seconds
Started Jul 04 05:22:12 PM PDT 24
Finished Jul 04 05:58:43 PM PDT 24
Peak memory 216000 kb
Host smart-63856198-3c3e-4618-876f-f9a18e2dc7b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3124048744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.3124048744
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.1306228488
Short name T309
Test name
Test status
Simulation time 129911796567 ps
CPU time 2227.68 seconds
Started Jul 04 05:22:17 PM PDT 24
Finished Jul 04 05:59:25 PM PDT 24
Peak memory 216008 kb
Host smart-f904d761-c2e0-41cf-a5b6-6282f8a98455
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1306228488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.1306228488
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3174802027
Short name T31
Test name
Test status
Simulation time 4550469275 ps
CPU time 14.93 seconds
Started Jul 04 05:22:16 PM PDT 24
Finished Jul 04 05:22:31 PM PDT 24
Peak memory 200324 kb
Host smart-3e8e6c6a-caa7-4d1e-b789-5737aa0f11e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174802027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3174802027
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.414857343
Short name T308
Test name
Test status
Simulation time 41818522 ps
CPU time 0.58 seconds
Started Jul 04 05:22:36 PM PDT 24
Finished Jul 04 05:22:37 PM PDT 24
Peak memory 196820 kb
Host smart-11b8151e-bb0e-417f-a797-3b441b63c6a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414857343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.414857343
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1565300291
Short name T228
Test name
Test status
Simulation time 3937294526 ps
CPU time 53.88 seconds
Started Jul 04 05:22:35 PM PDT 24
Finished Jul 04 05:23:29 PM PDT 24
Peak memory 200380 kb
Host smart-cb066e5a-aa28-42c6-aac5-57ce44e4d4e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1565300291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1565300291
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2919090604
Short name T158
Test name
Test status
Simulation time 3624369104 ps
CPU time 12.02 seconds
Started Jul 04 05:22:36 PM PDT 24
Finished Jul 04 05:22:48 PM PDT 24
Peak memory 200384 kb
Host smart-85c440bf-e363-49de-87b5-8e2fea8a9b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919090604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2919090604
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1202655687
Short name T334
Test name
Test status
Simulation time 6488164107 ps
CPU time 1265.65 seconds
Started Jul 04 05:22:37 PM PDT 24
Finished Jul 04 05:43:43 PM PDT 24
Peak memory 768840 kb
Host smart-9e76c059-611b-4dde-96d2-4d13de7e69ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1202655687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1202655687
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.773293114
Short name T489
Test name
Test status
Simulation time 5682579975 ps
CPU time 164.82 seconds
Started Jul 04 05:22:38 PM PDT 24
Finished Jul 04 05:25:23 PM PDT 24
Peak memory 200364 kb
Host smart-e072f149-5fb5-4c58-b07d-8c364000f2fd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773293114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.773293114
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1260784920
Short name T36
Test name
Test status
Simulation time 1400304918 ps
CPU time 41.05 seconds
Started Jul 04 05:22:36 PM PDT 24
Finished Jul 04 05:23:18 PM PDT 24
Peak memory 200264 kb
Host smart-7bc372ea-5ef9-4532-ba27-5884c6ad65de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260784920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1260784920
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3546912608
Short name T163
Test name
Test status
Simulation time 38492813 ps
CPU time 0.71 seconds
Started Jul 04 05:22:39 PM PDT 24
Finished Jul 04 05:22:40 PM PDT 24
Peak memory 196796 kb
Host smart-d9d1b6d8-b6a3-4b65-8bf7-037f8d13bbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546912608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3546912608
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3226263307
Short name T174
Test name
Test status
Simulation time 4707102011 ps
CPU time 41.78 seconds
Started Jul 04 05:22:38 PM PDT 24
Finished Jul 04 05:23:20 PM PDT 24
Peak memory 200356 kb
Host smart-c226bb5c-171b-474a-a464-a40245ad3af2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226263307 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3226263307
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1488723343
Short name T242
Test name
Test status
Simulation time 2664336748 ps
CPU time 13.43 seconds
Started Jul 04 05:22:36 PM PDT 24
Finished Jul 04 05:22:49 PM PDT 24
Peak memory 200268 kb
Host smart-ac4bd0c2-f8ae-40ed-9f5d-f9b4941dc0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488723343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1488723343
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1481442840
Short name T466
Test name
Test status
Simulation time 11118288 ps
CPU time 0.58 seconds
Started Jul 04 05:22:39 PM PDT 24
Finished Jul 04 05:22:40 PM PDT 24
Peak memory 196192 kb
Host smart-1e98f267-e68a-4f0e-96d4-f2fe3916feaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481442840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1481442840
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.4282734127
Short name T10
Test name
Test status
Simulation time 859528120 ps
CPU time 45.19 seconds
Started Jul 04 05:22:38 PM PDT 24
Finished Jul 04 05:23:24 PM PDT 24
Peak memory 200296 kb
Host smart-c4e39076-7d14-47da-82e9-5cbdd0492e8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4282734127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.4282734127
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.380627890
Short name T523
Test name
Test status
Simulation time 4346094921 ps
CPU time 39.55 seconds
Started Jul 04 05:22:40 PM PDT 24
Finished Jul 04 05:23:20 PM PDT 24
Peak memory 200368 kb
Host smart-61cd383f-d75f-4ad5-8c9b-dd8fa437796c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380627890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.380627890
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.147018344
Short name T28
Test name
Test status
Simulation time 3500326007 ps
CPU time 198.67 seconds
Started Jul 04 05:22:38 PM PDT 24
Finished Jul 04 05:25:57 PM PDT 24
Peak memory 395208 kb
Host smart-7b3eba67-d64f-4586-a57a-0b17fcd939f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=147018344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.147018344
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.4024925009
Short name T171
Test name
Test status
Simulation time 4735854285 ps
CPU time 70.11 seconds
Started Jul 04 05:22:38 PM PDT 24
Finished Jul 04 05:23:48 PM PDT 24
Peak memory 200352 kb
Host smart-3345735a-f730-4eed-b784-2b5e5cc25aa3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024925009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.4024925009
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.695784204
Short name T155
Test name
Test status
Simulation time 1532452728 ps
CPU time 23.01 seconds
Started Jul 04 05:22:35 PM PDT 24
Finished Jul 04 05:22:58 PM PDT 24
Peak memory 200256 kb
Host smart-a3c8d7a8-f92f-42f8-9f8a-2e46222000f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695784204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.695784204
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.26346396
Short name T522
Test name
Test status
Simulation time 1723509021 ps
CPU time 7.7 seconds
Started Jul 04 05:22:36 PM PDT 24
Finished Jul 04 05:22:44 PM PDT 24
Peak memory 200236 kb
Host smart-8a82610e-be3b-4f92-8784-c42840483457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26346396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.26346396
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3123113457
Short name T473
Test name
Test status
Simulation time 125817410867 ps
CPU time 5023.81 seconds
Started Jul 04 05:22:35 PM PDT 24
Finished Jul 04 06:46:19 PM PDT 24
Peak memory 839812 kb
Host smart-d430e3e8-93c2-4d84-ad05-a82eaec3a65f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123113457 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3123113457
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.3109201648
Short name T301
Test name
Test status
Simulation time 633018657 ps
CPU time 17.41 seconds
Started Jul 04 05:22:36 PM PDT 24
Finished Jul 04 05:22:54 PM PDT 24
Peak memory 200312 kb
Host smart-82fd8c93-222b-49c3-85b5-bb1c01befddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109201648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3109201648
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.889954899
Short name T447
Test name
Test status
Simulation time 35051349 ps
CPU time 0.6 seconds
Started Jul 04 05:22:38 PM PDT 24
Finished Jul 04 05:22:39 PM PDT 24
Peak memory 196876 kb
Host smart-b809f018-4371-427e-9b3e-78a20e6f3209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889954899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.889954899
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.1867773246
Short name T433
Test name
Test status
Simulation time 593287103 ps
CPU time 16.34 seconds
Started Jul 04 05:22:36 PM PDT 24
Finished Jul 04 05:22:53 PM PDT 24
Peak memory 200232 kb
Host smart-09f720ad-961d-4288-a390-bcb5ba82b312
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1867773246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.1867773246
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.318812924
Short name T24
Test name
Test status
Simulation time 122449491 ps
CPU time 6.44 seconds
Started Jul 04 05:22:37 PM PDT 24
Finished Jul 04 05:22:44 PM PDT 24
Peak memory 200336 kb
Host smart-5bd48871-7b4e-44b4-9b71-4c1c8cf47ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318812924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.318812924
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.162860736
Short name T321
Test name
Test status
Simulation time 2058541097 ps
CPU time 365.81 seconds
Started Jul 04 05:22:38 PM PDT 24
Finished Jul 04 05:28:44 PM PDT 24
Peak memory 663380 kb
Host smart-a3c8e270-03db-406f-905e-0d7635f34543
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=162860736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.162860736
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1435670201
Short name T62
Test name
Test status
Simulation time 2271729417 ps
CPU time 131.1 seconds
Started Jul 04 05:22:38 PM PDT 24
Finished Jul 04 05:24:50 PM PDT 24
Peak memory 200280 kb
Host smart-09b87096-7830-4a38-b366-cd44c743c723
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435670201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1435670201
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1262198389
Short name T275
Test name
Test status
Simulation time 5590526079 ps
CPU time 83.71 seconds
Started Jul 04 05:22:36 PM PDT 24
Finished Jul 04 05:24:01 PM PDT 24
Peak memory 200340 kb
Host smart-43d0b4de-2fc8-438c-9219-2918206957ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262198389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1262198389
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3259173652
Short name T181
Test name
Test status
Simulation time 22004560 ps
CPU time 0.72 seconds
Started Jul 04 05:22:38 PM PDT 24
Finished Jul 04 05:22:39 PM PDT 24
Peak memory 196860 kb
Host smart-38fc064c-8798-48e3-8280-9711ef782a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259173652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3259173652
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.843051180
Short name T223
Test name
Test status
Simulation time 93199213291 ps
CPU time 4191.19 seconds
Started Jul 04 05:22:38 PM PDT 24
Finished Jul 04 06:32:30 PM PDT 24
Peak memory 818440 kb
Host smart-b2dcd183-c95f-4537-a122-bf735592e24b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843051180 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.843051180
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2018533599
Short name T338
Test name
Test status
Simulation time 6210649617 ps
CPU time 110.41 seconds
Started Jul 04 05:22:37 PM PDT 24
Finished Jul 04 05:24:28 PM PDT 24
Peak memory 200380 kb
Host smart-4f425e5a-37ee-421f-be28-1eee54675b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018533599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2018533599
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2668247934
Short name T54
Test name
Test status
Simulation time 14682036 ps
CPU time 0.58 seconds
Started Jul 04 05:22:45 PM PDT 24
Finished Jul 04 05:22:46 PM PDT 24
Peak memory 195092 kb
Host smart-2cb4ad88-da2e-4fd5-9813-5cdb0f83b2d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668247934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2668247934
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2181188384
Short name T135
Test name
Test status
Simulation time 700140693 ps
CPU time 10.13 seconds
Started Jul 04 05:22:35 PM PDT 24
Finished Jul 04 05:22:46 PM PDT 24
Peak memory 200308 kb
Host smart-4ffa903b-31c9-4063-8048-dd2816d9e0f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2181188384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2181188384
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.831678285
Short name T147
Test name
Test status
Simulation time 133598742 ps
CPU time 0.65 seconds
Started Jul 04 05:22:37 PM PDT 24
Finished Jul 04 05:22:38 PM PDT 24
Peak memory 196740 kb
Host smart-f6064aba-e87f-42ea-8ca8-03738adce18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831678285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.831678285
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3306711848
Short name T337
Test name
Test status
Simulation time 22824755948 ps
CPU time 1041.29 seconds
Started Jul 04 05:22:40 PM PDT 24
Finished Jul 04 05:40:01 PM PDT 24
Peak memory 750708 kb
Host smart-2fecb3c1-932c-471b-968d-b902daae2130
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3306711848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3306711848
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2605656869
Short name T292
Test name
Test status
Simulation time 1644657649 ps
CPU time 88.57 seconds
Started Jul 04 05:22:38 PM PDT 24
Finished Jul 04 05:24:07 PM PDT 24
Peak memory 200320 kb
Host smart-604cce81-334d-49ca-87d6-4f25ec8bc4b7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605656869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2605656869
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.984780738
Short name T159
Test name
Test status
Simulation time 6781748567 ps
CPU time 110.07 seconds
Started Jul 04 05:22:38 PM PDT 24
Finished Jul 04 05:24:29 PM PDT 24
Peak memory 200404 kb
Host smart-252c10d6-5a3a-4ab8-965a-9cffb10ec8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984780738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.984780738
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3793184320
Short name T267
Test name
Test status
Simulation time 564517442 ps
CPU time 5.6 seconds
Started Jul 04 05:22:35 PM PDT 24
Finished Jul 04 05:22:40 PM PDT 24
Peak memory 200304 kb
Host smart-20e1f59e-7b78-4c8f-ab3b-e6a48ef9d082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793184320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3793184320
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3093924127
Short name T319
Test name
Test status
Simulation time 51720674847 ps
CPU time 987.08 seconds
Started Jul 04 05:22:44 PM PDT 24
Finished Jul 04 05:39:12 PM PDT 24
Peak memory 631844 kb
Host smart-97473647-2655-40ac-9ea5-2d9237a7906f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093924127 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3093924127
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.232787176
Short name T502
Test name
Test status
Simulation time 14986401296 ps
CPU time 139.94 seconds
Started Jul 04 05:22:40 PM PDT 24
Finished Jul 04 05:25:00 PM PDT 24
Peak memory 200352 kb
Host smart-4955095f-9af4-407a-ab2c-fce1fa25fd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232787176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.232787176
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1359374697
Short name T248
Test name
Test status
Simulation time 27950102 ps
CPU time 0.58 seconds
Started Jul 04 05:22:41 PM PDT 24
Finished Jul 04 05:22:42 PM PDT 24
Peak memory 196840 kb
Host smart-d92d7d19-8545-4a11-9ba0-ed09e7ca6fbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359374697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1359374697
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1784475505
Short name T34
Test name
Test status
Simulation time 5605317273 ps
CPU time 52.95 seconds
Started Jul 04 05:22:42 PM PDT 24
Finished Jul 04 05:23:35 PM PDT 24
Peak memory 215948 kb
Host smart-0651752d-c8a4-4348-aa67-1945506c0150
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1784475505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1784475505
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.1715528791
Short name T367
Test name
Test status
Simulation time 6678404882 ps
CPU time 44.04 seconds
Started Jul 04 05:22:45 PM PDT 24
Finished Jul 04 05:23:30 PM PDT 24
Peak memory 200356 kb
Host smart-a2b572e5-768d-4734-b3d6-efbac0922235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715528791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1715528791
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3901366610
Short name T490
Test name
Test status
Simulation time 5327421255 ps
CPU time 928.02 seconds
Started Jul 04 05:22:44 PM PDT 24
Finished Jul 04 05:38:13 PM PDT 24
Peak memory 716328 kb
Host smart-597f9b38-6f5b-47a2-b16e-dd6e26188c97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3901366610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3901366610
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.2816780772
Short name T27
Test name
Test status
Simulation time 5236174968 ps
CPU time 57 seconds
Started Jul 04 05:22:41 PM PDT 24
Finished Jul 04 05:23:38 PM PDT 24
Peak memory 200360 kb
Host smart-6e6d5798-327e-420c-8404-51bd9b96b5be
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816780772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.2816780772
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.133289467
Short name T129
Test name
Test status
Simulation time 2503792080 ps
CPU time 11.68 seconds
Started Jul 04 05:22:45 PM PDT 24
Finished Jul 04 05:22:57 PM PDT 24
Peak memory 200300 kb
Host smart-8ee22ae5-691c-448a-9579-847d927cbb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133289467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.133289467
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2414736185
Short name T183
Test name
Test status
Simulation time 1538211350 ps
CPU time 13.36 seconds
Started Jul 04 05:22:43 PM PDT 24
Finished Jul 04 05:22:57 PM PDT 24
Peak memory 200304 kb
Host smart-3303b450-a3c2-474e-8984-5a0d8d2ece62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414736185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2414736185
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.1738975354
Short name T239
Test name
Test status
Simulation time 117071503795 ps
CPU time 1442.06 seconds
Started Jul 04 05:22:43 PM PDT 24
Finished Jul 04 05:46:46 PM PDT 24
Peak memory 777072 kb
Host smart-65b10058-38eb-4411-82ca-68573a82e7fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738975354 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.1738975354
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2449894600
Short name T265
Test name
Test status
Simulation time 11797109750 ps
CPU time 26.87 seconds
Started Jul 04 05:22:45 PM PDT 24
Finished Jul 04 05:23:12 PM PDT 24
Peak memory 200356 kb
Host smart-e9da2630-0199-4c04-a58f-9933d7b39bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449894600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2449894600
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.139206014
Short name T246
Test name
Test status
Simulation time 20103669 ps
CPU time 0.58 seconds
Started Jul 04 05:22:41 PM PDT 24
Finished Jul 04 05:22:42 PM PDT 24
Peak memory 196092 kb
Host smart-6278c367-804e-4730-9a37-1a14fdca5d36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139206014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.139206014
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1600978934
Short name T237
Test name
Test status
Simulation time 4035667192 ps
CPU time 71.55 seconds
Started Jul 04 05:22:44 PM PDT 24
Finished Jul 04 05:23:56 PM PDT 24
Peak memory 200328 kb
Host smart-592bd2b3-e404-4228-8e66-842b22267d02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1600978934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1600978934
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3759888556
Short name T18
Test name
Test status
Simulation time 4268879614 ps
CPU time 44.08 seconds
Started Jul 04 05:22:43 PM PDT 24
Finished Jul 04 05:23:28 PM PDT 24
Peak memory 200296 kb
Host smart-926d7875-fd28-433e-8ae4-ab68b743e29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759888556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3759888556
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3137937663
Short name T432
Test name
Test status
Simulation time 21268283220 ps
CPU time 1160.82 seconds
Started Jul 04 05:22:41 PM PDT 24
Finished Jul 04 05:42:03 PM PDT 24
Peak memory 761232 kb
Host smart-1e90678e-cdeb-4183-83a5-99b3fc30a7ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3137937663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3137937663
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.90324437
Short name T138
Test name
Test status
Simulation time 932685818 ps
CPU time 12.22 seconds
Started Jul 04 05:22:43 PM PDT 24
Finished Jul 04 05:22:56 PM PDT 24
Peak memory 200340 kb
Host smart-02b6f264-870a-476d-ab19-254c524c4879
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90324437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.90324437
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2426166196
Short name T403
Test name
Test status
Simulation time 17859647132 ps
CPU time 111.86 seconds
Started Jul 04 05:22:44 PM PDT 24
Finished Jul 04 05:24:36 PM PDT 24
Peak memory 200364 kb
Host smart-2503b99e-50a2-42fe-9e70-ef0fb35f48e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426166196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2426166196
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2824310482
Short name T230
Test name
Test status
Simulation time 254302443 ps
CPU time 2.95 seconds
Started Jul 04 05:22:42 PM PDT 24
Finished Jul 04 05:22:45 PM PDT 24
Peak memory 200276 kb
Host smart-a08ff1e6-fac9-4433-aa61-358c6c300ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824310482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2824310482
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.33049889
Short name T343
Test name
Test status
Simulation time 35679616859 ps
CPU time 122 seconds
Started Jul 04 05:22:42 PM PDT 24
Finished Jul 04 05:24:44 PM PDT 24
Peak memory 200300 kb
Host smart-6050128e-ceed-4147-a357-812ef2387f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33049889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.33049889
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.461501507
Short name T213
Test name
Test status
Simulation time 43231275 ps
CPU time 0.6 seconds
Started Jul 04 05:22:43 PM PDT 24
Finished Jul 04 05:22:44 PM PDT 24
Peak memory 196196 kb
Host smart-6a8916c7-846a-45ff-b001-8a1613b1951b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461501507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.461501507
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.3983852081
Short name T299
Test name
Test status
Simulation time 5984096220 ps
CPU time 90.36 seconds
Started Jul 04 05:22:44 PM PDT 24
Finished Jul 04 05:24:15 PM PDT 24
Peak memory 208624 kb
Host smart-8bda201a-7c0d-4125-aedf-fd64a69639a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3983852081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3983852081
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.173774568
Short name T37
Test name
Test status
Simulation time 448456376 ps
CPU time 24.02 seconds
Started Jul 04 05:22:41 PM PDT 24
Finished Jul 04 05:23:05 PM PDT 24
Peak memory 200268 kb
Host smart-e7d686d7-c078-47e6-8e8f-d6cb20c01fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173774568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.173774568
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2879761873
Short name T487
Test name
Test status
Simulation time 24688825127 ps
CPU time 429.81 seconds
Started Jul 04 05:22:45 PM PDT 24
Finished Jul 04 05:29:55 PM PDT 24
Peak memory 475604 kb
Host smart-94ada9a7-d5d1-454e-a54f-aff7fc03368c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2879761873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2879761873
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.3652801590
Short name T140
Test name
Test status
Simulation time 17991547078 ps
CPU time 208.4 seconds
Started Jul 04 05:22:43 PM PDT 24
Finished Jul 04 05:26:13 PM PDT 24
Peak memory 200400 kb
Host smart-aef6bae8-2da6-4eb6-842c-e00f79f1b376
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652801590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3652801590
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3601729373
Short name T495
Test name
Test status
Simulation time 3398953677 ps
CPU time 43.07 seconds
Started Jul 04 05:22:43 PM PDT 24
Finished Jul 04 05:23:26 PM PDT 24
Peak memory 200352 kb
Host smart-a48d3695-3bda-4bb2-8571-596efd072a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601729373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3601729373
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.291556391
Short name T55
Test name
Test status
Simulation time 876705183 ps
CPU time 11.1 seconds
Started Jul 04 05:22:45 PM PDT 24
Finished Jul 04 05:22:56 PM PDT 24
Peak memory 200216 kb
Host smart-155c9fa4-65f1-48f1-bbdb-e15bfb4d4cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291556391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.291556391
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2191232669
Short name T401
Test name
Test status
Simulation time 10029322971 ps
CPU time 142.56 seconds
Started Jul 04 05:22:45 PM PDT 24
Finished Jul 04 05:25:08 PM PDT 24
Peak memory 208460 kb
Host smart-efee9399-ce20-4300-9ac5-8367866cca04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191232669 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2191232669
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.548540355
Short name T454
Test name
Test status
Simulation time 3380888211 ps
CPU time 21.33 seconds
Started Jul 04 05:22:42 PM PDT 24
Finished Jul 04 05:23:03 PM PDT 24
Peak memory 200360 kb
Host smart-0d90ef6e-fbf4-49a1-9726-dfac0011e5a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548540355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.548540355
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2651802184
Short name T270
Test name
Test status
Simulation time 12116674 ps
CPU time 0.57 seconds
Started Jul 04 05:22:42 PM PDT 24
Finished Jul 04 05:22:43 PM PDT 24
Peak memory 195800 kb
Host smart-131ed5dd-66c2-465d-a4af-cc1c6fff0fc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651802184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2651802184
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.763724724
Short name T470
Test name
Test status
Simulation time 1628277535 ps
CPU time 55.99 seconds
Started Jul 04 05:22:45 PM PDT 24
Finished Jul 04 05:23:41 PM PDT 24
Peak memory 200308 kb
Host smart-447cf32a-1795-4339-8f59-6ea127a307d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763724724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.763724724
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.616657009
Short name T389
Test name
Test status
Simulation time 10145654276 ps
CPU time 449.45 seconds
Started Jul 04 05:22:44 PM PDT 24
Finished Jul 04 05:30:14 PM PDT 24
Peak memory 639420 kb
Host smart-9858e160-61c5-49f7-addb-3e46f051cd4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=616657009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.616657009
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.102026484
Short name T378
Test name
Test status
Simulation time 9302392977 ps
CPU time 127.83 seconds
Started Jul 04 05:22:42 PM PDT 24
Finished Jul 04 05:24:50 PM PDT 24
Peak memory 200304 kb
Host smart-aca35f66-b0c1-4b90-a191-c6755eacf2f2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102026484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.102026484
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3781791863
Short name T164
Test name
Test status
Simulation time 32546497051 ps
CPU time 154.33 seconds
Started Jul 04 05:22:45 PM PDT 24
Finished Jul 04 05:25:20 PM PDT 24
Peak memory 208528 kb
Host smart-69107a5e-87d9-4530-834d-a223fc54436c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781791863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3781791863
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3923360121
Short name T384
Test name
Test status
Simulation time 1040662057 ps
CPU time 11.88 seconds
Started Jul 04 05:22:43 PM PDT 24
Finished Jul 04 05:22:55 PM PDT 24
Peak memory 200268 kb
Host smart-bc09308e-337c-412d-b138-40b5ba5667ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923360121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3923360121
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.4280389139
Short name T365
Test name
Test status
Simulation time 73849008834 ps
CPU time 298.66 seconds
Started Jul 04 05:22:44 PM PDT 24
Finished Jul 04 05:27:43 PM PDT 24
Peak memory 208568 kb
Host smart-6499be41-afba-4908-bd1c-8d43e8120059
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280389139 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.4280389139
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.2778389200
Short name T436
Test name
Test status
Simulation time 742833919 ps
CPU time 11.92 seconds
Started Jul 04 05:22:44 PM PDT 24
Finished Jul 04 05:22:56 PM PDT 24
Peak memory 200292 kb
Host smart-659e82e8-3014-446c-b8b4-29bac6c09d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778389200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.2778389200
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.963201989
Short name T46
Test name
Test status
Simulation time 41532439 ps
CPU time 0.57 seconds
Started Jul 04 05:22:44 PM PDT 24
Finished Jul 04 05:22:45 PM PDT 24
Peak memory 195164 kb
Host smart-69c38c06-aa1c-4270-bfd9-6b535693a52e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963201989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.963201989
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.100771074
Short name T349
Test name
Test status
Simulation time 1039442303 ps
CPU time 53.56 seconds
Started Jul 04 05:22:41 PM PDT 24
Finished Jul 04 05:23:35 PM PDT 24
Peak memory 200276 kb
Host smart-4c359949-8bd1-440f-a677-0bef64200e12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=100771074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.100771074
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.4144485567
Short name T427
Test name
Test status
Simulation time 650323585 ps
CPU time 9.31 seconds
Started Jul 04 05:22:43 PM PDT 24
Finished Jul 04 05:22:53 PM PDT 24
Peak memory 200284 kb
Host smart-3f5dce3f-2fcb-4a25-b5ec-9bd9fbf0a397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144485567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.4144485567
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1140999484
Short name T208
Test name
Test status
Simulation time 17847406586 ps
CPU time 712.23 seconds
Started Jul 04 05:22:44 PM PDT 24
Finished Jul 04 05:34:37 PM PDT 24
Peak memory 685280 kb
Host smart-f7e67887-9240-4a5e-ab2a-b07aa6525a31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1140999484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1140999484
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1305909569
Short name T250
Test name
Test status
Simulation time 1877471952 ps
CPU time 48.24 seconds
Started Jul 04 05:22:44 PM PDT 24
Finished Jul 04 05:23:33 PM PDT 24
Peak memory 200292 kb
Host smart-cc9e9402-6e32-46f1-a25f-4ec23e63720f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305909569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1305909569
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1665031378
Short name T521
Test name
Test status
Simulation time 3619371939 ps
CPU time 49.16 seconds
Started Jul 04 05:22:46 PM PDT 24
Finished Jul 04 05:23:35 PM PDT 24
Peak memory 200344 kb
Host smart-fbdb7e42-20af-41d5-92ff-aabdfb307ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665031378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1665031378
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.1910431600
Short name T15
Test name
Test status
Simulation time 313389005 ps
CPU time 14.11 seconds
Started Jul 04 05:22:41 PM PDT 24
Finished Jul 04 05:22:56 PM PDT 24
Peak memory 200280 kb
Host smart-dd5e765b-1589-40d7-9dbc-ac4d23b02b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910431600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.1910431600
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2022835985
Short name T241
Test name
Test status
Simulation time 14023355009 ps
CPU time 40.63 seconds
Started Jul 04 05:22:44 PM PDT 24
Finished Jul 04 05:23:25 PM PDT 24
Peak memory 200404 kb
Host smart-68e3959f-14ad-44fc-a043-35cf68424d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022835985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2022835985
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1977495807
Short name T16
Test name
Test status
Simulation time 25661805 ps
CPU time 0.67 seconds
Started Jul 04 05:22:48 PM PDT 24
Finished Jul 04 05:22:49 PM PDT 24
Peak memory 196192 kb
Host smart-4a80ad0d-06d7-4c04-b983-f73688fec7b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977495807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1977495807
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3256590653
Short name T38
Test name
Test status
Simulation time 1590729414 ps
CPU time 97.72 seconds
Started Jul 04 05:22:51 PM PDT 24
Finished Jul 04 05:24:29 PM PDT 24
Peak memory 200336 kb
Host smart-b25e5540-b414-4294-a979-ed3d1ee1e7c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3256590653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3256590653
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3715254283
Short name T193
Test name
Test status
Simulation time 23062695671 ps
CPU time 31.28 seconds
Started Jul 04 05:22:51 PM PDT 24
Finished Jul 04 05:23:23 PM PDT 24
Peak memory 200352 kb
Host smart-02da60c0-b524-4531-9628-6f222a33453d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715254283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3715254283
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1138222697
Short name T318
Test name
Test status
Simulation time 4680065581 ps
CPU time 432.64 seconds
Started Jul 04 05:22:49 PM PDT 24
Finished Jul 04 05:30:01 PM PDT 24
Peak memory 675212 kb
Host smart-0d2e1573-2a7a-4215-8da6-57756eb6ce9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1138222697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1138222697
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3080922148
Short name T412
Test name
Test status
Simulation time 10113129324 ps
CPU time 45.52 seconds
Started Jul 04 05:22:54 PM PDT 24
Finished Jul 04 05:23:39 PM PDT 24
Peak memory 200364 kb
Host smart-79191a63-eeb0-4a02-83f4-b4bc8fccbb47
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080922148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3080922148
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.499798367
Short name T144
Test name
Test status
Simulation time 3754323424 ps
CPU time 102.77 seconds
Started Jul 04 05:22:51 PM PDT 24
Finished Jul 04 05:24:34 PM PDT 24
Peak memory 200328 kb
Host smart-6f0b368a-7b36-4e6b-b20a-bfb10c67bda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499798367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.499798367
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2577348134
Short name T83
Test name
Test status
Simulation time 439318451 ps
CPU time 6.91 seconds
Started Jul 04 05:22:50 PM PDT 24
Finished Jul 04 05:22:57 PM PDT 24
Peak memory 200348 kb
Host smart-a6b80082-64c3-4ef8-9b69-84f110f0889e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577348134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2577348134
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1768033083
Short name T88
Test name
Test status
Simulation time 126518362057 ps
CPU time 350.84 seconds
Started Jul 04 05:22:53 PM PDT 24
Finished Jul 04 05:28:44 PM PDT 24
Peak memory 200376 kb
Host smart-635864e0-37ba-40a5-9f4c-d32eeb3d1c32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768033083 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1768033083
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.2092184715
Short name T507
Test name
Test status
Simulation time 3541695030 ps
CPU time 41.4 seconds
Started Jul 04 05:22:49 PM PDT 24
Finished Jul 04 05:23:30 PM PDT 24
Peak memory 200320 kb
Host smart-74bf8338-f3ab-4fd8-a9fa-6ad40bc06ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092184715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2092184715
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.4290755175
Short name T33
Test name
Test status
Simulation time 31641483 ps
CPU time 0.6 seconds
Started Jul 04 05:22:23 PM PDT 24
Finished Jul 04 05:22:24 PM PDT 24
Peak memory 196864 kb
Host smart-e183dac9-3921-45fe-a91b-ff872c12a7ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290755175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.4290755175
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3712605216
Short name T464
Test name
Test status
Simulation time 5228602837 ps
CPU time 69.89 seconds
Started Jul 04 05:22:20 PM PDT 24
Finished Jul 04 05:23:30 PM PDT 24
Peak memory 200336 kb
Host smart-45911045-071e-4e7f-848c-fd60ddc19ef6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3712605216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3712605216
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2162597311
Short name T283
Test name
Test status
Simulation time 405588580 ps
CPU time 4.47 seconds
Started Jul 04 05:22:21 PM PDT 24
Finished Jul 04 05:22:25 PM PDT 24
Peak memory 200280 kb
Host smart-fe7ff223-54db-4b78-a131-a64f5a08bc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162597311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2162597311
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2332572531
Short name T296
Test name
Test status
Simulation time 2195381077 ps
CPU time 61.28 seconds
Started Jul 04 05:22:22 PM PDT 24
Finished Jul 04 05:23:24 PM PDT 24
Peak memory 401596 kb
Host smart-b32ed87e-4cfc-479e-8580-b1fe7d17d87f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2332572531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2332572531
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.448687436
Short name T45
Test name
Test status
Simulation time 15485959768 ps
CPU time 226.21 seconds
Started Jul 04 05:22:19 PM PDT 24
Finished Jul 04 05:26:06 PM PDT 24
Peak memory 200280 kb
Host smart-feb3b02e-81e9-4186-9aee-ba01d69daf9b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448687436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.448687436
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.1854216716
Short name T238
Test name
Test status
Simulation time 9294873254 ps
CPU time 17.22 seconds
Started Jul 04 05:22:20 PM PDT 24
Finished Jul 04 05:22:38 PM PDT 24
Peak memory 200364 kb
Host smart-9608a22e-42bb-4a1f-9aa1-651fbacf0c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854216716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1854216716
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1496810526
Short name T51
Test name
Test status
Simulation time 237572930 ps
CPU time 0.94 seconds
Started Jul 04 05:22:21 PM PDT 24
Finished Jul 04 05:22:22 PM PDT 24
Peak memory 218420 kb
Host smart-c1d8b798-0e19-4a58-85e9-038f7e077add
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496810526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1496810526
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.4264015075
Short name T255
Test name
Test status
Simulation time 439921909 ps
CPU time 1.79 seconds
Started Jul 04 05:22:25 PM PDT 24
Finished Jul 04 05:22:27 PM PDT 24
Peak memory 200276 kb
Host smart-24d0435b-7ba1-46a8-afb5-44a29d4a29ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264015075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.4264015075
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.1220966642
Short name T282
Test name
Test status
Simulation time 38859442129 ps
CPU time 1098.8 seconds
Started Jul 04 05:22:23 PM PDT 24
Finished Jul 04 05:40:42 PM PDT 24
Peak memory 674488 kb
Host smart-5362fe34-a30f-48ff-b9be-95adef4aa957
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220966642 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1220966642
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.891898362
Short name T12
Test name
Test status
Simulation time 43973007948 ps
CPU time 162.58 seconds
Started Jul 04 05:22:22 PM PDT 24
Finished Jul 04 05:25:05 PM PDT 24
Peak memory 216448 kb
Host smart-41c0648b-8a01-47da-ab4d-4be8383a3cb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=891898362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.891898362
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.274416616
Short name T29
Test name
Test status
Simulation time 12049189137 ps
CPU time 50.63 seconds
Started Jul 04 05:22:22 PM PDT 24
Finished Jul 04 05:23:13 PM PDT 24
Peak memory 200360 kb
Host smart-f81bdf04-8a49-40d4-b321-de3a5a04fd1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=274416616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.274416616
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.4031011322
Short name T417
Test name
Test status
Simulation time 38520195548 ps
CPU time 103.33 seconds
Started Jul 04 05:22:22 PM PDT 24
Finished Jul 04 05:24:06 PM PDT 24
Peak memory 200348 kb
Host smart-db77a41a-421a-4a77-8df6-ea7dd31aa87c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4031011322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.4031011322
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.2751919053
Short name T438
Test name
Test status
Simulation time 6911680129 ps
CPU time 85.11 seconds
Started Jul 04 05:22:20 PM PDT 24
Finished Jul 04 05:23:45 PM PDT 24
Peak memory 200308 kb
Host smart-c139e6e0-b089-4ebe-9e3f-f25bb77ee039
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2751919053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.2751919053
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.2942051207
Short name T197
Test name
Test status
Simulation time 45786760296 ps
CPU time 564.34 seconds
Started Jul 04 05:22:21 PM PDT 24
Finished Jul 04 05:31:46 PM PDT 24
Peak memory 200340 kb
Host smart-85ddd369-825d-455a-99e2-739790ef1304
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2942051207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.2942051207
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.3914706764
Short name T25
Test name
Test status
Simulation time 163519349083 ps
CPU time 2288.49 seconds
Started Jul 04 05:22:26 PM PDT 24
Finished Jul 04 06:00:35 PM PDT 24
Peak memory 216576 kb
Host smart-89f7ae31-9ffd-4045-aeb4-7c7c492df4f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3914706764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3914706764
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.406754142
Short name T374
Test name
Test status
Simulation time 274763191549 ps
CPU time 2448.84 seconds
Started Jul 04 05:22:22 PM PDT 24
Finished Jul 04 06:03:11 PM PDT 24
Peak memory 216560 kb
Host smart-b3a57dba-ed1a-43f0-84d2-85cf21777d01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=406754142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.406754142
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2407704991
Short name T328
Test name
Test status
Simulation time 10739485145 ps
CPU time 65.9 seconds
Started Jul 04 05:22:25 PM PDT 24
Finished Jul 04 05:23:31 PM PDT 24
Peak memory 200360 kb
Host smart-cedbca67-af8a-413a-9659-97245d6fad3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407704991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2407704991
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.3070101222
Short name T287
Test name
Test status
Simulation time 45283312 ps
CPU time 0.58 seconds
Started Jul 04 05:22:51 PM PDT 24
Finished Jul 04 05:22:52 PM PDT 24
Peak memory 195848 kb
Host smart-5b62da64-6e81-4cfe-bb38-4b57c028cc9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070101222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.3070101222
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.39164449
Short name T437
Test name
Test status
Simulation time 3496746077 ps
CPU time 65.32 seconds
Started Jul 04 05:22:49 PM PDT 24
Finished Jul 04 05:23:55 PM PDT 24
Peak memory 200312 kb
Host smart-7996429a-4ea6-4f74-a904-4770a66b4ed6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=39164449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.39164449
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.15788873
Short name T194
Test name
Test status
Simulation time 5456988072 ps
CPU time 24.34 seconds
Started Jul 04 05:22:50 PM PDT 24
Finished Jul 04 05:23:15 PM PDT 24
Peak memory 200372 kb
Host smart-0833f221-364a-4e02-af24-90ac66045119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15788873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.15788873
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.770396096
Short name T148
Test name
Test status
Simulation time 6233232530 ps
CPU time 779.7 seconds
Started Jul 04 05:22:50 PM PDT 24
Finished Jul 04 05:35:50 PM PDT 24
Peak memory 696452 kb
Host smart-c01f59fa-e6b6-4b78-84a8-1581f4c4f261
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=770396096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.770396096
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2171825522
Short name T467
Test name
Test status
Simulation time 8540088546 ps
CPU time 71.28 seconds
Started Jul 04 05:22:55 PM PDT 24
Finished Jul 04 05:24:06 PM PDT 24
Peak memory 200348 kb
Host smart-131ed256-1c60-4091-80c2-0af82534b121
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171825522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2171825522
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3495426697
Short name T364
Test name
Test status
Simulation time 49878097047 ps
CPU time 150.57 seconds
Started Jul 04 05:22:55 PM PDT 24
Finished Jul 04 05:25:26 PM PDT 24
Peak memory 208580 kb
Host smart-bba9286f-4126-421d-9cb3-a5532e5f878e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495426697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3495426697
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1223893118
Short name T269
Test name
Test status
Simulation time 420055539 ps
CPU time 5.99 seconds
Started Jul 04 05:22:56 PM PDT 24
Finished Jul 04 05:23:02 PM PDT 24
Peak memory 200312 kb
Host smart-e326033f-bc53-45c9-bf91-a5b5dbe410d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223893118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1223893118
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1057185156
Short name T217
Test name
Test status
Simulation time 17349008688 ps
CPU time 1223.1 seconds
Started Jul 04 05:22:50 PM PDT 24
Finished Jul 04 05:43:14 PM PDT 24
Peak memory 684300 kb
Host smart-d34c5b5e-d8be-4b6a-b5b0-88b80f9ab60a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057185156 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1057185156
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1073297839
Short name T89
Test name
Test status
Simulation time 2326859410 ps
CPU time 20.28 seconds
Started Jul 04 05:22:52 PM PDT 24
Finished Jul 04 05:23:13 PM PDT 24
Peak memory 200276 kb
Host smart-00f83e79-bbb1-4d66-b2b6-a46348adf2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073297839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1073297839
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.8214715
Short name T271
Test name
Test status
Simulation time 42240657 ps
CPU time 0.61 seconds
Started Jul 04 05:22:50 PM PDT 24
Finished Jul 04 05:22:50 PM PDT 24
Peak memory 195132 kb
Host smart-fd2290f8-5341-400e-b24a-0384d67afeef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8214715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.8214715
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.387711532
Short name T472
Test name
Test status
Simulation time 7062677912 ps
CPU time 93.63 seconds
Started Jul 04 05:22:50 PM PDT 24
Finished Jul 04 05:24:25 PM PDT 24
Peak memory 200396 kb
Host smart-a73da222-fa9e-4329-bb8c-4195396e7dc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=387711532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.387711532
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1009273308
Short name T486
Test name
Test status
Simulation time 3999287664 ps
CPU time 53.37 seconds
Started Jul 04 05:22:50 PM PDT 24
Finished Jul 04 05:23:44 PM PDT 24
Peak memory 200376 kb
Host smart-3f24ccbc-6302-4202-ae6f-39e46f398667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009273308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1009273308
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1704638160
Short name T385
Test name
Test status
Simulation time 5678225220 ps
CPU time 214.24 seconds
Started Jul 04 05:22:50 PM PDT 24
Finished Jul 04 05:26:24 PM PDT 24
Peak memory 592460 kb
Host smart-c477c3af-c323-48cb-a0ca-ca4e5d8eba87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1704638160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1704638160
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2977983248
Short name T444
Test name
Test status
Simulation time 23923991033 ps
CPU time 97.58 seconds
Started Jul 04 05:22:51 PM PDT 24
Finished Jul 04 05:24:29 PM PDT 24
Peak memory 200324 kb
Host smart-472de557-750a-4ac2-a865-f838b57a0e10
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977983248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2977983248
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.4080759747
Short name T513
Test name
Test status
Simulation time 38067764917 ps
CPU time 177.24 seconds
Started Jul 04 05:22:50 PM PDT 24
Finished Jul 04 05:25:47 PM PDT 24
Peak memory 200336 kb
Host smart-51ea2b43-a100-496c-90cf-b3f65dbe7b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080759747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.4080759747
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.290532648
Short name T333
Test name
Test status
Simulation time 73756580 ps
CPU time 1.95 seconds
Started Jul 04 05:22:50 PM PDT 24
Finished Jul 04 05:22:52 PM PDT 24
Peak memory 200248 kb
Host smart-03221157-b35c-4525-81ec-3e0cda602ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290532648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.290532648
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3258095156
Short name T77
Test name
Test status
Simulation time 167343898295 ps
CPU time 2421.9 seconds
Started Jul 04 05:22:49 PM PDT 24
Finished Jul 04 06:03:12 PM PDT 24
Peak memory 807424 kb
Host smart-a3c13995-0a8f-4166-a245-99e40b4e2861
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258095156 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3258095156
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1164242668
Short name T431
Test name
Test status
Simulation time 20499650606 ps
CPU time 44.34 seconds
Started Jul 04 05:22:48 PM PDT 24
Finished Jul 04 05:23:33 PM PDT 24
Peak memory 200340 kb
Host smart-3ee2ba79-89b9-42bc-8d3f-4607e6a7eef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164242668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1164242668
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1224835595
Short name T78
Test name
Test status
Simulation time 30320580 ps
CPU time 0.62 seconds
Started Jul 04 05:22:58 PM PDT 24
Finished Jul 04 05:22:59 PM PDT 24
Peak memory 196868 kb
Host smart-dd76ca9a-400f-40a9-a70d-fa67dd6e9abb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224835595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1224835595
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2790065737
Short name T514
Test name
Test status
Simulation time 1636297418 ps
CPU time 93.47 seconds
Started Jul 04 05:22:50 PM PDT 24
Finished Jul 04 05:24:24 PM PDT 24
Peak memory 200236 kb
Host smart-b022e935-0cd6-4d76-841c-1979fab24fc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2790065737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2790065737
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2883736492
Short name T511
Test name
Test status
Simulation time 2721431147 ps
CPU time 48.32 seconds
Started Jul 04 05:22:51 PM PDT 24
Finished Jul 04 05:23:40 PM PDT 24
Peak memory 200340 kb
Host smart-de9437e0-19c5-459a-b597-7702548ce273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883736492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2883736492
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.176301936
Short name T306
Test name
Test status
Simulation time 2792815720 ps
CPU time 213.58 seconds
Started Jul 04 05:22:51 PM PDT 24
Finished Jul 04 05:26:25 PM PDT 24
Peak memory 406516 kb
Host smart-b8a76534-cbd1-4df1-ae78-fe0ea329ef98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=176301936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.176301936
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.874757576
Short name T169
Test name
Test status
Simulation time 15991795028 ps
CPU time 148.85 seconds
Started Jul 04 05:22:56 PM PDT 24
Finished Jul 04 05:25:25 PM PDT 24
Peak memory 200324 kb
Host smart-babdd058-ad51-4a9d-b83c-8941669c5b2b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874757576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.874757576
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2340982440
Short name T254
Test name
Test status
Simulation time 10510445053 ps
CPU time 137.27 seconds
Started Jul 04 05:22:51 PM PDT 24
Finished Jul 04 05:25:09 PM PDT 24
Peak memory 200476 kb
Host smart-30fa0f38-70f1-4100-9249-5c20539a9ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340982440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2340982440
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1536154443
Short name T434
Test name
Test status
Simulation time 352736884 ps
CPU time 3.73 seconds
Started Jul 04 05:22:54 PM PDT 24
Finished Jul 04 05:22:58 PM PDT 24
Peak memory 200328 kb
Host smart-b47ab644-112c-4cbc-9810-99ebb67dd580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536154443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1536154443
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.4157865155
Short name T82
Test name
Test status
Simulation time 34369939023 ps
CPU time 212.4 seconds
Started Jul 04 05:22:59 PM PDT 24
Finished Jul 04 05:26:32 PM PDT 24
Peak memory 208568 kb
Host smart-274ddec0-31ba-4f55-8744-8dedd91b8834
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157865155 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.4157865155
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2350361927
Short name T491
Test name
Test status
Simulation time 9606473822 ps
CPU time 129.77 seconds
Started Jul 04 05:23:10 PM PDT 24
Finished Jul 04 05:25:19 PM PDT 24
Peak memory 200408 kb
Host smart-ea94bd22-395c-47cd-8874-736915865713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350361927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2350361927
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3093213559
Short name T187
Test name
Test status
Simulation time 12594899 ps
CPU time 0.58 seconds
Started Jul 04 05:22:59 PM PDT 24
Finished Jul 04 05:23:00 PM PDT 24
Peak memory 195144 kb
Host smart-6e4c31be-19cb-4d6d-8bb1-6244f23a02ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093213559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3093213559
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3839650911
Short name T482
Test name
Test status
Simulation time 2214725159 ps
CPU time 63.04 seconds
Started Jul 04 05:22:58 PM PDT 24
Finished Jul 04 05:24:01 PM PDT 24
Peak memory 200348 kb
Host smart-1b736d93-9523-4250-9cb2-89bfcba5cd35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3839650911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3839650911
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.2566923185
Short name T293
Test name
Test status
Simulation time 11290682511 ps
CPU time 52.19 seconds
Started Jul 04 05:22:57 PM PDT 24
Finished Jul 04 05:23:49 PM PDT 24
Peak memory 208580 kb
Host smart-94ce6e51-f80e-47d6-950d-c78ba8fb3100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566923185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.2566923185
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.808789625
Short name T276
Test name
Test status
Simulation time 2339675092 ps
CPU time 117.91 seconds
Started Jul 04 05:22:59 PM PDT 24
Finished Jul 04 05:24:57 PM PDT 24
Peak memory 601348 kb
Host smart-43e04737-1827-4297-875b-6910d89b0f57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=808789625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.808789625
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3914913689
Short name T469
Test name
Test status
Simulation time 6401963181 ps
CPU time 120.38 seconds
Started Jul 04 05:22:57 PM PDT 24
Finished Jul 04 05:24:57 PM PDT 24
Peak memory 200348 kb
Host smart-8306f7cd-9b25-4fde-9428-ae1617c638f7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914913689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3914913689
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.927986890
Short name T32
Test name
Test status
Simulation time 3139328286 ps
CPU time 18.6 seconds
Started Jul 04 05:22:58 PM PDT 24
Finished Jul 04 05:23:17 PM PDT 24
Peak memory 200612 kb
Host smart-88d45c8a-b98a-4f53-b970-cc662417abde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927986890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.927986890
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2219852596
Short name T527
Test name
Test status
Simulation time 1047406573 ps
CPU time 9.88 seconds
Started Jul 04 05:22:57 PM PDT 24
Finished Jul 04 05:23:07 PM PDT 24
Peak memory 200300 kb
Host smart-64f06bc9-ea0b-43f2-90e4-271f8f306388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219852596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2219852596
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.2590548140
Short name T455
Test name
Test status
Simulation time 21627876168 ps
CPU time 468.39 seconds
Started Jul 04 05:22:58 PM PDT 24
Finished Jul 04 05:30:47 PM PDT 24
Peak memory 636200 kb
Host smart-9e28a53f-0bef-4a65-a894-093bad06d4aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590548140 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2590548140
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2511182109
Short name T178
Test name
Test status
Simulation time 21394394386 ps
CPU time 82.61 seconds
Started Jul 04 05:23:07 PM PDT 24
Finished Jul 04 05:24:30 PM PDT 24
Peak memory 200364 kb
Host smart-59d15171-657a-460c-95bf-6ba118f8863d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511182109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2511182109
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.779837935
Short name T196
Test name
Test status
Simulation time 44107152 ps
CPU time 0.56 seconds
Started Jul 04 05:23:00 PM PDT 24
Finished Jul 04 05:23:00 PM PDT 24
Peak memory 196828 kb
Host smart-17013e09-8201-4527-b4bb-ebb2354850c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779837935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.779837935
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2275020601
Short name T477
Test name
Test status
Simulation time 4762530919 ps
CPU time 80.24 seconds
Started Jul 04 05:22:57 PM PDT 24
Finished Jul 04 05:24:18 PM PDT 24
Peak memory 200392 kb
Host smart-196aa46d-4024-4c92-979d-7f60028119d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2275020601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2275020601
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3786757442
Short name T235
Test name
Test status
Simulation time 1184653857 ps
CPU time 22.96 seconds
Started Jul 04 05:23:00 PM PDT 24
Finished Jul 04 05:23:23 PM PDT 24
Peak memory 200308 kb
Host smart-a2a1978b-b721-4758-a97a-6286017198f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786757442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3786757442
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1920180893
Short name T525
Test name
Test status
Simulation time 9213717674 ps
CPU time 842.49 seconds
Started Jul 04 05:22:59 PM PDT 24
Finished Jul 04 05:37:02 PM PDT 24
Peak memory 750548 kb
Host smart-310dc027-e209-48ee-9c22-04fce42456eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1920180893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1920180893
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2054473926
Short name T221
Test name
Test status
Simulation time 24348282842 ps
CPU time 91.62 seconds
Started Jul 04 05:23:09 PM PDT 24
Finished Jul 04 05:24:41 PM PDT 24
Peak memory 200340 kb
Host smart-e5379048-7f31-4946-bd3c-f291b9b6cd03
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054473926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2054473926
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.6668583
Short name T67
Test name
Test status
Simulation time 767946356 ps
CPU time 43.37 seconds
Started Jul 04 05:22:59 PM PDT 24
Finished Jul 04 05:23:43 PM PDT 24
Peak memory 200284 kb
Host smart-acd514ad-9df5-4fc1-863f-69c2721fbfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6668583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.6668583
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.944666274
Short name T414
Test name
Test status
Simulation time 334392465 ps
CPU time 4.65 seconds
Started Jul 04 05:23:00 PM PDT 24
Finished Jul 04 05:23:04 PM PDT 24
Peak memory 200300 kb
Host smart-633dbe6a-5fc9-42d4-bfbc-4c82b7c3e6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944666274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.944666274
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3273235212
Short name T74
Test name
Test status
Simulation time 46964926997 ps
CPU time 630.79 seconds
Started Jul 04 05:23:10 PM PDT 24
Finished Jul 04 05:33:41 PM PDT 24
Peak memory 200392 kb
Host smart-90fe3d51-86d7-4c1e-bd9f-32bd1aafe964
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273235212 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3273235212
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2237987568
Short name T329
Test name
Test status
Simulation time 2908330673 ps
CPU time 142.54 seconds
Started Jul 04 05:23:09 PM PDT 24
Finished Jul 04 05:25:31 PM PDT 24
Peak memory 200364 kb
Host smart-e9fa6026-ddb1-4c33-b703-4631cf7414eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237987568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2237987568
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.1317442899
Short name T206
Test name
Test status
Simulation time 63798127 ps
CPU time 0.57 seconds
Started Jul 04 05:23:06 PM PDT 24
Finished Jul 04 05:23:06 PM PDT 24
Peak memory 195152 kb
Host smart-40939453-037b-488a-92c8-af4512de382c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317442899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.1317442899
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2035179103
Short name T363
Test name
Test status
Simulation time 4543154636 ps
CPU time 63.37 seconds
Started Jul 04 05:22:57 PM PDT 24
Finished Jul 04 05:24:01 PM PDT 24
Peak memory 200348 kb
Host smart-b7d19538-9bd0-48a8-8976-26cb0f4ee86f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2035179103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2035179103
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1330286593
Short name T494
Test name
Test status
Simulation time 4090228450 ps
CPU time 49.06 seconds
Started Jul 04 05:22:56 PM PDT 24
Finished Jul 04 05:23:45 PM PDT 24
Peak memory 200460 kb
Host smart-d7182b74-88ce-4fb9-a7ea-6ecbe98611ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330286593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1330286593
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2263391058
Short name T512
Test name
Test status
Simulation time 1376279161 ps
CPU time 209.56 seconds
Started Jul 04 05:22:57 PM PDT 24
Finished Jul 04 05:26:27 PM PDT 24
Peak memory 470688 kb
Host smart-4f72e59e-6b50-480a-ae64-20c952aed64e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2263391058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2263391058
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.4224245385
Short name T504
Test name
Test status
Simulation time 33728548519 ps
CPU time 110.93 seconds
Started Jul 04 05:22:59 PM PDT 24
Finished Jul 04 05:24:50 PM PDT 24
Peak memory 200324 kb
Host smart-3b0c61b4-9986-4388-9de8-f03235da6fa0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224245385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.4224245385
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.630850000
Short name T324
Test name
Test status
Simulation time 7433782789 ps
CPU time 42.66 seconds
Started Jul 04 05:22:58 PM PDT 24
Finished Jul 04 05:23:41 PM PDT 24
Peak memory 200420 kb
Host smart-50c1d663-a9da-4fe7-a12f-f7fb43b168a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630850000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.630850000
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.402788827
Short name T232
Test name
Test status
Simulation time 611412713 ps
CPU time 10.43 seconds
Started Jul 04 05:22:59 PM PDT 24
Finished Jul 04 05:23:09 PM PDT 24
Peak memory 200300 kb
Host smart-22f92577-abaf-4bf2-8956-0f6330e6fb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402788827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.402788827
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.4188461465
Short name T20
Test name
Test status
Simulation time 161961031778 ps
CPU time 2845.97 seconds
Started Jul 04 05:23:07 PM PDT 24
Finished Jul 04 06:10:34 PM PDT 24
Peak memory 773568 kb
Host smart-002bf2a9-a80a-4375-b62b-505c0afffcc4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188461465 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.4188461465
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3243759968
Short name T453
Test name
Test status
Simulation time 5417601382 ps
CPU time 124.35 seconds
Started Jul 04 05:22:57 PM PDT 24
Finished Jul 04 05:25:02 PM PDT 24
Peak memory 200340 kb
Host smart-f9ac668a-f870-44ef-97f4-012d0ccd4ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243759968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3243759968
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1823592863
Short name T476
Test name
Test status
Simulation time 14081372 ps
CPU time 0.6 seconds
Started Jul 04 05:23:04 PM PDT 24
Finished Jul 04 05:23:05 PM PDT 24
Peak memory 195148 kb
Host smart-c0d485f0-60de-4a10-bb85-aca8bbd180c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823592863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1823592863
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.800147695
Short name T189
Test name
Test status
Simulation time 663537715 ps
CPU time 9.4 seconds
Started Jul 04 05:23:04 PM PDT 24
Finished Jul 04 05:23:14 PM PDT 24
Peak memory 200280 kb
Host smart-2575668f-6468-4704-aa9b-bce2f5e10922
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=800147695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.800147695
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2536882450
Short name T247
Test name
Test status
Simulation time 1147671394 ps
CPU time 59.45 seconds
Started Jul 04 05:23:03 PM PDT 24
Finished Jul 04 05:24:03 PM PDT 24
Peak memory 200276 kb
Host smart-609f2610-0702-4ba4-8d7d-7890c5a480ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536882450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2536882450
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2043044122
Short name T64
Test name
Test status
Simulation time 17774252978 ps
CPU time 1039.74 seconds
Started Jul 04 05:23:03 PM PDT 24
Finished Jul 04 05:40:23 PM PDT 24
Peak memory 778884 kb
Host smart-a582cdfb-2f28-42ff-9b0f-af78e67ec93b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2043044122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2043044122
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3113812528
Short name T463
Test name
Test status
Simulation time 44117420524 ps
CPU time 141.68 seconds
Started Jul 04 05:23:05 PM PDT 24
Finished Jul 04 05:25:27 PM PDT 24
Peak memory 200348 kb
Host smart-71065b92-ea3f-4688-92a0-93d5643c1541
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113812528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3113812528
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3960292123
Short name T366
Test name
Test status
Simulation time 3477179345 ps
CPU time 99.01 seconds
Started Jul 04 05:23:03 PM PDT 24
Finished Jul 04 05:24:42 PM PDT 24
Peak memory 200372 kb
Host smart-c5a2d791-63c2-47e2-880a-11d209a809a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960292123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3960292123
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2272755000
Short name T286
Test name
Test status
Simulation time 485236996 ps
CPU time 6.75 seconds
Started Jul 04 05:23:04 PM PDT 24
Finished Jul 04 05:23:11 PM PDT 24
Peak memory 200296 kb
Host smart-9260a47d-5573-43a0-8e47-e158aece1ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272755000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2272755000
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.86506720
Short name T478
Test name
Test status
Simulation time 49439784034 ps
CPU time 202.94 seconds
Started Jul 04 05:23:03 PM PDT 24
Finished Jul 04 05:26:27 PM PDT 24
Peak memory 200312 kb
Host smart-5acd4ada-244e-4e26-b809-9b014b954517
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86506720 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.86506720
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2625326398
Short name T397
Test name
Test status
Simulation time 15048716787 ps
CPU time 45.43 seconds
Started Jul 04 05:23:04 PM PDT 24
Finished Jul 04 05:23:50 PM PDT 24
Peak memory 200344 kb
Host smart-829a5f47-3599-4a7a-9d15-ac3e5bd713be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625326398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2625326398
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3590151794
Short name T145
Test name
Test status
Simulation time 33673017 ps
CPU time 0.58 seconds
Started Jul 04 05:23:12 PM PDT 24
Finished Jul 04 05:23:13 PM PDT 24
Peak memory 195148 kb
Host smart-2c6628fe-0048-4f21-84d3-f277d4b34b3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590151794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3590151794
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2472532846
Short name T272
Test name
Test status
Simulation time 185049076 ps
CPU time 5.89 seconds
Started Jul 04 05:23:11 PM PDT 24
Finished Jul 04 05:23:17 PM PDT 24
Peak memory 200264 kb
Host smart-66de2c8a-b3e2-417c-8adb-ca74ca5254a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2472532846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2472532846
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2159364661
Short name T131
Test name
Test status
Simulation time 1094925356 ps
CPU time 61.9 seconds
Started Jul 04 05:23:12 PM PDT 24
Finished Jul 04 05:24:14 PM PDT 24
Peak memory 200284 kb
Host smart-0f9d15df-197f-49ca-91ae-570f8efa1ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159364661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2159364661
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.74261194
Short name T460
Test name
Test status
Simulation time 5457831652 ps
CPU time 1114.52 seconds
Started Jul 04 05:23:12 PM PDT 24
Finished Jul 04 05:41:47 PM PDT 24
Peak memory 755584 kb
Host smart-21d31d91-aa41-48e2-aa6a-11863864034a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=74261194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.74261194
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1996434487
Short name T501
Test name
Test status
Simulation time 7864579267 ps
CPU time 33.12 seconds
Started Jul 04 05:23:13 PM PDT 24
Finished Jul 04 05:23:46 PM PDT 24
Peak memory 200620 kb
Host smart-ba20bedd-b092-4bce-ba55-8070c608413a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996434487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1996434487
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.435698565
Short name T356
Test name
Test status
Simulation time 18649733452 ps
CPU time 113.69 seconds
Started Jul 04 05:23:11 PM PDT 24
Finished Jul 04 05:25:05 PM PDT 24
Peak memory 200304 kb
Host smart-b1e36d3d-1395-4b49-af7f-441a1b857b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435698565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.435698565
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1883072897
Short name T209
Test name
Test status
Simulation time 282681157 ps
CPU time 13.85 seconds
Started Jul 04 05:23:13 PM PDT 24
Finished Jul 04 05:23:27 PM PDT 24
Peak memory 200300 kb
Host smart-21349331-d3d0-4ed8-aaaa-3b010d93b02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883072897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1883072897
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.3043465134
Short name T72
Test name
Test status
Simulation time 69573065658 ps
CPU time 422.43 seconds
Started Jul 04 05:23:12 PM PDT 24
Finished Jul 04 05:30:15 PM PDT 24
Peak memory 200328 kb
Host smart-457811ac-2609-4f8f-ab0a-ce48624341ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043465134 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.3043465134
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1262198232
Short name T231
Test name
Test status
Simulation time 959651978 ps
CPU time 47.44 seconds
Started Jul 04 05:23:12 PM PDT 24
Finished Jul 04 05:24:00 PM PDT 24
Peak memory 200264 kb
Host smart-3fb86422-ba37-4146-95f9-b6f6afcf3a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262198232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1262198232
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.4084238665
Short name T262
Test name
Test status
Simulation time 48278123 ps
CPU time 0.58 seconds
Started Jul 04 05:23:20 PM PDT 24
Finished Jul 04 05:23:21 PM PDT 24
Peak memory 195148 kb
Host smart-9ddad588-5874-4539-a781-5d1ed1259439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084238665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.4084238665
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1712385436
Short name T443
Test name
Test status
Simulation time 1065116545 ps
CPU time 30.15 seconds
Started Jul 04 05:23:20 PM PDT 24
Finished Jul 04 05:23:50 PM PDT 24
Peak memory 200300 kb
Host smart-8a881e9d-0c39-4235-8c92-9ecae09f8064
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1712385436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1712385436
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3991551563
Short name T316
Test name
Test status
Simulation time 11454334984 ps
CPU time 42.51 seconds
Started Jul 04 05:23:20 PM PDT 24
Finished Jul 04 05:24:03 PM PDT 24
Peak memory 200308 kb
Host smart-14fb7cad-24e7-4a64-a994-c8e0fb1e2ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991551563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3991551563
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3969305832
Short name T351
Test name
Test status
Simulation time 3433898189 ps
CPU time 272.06 seconds
Started Jul 04 05:23:20 PM PDT 24
Finished Jul 04 05:27:52 PM PDT 24
Peak memory 478000 kb
Host smart-4131bb6d-6e49-485d-8ee2-85529d414287
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3969305832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3969305832
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.223552786
Short name T256
Test name
Test status
Simulation time 6850726594 ps
CPU time 122.68 seconds
Started Jul 04 05:23:19 PM PDT 24
Finished Jul 04 05:25:22 PM PDT 24
Peak memory 200316 kb
Host smart-1448d44e-1a15-4091-bcfa-a827745ce3b5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223552786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.223552786
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3774911848
Short name T219
Test name
Test status
Simulation time 1633511204 ps
CPU time 20.52 seconds
Started Jul 04 05:23:20 PM PDT 24
Finished Jul 04 05:23:41 PM PDT 24
Peak memory 200316 kb
Host smart-82abdb88-a8c2-479f-9f05-4697ec9664f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774911848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3774911848
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2003373191
Short name T199
Test name
Test status
Simulation time 634851290 ps
CPU time 6.59 seconds
Started Jul 04 05:23:20 PM PDT 24
Finished Jul 04 05:23:27 PM PDT 24
Peak memory 200324 kb
Host smart-ea0b7ae1-416a-4688-9dea-df781e7e2a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003373191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2003373191
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3958607207
Short name T76
Test name
Test status
Simulation time 74386699033 ps
CPU time 1668.67 seconds
Started Jul 04 05:23:24 PM PDT 24
Finished Jul 04 05:51:13 PM PDT 24
Peak memory 745792 kb
Host smart-7db13994-a782-4dfa-a289-131d0952b26b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958607207 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3958607207
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2041177051
Short name T386
Test name
Test status
Simulation time 2292225120 ps
CPU time 28.56 seconds
Started Jul 04 05:23:20 PM PDT 24
Finished Jul 04 05:23:49 PM PDT 24
Peak memory 200340 kb
Host smart-6327f07a-69e3-49d8-bc8b-7319e3d15d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041177051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2041177051
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2942908502
Short name T370
Test name
Test status
Simulation time 19530606 ps
CPU time 0.58 seconds
Started Jul 04 05:23:20 PM PDT 24
Finished Jul 04 05:23:21 PM PDT 24
Peak memory 195172 kb
Host smart-b6a9fb58-94ee-4597-b91b-ecab7cabbd1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942908502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2942908502
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3716948028
Short name T303
Test name
Test status
Simulation time 182173319 ps
CPU time 10.89 seconds
Started Jul 04 05:23:19 PM PDT 24
Finished Jul 04 05:23:30 PM PDT 24
Peak memory 200260 kb
Host smart-e0943ecc-b04d-4ac7-bc9c-bd4c8ce440b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3716948028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3716948028
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.514355420
Short name T394
Test name
Test status
Simulation time 4706406792 ps
CPU time 18.92 seconds
Started Jul 04 05:23:20 PM PDT 24
Finished Jul 04 05:23:39 PM PDT 24
Peak memory 200408 kb
Host smart-3e7c167f-f195-4a48-9e46-dcd678a8a97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514355420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.514355420
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1153486936
Short name T362
Test name
Test status
Simulation time 2323540506 ps
CPU time 110.51 seconds
Started Jul 04 05:23:24 PM PDT 24
Finished Jul 04 05:25:15 PM PDT 24
Peak memory 555176 kb
Host smart-fddbf9ed-84bd-41f1-99bb-849d3f2ae7bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1153486936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1153486936
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.936227533
Short name T291
Test name
Test status
Simulation time 15589436402 ps
CPU time 98.13 seconds
Started Jul 04 05:23:20 PM PDT 24
Finished Jul 04 05:24:58 PM PDT 24
Peak memory 200340 kb
Host smart-8b3dfa48-ef39-499b-9454-0320ec03fcc1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936227533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.936227533
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2420108019
Short name T65
Test name
Test status
Simulation time 3410950762 ps
CPU time 119.84 seconds
Started Jul 04 05:23:25 PM PDT 24
Finished Jul 04 05:25:25 PM PDT 24
Peak memory 200340 kb
Host smart-2869b7fb-0d14-48d9-82a5-b34fb95b63ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420108019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2420108019
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.3785835994
Short name T508
Test name
Test status
Simulation time 1717692045 ps
CPU time 8.21 seconds
Started Jul 04 05:23:21 PM PDT 24
Finished Jul 04 05:23:29 PM PDT 24
Peak memory 200312 kb
Host smart-3015e70e-5fd8-439a-821b-a03e9d7ac366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785835994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3785835994
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2207715407
Short name T73
Test name
Test status
Simulation time 123907983466 ps
CPU time 3376.48 seconds
Started Jul 04 05:23:19 PM PDT 24
Finished Jul 04 06:19:36 PM PDT 24
Peak memory 827280 kb
Host smart-16341fbf-4136-4afc-a7ff-6bd91be7d8c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207715407 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2207715407
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3509012343
Short name T90
Test name
Test status
Simulation time 21318986696 ps
CPU time 140.25 seconds
Started Jul 04 05:23:20 PM PDT 24
Finished Jul 04 05:25:41 PM PDT 24
Peak memory 200364 kb
Host smart-8700a4f6-6fd9-428d-82ea-14f62f959624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509012343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3509012343
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2618634570
Short name T421
Test name
Test status
Simulation time 13140689 ps
CPU time 0.57 seconds
Started Jul 04 05:22:22 PM PDT 24
Finished Jul 04 05:22:23 PM PDT 24
Peak memory 195108 kb
Host smart-04bc80e4-aa18-4ff4-8ac1-9525e2f7f7e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618634570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2618634570
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.675854429
Short name T430
Test name
Test status
Simulation time 191276481 ps
CPU time 11.42 seconds
Started Jul 04 05:22:26 PM PDT 24
Finished Jul 04 05:22:38 PM PDT 24
Peak memory 200280 kb
Host smart-001de566-6931-44f0-9a80-c7ef89766b19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=675854429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.675854429
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3439030809
Short name T43
Test name
Test status
Simulation time 3394446568 ps
CPU time 22.99 seconds
Started Jul 04 05:22:19 PM PDT 24
Finished Jul 04 05:22:43 PM PDT 24
Peak memory 200364 kb
Host smart-9ab67e0b-543c-4bf1-8455-530abfd1fa5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439030809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3439030809
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2942770683
Short name T406
Test name
Test status
Simulation time 4269019639 ps
CPU time 789.77 seconds
Started Jul 04 05:22:24 PM PDT 24
Finished Jul 04 05:35:34 PM PDT 24
Peak memory 696360 kb
Host smart-32df5681-e868-42e3-beb6-045ba3d655c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2942770683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2942770683
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.92070930
Short name T408
Test name
Test status
Simulation time 40790424514 ps
CPU time 179.29 seconds
Started Jul 04 05:22:22 PM PDT 24
Finished Jul 04 05:25:22 PM PDT 24
Peak memory 200316 kb
Host smart-0c2c18da-b3d7-4a7f-8073-c53f1e45567b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92070930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.92070930
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1503578838
Short name T423
Test name
Test status
Simulation time 3250006548 ps
CPU time 157.52 seconds
Started Jul 04 05:22:22 PM PDT 24
Finished Jul 04 05:25:00 PM PDT 24
Peak memory 200348 kb
Host smart-18b246e1-802e-49b1-997e-50018156281a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503578838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1503578838
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2987919227
Short name T48
Test name
Test status
Simulation time 281715328 ps
CPU time 0.93 seconds
Started Jul 04 05:22:20 PM PDT 24
Finished Jul 04 05:22:21 PM PDT 24
Peak memory 218304 kb
Host smart-cedaf137-0c76-4b3e-9a50-a0065e86059f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987919227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2987919227
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3137933604
Short name T528
Test name
Test status
Simulation time 777917824 ps
CPU time 5.01 seconds
Started Jul 04 05:22:22 PM PDT 24
Finished Jul 04 05:22:27 PM PDT 24
Peak memory 200264 kb
Host smart-1cd367c3-d62a-45f5-a5ec-5a26a1d292ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137933604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3137933604
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1573929525
Short name T380
Test name
Test status
Simulation time 128391654372 ps
CPU time 1803.18 seconds
Started Jul 04 05:22:22 PM PDT 24
Finished Jul 04 05:52:25 PM PDT 24
Peak memory 806868 kb
Host smart-ead46887-18eb-45e1-aff6-83fe1e36a7b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573929525 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1573929525
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.1215483655
Short name T331
Test name
Test status
Simulation time 3764953450 ps
CPU time 46.82 seconds
Started Jul 04 05:22:24 PM PDT 24
Finished Jul 04 05:23:11 PM PDT 24
Peak memory 200376 kb
Host smart-e4a9e73b-2a83-4276-b94b-2b1c4564d644
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1215483655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.1215483655
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.3751349713
Short name T295
Test name
Test status
Simulation time 57428243473 ps
CPU time 95.78 seconds
Started Jul 04 05:22:25 PM PDT 24
Finished Jul 04 05:24:01 PM PDT 24
Peak memory 200404 kb
Host smart-541b7538-15b1-41ce-8d42-97f3fa9c0d95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3751349713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.3751349713
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.1336810712
Short name T190
Test name
Test status
Simulation time 6259051377 ps
CPU time 76.46 seconds
Started Jul 04 05:22:22 PM PDT 24
Finished Jul 04 05:23:39 PM PDT 24
Peak memory 200380 kb
Host smart-8286047f-7ff8-4f97-b078-c2664820bca1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1336810712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.1336810712
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.2660092381
Short name T348
Test name
Test status
Simulation time 36263836821 ps
CPU time 604.55 seconds
Started Jul 04 05:22:23 PM PDT 24
Finished Jul 04 05:32:28 PM PDT 24
Peak memory 200376 kb
Host smart-557faf64-e7b8-485d-9a11-b3cf7697dc52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2660092381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2660092381
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.3077311643
Short name T202
Test name
Test status
Simulation time 39749391835 ps
CPU time 2285.88 seconds
Started Jul 04 05:22:22 PM PDT 24
Finished Jul 04 06:00:28 PM PDT 24
Peak memory 216068 kb
Host smart-8ca0e5c5-f5d6-4a40-b8d8-b646bf646c13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3077311643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.3077311643
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.705391318
Short name T81
Test name
Test status
Simulation time 385836046743 ps
CPU time 2573.59 seconds
Started Jul 04 05:22:23 PM PDT 24
Finished Jul 04 06:05:17 PM PDT 24
Peak memory 215856 kb
Host smart-b146ecd0-037f-40d2-a0bd-75b9e04f2979
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=705391318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.705391318
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2237930297
Short name T279
Test name
Test status
Simulation time 3050296339 ps
CPU time 9.73 seconds
Started Jul 04 05:22:22 PM PDT 24
Finished Jul 04 05:22:32 PM PDT 24
Peak memory 200348 kb
Host smart-60276109-3275-4906-8e0a-d8325aa883dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237930297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2237930297
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.98729679
Short name T307
Test name
Test status
Simulation time 12563734 ps
CPU time 0.59 seconds
Started Jul 04 05:23:20 PM PDT 24
Finished Jul 04 05:23:21 PM PDT 24
Peak memory 196212 kb
Host smart-59b2bbe7-21e4-4b93-a619-03c7804e639b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98729679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.98729679
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1399885484
Short name T399
Test name
Test status
Simulation time 3522408961 ps
CPU time 61.37 seconds
Started Jul 04 05:23:28 PM PDT 24
Finished Jul 04 05:24:30 PM PDT 24
Peak memory 200608 kb
Host smart-271106e9-f1ce-47c3-98c1-38d7d0184b8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1399885484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1399885484
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.2554006156
Short name T289
Test name
Test status
Simulation time 257934970 ps
CPU time 13.5 seconds
Started Jul 04 05:23:22 PM PDT 24
Finished Jul 04 05:23:36 PM PDT 24
Peak memory 200340 kb
Host smart-8579fb4a-3195-478b-9ec8-f4df69b90877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554006156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2554006156
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3740513105
Short name T428
Test name
Test status
Simulation time 322906992 ps
CPU time 15.37 seconds
Started Jul 04 05:23:20 PM PDT 24
Finished Jul 04 05:23:36 PM PDT 24
Peak memory 227136 kb
Host smart-e8fbef8c-2e82-45a5-8412-c1b32a696726
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3740513105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3740513105
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.2078522237
Short name T335
Test name
Test status
Simulation time 209989933 ps
CPU time 11.99 seconds
Started Jul 04 05:23:17 PM PDT 24
Finished Jul 04 05:23:30 PM PDT 24
Peak memory 200240 kb
Host smart-bf5dc546-7acb-4ac2-8e87-9642b1e83330
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078522237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2078522237
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.134913914
Short name T304
Test name
Test status
Simulation time 9028397996 ps
CPU time 154.91 seconds
Started Jul 04 05:23:20 PM PDT 24
Finished Jul 04 05:25:55 PM PDT 24
Peak memory 200360 kb
Host smart-8a3b6581-a8b2-4fd0-b8da-682dcc64cc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134913914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.134913914
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2932565849
Short name T311
Test name
Test status
Simulation time 2006140337 ps
CPU time 15.14 seconds
Started Jul 04 05:23:22 PM PDT 24
Finished Jul 04 05:23:37 PM PDT 24
Peak memory 200268 kb
Host smart-bce2aebb-117d-4c38-9415-4387bb84af18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932565849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2932565849
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.4198239945
Short name T215
Test name
Test status
Simulation time 19001871260 ps
CPU time 498.89 seconds
Started Jul 04 05:23:20 PM PDT 24
Finished Jul 04 05:31:39 PM PDT 24
Peak memory 200348 kb
Host smart-34b583a2-5417-4dee-9fdb-e3318f18fc8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198239945 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.4198239945
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3932488898
Short name T214
Test name
Test status
Simulation time 1099981542 ps
CPU time 9.78 seconds
Started Jul 04 05:23:20 PM PDT 24
Finished Jul 04 05:23:30 PM PDT 24
Peak memory 200348 kb
Host smart-b5caafa5-2f5b-47ab-b104-ee2abf4ad78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932488898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3932488898
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3614232238
Short name T312
Test name
Test status
Simulation time 13924298 ps
CPU time 0.57 seconds
Started Jul 04 05:23:28 PM PDT 24
Finished Jul 04 05:23:29 PM PDT 24
Peak memory 195140 kb
Host smart-74741713-9ddc-4d9d-8096-d221d8ea1b41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614232238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3614232238
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2856423571
Short name T198
Test name
Test status
Simulation time 746410641 ps
CPU time 41.61 seconds
Started Jul 04 05:23:27 PM PDT 24
Finished Jul 04 05:24:09 PM PDT 24
Peak memory 200332 kb
Host smart-eec5055f-fbd2-425f-bf81-8708a8b10100
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2856423571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2856423571
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1727173374
Short name T416
Test name
Test status
Simulation time 10297321069 ps
CPU time 33.99 seconds
Started Jul 04 05:23:28 PM PDT 24
Finished Jul 04 05:24:03 PM PDT 24
Peak memory 200196 kb
Host smart-ae7e5808-5740-43da-8834-2a84e63c1c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727173374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1727173374
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2951472226
Short name T227
Test name
Test status
Simulation time 6225406229 ps
CPU time 275.25 seconds
Started Jul 04 05:23:27 PM PDT 24
Finished Jul 04 05:28:03 PM PDT 24
Peak memory 453484 kb
Host smart-fd110373-5d2f-4790-94d3-8087cbe88bde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2951472226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2951472226
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.958306527
Short name T165
Test name
Test status
Simulation time 14513796041 ps
CPU time 183.44 seconds
Started Jul 04 05:23:28 PM PDT 24
Finished Jul 04 05:26:31 PM PDT 24
Peak memory 200276 kb
Host smart-6bcb0ffe-8cc8-4346-b584-89cbaa33da6e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958306527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.958306527
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3855078488
Short name T456
Test name
Test status
Simulation time 6961605121 ps
CPU time 116.76 seconds
Started Jul 04 05:23:27 PM PDT 24
Finished Jul 04 05:25:24 PM PDT 24
Peak memory 216420 kb
Host smart-544c5a8f-dee8-4bc1-992d-559de8b96279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855078488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3855078488
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.4185833211
Short name T449
Test name
Test status
Simulation time 39666567 ps
CPU time 1.05 seconds
Started Jul 04 05:23:23 PM PDT 24
Finished Jul 04 05:23:24 PM PDT 24
Peak memory 200528 kb
Host smart-f507771c-1000-4d75-adf0-01b5bcc58c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185833211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.4185833211
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2330273890
Short name T40
Test name
Test status
Simulation time 1249287404 ps
CPU time 73.29 seconds
Started Jul 04 05:23:29 PM PDT 24
Finished Jul 04 05:24:42 PM PDT 24
Peak memory 200448 kb
Host smart-84bb3976-ca7b-4d14-a2dd-20a0955c0e72
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330273890 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2330273890
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.3468446689
Short name T290
Test name
Test status
Simulation time 9262162203 ps
CPU time 40.56 seconds
Started Jul 04 05:23:28 PM PDT 24
Finished Jul 04 05:24:09 PM PDT 24
Peak memory 200412 kb
Host smart-b513fe59-5b9d-4159-92e4-827e5da82e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468446689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3468446689
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1026194120
Short name T354
Test name
Test status
Simulation time 14977875 ps
CPU time 0.64 seconds
Started Jul 04 05:23:29 PM PDT 24
Finished Jul 04 05:23:29 PM PDT 24
Peak memory 196144 kb
Host smart-23d5a312-7de5-4520-b035-f88470f2063b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026194120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1026194120
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2226361263
Short name T375
Test name
Test status
Simulation time 1192160946 ps
CPU time 20.05 seconds
Started Jul 04 05:23:29 PM PDT 24
Finished Jul 04 05:23:49 PM PDT 24
Peak memory 200352 kb
Host smart-635eb46c-ed50-498f-95d4-e624f0184f06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2226361263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2226361263
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1244130464
Short name T503
Test name
Test status
Simulation time 11507480559 ps
CPU time 34.58 seconds
Started Jul 04 05:23:27 PM PDT 24
Finished Jul 04 05:24:02 PM PDT 24
Peak memory 200360 kb
Host smart-4eab206f-9135-4732-8b51-0758a60d077e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244130464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1244130464
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2039082103
Short name T483
Test name
Test status
Simulation time 506073003 ps
CPU time 101.55 seconds
Started Jul 04 05:23:30 PM PDT 24
Finished Jul 04 05:25:11 PM PDT 24
Peak memory 564632 kb
Host smart-59b036a2-099e-4fde-bda7-fc8e4630528b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2039082103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2039082103
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.168661283
Short name T413
Test name
Test status
Simulation time 6392136544 ps
CPU time 85.43 seconds
Started Jul 04 05:23:28 PM PDT 24
Finished Jul 04 05:24:54 PM PDT 24
Peak memory 200644 kb
Host smart-319d4e89-3452-422c-8d49-ee232e8781f7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168661283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.168661283
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.879748937
Short name T137
Test name
Test status
Simulation time 3952582348 ps
CPU time 16.69 seconds
Started Jul 04 05:23:28 PM PDT 24
Finished Jul 04 05:23:45 PM PDT 24
Peak memory 200360 kb
Host smart-d5be60a3-6d4b-43e0-8bbe-e8d723fafdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879748937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.879748937
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.3523482239
Short name T3
Test name
Test status
Simulation time 576409918 ps
CPU time 9.27 seconds
Started Jul 04 05:23:26 PM PDT 24
Finished Jul 04 05:23:36 PM PDT 24
Peak memory 200268 kb
Host smart-e8c6b1ad-f711-44c2-a8a9-8ad31014ad81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523482239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.3523482239
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.4075941355
Short name T313
Test name
Test status
Simulation time 32071378364 ps
CPU time 4134.59 seconds
Started Jul 04 05:23:29 PM PDT 24
Finished Jul 04 06:32:24 PM PDT 24
Peak memory 829248 kb
Host smart-99f8efc4-7ec0-47a5-bca9-b80854cdaefc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075941355 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.4075941355
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1856079145
Short name T519
Test name
Test status
Simulation time 4580526970 ps
CPU time 122.8 seconds
Started Jul 04 05:23:28 PM PDT 24
Finished Jul 04 05:25:31 PM PDT 24
Peak memory 200332 kb
Host smart-4d0ea42d-2c73-4c5e-ad14-e2077add838c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856079145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1856079145
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.4251353513
Short name T191
Test name
Test status
Simulation time 18630250 ps
CPU time 0.58 seconds
Started Jul 04 05:23:37 PM PDT 24
Finished Jul 04 05:23:37 PM PDT 24
Peak memory 195788 kb
Host smart-250a85fa-1e52-4bc6-a4c0-de6ccc2dc649
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251353513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.4251353513
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.2765904339
Short name T498
Test name
Test status
Simulation time 243962193 ps
CPU time 13.04 seconds
Started Jul 04 05:23:36 PM PDT 24
Finished Jul 04 05:23:49 PM PDT 24
Peak memory 200288 kb
Host smart-78c7b0f0-b33a-4b63-bdc8-f378303cc620
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2765904339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2765904339
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.312202664
Short name T407
Test name
Test status
Simulation time 6439694002 ps
CPU time 11.46 seconds
Started Jul 04 05:23:38 PM PDT 24
Finished Jul 04 05:23:50 PM PDT 24
Peak memory 200376 kb
Host smart-0a7ec675-af32-46fa-9556-7369ea56df1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312202664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.312202664
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1203925547
Short name T422
Test name
Test status
Simulation time 2123972392 ps
CPU time 55.84 seconds
Started Jul 04 05:23:38 PM PDT 24
Finished Jul 04 05:24:34 PM PDT 24
Peak memory 263356 kb
Host smart-4f168ded-4db9-4afa-ac8f-012d9da8e3ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1203925547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1203925547
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.911684378
Short name T396
Test name
Test status
Simulation time 2001929914 ps
CPU time 5.96 seconds
Started Jul 04 05:23:35 PM PDT 24
Finished Jul 04 05:23:41 PM PDT 24
Peak memory 200168 kb
Host smart-fee9d07d-bfe6-44c8-951d-2e92f457c77d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911684378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.911684378
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2789077872
Short name T274
Test name
Test status
Simulation time 1754348042 ps
CPU time 99.79 seconds
Started Jul 04 05:23:35 PM PDT 24
Finished Jul 04 05:25:15 PM PDT 24
Peak memory 200324 kb
Host smart-86ab6876-3bb8-47fe-9bb0-f4b409fd2778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789077872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2789077872
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1343962882
Short name T127
Test name
Test status
Simulation time 321123844 ps
CPU time 13.32 seconds
Started Jul 04 05:23:38 PM PDT 24
Finished Jul 04 05:23:52 PM PDT 24
Peak memory 200296 kb
Host smart-5c5d7b85-1d77-42e8-91ff-012f58525cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343962882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1343962882
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3401430740
Short name T485
Test name
Test status
Simulation time 50451062280 ps
CPU time 177.59 seconds
Started Jul 04 05:23:35 PM PDT 24
Finished Jul 04 05:26:33 PM PDT 24
Peak memory 200312 kb
Host smart-d4091715-70bc-4238-a8ce-45afebc71a0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401430740 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3401430740
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_alert_test.496042238
Short name T395
Test name
Test status
Simulation time 15781221 ps
CPU time 0.61 seconds
Started Jul 04 05:23:33 PM PDT 24
Finished Jul 04 05:23:34 PM PDT 24
Peak memory 196872 kb
Host smart-16bcd18b-d76b-4bae-9b38-29112f7fa8fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496042238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.496042238
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.4053850343
Short name T297
Test name
Test status
Simulation time 5935169812 ps
CPU time 85.51 seconds
Started Jul 04 05:23:37 PM PDT 24
Finished Jul 04 05:25:02 PM PDT 24
Peak memory 200364 kb
Host smart-67a18f9e-0333-4f02-a678-ec1148c3a539
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4053850343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.4053850343
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.146843538
Short name T418
Test name
Test status
Simulation time 931750503 ps
CPU time 15.96 seconds
Started Jul 04 05:23:36 PM PDT 24
Finished Jul 04 05:23:52 PM PDT 24
Peak memory 200312 kb
Host smart-ba6d2d9b-a02f-40a6-a7bf-3b6773933038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146843538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.146843538
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.4247602349
Short name T277
Test name
Test status
Simulation time 4508388149 ps
CPU time 753.42 seconds
Started Jul 04 05:23:35 PM PDT 24
Finished Jul 04 05:36:09 PM PDT 24
Peak memory 766540 kb
Host smart-14199653-b8a5-4912-8a65-6a976c084706
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4247602349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.4247602349
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.254265004
Short name T332
Test name
Test status
Simulation time 9599496481 ps
CPU time 167.19 seconds
Started Jul 04 05:23:38 PM PDT 24
Finished Jul 04 05:26:25 PM PDT 24
Peak memory 200332 kb
Host smart-2b6dccee-df50-47ca-8d2d-82002b2989f3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254265004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.254265004
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3045993140
Short name T141
Test name
Test status
Simulation time 318608698 ps
CPU time 18.25 seconds
Started Jul 04 05:23:35 PM PDT 24
Finished Jul 04 05:23:53 PM PDT 24
Peak memory 200280 kb
Host smart-29612f48-d37a-401c-91e0-f64269b70197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045993140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3045993140
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2467342015
Short name T176
Test name
Test status
Simulation time 153778174 ps
CPU time 1.88 seconds
Started Jul 04 05:23:36 PM PDT 24
Finished Jul 04 05:23:38 PM PDT 24
Peak memory 200280 kb
Host smart-6830214b-f1ed-49a9-8348-ddd88040fb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467342015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2467342015
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1092778587
Short name T520
Test name
Test status
Simulation time 124831959668 ps
CPU time 1066.65 seconds
Started Jul 04 05:23:34 PM PDT 24
Finished Jul 04 05:41:21 PM PDT 24
Peak memory 719252 kb
Host smart-dadc1aa1-d482-4017-ac90-c627ba29231c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092778587 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1092778587
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.191949346
Short name T91
Test name
Test status
Simulation time 2649857609 ps
CPU time 42.45 seconds
Started Jul 04 05:23:35 PM PDT 24
Finished Jul 04 05:24:18 PM PDT 24
Peak memory 200372 kb
Host smart-6f32bdc6-5576-4035-907f-827e85167677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191949346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.191949346
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.346505513
Short name T457
Test name
Test status
Simulation time 13068289 ps
CPU time 0.61 seconds
Started Jul 04 05:23:35 PM PDT 24
Finished Jul 04 05:23:36 PM PDT 24
Peak memory 196100 kb
Host smart-2d17c357-a4f3-44b5-b849-300f3d0b5a3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346505513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.346505513
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3590501037
Short name T157
Test name
Test status
Simulation time 1073589427 ps
CPU time 16.24 seconds
Started Jul 04 05:23:40 PM PDT 24
Finished Jul 04 05:23:56 PM PDT 24
Peak memory 200280 kb
Host smart-9374339d-a984-46c8-a17d-904115d35ef7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3590501037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3590501037
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1808079636
Short name T368
Test name
Test status
Simulation time 1292821176 ps
CPU time 24.34 seconds
Started Jul 04 05:23:35 PM PDT 24
Finished Jul 04 05:23:59 PM PDT 24
Peak memory 200328 kb
Host smart-d217dda2-8ab3-4cac-91d6-3112305f99e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808079636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1808079636
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.816691797
Short name T369
Test name
Test status
Simulation time 6046430799 ps
CPU time 412.54 seconds
Started Jul 04 05:23:38 PM PDT 24
Finished Jul 04 05:30:31 PM PDT 24
Peak memory 688992 kb
Host smart-571f8427-8eee-4f54-82b4-6f8aab35591e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=816691797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.816691797
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.171164801
Short name T315
Test name
Test status
Simulation time 9472515893 ps
CPU time 171.29 seconds
Started Jul 04 05:23:35 PM PDT 24
Finished Jul 04 05:26:27 PM PDT 24
Peak memory 200392 kb
Host smart-34c23714-16ab-443c-80fc-3f5ad724a8ca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171164801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.171164801
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.232419184
Short name T479
Test name
Test status
Simulation time 7233617747 ps
CPU time 69.03 seconds
Started Jul 04 05:23:35 PM PDT 24
Finished Jul 04 05:24:44 PM PDT 24
Peak memory 200368 kb
Host smart-ab6349f5-c5e5-4fd0-9ed1-5605711df6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232419184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.232419184
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.787661568
Short name T305
Test name
Test status
Simulation time 1200017564 ps
CPU time 11.19 seconds
Started Jul 04 05:23:36 PM PDT 24
Finished Jul 04 05:23:47 PM PDT 24
Peak memory 200340 kb
Host smart-e6610312-bc26-4fb2-91b3-788ac9aa9e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787661568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.787661568
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3348217276
Short name T128
Test name
Test status
Simulation time 216242981204 ps
CPU time 2700.31 seconds
Started Jul 04 05:23:35 PM PDT 24
Finished Jul 04 06:08:35 PM PDT 24
Peak memory 829880 kb
Host smart-b238bc8c-2133-4c02-94e3-47871647c186
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348217276 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3348217276
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.292284035
Short name T435
Test name
Test status
Simulation time 9424599985 ps
CPU time 133.19 seconds
Started Jul 04 05:23:35 PM PDT 24
Finished Jul 04 05:25:48 PM PDT 24
Peak memory 200336 kb
Host smart-f1fcf7b7-d870-4a99-b5ce-11680d1271d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292284035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.292284035
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1334880521
Short name T173
Test name
Test status
Simulation time 24292212 ps
CPU time 0.6 seconds
Started Jul 04 05:23:43 PM PDT 24
Finished Jul 04 05:23:44 PM PDT 24
Peak memory 196184 kb
Host smart-da516efd-1017-4201-bd8a-52aeaca8fb81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334880521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1334880521
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3561135747
Short name T220
Test name
Test status
Simulation time 1892035871 ps
CPU time 27.18 seconds
Started Jul 04 05:23:35 PM PDT 24
Finished Jul 04 05:24:03 PM PDT 24
Peak memory 200336 kb
Host smart-2fd4e521-683d-488c-9718-e5ff885cbf3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3561135747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3561135747
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.17397414
Short name T506
Test name
Test status
Simulation time 58144090 ps
CPU time 2.32 seconds
Started Jul 04 05:23:38 PM PDT 24
Finished Jul 04 05:23:41 PM PDT 24
Peak memory 200320 kb
Host smart-705ca6f9-7a2e-45af-928c-90158d38f5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17397414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.17397414
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2300109826
Short name T1
Test name
Test status
Simulation time 4050457390 ps
CPU time 610.98 seconds
Started Jul 04 05:23:36 PM PDT 24
Finished Jul 04 05:33:47 PM PDT 24
Peak memory 681720 kb
Host smart-f10b105d-10f5-476c-b585-32423c9809da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2300109826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2300109826
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.862290267
Short name T288
Test name
Test status
Simulation time 3274102449 ps
CPU time 2.99 seconds
Started Jul 04 05:23:43 PM PDT 24
Finished Jul 04 05:23:47 PM PDT 24
Peak memory 200280 kb
Host smart-58f8348b-4442-44b8-b607-677c2d480aea
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862290267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.862290267
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2485898752
Short name T450
Test name
Test status
Simulation time 1533404441 ps
CPU time 21.88 seconds
Started Jul 04 05:23:35 PM PDT 24
Finished Jul 04 05:23:57 PM PDT 24
Peak memory 200336 kb
Host smart-f8f11b28-717e-4137-9b06-801f8e82d2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485898752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2485898752
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1481993379
Short name T510
Test name
Test status
Simulation time 764711269 ps
CPU time 8.86 seconds
Started Jul 04 05:23:39 PM PDT 24
Finished Jul 04 05:23:48 PM PDT 24
Peak memory 200288 kb
Host smart-9c4f384b-2cf0-4983-8acb-c7a2ffea7da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481993379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1481993379
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2028437836
Short name T56
Test name
Test status
Simulation time 5201821873 ps
CPU time 88.06 seconds
Started Jul 04 05:23:41 PM PDT 24
Finished Jul 04 05:25:09 PM PDT 24
Peak memory 200340 kb
Host smart-ee0e05f5-7bfa-4b13-9878-9678da2d6fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028437836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2028437836
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2714617484
Short name T17
Test name
Test status
Simulation time 21165497 ps
CPU time 0.62 seconds
Started Jul 04 05:23:43 PM PDT 24
Finished Jul 04 05:23:44 PM PDT 24
Peak memory 196192 kb
Host smart-ffeff868-4717-4404-a710-b749931d7759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714617484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2714617484
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3676567699
Short name T325
Test name
Test status
Simulation time 6789285180 ps
CPU time 93.3 seconds
Started Jul 04 05:23:41 PM PDT 24
Finished Jul 04 05:25:14 PM PDT 24
Peak memory 200304 kb
Host smart-be4a7a5d-5a81-45f2-bd82-af1d5efa9f07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3676567699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3676567699
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.681908817
Short name T387
Test name
Test status
Simulation time 429266257 ps
CPU time 25.29 seconds
Started Jul 04 05:23:43 PM PDT 24
Finished Jul 04 05:24:09 PM PDT 24
Peak memory 200276 kb
Host smart-d55aa049-69ed-4e03-a736-0fd893541a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681908817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.681908817
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.4279416529
Short name T182
Test name
Test status
Simulation time 16664075436 ps
CPU time 716.03 seconds
Started Jul 04 05:23:42 PM PDT 24
Finished Jul 04 05:35:39 PM PDT 24
Peak memory 726860 kb
Host smart-f853b975-b611-47e3-aa9b-8c063c640ae1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4279416529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.4279416529
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.768719669
Short name T263
Test name
Test status
Simulation time 41973250089 ps
CPU time 266.95 seconds
Started Jul 04 05:23:44 PM PDT 24
Finished Jul 04 05:28:11 PM PDT 24
Peak memory 200340 kb
Host smart-ef2c78d8-f7d3-47af-ac92-df73a44aeff9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768719669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.768719669
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3287173048
Short name T253
Test name
Test status
Simulation time 9967166678 ps
CPU time 131.48 seconds
Started Jul 04 05:23:40 PM PDT 24
Finished Jul 04 05:25:52 PM PDT 24
Peak memory 200400 kb
Host smart-7811c0b1-684d-4034-854c-921baff98ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287173048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3287173048
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2038007992
Short name T234
Test name
Test status
Simulation time 587630209 ps
CPU time 3.23 seconds
Started Jul 04 05:23:40 PM PDT 24
Finished Jul 04 05:23:43 PM PDT 24
Peak memory 200300 kb
Host smart-a8c7dc99-eb82-4455-b402-f823f98cff28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038007992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2038007992
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2545937962
Short name T134
Test name
Test status
Simulation time 52239126738 ps
CPU time 1027.54 seconds
Started Jul 04 05:23:43 PM PDT 24
Finished Jul 04 05:40:51 PM PDT 24
Peak memory 489280 kb
Host smart-ad1a4237-b3e5-4fd2-9e27-2ce24e1368d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545937962 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2545937962
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3713659183
Short name T452
Test name
Test status
Simulation time 238147377 ps
CPU time 4.31 seconds
Started Jul 04 05:23:41 PM PDT 24
Finished Jul 04 05:23:45 PM PDT 24
Peak memory 200308 kb
Host smart-dfee42e2-f414-458d-95be-9ad59f90232a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713659183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3713659183
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1426087075
Short name T298
Test name
Test status
Simulation time 43790734 ps
CPU time 0.59 seconds
Started Jul 04 05:23:51 PM PDT 24
Finished Jul 04 05:23:52 PM PDT 24
Peak memory 196804 kb
Host smart-7c3b85a9-4732-4f0f-a0d4-95dc6b949394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426087075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1426087075
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.855555727
Short name T229
Test name
Test status
Simulation time 475784028 ps
CPU time 13.07 seconds
Started Jul 04 05:23:42 PM PDT 24
Finished Jul 04 05:23:55 PM PDT 24
Peak memory 200308 kb
Host smart-c374222e-e752-4c5d-8ba0-8d2acb7ca37d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=855555727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.855555727
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.751990613
Short name T14
Test name
Test status
Simulation time 2414386606 ps
CPU time 30.82 seconds
Started Jul 04 05:23:51 PM PDT 24
Finished Jul 04 05:24:22 PM PDT 24
Peak memory 200332 kb
Host smart-0137a27b-4536-4217-a6a4-066a607a80f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751990613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.751990613
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.349177918
Short name T446
Test name
Test status
Simulation time 585090142 ps
CPU time 62.64 seconds
Started Jul 04 05:23:44 PM PDT 24
Finished Jul 04 05:24:47 PM PDT 24
Peak memory 252904 kb
Host smart-b863c1f7-7cc3-4616-8c80-60ee02a45585
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=349177918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.349177918
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2812469791
Short name T136
Test name
Test status
Simulation time 9345618634 ps
CPU time 88.86 seconds
Started Jul 04 05:23:56 PM PDT 24
Finished Jul 04 05:25:25 PM PDT 24
Peak memory 200340 kb
Host smart-20f3b2f2-d8e4-4bfe-8db4-dec2dbb1fd42
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812469791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2812469791
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2520614317
Short name T168
Test name
Test status
Simulation time 7709837144 ps
CPU time 130.9 seconds
Started Jul 04 05:23:41 PM PDT 24
Finished Jul 04 05:25:52 PM PDT 24
Peak memory 216736 kb
Host smart-e95df161-e871-456a-85ee-0c7d934f851f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520614317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2520614317
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1135299997
Short name T26
Test name
Test status
Simulation time 330611983 ps
CPU time 3.57 seconds
Started Jul 04 05:23:40 PM PDT 24
Finished Jul 04 05:23:44 PM PDT 24
Peak memory 200280 kb
Host smart-fe9d6987-785d-47c7-ab2b-c576fb03eee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135299997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1135299997
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1721469909
Short name T260
Test name
Test status
Simulation time 21496008339 ps
CPU time 1027.47 seconds
Started Jul 04 05:23:50 PM PDT 24
Finished Jul 04 05:40:58 PM PDT 24
Peak memory 200288 kb
Host smart-016996e0-7d46-48bf-96a7-8139483b7c34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721469909 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1721469909
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2021733333
Short name T284
Test name
Test status
Simulation time 5838857984 ps
CPU time 26.03 seconds
Started Jul 04 05:23:52 PM PDT 24
Finished Jul 04 05:24:19 PM PDT 24
Peak memory 200360 kb
Host smart-dacff865-0b06-4533-9715-f2e466b56d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021733333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2021733333
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1464574991
Short name T400
Test name
Test status
Simulation time 12703164 ps
CPU time 0.59 seconds
Started Jul 04 05:23:49 PM PDT 24
Finished Jul 04 05:23:50 PM PDT 24
Peak memory 196172 kb
Host smart-02e253a4-bfa6-4196-9cec-030802141a61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464574991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1464574991
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.4197501522
Short name T162
Test name
Test status
Simulation time 1461762389 ps
CPU time 84.71 seconds
Started Jul 04 05:23:50 PM PDT 24
Finished Jul 04 05:25:15 PM PDT 24
Peak memory 200300 kb
Host smart-7d336633-45b3-45c1-859b-358c5116c4ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4197501522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.4197501522
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3885781497
Short name T358
Test name
Test status
Simulation time 8636012864 ps
CPU time 23.38 seconds
Started Jul 04 05:23:50 PM PDT 24
Finished Jul 04 05:24:14 PM PDT 24
Peak memory 200384 kb
Host smart-94e482a7-e048-4f16-9ef3-bbe9777c9c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885781497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3885781497
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2865379265
Short name T186
Test name
Test status
Simulation time 17005772652 ps
CPU time 837.72 seconds
Started Jul 04 05:23:52 PM PDT 24
Finished Jul 04 05:37:50 PM PDT 24
Peak memory 746284 kb
Host smart-8088c81f-cff1-4f9b-967e-f1609e9cf648
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2865379265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2865379265
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3451506084
Short name T280
Test name
Test status
Simulation time 9575493647 ps
CPU time 177.26 seconds
Started Jul 04 05:23:53 PM PDT 24
Finished Jul 04 05:26:50 PM PDT 24
Peak memory 200352 kb
Host smart-21686239-0aaf-42b1-9970-da44bef04e25
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451506084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3451506084
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1829748900
Short name T266
Test name
Test status
Simulation time 9350619805 ps
CPU time 94.65 seconds
Started Jul 04 05:23:50 PM PDT 24
Finished Jul 04 05:25:25 PM PDT 24
Peak memory 200368 kb
Host smart-0d5177bf-4ec8-4eb1-aa96-bf3390bf77db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829748900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1829748900
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3728881297
Short name T212
Test name
Test status
Simulation time 263970510 ps
CPU time 11.68 seconds
Started Jul 04 05:23:50 PM PDT 24
Finished Jul 04 05:24:01 PM PDT 24
Peak memory 200240 kb
Host smart-80675b33-2c1c-4714-a8e8-5f81cf72a63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728881297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3728881297
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.765255032
Short name T465
Test name
Test status
Simulation time 102475365552 ps
CPU time 2391.77 seconds
Started Jul 04 05:23:51 PM PDT 24
Finished Jul 04 06:03:43 PM PDT 24
Peak memory 782416 kb
Host smart-83662e82-ee1f-4569-a320-5a8605506b56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765255032 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.765255032
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.440050086
Short name T496
Test name
Test status
Simulation time 4069774822 ps
CPU time 52.17 seconds
Started Jul 04 05:23:56 PM PDT 24
Finished Jul 04 05:24:48 PM PDT 24
Peak memory 200352 kb
Host smart-63c0df50-ec64-4cfe-bc33-ab76a947fff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440050086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.440050086
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3772249572
Short name T402
Test name
Test status
Simulation time 32620613 ps
CPU time 0.6 seconds
Started Jul 04 05:22:34 PM PDT 24
Finished Jul 04 05:22:35 PM PDT 24
Peak memory 195116 kb
Host smart-cc154877-07b5-4aa0-b64f-607a03e7dbd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772249572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3772249572
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2488282755
Short name T392
Test name
Test status
Simulation time 1103823809 ps
CPU time 32.56 seconds
Started Jul 04 05:22:23 PM PDT 24
Finished Jul 04 05:22:56 PM PDT 24
Peak memory 200308 kb
Host smart-198caaaf-d27e-46b7-adb3-0fd691dfe39a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2488282755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2488282755
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.907840669
Short name T53
Test name
Test status
Simulation time 38747730699 ps
CPU time 57.75 seconds
Started Jul 04 05:22:21 PM PDT 24
Finished Jul 04 05:23:19 PM PDT 24
Peak memory 200328 kb
Host smart-6c1f2bee-2a31-4a14-8e5d-b82cc6172677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907840669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.907840669
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.864024437
Short name T167
Test name
Test status
Simulation time 12161318178 ps
CPU time 1257.79 seconds
Started Jul 04 05:22:20 PM PDT 24
Finished Jul 04 05:43:18 PM PDT 24
Peak memory 765176 kb
Host smart-b7044238-9224-4b3c-ba12-286f1aa00179
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=864024437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.864024437
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1412094639
Short name T216
Test name
Test status
Simulation time 5232296651 ps
CPU time 92.41 seconds
Started Jul 04 05:22:23 PM PDT 24
Finished Jul 04 05:23:55 PM PDT 24
Peak memory 200296 kb
Host smart-05e9df5b-b9ab-432a-a4d6-86cbffec721f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412094639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1412094639
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.123160500
Short name T285
Test name
Test status
Simulation time 18269674924 ps
CPU time 115.73 seconds
Started Jul 04 05:22:20 PM PDT 24
Finished Jul 04 05:24:16 PM PDT 24
Peak memory 200528 kb
Host smart-77e270bb-1f77-47b3-a32a-f89ae1c9a3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123160500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.123160500
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1041854203
Short name T49
Test name
Test status
Simulation time 158795459 ps
CPU time 0.98 seconds
Started Jul 04 05:22:24 PM PDT 24
Finished Jul 04 05:22:26 PM PDT 24
Peak memory 219388 kb
Host smart-69c65e2b-b416-461b-98b2-aab774a7eb9f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041854203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1041854203
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2824990040
Short name T258
Test name
Test status
Simulation time 1635796849 ps
CPU time 2.94 seconds
Started Jul 04 05:22:21 PM PDT 24
Finished Jul 04 05:22:24 PM PDT 24
Peak memory 200272 kb
Host smart-dd708d43-dcf7-487c-b915-d0bf74cd5691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824990040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2824990040
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1808030264
Short name T350
Test name
Test status
Simulation time 102256805769 ps
CPU time 2344.34 seconds
Started Jul 04 05:22:24 PM PDT 24
Finished Jul 04 06:01:29 PM PDT 24
Peak memory 797684 kb
Host smart-4e69b67b-6441-43af-9a09-246a92bc9ba3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808030264 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1808030264
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.2978677037
Short name T179
Test name
Test status
Simulation time 10374490072 ps
CPU time 43.26 seconds
Started Jul 04 05:22:21 PM PDT 24
Finished Jul 04 05:23:04 PM PDT 24
Peak memory 200324 kb
Host smart-0cc8a188-8269-4f76-b807-9e8649dab5ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2978677037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.2978677037
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.2809060126
Short name T377
Test name
Test status
Simulation time 6082965082 ps
CPU time 69.49 seconds
Started Jul 04 05:22:25 PM PDT 24
Finished Jul 04 05:23:35 PM PDT 24
Peak memory 200332 kb
Host smart-15365fa3-2e23-487b-8a15-52b88ff79263
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2809060126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.2809060126
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.2227673874
Short name T175
Test name
Test status
Simulation time 34752579821 ps
CPU time 86.37 seconds
Started Jul 04 05:22:26 PM PDT 24
Finished Jul 04 05:23:52 PM PDT 24
Peak memory 200332 kb
Host smart-a4b37244-56a5-4683-a1a2-bd001297cc19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2227673874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.2227673874
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.2974223067
Short name T245
Test name
Test status
Simulation time 142991609354 ps
CPU time 619.27 seconds
Started Jul 04 05:22:25 PM PDT 24
Finished Jul 04 05:32:45 PM PDT 24
Peak memory 200364 kb
Host smart-85768a4c-b4c7-4a9d-931c-61837243deb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2974223067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2974223067
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.4074287562
Short name T404
Test name
Test status
Simulation time 155463509227 ps
CPU time 2149.56 seconds
Started Jul 04 05:22:24 PM PDT 24
Finished Jul 04 05:58:14 PM PDT 24
Peak memory 216432 kb
Host smart-d3f71cb8-c168-4c94-b715-c1daa578db5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4074287562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.4074287562
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.3253391890
Short name T353
Test name
Test status
Simulation time 76650666797 ps
CPU time 2355.32 seconds
Started Jul 04 05:22:22 PM PDT 24
Finished Jul 04 06:01:37 PM PDT 24
Peak memory 215844 kb
Host smart-a2500d42-d543-4b69-b99f-2222c20789e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3253391890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.3253391890
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3679357389
Short name T294
Test name
Test status
Simulation time 11870073461 ps
CPU time 143.2 seconds
Started Jul 04 05:22:24 PM PDT 24
Finished Jul 04 05:24:48 PM PDT 24
Peak memory 200364 kb
Host smart-86159afa-a1a1-4f67-bc01-98adb204c87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679357389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3679357389
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1586958973
Short name T458
Test name
Test status
Simulation time 14313250 ps
CPU time 0.6 seconds
Started Jul 04 05:23:59 PM PDT 24
Finished Jul 04 05:23:59 PM PDT 24
Peak memory 196180 kb
Host smart-bd975620-5cd6-48cf-b678-9409ca219a82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586958973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1586958973
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.4105953110
Short name T481
Test name
Test status
Simulation time 903104726 ps
CPU time 25.35 seconds
Started Jul 04 05:23:56 PM PDT 24
Finished Jul 04 05:24:22 PM PDT 24
Peak memory 200320 kb
Host smart-68ff29be-b2bf-42e7-a9b2-3a98c16b82ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105953110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.4105953110
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.772472084
Short name T172
Test name
Test status
Simulation time 508364984 ps
CPU time 25.06 seconds
Started Jul 04 05:23:58 PM PDT 24
Finished Jul 04 05:24:24 PM PDT 24
Peak memory 255000 kb
Host smart-6df8a0cd-cddc-4f58-a7d5-169e98a03539
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=772472084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.772472084
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.487346046
Short name T153
Test name
Test status
Simulation time 19623555146 ps
CPU time 70.36 seconds
Started Jul 04 05:23:56 PM PDT 24
Finished Jul 04 05:25:07 PM PDT 24
Peak memory 200324 kb
Host smart-f88d84e7-d379-4757-99c6-48192422a637
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487346046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.487346046
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1123312326
Short name T468
Test name
Test status
Simulation time 41682037652 ps
CPU time 188.87 seconds
Started Jul 04 05:24:01 PM PDT 24
Finished Jul 04 05:27:10 PM PDT 24
Peak memory 200312 kb
Host smart-29a5bf18-c5c5-4f1a-9724-f18e6d0693c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123312326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1123312326
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1029395055
Short name T440
Test name
Test status
Simulation time 304065666 ps
CPU time 13.84 seconds
Started Jul 04 05:23:56 PM PDT 24
Finished Jul 04 05:24:10 PM PDT 24
Peak memory 200348 kb
Host smart-6edf9f8b-fc6e-461c-9e1f-f6af6b3bb5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029395055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1029395055
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.953200700
Short name T361
Test name
Test status
Simulation time 360201770557 ps
CPU time 2175.28 seconds
Started Jul 04 05:23:58 PM PDT 24
Finished Jul 04 06:00:14 PM PDT 24
Peak memory 797368 kb
Host smart-c5c00a70-8567-44a0-86c9-59a5f0d4616c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953200700 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.953200700
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3776253409
Short name T66
Test name
Test status
Simulation time 1450859235 ps
CPU time 6.61 seconds
Started Jul 04 05:23:59 PM PDT 24
Finished Jul 04 05:24:06 PM PDT 24
Peak memory 200244 kb
Host smart-517ee0cd-4d78-4f9c-9812-5d2c9f42b4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776253409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3776253409
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.68378430
Short name T195
Test name
Test status
Simulation time 13463114 ps
CPU time 0.6 seconds
Started Jul 04 05:23:57 PM PDT 24
Finished Jul 04 05:23:57 PM PDT 24
Peak memory 196848 kb
Host smart-f70e77d8-aa33-4b61-98d7-13b4f3deb9c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68378430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.68378430
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3722114505
Short name T192
Test name
Test status
Simulation time 3907164339 ps
CPU time 58.55 seconds
Started Jul 04 05:23:57 PM PDT 24
Finished Jul 04 05:24:56 PM PDT 24
Peak memory 200352 kb
Host smart-ebcbda03-4a4c-4d17-94ba-27ac2e2f354d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3722114505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3722114505
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1645129366
Short name T259
Test name
Test status
Simulation time 739220839 ps
CPU time 10.23 seconds
Started Jul 04 05:23:56 PM PDT 24
Finished Jul 04 05:24:06 PM PDT 24
Peak memory 200312 kb
Host smart-715f118e-4844-4d94-b589-66f99ca6808b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645129366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1645129366
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.552112557
Short name T310
Test name
Test status
Simulation time 7255064585 ps
CPU time 1133.91 seconds
Started Jul 04 05:23:59 PM PDT 24
Finished Jul 04 05:42:53 PM PDT 24
Peak memory 759536 kb
Host smart-fcd05d25-2814-40e1-9312-c7ce3bfbc205
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=552112557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.552112557
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3552752787
Short name T203
Test name
Test status
Simulation time 4990680215 ps
CPU time 69.2 seconds
Started Jul 04 05:23:56 PM PDT 24
Finished Jul 04 05:25:06 PM PDT 24
Peak memory 200360 kb
Host smart-162aa8af-9bc3-4d4f-8752-0956f7b43aef
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552752787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3552752787
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.47672009
Short name T340
Test name
Test status
Simulation time 9858852195 ps
CPU time 58.54 seconds
Started Jul 04 05:23:57 PM PDT 24
Finished Jul 04 05:24:55 PM PDT 24
Peak memory 216508 kb
Host smart-3c42045c-b0c9-484d-84cf-c55ad6581e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47672009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.47672009
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2637985606
Short name T84
Test name
Test status
Simulation time 1398172911 ps
CPU time 2.48 seconds
Started Jul 04 05:23:59 PM PDT 24
Finished Jul 04 05:24:02 PM PDT 24
Peak memory 200280 kb
Host smart-a84eb42e-8706-43e1-ad26-83fe8ccb7523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637985606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2637985606
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.931380619
Short name T327
Test name
Test status
Simulation time 62871972188 ps
CPU time 1407.44 seconds
Started Jul 04 05:23:57 PM PDT 24
Finished Jul 04 05:47:25 PM PDT 24
Peak memory 737292 kb
Host smart-d19672bb-c237-46fd-8b6e-c85cd5adf24c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931380619 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.931380619
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3176639553
Short name T352
Test name
Test status
Simulation time 1168131938 ps
CPU time 15.77 seconds
Started Jul 04 05:24:00 PM PDT 24
Finished Jul 04 05:24:16 PM PDT 24
Peak memory 200256 kb
Host smart-81e7edd8-1aa3-4798-aa90-5d0e115042d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176639553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3176639553
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1431060918
Short name T357
Test name
Test status
Simulation time 14132496 ps
CPU time 0.61 seconds
Started Jul 04 05:24:04 PM PDT 24
Finished Jul 04 05:24:04 PM PDT 24
Peak memory 196168 kb
Host smart-b695d7c8-9d38-4eea-8166-5ff17ed204a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431060918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1431060918
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.537834587
Short name T35
Test name
Test status
Simulation time 1582362085 ps
CPU time 91.37 seconds
Started Jul 04 05:23:59 PM PDT 24
Finished Jul 04 05:25:31 PM PDT 24
Peak memory 200248 kb
Host smart-c25a3a0b-1654-444d-b2d4-8976aca223b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=537834587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.537834587
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1577210066
Short name T360
Test name
Test status
Simulation time 13260033916 ps
CPU time 61.36 seconds
Started Jul 04 05:24:04 PM PDT 24
Finished Jul 04 05:25:06 PM PDT 24
Peak memory 200348 kb
Host smart-2189d487-bf80-4bf4-a620-fa1e2425eab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577210066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1577210066
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3896596854
Short name T205
Test name
Test status
Simulation time 8019465555 ps
CPU time 350.05 seconds
Started Jul 04 05:23:58 PM PDT 24
Finished Jul 04 05:29:48 PM PDT 24
Peak memory 484564 kb
Host smart-c9c22ba3-22de-40f0-8a0f-fca96cfc4949
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3896596854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3896596854
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2222438237
Short name T243
Test name
Test status
Simulation time 266945080 ps
CPU time 4.32 seconds
Started Jul 04 05:24:05 PM PDT 24
Finished Jul 04 05:24:09 PM PDT 24
Peak memory 200208 kb
Host smart-94706a7f-a8d5-473e-a10b-097a5436bf8b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222438237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2222438237
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2694314213
Short name T210
Test name
Test status
Simulation time 16750731146 ps
CPU time 93.86 seconds
Started Jul 04 05:23:58 PM PDT 24
Finished Jul 04 05:25:32 PM PDT 24
Peak memory 200364 kb
Host smart-dde53d57-306d-4792-8480-f97890e66ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694314213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2694314213
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2169056704
Short name T152
Test name
Test status
Simulation time 38725684 ps
CPU time 1.27 seconds
Started Jul 04 05:23:57 PM PDT 24
Finished Jul 04 05:23:58 PM PDT 24
Peak memory 200344 kb
Host smart-e5995197-2f37-44ce-b23e-9f5bf4b92da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169056704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2169056704
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3883794345
Short name T371
Test name
Test status
Simulation time 27248511432 ps
CPU time 37.99 seconds
Started Jul 04 05:24:03 PM PDT 24
Finished Jul 04 05:24:41 PM PDT 24
Peak memory 200368 kb
Host smart-637125ef-3d4e-4dd4-ba70-c23d0a7be738
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883794345 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3883794345
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.4099994797
Short name T70
Test name
Test status
Simulation time 3112710536 ps
CPU time 88.27 seconds
Started Jul 04 05:24:04 PM PDT 24
Finished Jul 04 05:25:33 PM PDT 24
Peak memory 200404 kb
Host smart-d781cabc-d421-47c1-afac-0aa95db5ae23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099994797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.4099994797
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2545898549
Short name T471
Test name
Test status
Simulation time 19725099 ps
CPU time 0.61 seconds
Started Jul 04 05:24:05 PM PDT 24
Finished Jul 04 05:24:06 PM PDT 24
Peak memory 195172 kb
Host smart-c3da2f55-817f-4a35-947b-56891f8fb3c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545898549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2545898549
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.890595322
Short name T442
Test name
Test status
Simulation time 592817516 ps
CPU time 18.69 seconds
Started Jul 04 05:24:05 PM PDT 24
Finished Jul 04 05:24:24 PM PDT 24
Peak memory 200356 kb
Host smart-160acbb8-3f44-4b9b-ad30-3d66bb26295f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=890595322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.890595322
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2939214634
Short name T278
Test name
Test status
Simulation time 10756740698 ps
CPU time 50.55 seconds
Started Jul 04 05:24:05 PM PDT 24
Finished Jul 04 05:24:55 PM PDT 24
Peak memory 216600 kb
Host smart-597eed2f-4a7d-44ef-a09b-bb042921a5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939214634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2939214634
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.4064742920
Short name T226
Test name
Test status
Simulation time 11689272453 ps
CPU time 468.29 seconds
Started Jul 04 05:24:04 PM PDT 24
Finished Jul 04 05:31:53 PM PDT 24
Peak memory 626212 kb
Host smart-7840a4fd-242f-40e1-9b7f-664345604576
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4064742920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.4064742920
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.2894814713
Short name T200
Test name
Test status
Simulation time 11696468292 ps
CPU time 157.08 seconds
Started Jul 04 05:24:06 PM PDT 24
Finished Jul 04 05:26:43 PM PDT 24
Peak memory 200316 kb
Host smart-237bfc50-a77b-4efd-85f9-84eed08530ab
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894814713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2894814713
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3088051670
Short name T211
Test name
Test status
Simulation time 13545047201 ps
CPU time 11.53 seconds
Started Jul 04 05:24:04 PM PDT 24
Finished Jul 04 05:24:16 PM PDT 24
Peak memory 200388 kb
Host smart-faa80863-cf34-49f4-9aca-e69fff0b2ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088051670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3088051670
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3130870898
Short name T264
Test name
Test status
Simulation time 1712762245 ps
CPU time 14.7 seconds
Started Jul 04 05:24:05 PM PDT 24
Finished Jul 04 05:24:19 PM PDT 24
Peak memory 200312 kb
Host smart-4cfb1c81-5837-45ae-be8a-c6a0a64c52a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130870898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3130870898
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1609617489
Short name T5
Test name
Test status
Simulation time 27097533633 ps
CPU time 376.31 seconds
Started Jul 04 05:24:05 PM PDT 24
Finished Jul 04 05:30:22 PM PDT 24
Peak memory 442400 kb
Host smart-181e4331-0733-4995-9f90-b366edb88b4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609617489 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1609617489
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2053919812
Short name T388
Test name
Test status
Simulation time 634653243 ps
CPU time 29.05 seconds
Started Jul 04 05:24:03 PM PDT 24
Finished Jul 04 05:24:32 PM PDT 24
Peak memory 200260 kb
Host smart-6b72c301-33f5-490d-9bb1-f96c985c75e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053919812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2053919812
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1026466818
Short name T488
Test name
Test status
Simulation time 38074410 ps
CPU time 0.58 seconds
Started Jul 04 05:24:12 PM PDT 24
Finished Jul 04 05:24:13 PM PDT 24
Peak memory 195896 kb
Host smart-19e9e207-b5a4-4ae0-b2a2-698307c577c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026466818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1026466818
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3256545746
Short name T68
Test name
Test status
Simulation time 1182095211 ps
CPU time 12.03 seconds
Started Jul 04 05:24:07 PM PDT 24
Finished Jul 04 05:24:19 PM PDT 24
Peak memory 200276 kb
Host smart-b9600a10-ba1d-4d0e-a298-d7fab4e92766
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3256545746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3256545746
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1102481803
Short name T505
Test name
Test status
Simulation time 1568574224 ps
CPU time 42.09 seconds
Started Jul 04 05:24:13 PM PDT 24
Finished Jul 04 05:24:55 PM PDT 24
Peak memory 200280 kb
Host smart-bbd8075a-d3d7-4640-b521-797d3522f3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102481803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1102481803
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.2256008016
Short name T207
Test name
Test status
Simulation time 6391680529 ps
CPU time 304.24 seconds
Started Jul 04 05:24:04 PM PDT 24
Finished Jul 04 05:29:08 PM PDT 24
Peak memory 649692 kb
Host smart-31ad0aae-224c-4828-bca6-cf11e163e282
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2256008016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2256008016
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3137873116
Short name T317
Test name
Test status
Simulation time 23613817079 ps
CPU time 74.88 seconds
Started Jul 04 05:24:11 PM PDT 24
Finished Jul 04 05:25:26 PM PDT 24
Peak memory 200344 kb
Host smart-993fdeb9-b2ab-4611-b9ef-5a4492a1208f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137873116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3137873116
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2414035025
Short name T462
Test name
Test status
Simulation time 4824801533 ps
CPU time 47.17 seconds
Started Jul 04 05:24:06 PM PDT 24
Finished Jul 04 05:24:53 PM PDT 24
Peak memory 200320 kb
Host smart-af343bf0-6fe9-480c-a222-4bdf023b8cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414035025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2414035025
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2945040208
Short name T391
Test name
Test status
Simulation time 2913713640 ps
CPU time 12.64 seconds
Started Jul 04 05:24:05 PM PDT 24
Finished Jul 04 05:24:18 PM PDT 24
Peak memory 200352 kb
Host smart-075df867-edc6-4321-af0f-d02e55cb6fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945040208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2945040208
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3219587939
Short name T79
Test name
Test status
Simulation time 4596454757 ps
CPU time 19.26 seconds
Started Jul 04 05:24:12 PM PDT 24
Finished Jul 04 05:24:32 PM PDT 24
Peak memory 200336 kb
Host smart-2d5fefd5-bf02-4ee9-8fca-94a6016fc38d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219587939 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3219587939
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1861411227
Short name T154
Test name
Test status
Simulation time 4381881933 ps
CPU time 87.67 seconds
Started Jul 04 05:24:12 PM PDT 24
Finished Jul 04 05:25:40 PM PDT 24
Peak memory 200352 kb
Host smart-0bd32593-339f-416a-931b-5d9d18a1449f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861411227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1861411227
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.145782728
Short name T201
Test name
Test status
Simulation time 41520538 ps
CPU time 0.61 seconds
Started Jul 04 05:24:12 PM PDT 24
Finished Jul 04 05:24:13 PM PDT 24
Peak memory 196836 kb
Host smart-be24b6a1-65c4-45bb-97ee-dc54da059911
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145782728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.145782728
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2193428249
Short name T249
Test name
Test status
Simulation time 3218294035 ps
CPU time 53.19 seconds
Started Jul 04 05:24:13 PM PDT 24
Finished Jul 04 05:25:07 PM PDT 24
Peak memory 200360 kb
Host smart-f66216cd-90f9-421b-933a-5a31bbe60eba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2193428249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2193428249
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3482865260
Short name T475
Test name
Test status
Simulation time 10443475573 ps
CPU time 36.52 seconds
Started Jul 04 05:24:13 PM PDT 24
Finished Jul 04 05:24:50 PM PDT 24
Peak memory 208472 kb
Host smart-9e8a29c4-3818-4cce-99f9-40bf53b361c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482865260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3482865260
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2009785637
Short name T426
Test name
Test status
Simulation time 1891751121 ps
CPU time 53.36 seconds
Started Jul 04 05:24:12 PM PDT 24
Finished Jul 04 05:25:06 PM PDT 24
Peak memory 329656 kb
Host smart-60157592-3f71-4724-b141-b0a5f888e548
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2009785637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2009785637
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1029479592
Short name T347
Test name
Test status
Simulation time 2255927490 ps
CPU time 125.4 seconds
Started Jul 04 05:24:12 PM PDT 24
Finished Jul 04 05:26:17 PM PDT 24
Peak memory 200348 kb
Host smart-627f547e-3f5a-404f-bc06-e5e6f8ad79b3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029479592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1029479592
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.518958910
Short name T225
Test name
Test status
Simulation time 11624541747 ps
CPU time 191.78 seconds
Started Jul 04 05:24:13 PM PDT 24
Finished Jul 04 05:27:25 PM PDT 24
Peak memory 200416 kb
Host smart-243ac260-7b85-4c48-84a6-4b9ec669fba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518958910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.518958910
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.4046465697
Short name T180
Test name
Test status
Simulation time 353985712 ps
CPU time 3.65 seconds
Started Jul 04 05:24:12 PM PDT 24
Finished Jul 04 05:24:16 PM PDT 24
Peak memory 200280 kb
Host smart-9bd9831c-c702-485f-9c23-7055b0036328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046465697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.4046465697
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.1412289738
Short name T133
Test name
Test status
Simulation time 7372742173 ps
CPU time 477 seconds
Started Jul 04 05:24:12 PM PDT 24
Finished Jul 04 05:32:10 PM PDT 24
Peak memory 407096 kb
Host smart-4392419e-cb0b-4d24-8f53-7cecc0583596
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412289738 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1412289738
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1942549904
Short name T161
Test name
Test status
Simulation time 3915007769 ps
CPU time 87.6 seconds
Started Jul 04 05:24:12 PM PDT 24
Finished Jul 04 05:25:40 PM PDT 24
Peak memory 200384 kb
Host smart-c3dadf53-d8b3-42f0-9fba-571833d063d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942549904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1942549904
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.464548206
Short name T344
Test name
Test status
Simulation time 43756480 ps
CPU time 0.6 seconds
Started Jul 04 05:24:13 PM PDT 24
Finished Jul 04 05:24:13 PM PDT 24
Peak memory 196828 kb
Host smart-a347ff0c-a8f6-4300-874c-cd07097684f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464548206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.464548206
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3698409153
Short name T459
Test name
Test status
Simulation time 1124743856 ps
CPU time 33.86 seconds
Started Jul 04 05:24:13 PM PDT 24
Finished Jul 04 05:24:47 PM PDT 24
Peak memory 200252 kb
Host smart-6efa4360-c5bf-4e4a-a023-91f42cadeac5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3698409153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3698409153
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.3837837722
Short name T160
Test name
Test status
Simulation time 2108768137 ps
CPU time 3.41 seconds
Started Jul 04 05:24:11 PM PDT 24
Finished Jul 04 05:24:14 PM PDT 24
Peak memory 200288 kb
Host smart-262e9ea2-a94e-47d9-afe6-bbe30b015c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837837722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3837837722
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2305397328
Short name T142
Test name
Test status
Simulation time 57992659760 ps
CPU time 728.28 seconds
Started Jul 04 05:24:11 PM PDT 24
Finished Jul 04 05:36:19 PM PDT 24
Peak memory 695664 kb
Host smart-3ae357dd-7e25-4b1d-b78a-45303938c576
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2305397328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2305397328
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.3590644034
Short name T390
Test name
Test status
Simulation time 12919463761 ps
CPU time 60.4 seconds
Started Jul 04 05:24:13 PM PDT 24
Finished Jul 04 05:25:13 PM PDT 24
Peak memory 200348 kb
Host smart-0a1ac61e-3010-4f6f-b879-cbde8eba8e58
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590644034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.3590644034
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2751599976
Short name T383
Test name
Test status
Simulation time 3441393373 ps
CPU time 66.7 seconds
Started Jul 04 05:24:12 PM PDT 24
Finished Jul 04 05:25:19 PM PDT 24
Peak memory 200260 kb
Host smart-8e1481b7-06a0-4094-a836-70e5379a62cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751599976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2751599976
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3453068150
Short name T381
Test name
Test status
Simulation time 39280750 ps
CPU time 0.98 seconds
Started Jul 04 05:24:12 PM PDT 24
Finished Jul 04 05:24:13 PM PDT 24
Peak memory 199804 kb
Host smart-d90485b8-06db-4e64-a653-41377dc294cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453068150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3453068150
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.45926470
Short name T251
Test name
Test status
Simulation time 155153294027 ps
CPU time 4375.42 seconds
Started Jul 04 05:24:11 PM PDT 24
Finished Jul 04 06:37:07 PM PDT 24
Peak memory 836816 kb
Host smart-f6c4500f-0ba9-4946-857f-c7882958dfaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45926470 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.45926470
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.965157073
Short name T420
Test name
Test status
Simulation time 17615568391 ps
CPU time 34.14 seconds
Started Jul 04 05:24:13 PM PDT 24
Finished Jul 04 05:24:47 PM PDT 24
Peak memory 200340 kb
Host smart-8ccea016-db76-401e-8883-5f026e7284ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965157073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.965157073
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3355818128
Short name T330
Test name
Test status
Simulation time 12414243 ps
CPU time 0.58 seconds
Started Jul 04 05:24:20 PM PDT 24
Finished Jul 04 05:24:20 PM PDT 24
Peak memory 195116 kb
Host smart-cb8a397a-5b4c-4f1d-8c1c-53844eae4d98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355818128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3355818128
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1004973551
Short name T393
Test name
Test status
Simulation time 906233889 ps
CPU time 15.83 seconds
Started Jul 04 05:24:12 PM PDT 24
Finished Jul 04 05:24:28 PM PDT 24
Peak memory 200356 kb
Host smart-9a1084cf-6434-4d56-8590-9b72912d3be8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004973551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1004973551
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1570995816
Short name T492
Test name
Test status
Simulation time 2137517444 ps
CPU time 26.36 seconds
Started Jul 04 05:24:18 PM PDT 24
Finished Jul 04 05:24:45 PM PDT 24
Peak memory 200340 kb
Host smart-b5f2a811-59a9-4d06-a315-76d9576d69b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570995816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1570995816
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3037820077
Short name T252
Test name
Test status
Simulation time 7076620253 ps
CPU time 1492.81 seconds
Started Jul 04 05:24:10 PM PDT 24
Finished Jul 04 05:49:04 PM PDT 24
Peak memory 748000 kb
Host smart-c73db058-9a31-4b21-8847-6a1158a27226
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3037820077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3037820077
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.65171475
Short name T149
Test name
Test status
Simulation time 64237290874 ps
CPU time 208.24 seconds
Started Jul 04 05:24:18 PM PDT 24
Finished Jul 04 05:27:46 PM PDT 24
Peak memory 200388 kb
Host smart-b25cda7d-9cca-46a3-9b67-b41cac1f6ceb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65171475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.65171475
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.497371325
Short name T379
Test name
Test status
Simulation time 1373359574 ps
CPU time 76.44 seconds
Started Jul 04 05:24:12 PM PDT 24
Finished Jul 04 05:25:28 PM PDT 24
Peak memory 200316 kb
Host smart-8ef795c4-9b60-4f4d-81e4-eb6ebaa88460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497371325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.497371325
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.1239924572
Short name T222
Test name
Test status
Simulation time 279363547 ps
CPU time 12.44 seconds
Started Jul 04 05:24:12 PM PDT 24
Finished Jul 04 05:24:25 PM PDT 24
Peak memory 200288 kb
Host smart-95008f60-edc5-43c5-a654-0bdd20b8b332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239924572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.1239924572
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3983735602
Short name T75
Test name
Test status
Simulation time 68028545817 ps
CPU time 391.88 seconds
Started Jul 04 05:24:22 PM PDT 24
Finished Jul 04 05:30:54 PM PDT 24
Peak memory 208572 kb
Host smart-ba7f9637-0f87-4c96-a14f-7f8161be94f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983735602 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3983735602
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3478285910
Short name T484
Test name
Test status
Simulation time 1547675764 ps
CPU time 77.65 seconds
Started Jul 04 05:24:19 PM PDT 24
Finished Jul 04 05:25:37 PM PDT 24
Peak memory 200280 kb
Host smart-d0fb12e8-5b6e-495c-b3ad-204b4554104c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478285910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3478285910
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1293434593
Short name T419
Test name
Test status
Simulation time 42496651 ps
CPU time 0.58 seconds
Started Jul 04 05:24:19 PM PDT 24
Finished Jul 04 05:24:20 PM PDT 24
Peak memory 195800 kb
Host smart-c53af0f9-a099-447c-b7d1-3fbb0e31a887
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293434593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1293434593
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.3000825747
Short name T218
Test name
Test status
Simulation time 914713179 ps
CPU time 27.72 seconds
Started Jul 04 05:24:17 PM PDT 24
Finished Jul 04 05:24:45 PM PDT 24
Peak memory 200308 kb
Host smart-d8c53a7d-de36-4a50-b99d-04622d043b97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3000825747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.3000825747
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2879998037
Short name T415
Test name
Test status
Simulation time 16519666241 ps
CPU time 45.57 seconds
Started Jul 04 05:24:22 PM PDT 24
Finished Jul 04 05:25:08 PM PDT 24
Peak memory 200356 kb
Host smart-eb79776a-ab51-4daa-ad07-2590ef48c172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879998037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2879998037
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.649541164
Short name T257
Test name
Test status
Simulation time 9566272257 ps
CPU time 1662.43 seconds
Started Jul 04 05:24:20 PM PDT 24
Finished Jul 04 05:52:03 PM PDT 24
Peak memory 713884 kb
Host smart-6903102c-00d1-405b-a128-2be88c71c449
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=649541164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.649541164
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.2127365425
Short name T499
Test name
Test status
Simulation time 14810304524 ps
CPU time 93.96 seconds
Started Jul 04 05:24:23 PM PDT 24
Finished Jul 04 05:25:57 PM PDT 24
Peak memory 200352 kb
Host smart-e3c2c94f-7466-4e98-a68a-0a744de3d2b4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127365425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2127365425
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1289715292
Short name T320
Test name
Test status
Simulation time 968490333 ps
CPU time 10.88 seconds
Started Jul 04 05:24:20 PM PDT 24
Finished Jul 04 05:24:31 PM PDT 24
Peak memory 200252 kb
Host smart-f93b52fe-e977-4ddb-bc1f-571b39bf85bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289715292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1289715292
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.522812144
Short name T224
Test name
Test status
Simulation time 994990706 ps
CPU time 11.84 seconds
Started Jul 04 05:24:23 PM PDT 24
Finished Jul 04 05:24:35 PM PDT 24
Peak memory 200296 kb
Host smart-d8e99f98-3033-4ce4-b901-4a61be0fde05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522812144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.522812144
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3770476769
Short name T92
Test name
Test status
Simulation time 593835768046 ps
CPU time 1037.87 seconds
Started Jul 04 05:24:23 PM PDT 24
Finished Jul 04 05:41:41 PM PDT 24
Peak memory 701924 kb
Host smart-54307ecc-48af-4726-8ae2-b8e93dd48e10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770476769 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3770476769
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1141787378
Short name T86
Test name
Test status
Simulation time 7722237460 ps
CPU time 93.14 seconds
Started Jul 04 05:24:20 PM PDT 24
Finished Jul 04 05:25:53 PM PDT 24
Peak memory 200336 kb
Host smart-96512302-c138-4606-a093-4b15bd3dbcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141787378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1141787378
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.722086002
Short name T323
Test name
Test status
Simulation time 10994056 ps
CPU time 0.57 seconds
Started Jul 04 05:24:25 PM PDT 24
Finished Jul 04 05:24:26 PM PDT 24
Peak memory 195120 kb
Host smart-ef41a24b-cfaa-475b-b4ec-5def451e9d26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722086002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.722086002
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2715618789
Short name T185
Test name
Test status
Simulation time 1913491662 ps
CPU time 52.8 seconds
Started Jul 04 05:24:18 PM PDT 24
Finished Jul 04 05:25:11 PM PDT 24
Peak memory 200316 kb
Host smart-d607d260-b174-4aba-910f-349286f3ae5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2715618789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2715618789
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.509744454
Short name T52
Test name
Test status
Simulation time 6908587770 ps
CPU time 40.39 seconds
Started Jul 04 05:24:23 PM PDT 24
Finished Jul 04 05:25:03 PM PDT 24
Peak memory 200356 kb
Host smart-d65737f0-8d5e-4cbe-a80d-89e3a8b242fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509744454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.509744454
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3248221793
Short name T170
Test name
Test status
Simulation time 115133953576 ps
CPU time 1988.77 seconds
Started Jul 04 05:24:17 PM PDT 24
Finished Jul 04 05:57:26 PM PDT 24
Peak memory 779520 kb
Host smart-05c6725b-2db8-4cc7-aefd-94469f73f570
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3248221793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3248221793
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2960187360
Short name T273
Test name
Test status
Simulation time 833095339 ps
CPU time 45.89 seconds
Started Jul 04 05:24:18 PM PDT 24
Finished Jul 04 05:25:04 PM PDT 24
Peak memory 200280 kb
Host smart-c9530616-5000-4b9b-8e49-3b53d40f4e83
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960187360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2960187360
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.791187646
Short name T342
Test name
Test status
Simulation time 1293394251 ps
CPU time 7.33 seconds
Started Jul 04 05:24:19 PM PDT 24
Finished Jul 04 05:24:26 PM PDT 24
Peak memory 200252 kb
Host smart-c4ae813d-5100-49df-b77a-4e7e0243c572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791187646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.791187646
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.4199473012
Short name T500
Test name
Test status
Simulation time 228863108 ps
CPU time 3.44 seconds
Started Jul 04 05:24:20 PM PDT 24
Finished Jul 04 05:24:24 PM PDT 24
Peak memory 200256 kb
Host smart-1aea4d6a-5b3f-4a25-b18f-f115e5168ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199473012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.4199473012
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.818189798
Short name T451
Test name
Test status
Simulation time 8941191880 ps
CPU time 836.29 seconds
Started Jul 04 05:24:25 PM PDT 24
Finished Jul 04 05:38:22 PM PDT 24
Peak memory 668544 kb
Host smart-9dbe790c-c2f3-4b4c-95fa-184333b03548
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818189798 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.818189798
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.156300317
Short name T300
Test name
Test status
Simulation time 5521153696 ps
CPU time 97.51 seconds
Started Jul 04 05:24:18 PM PDT 24
Finished Jul 04 05:25:56 PM PDT 24
Peak memory 200340 kb
Host smart-93f349fb-07b7-47f6-9a18-208a4c10be89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156300317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.156300317
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.212199271
Short name T143
Test name
Test status
Simulation time 27699739 ps
CPU time 0.6 seconds
Started Jul 04 05:22:31 PM PDT 24
Finished Jul 04 05:22:31 PM PDT 24
Peak memory 196192 kb
Host smart-bbe96360-bf96-4a0f-ab8f-d8e6877122e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212199271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.212199271
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.476772949
Short name T445
Test name
Test status
Simulation time 1166880800 ps
CPU time 36.05 seconds
Started Jul 04 05:22:27 PM PDT 24
Finished Jul 04 05:23:03 PM PDT 24
Peak memory 200268 kb
Host smart-643eca6d-dd90-403d-9a01-5b1c20af3880
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=476772949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.476772949
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3290927032
Short name T244
Test name
Test status
Simulation time 1593609901 ps
CPU time 29.06 seconds
Started Jul 04 05:22:29 PM PDT 24
Finished Jul 04 05:22:59 PM PDT 24
Peak memory 200352 kb
Host smart-cfdc1286-e671-477c-ba28-090fba244247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290927032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3290927032
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2189802946
Short name T405
Test name
Test status
Simulation time 6956746726 ps
CPU time 639.49 seconds
Started Jul 04 05:22:27 PM PDT 24
Finished Jul 04 05:33:07 PM PDT 24
Peak memory 692896 kb
Host smart-2eb0f939-ef54-4847-8c19-a9adae866c59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2189802946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2189802946
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.2998122874
Short name T524
Test name
Test status
Simulation time 41133421270 ps
CPU time 176.83 seconds
Started Jul 04 05:22:29 PM PDT 24
Finished Jul 04 05:25:27 PM PDT 24
Peak memory 200332 kb
Host smart-58a18de1-3480-453f-8752-a447feccf737
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998122874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2998122874
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.174522760
Short name T233
Test name
Test status
Simulation time 28580307794 ps
CPU time 184.65 seconds
Started Jul 04 05:22:29 PM PDT 24
Finished Jul 04 05:25:34 PM PDT 24
Peak memory 200576 kb
Host smart-4757968c-baac-445e-a348-d055ab9c6d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174522760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.174522760
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3571720209
Short name T69
Test name
Test status
Simulation time 76048596 ps
CPU time 1.77 seconds
Started Jul 04 05:22:29 PM PDT 24
Finished Jul 04 05:22:30 PM PDT 24
Peak memory 200248 kb
Host smart-388075cd-13c9-4851-a8ea-274e071ff87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571720209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3571720209
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3139344784
Short name T373
Test name
Test status
Simulation time 48810621050 ps
CPU time 64.34 seconds
Started Jul 04 05:22:31 PM PDT 24
Finished Jul 04 05:23:35 PM PDT 24
Peak memory 200376 kb
Host smart-f53e747e-b047-452d-8d12-4eac09f10021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139344784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3139344784
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.391250339
Short name T146
Test name
Test status
Simulation time 37305379 ps
CPU time 0.57 seconds
Started Jul 04 05:22:29 PM PDT 24
Finished Jul 04 05:22:30 PM PDT 24
Peak memory 195152 kb
Host smart-13a2a5f7-3f6f-43c4-ae79-225dd6a48fd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391250339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.391250339
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.4060356733
Short name T526
Test name
Test status
Simulation time 1445588540 ps
CPU time 36.13 seconds
Started Jul 04 05:22:29 PM PDT 24
Finished Jul 04 05:23:06 PM PDT 24
Peak memory 200288 kb
Host smart-8384da40-02cf-4e1e-b953-714fb236e93d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4060356733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.4060356733
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3510038929
Short name T480
Test name
Test status
Simulation time 27905139663 ps
CPU time 52.77 seconds
Started Jul 04 05:22:31 PM PDT 24
Finished Jul 04 05:23:24 PM PDT 24
Peak memory 200352 kb
Host smart-1a93b563-2ed6-4f1c-92d1-c4136097e179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510038929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3510038929
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.828560250
Short name T204
Test name
Test status
Simulation time 2555853595 ps
CPU time 104.28 seconds
Started Jul 04 05:22:28 PM PDT 24
Finished Jul 04 05:24:12 PM PDT 24
Peak memory 559636 kb
Host smart-6961bf53-e0c7-4336-81a3-7853839212f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=828560250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.828560250
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3034287118
Short name T359
Test name
Test status
Simulation time 2398081285 ps
CPU time 33.19 seconds
Started Jul 04 05:22:29 PM PDT 24
Finished Jul 04 05:23:02 PM PDT 24
Peak memory 200344 kb
Host smart-25989dc5-48ca-4013-b1f6-1834fa62c35b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034287118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3034287118
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.591923533
Short name T411
Test name
Test status
Simulation time 31204443058 ps
CPU time 159.75 seconds
Started Jul 04 05:22:30 PM PDT 24
Finished Jul 04 05:25:10 PM PDT 24
Peak memory 200372 kb
Host smart-30ce2727-a99e-4481-914d-89e08f7dcf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591923533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.591923533
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.2355260483
Short name T281
Test name
Test status
Simulation time 284157464 ps
CPU time 11.44 seconds
Started Jul 04 05:22:27 PM PDT 24
Finished Jul 04 05:22:39 PM PDT 24
Peak memory 200212 kb
Host smart-ca793761-3f08-4c2f-913d-97d7d90d97d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355260483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.2355260483
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.544006135
Short name T19
Test name
Test status
Simulation time 10749682269 ps
CPU time 428.24 seconds
Started Jul 04 05:22:32 PM PDT 24
Finished Jul 04 05:29:40 PM PDT 24
Peak memory 208568 kb
Host smart-e81f1828-754a-423e-a76d-9f497cea29f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544006135 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.544006135
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.1156619394
Short name T61
Test name
Test status
Simulation time 99274867979 ps
CPU time 1657.55 seconds
Started Jul 04 05:22:32 PM PDT 24
Finished Jul 04 05:50:10 PM PDT 24
Peak memory 739252 kb
Host smart-165a65cb-38f3-4fc3-aca4-87bffeb7ee8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1156619394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.1156619394
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.3400164463
Short name T139
Test name
Test status
Simulation time 1749006967 ps
CPU time 17.16 seconds
Started Jul 04 05:22:29 PM PDT 24
Finished Jul 04 05:22:47 PM PDT 24
Peak memory 200340 kb
Host smart-abb14311-5536-42c4-8417-a278433c25b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400164463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3400164463
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3581351643
Short name T261
Test name
Test status
Simulation time 12433891 ps
CPU time 0.59 seconds
Started Jul 04 05:22:34 PM PDT 24
Finished Jul 04 05:22:34 PM PDT 24
Peak memory 195936 kb
Host smart-79b6fbbe-5344-4399-9398-f37f6b9d8636
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581351643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3581351643
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.4057195924
Short name T410
Test name
Test status
Simulation time 1625184356 ps
CPU time 25.07 seconds
Started Jul 04 05:22:29 PM PDT 24
Finished Jul 04 05:22:54 PM PDT 24
Peak memory 200304 kb
Host smart-e0e352fc-829d-4a79-9dcb-3f919a9fe70a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4057195924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.4057195924
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3861126115
Short name T132
Test name
Test status
Simulation time 3341851871 ps
CPU time 42.22 seconds
Started Jul 04 05:22:28 PM PDT 24
Finished Jul 04 05:23:10 PM PDT 24
Peak memory 200384 kb
Host smart-8f5e2464-8f40-4d69-be95-fd2389f06d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861126115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3861126115
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.765377338
Short name T429
Test name
Test status
Simulation time 6036483731 ps
CPU time 1147.08 seconds
Started Jul 04 05:22:29 PM PDT 24
Finished Jul 04 05:41:37 PM PDT 24
Peak memory 725780 kb
Host smart-5416b65b-316a-42ea-8321-dd975d614f17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=765377338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.765377338
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3172629206
Short name T339
Test name
Test status
Simulation time 6489066886 ps
CPU time 109.12 seconds
Started Jul 04 05:22:34 PM PDT 24
Finished Jul 04 05:24:23 PM PDT 24
Peak memory 200368 kb
Host smart-39455d3b-bccc-48f8-9f3b-34557de85559
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172629206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3172629206
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2630677214
Short name T376
Test name
Test status
Simulation time 3878021784 ps
CPU time 70.49 seconds
Started Jul 04 05:22:32 PM PDT 24
Finished Jul 04 05:23:42 PM PDT 24
Peak memory 200432 kb
Host smart-abf7ed58-4d23-49fe-b8e2-cc340ee417ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630677214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2630677214
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1838695437
Short name T80
Test name
Test status
Simulation time 193344815 ps
CPU time 8.67 seconds
Started Jul 04 05:22:29 PM PDT 24
Finished Jul 04 05:22:38 PM PDT 24
Peak memory 200280 kb
Host smart-7119dad1-fbd0-4fc8-9f0a-98cf274102c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838695437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1838695437
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1739566254
Short name T322
Test name
Test status
Simulation time 506735082 ps
CPU time 2.85 seconds
Started Jul 04 05:22:29 PM PDT 24
Finished Jul 04 05:22:32 PM PDT 24
Peak memory 200224 kb
Host smart-81ac4c93-664e-45b6-a3aa-becda5303aca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739566254 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1739566254
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.2182290924
Short name T60
Test name
Test status
Simulation time 259270983696 ps
CPU time 1852 seconds
Started Jul 04 05:22:29 PM PDT 24
Finished Jul 04 05:53:21 PM PDT 24
Peak memory 674580 kb
Host smart-e35dbf5e-3c4e-4cf5-bb9c-1ef4f062d17d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2182290924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.2182290924
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.4126597384
Short name T87
Test name
Test status
Simulation time 6188675167 ps
CPU time 77.84 seconds
Started Jul 04 05:22:32 PM PDT 24
Finished Jul 04 05:23:50 PM PDT 24
Peak memory 200404 kb
Host smart-58a2861c-9be9-45fe-ab35-edeaa95ff78f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126597384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.4126597384
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.4044809464
Short name T85
Test name
Test status
Simulation time 43831617 ps
CPU time 0.56 seconds
Started Jul 04 05:22:36 PM PDT 24
Finished Jul 04 05:22:37 PM PDT 24
Peak memory 195172 kb
Host smart-2823b234-aae7-4675-8090-4b26d5213fe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044809464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.4044809464
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3676905722
Short name T529
Test name
Test status
Simulation time 850856746 ps
CPU time 48.18 seconds
Started Jul 04 05:22:34 PM PDT 24
Finished Jul 04 05:23:23 PM PDT 24
Peak memory 200288 kb
Host smart-493c77ae-b406-4b00-8cfd-e689f02a30e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3676905722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3676905722
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1478696830
Short name T474
Test name
Test status
Simulation time 5194857375 ps
CPU time 36.72 seconds
Started Jul 04 05:22:39 PM PDT 24
Finished Jul 04 05:23:16 PM PDT 24
Peak memory 200360 kb
Host smart-60bd30f3-5a2c-4f77-846c-3f521b5b4bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478696830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1478696830
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1416449550
Short name T188
Test name
Test status
Simulation time 34770948229 ps
CPU time 415.26 seconds
Started Jul 04 05:22:35 PM PDT 24
Finished Jul 04 05:29:31 PM PDT 24
Peak memory 659076 kb
Host smart-76abcb75-3a39-44f3-a31f-8c18d2cac358
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1416449550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1416449550
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3728178298
Short name T156
Test name
Test status
Simulation time 4620626339 ps
CPU time 21.88 seconds
Started Jul 04 05:22:35 PM PDT 24
Finished Jul 04 05:22:57 PM PDT 24
Peak memory 200256 kb
Host smart-22243196-3a3c-4d5f-b13f-ed995140612b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728178298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3728178298
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.2209467364
Short name T439
Test name
Test status
Simulation time 10822846649 ps
CPU time 201.39 seconds
Started Jul 04 05:22:30 PM PDT 24
Finished Jul 04 05:25:52 PM PDT 24
Peak memory 200376 kb
Host smart-49f5e26b-8f86-4a06-9f93-c1a671c0d85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209467364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2209467364
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.994901621
Short name T126
Test name
Test status
Simulation time 1195314832 ps
CPU time 14.89 seconds
Started Jul 04 05:22:30 PM PDT 24
Finished Jul 04 05:22:45 PM PDT 24
Peak memory 200336 kb
Host smart-176b9b76-399e-4369-929c-b97733ba5f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994901621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.994901621
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2138278621
Short name T518
Test name
Test status
Simulation time 74465207458 ps
CPU time 1396.07 seconds
Started Jul 04 05:22:34 PM PDT 24
Finished Jul 04 05:45:50 PM PDT 24
Peak memory 664052 kb
Host smart-e890a9bb-7778-4c0f-9e9e-1147a9bf43c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138278621 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2138278621
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.4144106596
Short name T8
Test name
Test status
Simulation time 2337338172758 ps
CPU time 3607.82 seconds
Started Jul 04 05:22:36 PM PDT 24
Finished Jul 04 06:22:44 PM PDT 24
Peak memory 728356 kb
Host smart-952a728f-7632-4f5f-a9bd-d3e3049c23d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4144106596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.4144106596
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1097796692
Short name T114
Test name
Test status
Simulation time 98050383090 ps
CPU time 59.53 seconds
Started Jul 04 05:22:37 PM PDT 24
Finished Jul 04 05:23:37 PM PDT 24
Peak memory 200400 kb
Host smart-8a921f23-aa5f-46a3-8663-2269b103eced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097796692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1097796692
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3774172186
Short name T302
Test name
Test status
Simulation time 28736247 ps
CPU time 0.57 seconds
Started Jul 04 05:22:37 PM PDT 24
Finished Jul 04 05:22:38 PM PDT 24
Peak memory 195168 kb
Host smart-e172cee0-36f3-451b-8f5f-0ec49de812de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774172186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3774172186
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.207886035
Short name T240
Test name
Test status
Simulation time 2648656169 ps
CPU time 41.42 seconds
Started Jul 04 05:22:37 PM PDT 24
Finished Jul 04 05:23:19 PM PDT 24
Peak memory 200328 kb
Host smart-07182654-add6-4003-a653-be516963a38e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=207886035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.207886035
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.687732440
Short name T130
Test name
Test status
Simulation time 498463394 ps
CPU time 25.01 seconds
Started Jul 04 05:22:39 PM PDT 24
Finished Jul 04 05:23:04 PM PDT 24
Peak memory 200244 kb
Host smart-75ab252e-eca4-4e2f-9cf1-df6e841bdf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687732440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.687732440
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.706462736
Short name T497
Test name
Test status
Simulation time 13211822062 ps
CPU time 97.58 seconds
Started Jul 04 05:22:35 PM PDT 24
Finished Jul 04 05:24:13 PM PDT 24
Peak memory 344180 kb
Host smart-22b92179-28f2-4a6b-8099-913b9a237b76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=706462736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.706462736
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.777295704
Short name T346
Test name
Test status
Simulation time 6093174714 ps
CPU time 81.16 seconds
Started Jul 04 05:22:37 PM PDT 24
Finished Jul 04 05:23:58 PM PDT 24
Peak memory 200344 kb
Host smart-a0d63375-c63b-4443-bf0f-35f6f868e341
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777295704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.777295704
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.131722116
Short name T461
Test name
Test status
Simulation time 10747842679 ps
CPU time 198.79 seconds
Started Jul 04 05:22:38 PM PDT 24
Finished Jul 04 05:25:58 PM PDT 24
Peak memory 208572 kb
Host smart-b795c033-0b35-46a7-88ec-d813902aa78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131722116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.131722116
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.966151662
Short name T150
Test name
Test status
Simulation time 776578679 ps
CPU time 12.46 seconds
Started Jul 04 05:22:35 PM PDT 24
Finished Jul 04 05:22:48 PM PDT 24
Peak memory 200300 kb
Host smart-6c2a22b9-3d15-40db-97c8-8267ca96d988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966151662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.966151662
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2972480208
Short name T184
Test name
Test status
Simulation time 14210715036 ps
CPU time 1151.93 seconds
Started Jul 04 05:22:38 PM PDT 24
Finished Jul 04 05:41:50 PM PDT 24
Peak memory 702256 kb
Host smart-209f7183-55da-483f-be38-e192f532b866
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972480208 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2972480208
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.2308589619
Short name T11
Test name
Test status
Simulation time 4934031987 ps
CPU time 70.02 seconds
Started Jul 04 05:22:34 PM PDT 24
Finished Jul 04 05:23:44 PM PDT 24
Peak memory 208596 kb
Host smart-a151a850-5491-4ce1-836e-498488c1ae83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2308589619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.2308589619
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.557678823
Short name T448
Test name
Test status
Simulation time 6562289934 ps
CPU time 76.84 seconds
Started Jul 04 05:22:35 PM PDT 24
Finished Jul 04 05:23:52 PM PDT 24
Peak memory 200420 kb
Host smart-222a080e-f634-416b-9e0a-c2485d93d752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557678823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.557678823
Directory /workspace/9.hmac_wipe_secret/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%