Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	18860979	1			T2	16972		T7	11239		T4	9265
all_values[1]	18860979	1			T2	16972		T7	11239		T4	9265
all_values[2]	18860979	1			T2	16972		T7	11239		T4	9265

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

241346

1

T4

2

T5

3770

T21

1298

auto[1]

56341591

1

T2

50916

T7

33717

T4

27793

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48024668

1

T2

42036

T7

26128

T4

25514

auto[1]

8558269

1

T2

8880

T7

7589

T4

2281

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	90951	1			T21	649		T138	385		T25	5
all_values[0]	auto[0]	auto[1]	330	1			T138	2		T25	5		T11	1
all_values[0]	auto[1]	auto[0]	18748902	1			T2	16958		T7	11237		T4	9258
all_values[0]	auto[1]	auto[1]	20796	1			T2	14		T7	2		T4	7
all_values[1]	auto[0]	auto[0]	66677	1			T5	3770		T21	649		T57	243
all_values[1]	auto[0]	auto[1]	209	1			T25	5		T11	6		T26	2
all_values[1]	auto[1]	auto[0]	18793773	1			T2	16972		T7	11239		T4	9265
all_values[1]	auto[1]	auto[1]	320	1			T25	9		T11	5		T26	13
all_values[2]	auto[0]	auto[0]	36869	1			T58	97		T25	171		T139	2
all_values[2]	auto[0]	auto[1]	46310	1			T4	2		T57	243		T25	294
all_values[2]	auto[1]	auto[0]	10287496	1			T2	8106		T7	3652		T4	6991
all_values[2]	auto[1]	auto[1]	8490304	1			T2	8866		T7	7587		T4	2272