Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

129083

1

T2

26

T7

4

T6

28

auto[1]

129160

1

T2

18

T7

8

T4

12

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	99370	1			T2	16		T4	1		T5	2
len_1026_2046	5383	1			T2	3		T6	1		T8	30
len_514_1022	3756	1			T6	1		T9	1		T8	16
len_2_510	3913	1			T2	3		T8	11		T23	2
len_2056	192	1			T59	4		T11	3		T75	6
len_2048	389	1			T9	1		T10	3		T8	2
len_2040	184	1			T59	1		T11	7		T149	1
len_1032	163	1			T11	5		T77	1		T150	2
len_1024	1779	1			T10	2		T8	2		T21	1
len_1016	170	1			T52	2		T151	3		T11	4
len_520	213	1			T52	2		T59	3		T11	14
len_512	353	1			T5	1		T10	5		T52	2
len_504	258	1			T10	1		T52	1		T59	4
len_8	1123	1			T4	5		T52	1		T25	4
len_0	11876	1			T7	6		T9	4		T10	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

137

1

T10

1

T8

2

T21

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	49714	1			T2	9		T6	13		T9	14
auto[0]	len_1026_2046	2913	1			T2	2		T8	5		T22	1
auto[0]	len_514_1022	2150	1			T6	1		T9	1		T8	4
auto[0]	len_2_510	2444	1			T2	2		T8	4		T52	59
auto[0]	len_2056	111	1			T59	3		T75	4		T77	2
auto[0]	len_2048	216	1			T9	1		T8	1		T57	2
auto[0]	len_2040	102	1			T59	1		T11	1		T26	1
auto[0]	len_1032	91	1			T11	2		T77	1		T150	2
auto[0]	len_1024	281	1			T10	1		T8	1		T52	1
auto[0]	len_1016	92	1			T52	2		T151	3		T11	4
auto[0]	len_520	121	1			T52	2		T59	2		T11	6
auto[0]	len_512	213	1			T10	3		T52	2		T22	1
auto[0]	len_504	166	1			T10	1		T52	1		T59	3
auto[0]	len_8	101	1			T52	1		T152	1		T15	14
auto[0]	len_0	5827	1			T7	2		T9	2		T10	1
auto[1]	len_2050_plus	49656	1			T2	7		T4	1		T5	2
auto[1]	len_1026_2046	2470	1			T2	1		T6	1		T8	25
auto[1]	len_514_1022	1606	1			T8	12		T58	3		T138	47
auto[1]	len_2_510	1469	1			T2	1		T8	7		T23	2
auto[1]	len_2056	81	1			T59	1		T11	3		T75	2
auto[1]	len_2048	173	1			T10	3		T8	1		T21	1
auto[1]	len_2040	82	1			T11	6		T149	1		T26	1
auto[1]	len_1032	72	1			T11	3		T135	3		T153	2
auto[1]	len_1024	1498	1			T10	1		T8	1		T21	1
auto[1]	len_1016	78	1			T77	1		T149	3		T37	1
auto[1]	len_520	92	1			T59	1		T11	8		T153	1
auto[1]	len_512	140	1			T5	1		T10	2		T53	1
auto[1]	len_504	92	1			T59	1		T11	11		T77	1
auto[1]	len_8	1022	1			T4	5		T25	4		T139	7
auto[1]	len_0	6049	1			T7	4		T9	2		T8	8

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

79

1

T132

2

T11

2

T77

2

auto[1]

len_upper

58

1

T10

1

T8

2

T21

1