Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	192	0	192	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
key_swap	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	32	0	32	100.00	100	1	1	0
fifo_full_cross	32	0	32	100.00	100	1	1	0
fifo_depth_cross	128	0	128	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4521245

1

T2

3253

T7

1443

T4

1107

auto[1]

2965120

1

T2

5168

T7

425

T4

3472

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2903115

1

T2

4934

T7

51

T4

3472

auto[1]

4583250

1

T2

3487

T7

1817

T4

1107

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3281468

1

T2

4009

T7

11

T6

23

auto[1]

4204897

1

T2

4412

T7

1857

T4

4579

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4603866

1

T2

4866

T7

428

T4

4574

auto[1]

2882499

1

T2

3555

T7

1440

T4

5

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6747693	1			T2	8323		T7	1868		T4	3726
fifo_depth[1]	125406	1			T2	70		T4	143		T5	55
fifo_depth[2]	99660	1			T2	23		T4	131		T5	47
fifo_depth[3]	79957	1			T2	5		T4	128		T5	63
fifo_depth[4]	70976	1			T4	138		T5	56		T6	2
fifo_depth[5]	55616	1			T4	127		T5	49		T9	284
fifo_depth[6]	43876	1			T4	100		T5	22		T6	1
fifo_depth[7]	29048	1			T4	53		T5	9		T6	3

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

738672

1

T2

98

T4

853

T5

303

auto[1]

6747693

1

T2

8323

T7

1868

T4

3726

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7476092

1

T2

8421

T7

1868

T4

4579

auto[1]

10273

1

T25

686

T11

32

T26

583

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

37451

1

T2

6

T6

1

T9

294

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

34616

1

T2

23

T9

418

T8

161

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

31051

1

T6

2

T23

5

T21

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

31668

1

T2

2

T6

1

T9

76

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

177465

1

T2

3

T6

1

T52

21113

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

26695

1

T9

335

T21

1

T22

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

34831

1

T2

16

T9

168

T57

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

28489

1

T2

16

T6

1

T9

172

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

46015

1

T6

1

T57

1

T53

39

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

33684

1

T6

1

T10

10

T8

114

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

43417

1

T2

13

T4

443

T6

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

46500

1

T5

303

T6

1

T8

35

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

51253

1

T4

410

T10

6

T22

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

40640

1

T6

2

T9

97

T10

12

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

39485

1

T6

1

T9

290

T10

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

35412

1

T2

19

T9

246

T10

9

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

190560

1

T2

187

T7

8

T6

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

187121

1

T2

1132

T6

2

T9

685

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

180670

1

T2

1042

T7

1

T6

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

197867

1

T2

29

T7

1

T6

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1567847

1

T2

522

T6

1

T23

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

178757

1

T2

13

T7

1

T6

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

195698

1

T2

732

T6

3

T9

736

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

180682

1

T2

286

T6

2

T9

734

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

455632

1

T2

533

T6

2

T9

449

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

459238

1

T2

450

T7

38

T4

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

465110

1

T2

835

T4

3027

T9

174

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

462515

1

T2

682

T7

3

T5

537

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

558570

1

T2

29

T4

692

T6

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

475701

1

T2

355

T7

1396

T4

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

528811

1

T2

948

T7

419

T4

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

462914

1

T2

548

T7

1

T6

3

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

227478

1

T2

193

T7

8

T6

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

220034

1

T2

1155

T6

2

T9

1103

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

210406

1

T2

1042

T7

1

T6

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

228154

1

T2

31

T7

1

T6

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1744668

1

T2

525

T6

2

T23

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

204913

1

T2

13

T7

1

T6

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

230290

1

T2

748

T6

3

T9

904

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

208781

1

T2

302

T6

3

T9

906

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

500982

1

T2

533

T6

3

T9

449

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

492572

1

T2

450

T7

38

T4

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

507910

1

T2

848

T4

3470

T6

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

508537

1

T2

682

T7

3

T5

840

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

609505

1

T2

29

T4

1102

T6

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

515475

1

T2

355

T7

1396

T4

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

568162

1

T2

948

T7

419

T4

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

498225

1

T2

567

T7

1

T6

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

533

1

T25

25

T26

1

T14

11

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1703

1

T25

31

T26

54

T134

15

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1315

1

T25

233

T11

6

T26

310

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1381

1

T25

3

T11

5

T134

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

644

1

T25

72

T11

8

T26

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

539

1

T11

11

T26

1

T15

22

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

239

1

T25

25

T100

3

T15

80

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

390

1

T25

9

T26

42

T134

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

665

1

T25

168

T26

3

T134

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

350

1

T26

22

T100

18

T15

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

617

1

T26

87

T15

255

T94

24

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

478

1

T11

2

T26

15

T100

10

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

318

1

T25

120

T15

23

T44

7

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

866

1

T134

29

T15

82

T154

6

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

134

1

T26

45

T100

25

T155

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

101

1

T134

16

T156

11

T15

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[0]

190560

1

T2

187

T7

8

T6

2

fifo_depth[0]

auto[0]

auto[0]

auto[0]

auto[1]

187121

1

T2

1132

T6

2

T9

685

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[0]

180670

1

T2

1042

T7

1

T6

1

fifo_depth[0]

auto[0]

auto[0]

auto[1]

auto[1]

197867

1

T2

29

T7

1

T6

4

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[0]

1567847

1

T2

522

T6

1

T23

1

fifo_depth[0]

auto[0]

auto[1]

auto[0]

auto[1]

178757

1

T2

13

T7

1

T6

2

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[0]

195698

1

T2

732

T6

3

T9

736

fifo_depth[0]

auto[0]

auto[1]

auto[1]

auto[1]

180682

1

T2

286

T6

2

T9

734

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[0]

455632

1

T2

533

T6

2

T9

449

fifo_depth[0]

auto[1]

auto[0]

auto[0]

auto[1]

459238

1

T2

450

T7

38

T4

2

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[0]

465110

1

T2

835

T4

3027

T9

174

fifo_depth[0]

auto[1]

auto[0]

auto[1]

auto[1]

462515

1

T2

682

T7

3

T5

537

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[0]

558570

1

T2

29

T4

692

T6

3

fifo_depth[0]

auto[1]

auto[1]

auto[0]

auto[1]

475701

1

T2

355

T7

1396

T4

3

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[0]

528811

1

T2

948

T7

419

T4

2

fifo_depth[0]

auto[1]

auto[1]

auto[1]

auto[1]

462914

1

T2

548

T7

1

T6

3

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[0]

3712

1

T2

2

T9

44

T21

1

fifo_depth[1]

auto[0]

auto[0]

auto[0]

auto[1]

3886

1

T2

20

T9

79

T8

6

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[0]

3473

1

T23

4

T21

1

T53

10

fifo_depth[1]

auto[0]

auto[0]

auto[1]

auto[1]

4086

1

T2

1

T9

14

T8

1

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[0]

45419

1

T2

2

T52

4763

T58

11

fifo_depth[1]

auto[0]

auto[1]

auto[0]

auto[1]

3446

1

T9

54

T21

1

T58

2

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[0]

4338

1

T2

10

T9

28

T53

15

fifo_depth[1]

auto[0]

auto[1]

auto[1]

auto[1]

3653

1

T2

13

T9

25

T58

3

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[0]

6591

1

T53

16

T25

15

T55

11

fifo_depth[1]

auto[1]

auto[0]

auto[0]

auto[1]

5508

1

T10

3

T53

12

T58

8

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[0]

6226

1

T2

9

T4

70

T8

2

fifo_depth[1]

auto[1]

auto[0]

auto[1]

auto[1]

6528

1

T5

55

T8

4

T21

1

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[0]

9409

1

T4

73

T10

2

T25

27

fifo_depth[1]

auto[1]

auto[1]

auto[0]

auto[1]

6373

1

T9

11

T10

2

T8

4

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[0]

6680

1

T9

52

T10

1

T8

26

fifo_depth[1]

auto[1]

auto[1]

auto[1]

auto[1]

6078

1

T2

13

T9

38

T10

1

fifo_depth[2]

auto[0]

auto[0]

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21

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22

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1

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5

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12

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11

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1

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32

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17

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62

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3

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4

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7

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47

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21

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61

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5

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1

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16

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46

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33

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69

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3

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37

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31

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34

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102

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21

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19

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236

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1

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75

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37

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1

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71

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137

fifo_depth[7]

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844

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9

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56

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50

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13

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1

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26

fifo_depth[7]

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1

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15

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14

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151

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1

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82

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29

fifo_depth[7]

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1

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37

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1

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8

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1

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2

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1

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1

T4

16

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1

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16

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1

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7

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2

T57

1

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1

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18

T25

83

T59

35

fifo_depth[7]

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1

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18

T10

1

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33