Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	18860979	1			T2	16972		T7	11239		T4	9265
all_pins[1]	18860979	1			T2	16972		T7	11239		T4	9265
all_pins[2]	18860979	1			T2	16972		T7	11239		T4	9265

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	48070552	1			T2	42036		T7	26128		T4	25515
values[0x1]	8512385	1			T2	8880		T7	7589		T4	2280
transitions[0x0=>0x1]	8512189	1			T2	8880		T7	7589		T4	2280
transitions[0x1=>0x0]	8512201	1			T2	8880		T7	7589		T4	2280

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	18839249	1			T2	16958		T7	11237		T4	9257
all_pins[0]	values[0x1]	21730	1			T2	14		T7	2		T4	8
all_pins[0]	transitions[0x0=>0x1]	21655	1			T2	14		T7	2		T4	8
all_pins[0]	transitions[0x1=>0x0]	8490241	1			T2	8866		T7	7587		T4	2272
all_pins[1]	values[0x0]	18860628	1			T2	16972		T7	11239		T4	9265
all_pins[1]	values[0x1]	351	1			T25	11		T11	5		T26	15
all_pins[1]	transitions[0x0=>0x1]	289	1			T25	10		T11	2		T26	12
all_pins[1]	transitions[0x1=>0x0]	21668	1			T2	14		T7	2		T4	8
all_pins[2]	values[0x0]	10370675	1			T2	8106		T7	3652		T4	6993
all_pins[2]	values[0x1]	8490304	1			T2	8866		T7	7587		T4	2272
all_pins[2]	transitions[0x0=>0x1]	8490245	1			T2	8866		T7	7587		T4	2272
all_pins[2]	transitions[0x1=>0x0]	292	1			T25	11		T11	3		T26	15