Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 958 1 T25 17 T11 18 T26 7
all_values[1] 958 1 T25 17 T11 18 T26 7
all_values[2] 958 1 T25 17 T11 18 T26 7


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1505 1 T25 35 T11 22 T26 11
auto[1] 1369 1 T25 16 T11 32 T26 10


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1032 1 T25 18 T11 21 T26 5
auto[1] 1842 1 T25 33 T11 33 T26 16


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1654 1 T25 31 T11 33 T26 10
auto[1] 1220 1 T25 20 T11 21 T26 11


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 191 1 T25 5 T11 4 T135 2
all_values[0] auto[0] auto[0] auto[1] 98 1 T25 5 T11 1 T26 1
all_values[0] auto[0] auto[1] auto[0] 182 1 T11 4 T26 1 T12 1
all_values[0] auto[0] auto[1] auto[1] 87 1 T25 2 T11 2 T26 1
all_values[0] auto[1] auto[0] auto[1] 198 1 T25 2 T26 1 T12 1
all_values[0] auto[1] auto[1] auto[1] 202 1 T25 3 T11 7 T26 3
all_values[1] auto[0] auto[0] auto[0] 139 1 T25 2 T11 2 T12 3
all_values[1] auto[0] auto[0] auto[1] 120 1 T25 4 T11 2 T26 1
all_values[1] auto[0] auto[1] auto[0] 139 1 T25 1 T135 1 T12 3
all_values[1] auto[0] auto[1] auto[1] 128 1 T25 1 T11 3 T26 1
all_values[1] auto[1] auto[0] auto[1] 234 1 T25 4 T11 5 T26 3
all_values[1] auto[1] auto[1] auto[1] 198 1 T25 5 T11 6 T26 2
all_values[2] auto[0] auto[0] auto[0] 206 1 T25 8 T11 6 T26 2
all_values[2] auto[0] auto[0] auto[1] 107 1 T25 1 T11 1 T26 1
all_values[2] auto[0] auto[1] auto[0] 175 1 T25 2 T11 5 T26 2
all_values[2] auto[0] auto[1] auto[1] 82 1 T11 3 T135 2 T12 1
all_values[2] auto[1] auto[0] auto[1] 212 1 T25 4 T11 1 T26 2
all_values[2] auto[1] auto[1] auto[1] 176 1 T25 2 T11 2 T135 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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