Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4667	1			T2	7		T7	2		T4	3
sha2_none	4599	1			T2	3		T7	4		T4	3
sha2_512	8107	1			T2	4		T7	2		T4	2
sha2_384	7456	1			T2	6		T7	1		T4	2
sha2_256	6876	1			T2	6		T7	2		T4	2

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19543

1

T2

12

T7

9

T4

7

auto[1]

12576

1

T2

15

T7

2

T4

6

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12418

1

T2

15

T7

7

T4

5

auto[1]

19701

1

T2

12

T7

4

T4

8

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

16760

1

T2

13

T7

5

T4

13

disabled

15359

1

T2

14

T7

6

T6

25

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4996	1			T2	7		T7	7		T6	10
key_none	7729	1			T2	3		T7	1		T6	3
key_1024	4763	1			T2	3		T7	1		T4	3
key_512	4129	1			T2	2		T4	2		T6	8
key_384	3662	1			T2	2		T4	2		T6	3
key_256	3491	1			T2	7		T4	1		T6	6
key_128	3257	1			T2	3		T7	2		T4	5

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19778

1

T2

15

T7

7

T4

10

auto[1]

12341

1

T2

12

T7

4

T4

3

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

31885

1

T2

27

T7

11

T4

13

disabled

234

1

T25

2

T54

2

T55

2

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1788

1

T2

2

T7

2

T6

3

enabled

auto[0]

auto[0]

auto[1]

1747

1

T2

1

T7

1

T4

1

enabled

auto[0]

auto[1]

auto[0]

1688

1

T2

2

T4

4

T6

1

enabled

auto[0]

auto[1]

auto[1]

1763

1

T2

2

T5

2

T6

4

enabled

auto[1]

auto[0]

auto[0]

4407

1

T2

1

T4

4

T6

3

enabled

auto[1]

auto[0]

auto[1]

1714

1

T2

1

T7

1

T4

2

enabled

auto[1]

auto[1]

auto[0]

1918

1

T2

2

T7

1

T4

2

enabled

auto[1]

auto[1]

auto[1]

1735

1

T2

2

T6

3

T9

3

disabled

auto[0]

auto[0]

auto[0]

1364

1

T2

1

T7

3

T6

4

disabled

auto[0]

auto[0]

auto[1]

1321

1

T2

3

T6

2

T9

1

disabled

auto[0]

auto[1]

auto[0]

1368

1

T2

3

T7

1

T6

4

disabled

auto[0]

auto[1]

auto[1]

1379

1

T2

1

T6

5

T9

3

disabled

auto[1]

auto[0]

auto[0]

5899

1

T2

2

T6

2

T23

1

disabled

auto[1]

auto[0]

auto[1]

1303

1

T2

1

T7

2

T6

2

disabled

auto[1]

auto[1]

auto[0]

1346

1

T2

2

T6

3

T9

5

disabled

auto[1]

auto[1]

auto[1]

1379

1

T2

1

T6

3

T9

3

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

16674

1

T2

13

T7

5

T4

13

enabled

disabled

86

1

T59

2

T74

2

T76

2

disabled

disabled

148

1

T25

2

T54

2

T55

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15211

1

T2

14

T7

6

T6

25

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1186	1			T2	2		T7	1		T6	2
key_invalid	sha2_none	889	1			T2	1		T7	2		T6	3
key_invalid	sha2_512	939	1			T2	1		T7	1		T6	1
key_invalid	sha2_384	908	1			T2	1		T7	1		T6	1
key_invalid	sha2_256	979	1			T2	2		T7	2		T6	2
key_none	sha2_invalid	566	1			T6	1		T23	1		T21	1
key_none	sha2_none	638	1			T7	1		T6	1		T9	1
key_none	sha2_512	2576	1			T2	1		T8	2		T23	1
key_none	sha2_384	2224	1			T2	2		T6	1		T9	1
key_none	sha2_256	1673	1			T9	3		T8	2		T21	2
key_1024	sha2_invalid	609	1			T2	1		T4	1		T8	1
key_1024	sha2_none	613	1			T6	1		T21	2		T57	3
key_1024	sha2_512	1835	1			T7	1		T6	1		T10	1
key_1024	sha2_384	1016	1			T4	1		T6	5		T9	4
key_512	sha2_invalid	597	1			T2	1		T6	2		T8	1
key_512	sha2_none	583	1			T4	1		T6	2		T9	1
key_512	sha2_512	668	1			T6	1		T8	3		T21	1
key_512	sha2_384	1284	1			T2	1		T6	1		T23	2
key_512	sha2_256	933	1			T4	1		T6	1		T10	1
key_384	sha2_invalid	549	1			T2	2		T6	2		T9	2
key_384	sha2_none	619	1			T4	2		T9	1		T53	1
key_384	sha2_512	673	1			T6	1		T9	2		T10	1
key_384	sha2_384	639	1			T10	2		T8	2		T23	2
key_384	sha2_256	1131	1			T9	1		T8	1		T53	1
key_256	sha2_invalid	550	1			T2	1		T6	1		T8	2
key_256	sha2_none	630	1			T2	1		T9	3		T23	1
key_256	sha2_512	719	1			T6	1		T9	1		T8	1
key_256	sha2_384	700	1			T2	2		T9	1		T8	1
key_256	sha2_256	836	1			T2	2		T4	1		T6	3
key_128	sha2_invalid	589	1			T7	1		T4	2		T5	1
key_128	sha2_none	602	1			T2	1		T7	1		T6	2
key_128	sha2_512	679	1			T2	2		T4	2		T6	1
key_128	sha2_384	674	1			T4	1		T6	2		T9	5
key_128	sha2_256	667	1			T5	2		T9	1		T8	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

643

1

T2

2

T6

2

T57

2

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1186	1			T2	2		T7	1		T6	2
key_invalid	sha2_none	889	1			T2	1		T7	2		T6	3
key_invalid	sha2_512	939	1			T2	1		T7	1		T6	1
key_invalid	sha2_384	908	1			T2	1		T7	1		T6	1
key_invalid	sha2_256	979	1			T2	2		T7	2		T6	2
key_none	sha2_invalid	566	1			T6	1		T23	1		T21	1
key_none	sha2_none	638	1			T7	1		T6	1		T9	1
key_none	sha2_512	2576	1			T2	1		T8	2		T23	1
key_none	sha2_384	2224	1			T2	2		T6	1		T9	1
key_none	sha2_256	1673	1			T9	3		T8	2		T21	2
key_1024	sha2_invalid	609	1			T2	1		T4	1		T8	1
key_1024	sha2_none	613	1			T6	1		T21	2		T57	3
key_1024	sha2_512	1835	1			T7	1		T6	1		T10	1
key_1024	sha2_384	1016	1			T4	1		T6	5		T9	4
key_1024	sha2_256	643	1			T2	2		T6	2		T57	2
key_512	sha2_invalid	597	1			T2	1		T6	2		T8	1
key_512	sha2_none	583	1			T4	1		T6	2		T9	1
key_512	sha2_512	668	1			T6	1		T8	3		T21	1
key_512	sha2_384	1284	1			T2	1		T6	1		T23	2
key_512	sha2_256	933	1			T4	1		T6	1		T10	1
key_384	sha2_invalid	549	1			T2	2		T6	2		T9	2
key_384	sha2_none	619	1			T4	2		T9	1		T53	1
key_384	sha2_512	673	1			T6	1		T9	2		T10	1
key_384	sha2_384	639	1			T10	2		T8	2		T23	2
key_384	sha2_256	1131	1			T9	1		T8	1		T53	1
key_256	sha2_invalid	550	1			T2	1		T6	1		T8	2
key_256	sha2_none	630	1			T2	1		T9	3		T23	1
key_256	sha2_512	719	1			T6	1		T9	1		T8	1
key_256	sha2_384	700	1			T2	2		T9	1		T8	1
key_256	sha2_256	836	1			T2	2		T4	1		T6	3
key_128	sha2_invalid	589	1			T7	1		T4	2		T5	1
key_128	sha2_none	602	1			T2	1		T7	1		T6	2
key_128	sha2_512	679	1			T2	2		T4	2		T6	1
key_128	sha2_384	674	1			T4	1		T6	2		T9	5
key_128	sha2_256	667	1			T5	2		T9	1		T8	1