Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.00 97.15 97.27 100.00 86.84 98.43 99.49 99.85


Total test records in report: 658
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T531 /workspace/coverage/cover_reg_top/14.hmac_intr_test.995169698 Jul 05 05:22:39 PM PDT 24 Jul 05 05:22:40 PM PDT 24 12819187 ps
T532 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3939965722 Jul 05 05:22:52 PM PDT 24 Jul 05 05:22:53 PM PDT 24 33061044 ps
T113 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3838081643 Jul 05 05:22:46 PM PDT 24 Jul 05 05:22:47 PM PDT 24 27088683 ps
T533 /workspace/coverage/cover_reg_top/4.hmac_intr_test.4193661565 Jul 05 05:22:11 PM PDT 24 Jul 05 05:22:12 PM PDT 24 14934298 ps
T534 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1344173800 Jul 05 05:22:35 PM PDT 24 Jul 05 05:34:18 PM PDT 24 147674581881 ps
T114 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2866706401 Jul 05 05:22:05 PM PDT 24 Jul 05 05:22:06 PM PDT 24 55170412 ps
T115 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1330071714 Jul 05 05:22:31 PM PDT 24 Jul 05 05:22:33 PM PDT 24 32549032 ps
T129 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1766161294 Jul 05 05:22:40 PM PDT 24 Jul 05 05:22:42 PM PDT 24 42546549 ps
T65 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1544443228 Jul 05 05:22:33 PM PDT 24 Jul 05 05:22:39 PM PDT 24 433321567 ps
T116 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.241997701 Jul 05 05:21:57 PM PDT 24 Jul 05 05:21:59 PM PDT 24 72032253 ps
T535 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2699036814 Jul 05 05:22:33 PM PDT 24 Jul 05 05:22:38 PM PDT 24 45819554 ps
T66 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1920471996 Jul 05 05:23:12 PM PDT 24 Jul 05 05:23:15 PM PDT 24 82962371 ps
T536 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3749912354 Jul 05 05:22:59 PM PDT 24 Jul 05 05:23:00 PM PDT 24 29566468 ps
T67 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3992980223 Jul 05 05:21:59 PM PDT 24 Jul 05 05:22:01 PM PDT 24 86329661 ps
T130 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3469133579 Jul 05 05:22:43 PM PDT 24 Jul 05 05:22:44 PM PDT 24 186259332 ps
T537 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1130263103 Jul 05 05:21:57 PM PDT 24 Jul 05 05:22:03 PM PDT 24 598995846 ps
T117 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2673442307 Jul 05 05:22:09 PM PDT 24 Jul 05 05:22:18 PM PDT 24 629708328 ps
T538 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3595346948 Jul 05 05:22:17 PM PDT 24 Jul 05 05:22:20 PM PDT 24 249553845 ps
T539 /workspace/coverage/cover_reg_top/9.hmac_intr_test.3243431503 Jul 05 05:22:24 PM PDT 24 Jul 05 05:22:25 PM PDT 24 71894916 ps
T540 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.4148670103 Jul 05 05:22:37 PM PDT 24 Jul 05 05:22:42 PM PDT 24 475359961 ps
T541 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2758025956 Jul 05 05:22:59 PM PDT 24 Jul 05 05:23:01 PM PDT 24 15286607 ps
T542 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2514682441 Jul 05 05:22:51 PM PDT 24 Jul 05 05:22:52 PM PDT 24 13293324 ps
T543 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3705312274 Jul 05 05:22:57 PM PDT 24 Jul 05 05:22:58 PM PDT 24 49416707 ps
T544 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1917387414 Jul 05 05:23:00 PM PDT 24 Jul 05 05:23:02 PM PDT 24 69693754 ps
T545 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.233554779 Jul 05 05:22:20 PM PDT 24 Jul 05 05:22:23 PM PDT 24 1185397073 ps
T118 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2897315835 Jul 05 05:22:25 PM PDT 24 Jul 05 05:22:27 PM PDT 24 141864958 ps
T131 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.739001221 Jul 05 05:30:39 PM PDT 24 Jul 05 05:30:41 PM PDT 24 58799822 ps
T119 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.4247865595 Jul 05 05:22:33 PM PDT 24 Jul 05 05:22:36 PM PDT 24 60169401 ps
T546 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2853986993 Jul 05 05:22:18 PM PDT 24 Jul 05 05:22:21 PM PDT 24 146557959 ps
T547 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2347787936 Jul 05 05:22:26 PM PDT 24 Jul 05 05:22:29 PM PDT 24 90123852 ps
T548 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1831770482 Jul 05 05:22:31 PM PDT 24 Jul 05 05:22:32 PM PDT 24 21608413 ps
T120 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1055257041 Jul 05 05:22:19 PM PDT 24 Jul 05 05:22:21 PM PDT 24 56053003 ps
T549 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1703430254 Jul 05 05:22:38 PM PDT 24 Jul 05 05:22:41 PM PDT 24 113301742 ps
T550 /workspace/coverage/cover_reg_top/27.hmac_intr_test.965698883 Jul 05 05:22:59 PM PDT 24 Jul 05 05:23:00 PM PDT 24 22040520 ps
T551 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1107933112 Jul 05 05:23:00 PM PDT 24 Jul 05 05:23:02 PM PDT 24 43169084 ps
T142 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.438554321 Jul 05 05:22:34 PM PDT 24 Jul 05 05:22:40 PM PDT 24 412036490 ps
T121 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.346015416 Jul 05 05:22:27 PM PDT 24 Jul 05 05:22:28 PM PDT 24 35000207 ps
T552 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3561488027 Jul 05 05:21:51 PM PDT 24 Jul 05 05:21:55 PM PDT 24 222903319 ps
T553 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2010865588 Jul 05 05:23:12 PM PDT 24 Jul 05 05:23:13 PM PDT 24 48964906 ps
T140 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1082271263 Jul 05 05:22:25 PM PDT 24 Jul 05 05:22:29 PM PDT 24 184200358 ps
T122 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.456343556 Jul 05 05:21:52 PM PDT 24 Jul 05 05:22:08 PM PDT 24 312368377 ps
T554 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.324296520 Jul 05 05:22:34 PM PDT 24 Jul 05 05:22:37 PM PDT 24 107116284 ps
T123 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2228077322 Jul 05 05:21:50 PM PDT 24 Jul 05 05:21:51 PM PDT 24 70929728 ps
T555 /workspace/coverage/cover_reg_top/19.hmac_intr_test.3261601145 Jul 05 05:22:46 PM PDT 24 Jul 05 05:22:47 PM PDT 24 30513037 ps
T556 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1509196934 Jul 05 05:22:14 PM PDT 24 Jul 05 05:22:16 PM PDT 24 46764925 ps
T124 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2430738038 Jul 05 05:21:58 PM PDT 24 Jul 05 05:22:00 PM PDT 24 40983573 ps
T557 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.4124179969 Jul 05 05:22:34 PM PDT 24 Jul 05 05:22:40 PM PDT 24 938229441 ps
T558 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.688008442 Jul 05 05:22:19 PM PDT 24 Jul 05 05:22:23 PM PDT 24 96799559 ps
T559 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.377669881 Jul 05 05:21:58 PM PDT 24 Jul 05 05:22:03 PM PDT 24 113253723 ps
T560 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.810892991 Jul 05 05:21:51 PM PDT 24 Jul 05 05:21:54 PM PDT 24 633111040 ps
T561 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1250184890 Jul 05 05:22:11 PM PDT 24 Jul 05 05:22:17 PM PDT 24 117343734 ps
T562 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.387520119 Jul 05 05:21:51 PM PDT 24 Jul 05 05:21:53 PM PDT 24 56241046 ps
T147 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3194466615 Jul 05 05:22:13 PM PDT 24 Jul 05 05:22:15 PM PDT 24 58085171 ps
T563 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1745530265 Jul 05 05:22:17 PM PDT 24 Jul 05 05:22:19 PM PDT 24 42104208 ps
T564 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1472579415 Jul 05 05:22:50 PM PDT 24 Jul 05 05:22:51 PM PDT 24 39556390 ps
T565 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1421933281 Jul 05 05:22:06 PM PDT 24 Jul 05 05:22:10 PM PDT 24 58823662 ps
T566 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2715206418 Jul 05 05:22:19 PM PDT 24 Jul 05 05:22:22 PM PDT 24 36467100 ps
T567 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2241913285 Jul 05 05:22:42 PM PDT 24 Jul 05 05:22:46 PM PDT 24 910088772 ps
T568 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3759056337 Jul 05 05:22:27 PM PDT 24 Jul 05 05:22:30 PM PDT 24 164543436 ps
T569 /workspace/coverage/cover_reg_top/30.hmac_intr_test.4079701111 Jul 05 05:22:57 PM PDT 24 Jul 05 05:22:58 PM PDT 24 49260100 ps
T570 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2351695676 Jul 05 05:21:48 PM PDT 24 Jul 05 05:21:49 PM PDT 24 50509152 ps
T571 /workspace/coverage/cover_reg_top/0.hmac_intr_test.3565760849 Jul 05 05:21:51 PM PDT 24 Jul 05 05:21:52 PM PDT 24 13432054 ps
T572 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1379775956 Jul 05 05:22:33 PM PDT 24 Jul 05 05:22:35 PM PDT 24 150482375 ps
T573 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1194140450 Jul 05 05:22:35 PM PDT 24 Jul 05 05:22:37 PM PDT 24 18643977 ps
T574 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.4116736426 Jul 05 05:21:50 PM PDT 24 Jul 05 05:21:51 PM PDT 24 122101207 ps
T141 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2700299241 Jul 05 05:22:04 PM PDT 24 Jul 05 05:22:09 PM PDT 24 639525338 ps
T575 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1788200695 Jul 05 05:22:25 PM PDT 24 Jul 05 05:22:28 PM PDT 24 149214273 ps
T576 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2920326667 Jul 05 05:22:11 PM PDT 24 Jul 05 05:22:12 PM PDT 24 41376119 ps
T577 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1597385533 Jul 05 05:22:44 PM PDT 24 Jul 05 05:22:47 PM PDT 24 157668762 ps
T145 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1773506156 Jul 05 05:22:20 PM PDT 24 Jul 05 05:22:26 PM PDT 24 232376149 ps
T578 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2574514259 Jul 05 05:22:50 PM PDT 24 Jul 05 05:22:51 PM PDT 24 29606097 ps
T579 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.983043439 Jul 05 05:22:03 PM PDT 24 Jul 05 05:22:06 PM PDT 24 82525079 ps
T580 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2887663462 Jul 05 05:22:11 PM PDT 24 Jul 05 05:34:28 PM PDT 24 50073661312 ps
T581 /workspace/coverage/cover_reg_top/10.hmac_intr_test.187636922 Jul 05 05:22:32 PM PDT 24 Jul 05 05:22:33 PM PDT 24 19586131 ps
T582 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.399079739 Jul 05 05:22:35 PM PDT 24 Jul 05 05:22:38 PM PDT 24 67947039 ps
T583 /workspace/coverage/cover_reg_top/22.hmac_intr_test.579610431 Jul 05 05:22:47 PM PDT 24 Jul 05 05:22:48 PM PDT 24 13465369 ps
T584 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3849072318 Jul 05 05:22:33 PM PDT 24 Jul 05 05:22:38 PM PDT 24 83616921 ps
T585 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3294418771 Jul 05 05:22:25 PM PDT 24 Jul 05 05:24:05 PM PDT 24 7164708430 ps
T586 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3535629882 Jul 05 05:22:32 PM PDT 24 Jul 05 05:22:35 PM PDT 24 106263118 ps
T587 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.640501085 Jul 05 05:22:38 PM PDT 24 Jul 05 05:22:41 PM PDT 24 428276511 ps
T588 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1863599193 Jul 05 05:22:03 PM PDT 24 Jul 05 05:22:04 PM PDT 24 15996594 ps
T589 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2310205673 Jul 05 05:23:12 PM PDT 24 Jul 05 05:23:14 PM PDT 24 203052850 ps
T590 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2739345554 Jul 05 05:22:52 PM PDT 24 Jul 05 05:22:53 PM PDT 24 36147494 ps
T591 /workspace/coverage/cover_reg_top/20.hmac_intr_test.3348185763 Jul 05 05:22:45 PM PDT 24 Jul 05 05:22:46 PM PDT 24 29538384 ps
T592 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1344877554 Jul 05 05:22:36 PM PDT 24 Jul 05 05:22:38 PM PDT 24 10996506 ps
T593 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2138247081 Jul 05 05:22:32 PM PDT 24 Jul 05 05:22:33 PM PDT 24 44285359 ps
T594 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3761554461 Jul 05 05:22:11 PM PDT 24 Jul 05 05:22:12 PM PDT 24 188940556 ps
T143 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2499557413 Jul 05 05:22:19 PM PDT 24 Jul 05 05:22:22 PM PDT 24 106032730 ps
T595 /workspace/coverage/cover_reg_top/45.hmac_intr_test.902800769 Jul 05 05:23:01 PM PDT 24 Jul 05 05:23:02 PM PDT 24 14405916 ps
T596 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3794820144 Jul 05 05:22:34 PM PDT 24 Jul 05 05:22:36 PM PDT 24 55363221 ps
T597 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1291218352 Jul 05 05:22:37 PM PDT 24 Jul 05 05:22:40 PM PDT 24 253681981 ps
T598 /workspace/coverage/cover_reg_top/13.hmac_intr_test.23270282 Jul 05 05:22:33 PM PDT 24 Jul 05 05:22:35 PM PDT 24 46870767 ps
T148 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2647810419 Jul 05 05:22:39 PM PDT 24 Jul 05 05:22:42 PM PDT 24 65174450 ps
T125 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2527462995 Jul 05 05:21:51 PM PDT 24 Jul 05 05:21:58 PM PDT 24 370780435 ps
T599 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1805171711 Jul 05 05:24:56 PM PDT 24 Jul 05 05:24:59 PM PDT 24 104728928 ps
T600 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2318765284 Jul 05 05:21:50 PM PDT 24 Jul 05 05:21:55 PM PDT 24 296680026 ps
T601 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2598626479 Jul 05 05:21:49 PM PDT 24 Jul 05 05:21:50 PM PDT 24 11936124 ps
T602 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3505564342 Jul 05 05:22:17 PM PDT 24 Jul 05 05:22:19 PM PDT 24 36823295 ps
T144 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2676264545 Jul 05 05:22:33 PM PDT 24 Jul 05 05:22:38 PM PDT 24 228903878 ps
T603 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3491012963 Jul 05 05:22:39 PM PDT 24 Jul 05 05:22:42 PM PDT 24 110919912 ps
T604 /workspace/coverage/cover_reg_top/23.hmac_intr_test.642453246 Jul 05 05:22:43 PM PDT 24 Jul 05 05:22:44 PM PDT 24 99881209 ps
T605 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1847904832 Jul 05 05:22:37 PM PDT 24 Jul 05 05:22:40 PM PDT 24 75870303 ps
T606 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2413451366 Jul 05 05:22:11 PM PDT 24 Jul 05 05:22:13 PM PDT 24 19572754 ps
T607 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3040871820 Jul 05 05:22:39 PM PDT 24 Jul 05 05:22:42 PM PDT 24 104420689 ps
T608 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3577347650 Jul 05 05:22:59 PM PDT 24 Jul 05 05:23:01 PM PDT 24 12690539 ps
T609 /workspace/coverage/cover_reg_top/26.hmac_intr_test.316321012 Jul 05 05:23:12 PM PDT 24 Jul 05 05:23:13 PM PDT 24 18082324 ps
T610 /workspace/coverage/cover_reg_top/34.hmac_intr_test.2030401130 Jul 05 05:22:50 PM PDT 24 Jul 05 05:22:51 PM PDT 24 29570950 ps
T146 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.803307912 Jul 05 05:21:49 PM PDT 24 Jul 05 05:21:52 PM PDT 24 175057137 ps
T611 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2219183996 Jul 05 05:21:43 PM PDT 24 Jul 05 05:21:45 PM PDT 24 25914194 ps
T612 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2499850850 Jul 05 05:22:11 PM PDT 24 Jul 05 05:22:13 PM PDT 24 143631952 ps
T613 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.607990936 Jul 05 05:22:10 PM PDT 24 Jul 05 05:22:13 PM PDT 24 542804334 ps
T614 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2606275608 Jul 05 05:22:33 PM PDT 24 Jul 05 05:22:36 PM PDT 24 45677919 ps
T615 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.977272315 Jul 05 05:22:39 PM PDT 24 Jul 05 05:22:43 PM PDT 24 647718936 ps
T68 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2369936159 Jul 05 05:22:41 PM PDT 24 Jul 05 05:22:46 PM PDT 24 537845834 ps
T616 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2583926861 Jul 05 05:22:05 PM PDT 24 Jul 05 05:22:07 PM PDT 24 153964135 ps
T617 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.722050627 Jul 05 05:22:08 PM PDT 24 Jul 05 05:22:10 PM PDT 24 58042730 ps
T618 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.397534812 Jul 05 05:22:47 PM PDT 24 Jul 05 05:22:49 PM PDT 24 198892401 ps
T619 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2314832804 Jul 05 05:22:31 PM PDT 24 Jul 05 05:22:35 PM PDT 24 689493765 ps
T620 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2110155654 Jul 05 05:22:34 PM PDT 24 Jul 05 05:22:37 PM PDT 24 31300613 ps
T621 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.4289736648 Jul 05 05:22:19 PM PDT 24 Jul 05 05:22:23 PM PDT 24 103584651 ps
T126 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3305074349 Jul 05 05:21:48 PM PDT 24 Jul 05 05:21:54 PM PDT 24 362211206 ps
T622 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.963628393 Jul 05 05:22:34 PM PDT 24 Jul 05 05:22:38 PM PDT 24 98030816 ps
T623 /workspace/coverage/cover_reg_top/2.hmac_intr_test.1289501263 Jul 05 05:21:56 PM PDT 24 Jul 05 05:21:57 PM PDT 24 38280268 ps
T624 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1685489856 Jul 05 05:21:49 PM PDT 24 Jul 05 05:21:51 PM PDT 24 332220033 ps
T625 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.4219557297 Jul 05 05:22:06 PM PDT 24 Jul 05 05:22:08 PM PDT 24 36722672 ps
T626 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.448333836 Jul 05 05:22:35 PM PDT 24 Jul 05 05:22:40 PM PDT 24 259332460 ps
T627 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3986189700 Jul 05 05:22:04 PM PDT 24 Jul 05 05:22:08 PM PDT 24 202280032 ps
T628 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1312864284 Jul 05 05:22:46 PM PDT 24 Jul 05 05:22:47 PM PDT 24 32039587 ps
T629 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3929601858 Jul 05 05:22:44 PM PDT 24 Jul 05 05:22:46 PM PDT 24 19311366 ps
T630 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.733733846 Jul 05 05:21:51 PM PDT 24 Jul 05 05:21:57 PM PDT 24 741663511 ps
T631 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1356437003 Jul 05 05:22:38 PM PDT 24 Jul 05 05:22:40 PM PDT 24 34038524 ps
T632 /workspace/coverage/cover_reg_top/6.hmac_intr_test.378495931 Jul 05 05:22:20 PM PDT 24 Jul 05 05:22:21 PM PDT 24 29427793 ps
T633 /workspace/coverage/cover_reg_top/11.hmac_intr_test.1137815126 Jul 05 05:22:35 PM PDT 24 Jul 05 05:22:37 PM PDT 24 43300718 ps
T634 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3375732849 Jul 05 05:22:19 PM PDT 24 Jul 05 05:22:20 PM PDT 24 17819833 ps
T635 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2466263397 Jul 05 05:22:39 PM PDT 24 Jul 05 05:22:41 PM PDT 24 15913197 ps
T636 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.312811176 Jul 05 05:22:10 PM PDT 24 Jul 05 05:22:11 PM PDT 24 72523149 ps
T637 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1740968945 Jul 05 05:22:58 PM PDT 24 Jul 05 05:23:00 PM PDT 24 14739509 ps
T638 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2109759263 Jul 05 05:23:00 PM PDT 24 Jul 05 05:23:02 PM PDT 24 24151200 ps
T639 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.5639044 Jul 05 05:22:44 PM PDT 24 Jul 05 05:22:49 PM PDT 24 956346909 ps
T640 /workspace/coverage/cover_reg_top/31.hmac_intr_test.620260688 Jul 05 05:22:51 PM PDT 24 Jul 05 05:22:52 PM PDT 24 69080932 ps
T641 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2467472498 Jul 05 05:22:39 PM PDT 24 Jul 05 05:22:44 PM PDT 24 255835408 ps
T642 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2676708340 Jul 05 05:23:12 PM PDT 24 Jul 05 05:23:15 PM PDT 24 137573781 ps
T643 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2804871082 Jul 05 05:23:12 PM PDT 24 Jul 05 05:23:14 PM PDT 24 95110127 ps
T644 /workspace/coverage/cover_reg_top/37.hmac_intr_test.3106594787 Jul 05 05:22:52 PM PDT 24 Jul 05 05:22:53 PM PDT 24 58784589 ps
T645 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3224236968 Jul 05 05:22:44 PM PDT 24 Jul 05 05:22:45 PM PDT 24 42065662 ps
T646 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3189397899 Jul 05 05:22:38 PM PDT 24 Jul 05 05:22:40 PM PDT 24 56347822 ps
T647 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2795924252 Jul 05 05:22:25 PM PDT 24 Jul 05 05:22:28 PM PDT 24 36301579 ps
T648 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.854394609 Jul 05 05:22:45 PM PDT 24 Jul 05 05:22:48 PM PDT 24 49142000 ps
T649 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3497024034 Jul 05 05:22:26 PM PDT 24 Jul 05 05:22:28 PM PDT 24 42956428 ps
T650 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3402148952 Jul 05 05:23:00 PM PDT 24 Jul 05 05:23:02 PM PDT 24 14616204 ps
T651 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3535076455 Jul 05 05:22:04 PM PDT 24 Jul 05 05:22:16 PM PDT 24 6423053812 ps
T652 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.793288337 Jul 05 05:21:51 PM PDT 24 Jul 05 05:21:53 PM PDT 24 62125142 ps
T653 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1233707613 Jul 05 05:22:19 PM PDT 24 Jul 05 05:22:20 PM PDT 24 11106719 ps
T654 /workspace/coverage/cover_reg_top/38.hmac_intr_test.117016521 Jul 05 05:22:58 PM PDT 24 Jul 05 05:22:59 PM PDT 24 23317221 ps
T655 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1515113148 Jul 05 05:22:19 PM PDT 24 Jul 05 05:22:21 PM PDT 24 45273229 ps
T656 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4095092361 Jul 05 05:22:01 PM PDT 24 Jul 05 05:22:04 PM PDT 24 816873973 ps
T657 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3100574915 Jul 05 05:22:19 PM PDT 24 Jul 05 05:22:21 PM PDT 24 65122630 ps
T658 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3158491855 Jul 05 05:21:51 PM PDT 24 Jul 05 05:21:52 PM PDT 24 51362036 ps

Test location /workspace/coverage/default/33.hmac_datapath_stress.3285005095
Short name T4
Test name
Test status
Simulation time 811950271 ps
CPU time 118.58 seconds
Started Jul 05 05:46:59 PM PDT 24
Finished Jul 05 05:48:58 PM PDT 24
Peak memory 356552 kb
Host smart-8466e73c-5a32-4ccc-9a06-458a5d9883e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3285005095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.3285005095
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.3537460301
Short name T11
Test name
Test status
Simulation time 50754922476 ps
CPU time 2766.75 seconds
Started Jul 05 05:45:51 PM PDT 24
Finished Jul 05 06:31:58 PM PDT 24
Peak memory 684864 kb
Host smart-cfd4e562-bebb-4eab-852f-6397feb9136d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3537460301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.3537460301
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2063199370
Short name T21
Test name
Test status
Simulation time 1191484300 ps
CPU time 69.74 seconds
Started Jul 05 05:46:34 PM PDT 24
Finished Jul 05 05:47:44 PM PDT 24
Peak memory 200316 kb
Host smart-a5cffd3d-b9ad-4e50-abf2-65221eb0b4b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2063199370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2063199370
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2233073823
Short name T25
Test name
Test status
Simulation time 10100943400 ps
CPU time 826.34 seconds
Started Jul 05 05:46:07 PM PDT 24
Finished Jul 05 05:59:54 PM PDT 24
Peak memory 699584 kb
Host smart-7ef9abe1-68b9-4b4e-969d-081585b04a3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233073823 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2233073823
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1544443228
Short name T65
Test name
Test status
Simulation time 433321567 ps
CPU time 3.97 seconds
Started Jul 05 05:22:33 PM PDT 24
Finished Jul 05 05:22:39 PM PDT 24
Peak memory 200204 kb
Host smart-de4c118f-b580-4121-b884-72725bb49ac5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544443228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1544443228
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.96091156
Short name T19
Test name
Test status
Simulation time 282532856026 ps
CPU time 3709 seconds
Started Jul 05 05:45:48 PM PDT 24
Finished Jul 05 06:47:38 PM PDT 24
Peak memory 788284 kb
Host smart-ee3b1fc2-ff3e-41c6-b5eb-af615f591c5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=96091156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.96091156
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2531021564
Short name T3
Test name
Test status
Simulation time 314369197 ps
CPU time 0.97 seconds
Started Jul 05 05:45:25 PM PDT 24
Finished Jul 05 05:45:26 PM PDT 24
Peak memory 218316 kb
Host smart-fa15ad26-8db4-46fa-8b62-2c5cb027ab96
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531021564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2531021564
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/49.hmac_stress_all.3517304390
Short name T15
Test name
Test status
Simulation time 33366490153 ps
CPU time 1069.99 seconds
Started Jul 05 05:47:43 PM PDT 24
Finished Jul 05 06:05:34 PM PDT 24
Peak memory 473468 kb
Host smart-68a88fde-aadf-418d-a96b-93f814275c53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517304390 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3517304390
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1330071714
Short name T115
Test name
Test status
Simulation time 32549032 ps
CPU time 0.95 seconds
Started Jul 05 05:22:31 PM PDT 24
Finished Jul 05 05:22:33 PM PDT 24
Peak memory 199860 kb
Host smart-8e7d95ab-60c6-482e-b8bb-ce2061c6cd76
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330071714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1330071714
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2032764890
Short name T16
Test name
Test status
Simulation time 7171407100 ps
CPU time 103.16 seconds
Started Jul 05 05:45:49 PM PDT 24
Finished Jul 05 05:47:32 PM PDT 24
Peak memory 200440 kb
Host smart-26e41b85-993b-4554-bc7a-db92bb78e1e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2032764890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2032764890
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2369936159
Short name T68
Test name
Test status
Simulation time 537845834 ps
CPU time 4.66 seconds
Started Jul 05 05:22:41 PM PDT 24
Finished Jul 05 05:22:46 PM PDT 24
Peak memory 200352 kb
Host smart-534de6b0-d6ae-4e8f-8e06-585e885f8828
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369936159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2369936159
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3572935465
Short name T160
Test name
Test status
Simulation time 17201444 ps
CPU time 0.58 seconds
Started Jul 05 05:45:53 PM PDT 24
Finished Jul 05 05:45:54 PM PDT 24
Peak memory 195104 kb
Host smart-066366fb-7eed-48c5-9e04-bc0b3577a209
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572935465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3572935465
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2499557413
Short name T143
Test name
Test status
Simulation time 106032730 ps
CPU time 1.89 seconds
Started Jul 05 05:22:19 PM PDT 24
Finished Jul 05 05:22:22 PM PDT 24
Peak memory 200320 kb
Host smart-667e2ce2-0913-49fd-949a-b8b10ba8c969
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499557413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2499557413
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3746622042
Short name T100
Test name
Test status
Simulation time 879348176 ps
CPU time 48.1 seconds
Started Jul 05 05:45:22 PM PDT 24
Finished Jul 05 05:46:10 PM PDT 24
Peak memory 200340 kb
Host smart-582c744d-c6d4-4437-acd8-ded31fb99684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746622042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3746622042
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3305074349
Short name T126
Test name
Test status
Simulation time 362211206 ps
CPU time 5.92 seconds
Started Jul 05 05:21:48 PM PDT 24
Finished Jul 05 05:21:54 PM PDT 24
Peak memory 200296 kb
Host smart-fbe3f2a8-3a55-43bf-9c7c-a773113c23b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305074349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3305074349
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.733733846
Short name T630
Test name
Test status
Simulation time 741663511 ps
CPU time 5.64 seconds
Started Jul 05 05:21:51 PM PDT 24
Finished Jul 05 05:21:57 PM PDT 24
Peak memory 200168 kb
Host smart-37c4c4e8-8118-4ecd-a6f7-0a2ba0bc7590
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733733846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.733733846
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2228077322
Short name T123
Test name
Test status
Simulation time 70929728 ps
CPU time 0.79 seconds
Started Jul 05 05:21:50 PM PDT 24
Finished Jul 05 05:21:51 PM PDT 24
Peak memory 198576 kb
Host smart-f7c10375-9e7a-4b46-b814-20e2655d7139
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228077322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2228077322
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.793288337
Short name T652
Test name
Test status
Simulation time 62125142 ps
CPU time 1.13 seconds
Started Jul 05 05:21:51 PM PDT 24
Finished Jul 05 05:21:53 PM PDT 24
Peak memory 200120 kb
Host smart-2a617dd7-db0c-48d1-b767-3a7f64393824
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793288337 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.793288337
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3158491855
Short name T658
Test name
Test status
Simulation time 51362036 ps
CPU time 0.78 seconds
Started Jul 05 05:21:51 PM PDT 24
Finished Jul 05 05:21:52 PM PDT 24
Peak memory 200020 kb
Host smart-5d441328-add8-4088-85e1-1c66612095e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158491855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3158491855
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3565760849
Short name T571
Test name
Test status
Simulation time 13432054 ps
CPU time 0.59 seconds
Started Jul 05 05:21:51 PM PDT 24
Finished Jul 05 05:21:52 PM PDT 24
Peak memory 195156 kb
Host smart-707568f1-179b-478d-a29e-ba7fad5c64e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565760849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3565760849
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.387520119
Short name T562
Test name
Test status
Simulation time 56241046 ps
CPU time 1.24 seconds
Started Jul 05 05:21:51 PM PDT 24
Finished Jul 05 05:21:53 PM PDT 24
Peak memory 200288 kb
Host smart-fc1611bf-b8bf-49df-88ef-6c9ca38b5bcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387520119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.387520119
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2219183996
Short name T611
Test name
Test status
Simulation time 25914194 ps
CPU time 1.34 seconds
Started Jul 05 05:21:43 PM PDT 24
Finished Jul 05 05:21:45 PM PDT 24
Peak memory 200292 kb
Host smart-f246a587-1d88-4c11-bf82-64d42b0074e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219183996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2219183996
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.803307912
Short name T146
Test name
Test status
Simulation time 175057137 ps
CPU time 2.01 seconds
Started Jul 05 05:21:49 PM PDT 24
Finished Jul 05 05:21:52 PM PDT 24
Peak memory 200284 kb
Host smart-0807cf09-bb93-49c9-9236-e4e5e03d0415
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803307912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.803307912
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2527462995
Short name T125
Test name
Test status
Simulation time 370780435 ps
CPU time 5.98 seconds
Started Jul 05 05:21:51 PM PDT 24
Finished Jul 05 05:21:58 PM PDT 24
Peak memory 200332 kb
Host smart-c5a7df14-98f4-4cb5-bca1-19afac327c2b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527462995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.2527462995
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.456343556
Short name T122
Test name
Test status
Simulation time 312368377 ps
CPU time 15.19 seconds
Started Jul 05 05:21:52 PM PDT 24
Finished Jul 05 05:22:08 PM PDT 24
Peak memory 200300 kb
Host smart-257261ed-2c52-412c-bfbb-75d17083770d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456343556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.456343556
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2201862393
Short name T112
Test name
Test status
Simulation time 316524855 ps
CPU time 1.01 seconds
Started Jul 05 05:21:50 PM PDT 24
Finished Jul 05 05:21:51 PM PDT 24
Peak memory 199884 kb
Host smart-9f68b4ff-38b3-493e-a35d-a227fbbe17cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201862393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2201862393
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.4116736426
Short name T574
Test name
Test status
Simulation time 122101207 ps
CPU time 1.13 seconds
Started Jul 05 05:21:50 PM PDT 24
Finished Jul 05 05:21:51 PM PDT 24
Peak memory 200184 kb
Host smart-1d545b49-2911-41c1-83d0-81e6c3f84299
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116736426 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.4116736426
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2351695676
Short name T570
Test name
Test status
Simulation time 50509152 ps
CPU time 0.67 seconds
Started Jul 05 05:21:48 PM PDT 24
Finished Jul 05 05:21:49 PM PDT 24
Peak memory 198728 kb
Host smart-4138e64b-76fa-48c7-a08f-514ba604e56f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351695676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2351695676
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2598626479
Short name T601
Test name
Test status
Simulation time 11936124 ps
CPU time 0.58 seconds
Started Jul 05 05:21:49 PM PDT 24
Finished Jul 05 05:21:50 PM PDT 24
Peak memory 195340 kb
Host smart-b39867b3-784b-4e54-8666-2e667edc04c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598626479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2598626479
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.810892991
Short name T560
Test name
Test status
Simulation time 633111040 ps
CPU time 2.36 seconds
Started Jul 05 05:21:51 PM PDT 24
Finished Jul 05 05:21:54 PM PDT 24
Peak memory 200344 kb
Host smart-b8fd2b74-97e8-4261-9eab-c61fb30b7eb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810892991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.810892991
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2318765284
Short name T600
Test name
Test status
Simulation time 296680026 ps
CPU time 4.2 seconds
Started Jul 05 05:21:50 PM PDT 24
Finished Jul 05 05:21:55 PM PDT 24
Peak memory 200320 kb
Host smart-5e83ce99-0a84-408f-bb2e-976720e23e38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318765284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2318765284
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1685489856
Short name T624
Test name
Test status
Simulation time 332220033 ps
CPU time 1.88 seconds
Started Jul 05 05:21:49 PM PDT 24
Finished Jul 05 05:21:51 PM PDT 24
Peak memory 200332 kb
Host smart-347d15db-7f03-4c8f-ae33-ee928664f4c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685489856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1685489856
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2606275608
Short name T614
Test name
Test status
Simulation time 45677919 ps
CPU time 2.49 seconds
Started Jul 05 05:22:33 PM PDT 24
Finished Jul 05 05:22:36 PM PDT 24
Peak memory 200376 kb
Host smart-c89ebeca-9240-4e3a-a142-5e7ddee15ad2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606275608 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2606275608
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1831770482
Short name T548
Test name
Test status
Simulation time 21608413 ps
CPU time 0.71 seconds
Started Jul 05 05:22:31 PM PDT 24
Finished Jul 05 05:22:32 PM PDT 24
Peak memory 198176 kb
Host smart-27896a2a-8f2e-456a-b487-db63817d0579
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831770482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1831770482
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.187636922
Short name T581
Test name
Test status
Simulation time 19586131 ps
CPU time 0.63 seconds
Started Jul 05 05:22:32 PM PDT 24
Finished Jul 05 05:22:33 PM PDT 24
Peak memory 195216 kb
Host smart-fd2180bd-f124-4807-a584-0e9e11e6051b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187636922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.187636922
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3794820144
Short name T596
Test name
Test status
Simulation time 55363221 ps
CPU time 1.22 seconds
Started Jul 05 05:22:34 PM PDT 24
Finished Jul 05 05:22:36 PM PDT 24
Peak memory 200176 kb
Host smart-ba8d9403-e436-4dd4-b943-a4191dafef9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794820144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3794820144
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3759056337
Short name T568
Test name
Test status
Simulation time 164543436 ps
CPU time 2.29 seconds
Started Jul 05 05:22:27 PM PDT 24
Finished Jul 05 05:22:30 PM PDT 24
Peak memory 200360 kb
Host smart-f68bad4a-b011-4906-835c-6bb5a33e7cff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759056337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3759056337
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2676264545
Short name T144
Test name
Test status
Simulation time 228903878 ps
CPU time 4.19 seconds
Started Jul 05 05:22:33 PM PDT 24
Finished Jul 05 05:22:38 PM PDT 24
Peak memory 200292 kb
Host smart-e6db8d7a-4b74-47c1-bc57-6d79f65cc07b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676264545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2676264545
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.399079739
Short name T582
Test name
Test status
Simulation time 67947039 ps
CPU time 2.14 seconds
Started Jul 05 05:22:35 PM PDT 24
Finished Jul 05 05:22:38 PM PDT 24
Peak memory 200360 kb
Host smart-412f2b20-43b6-4358-89f8-cb6e67716d19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399079739 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.399079739
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.1137815126
Short name T633
Test name
Test status
Simulation time 43300718 ps
CPU time 0.62 seconds
Started Jul 05 05:22:35 PM PDT 24
Finished Jul 05 05:22:37 PM PDT 24
Peak memory 195132 kb
Host smart-461e2f27-a611-4fb1-8d1f-af79f294099a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137815126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.1137815126
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2666352431
Short name T128
Test name
Test status
Simulation time 177869304 ps
CPU time 2.3 seconds
Started Jul 05 05:22:32 PM PDT 24
Finished Jul 05 05:22:35 PM PDT 24
Peak memory 200364 kb
Host smart-00d6eaec-694e-46b4-a512-5c4d80200487
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666352431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2666352431
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3849072318
Short name T584
Test name
Test status
Simulation time 83616921 ps
CPU time 3.83 seconds
Started Jul 05 05:22:33 PM PDT 24
Finished Jul 05 05:22:38 PM PDT 24
Peak memory 200356 kb
Host smart-b6a57161-cded-48d1-8910-295c17616356
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849072318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3849072318
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1344173800
Short name T534
Test name
Test status
Simulation time 147674581881 ps
CPU time 701.32 seconds
Started Jul 05 05:22:35 PM PDT 24
Finished Jul 05 05:34:18 PM PDT 24
Peak memory 216716 kb
Host smart-fc31adda-8865-498f-848a-1eedd3e5c15b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344173800 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1344173800
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.4247865595
Short name T119
Test name
Test status
Simulation time 60169401 ps
CPU time 0.91 seconds
Started Jul 05 05:22:33 PM PDT 24
Finished Jul 05 05:22:36 PM PDT 24
Peak memory 200156 kb
Host smart-294c0320-cd28-4d52-aa44-664bc130a023
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247865595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.4247865595
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2110155654
Short name T620
Test name
Test status
Simulation time 31300613 ps
CPU time 0.57 seconds
Started Jul 05 05:22:34 PM PDT 24
Finished Jul 05 05:22:37 PM PDT 24
Peak memory 195176 kb
Host smart-f450ee3b-a19e-4c96-9ad6-d7dcf7ebc3d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110155654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2110155654
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.324296520
Short name T554
Test name
Test status
Simulation time 107116284 ps
CPU time 1.8 seconds
Started Jul 05 05:22:34 PM PDT 24
Finished Jul 05 05:22:37 PM PDT 24
Peak memory 200120 kb
Host smart-c252cbd2-87dc-421d-84ef-84ad776fe5e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324296520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.324296520
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.4124179969
Short name T557
Test name
Test status
Simulation time 938229441 ps
CPU time 4.45 seconds
Started Jul 05 05:22:34 PM PDT 24
Finished Jul 05 05:22:40 PM PDT 24
Peak memory 200348 kb
Host smart-11ebea9b-0662-4ec6-82ef-16c0c253864b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124179969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.4124179969
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.963628393
Short name T622
Test name
Test status
Simulation time 98030816 ps
CPU time 2.84 seconds
Started Jul 05 05:22:34 PM PDT 24
Finished Jul 05 05:22:38 PM PDT 24
Peak memory 200308 kb
Host smart-8da77748-3395-4fcc-8f01-293ba2f495a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963628393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.963628393
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2699036814
Short name T535
Test name
Test status
Simulation time 45819554 ps
CPU time 2.9 seconds
Started Jul 05 05:22:33 PM PDT 24
Finished Jul 05 05:22:38 PM PDT 24
Peak memory 208624 kb
Host smart-249ba47b-87aa-4090-8e30-b605eff6bda3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699036814 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2699036814
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1379775956
Short name T572
Test name
Test status
Simulation time 150482375 ps
CPU time 0.85 seconds
Started Jul 05 05:22:33 PM PDT 24
Finished Jul 05 05:22:35 PM PDT 24
Peak memory 199948 kb
Host smart-c54cc38d-819e-4f1b-b174-d81fee46236a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379775956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1379775956
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.23270282
Short name T598
Test name
Test status
Simulation time 46870767 ps
CPU time 0.59 seconds
Started Jul 05 05:22:33 PM PDT 24
Finished Jul 05 05:22:35 PM PDT 24
Peak memory 195280 kb
Host smart-7ed0b235-5a9e-4508-a2ee-110116ba0895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23270282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.23270282
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2138247081
Short name T593
Test name
Test status
Simulation time 44285359 ps
CPU time 1.09 seconds
Started Jul 05 05:22:32 PM PDT 24
Finished Jul 05 05:22:33 PM PDT 24
Peak memory 198876 kb
Host smart-b91145b7-c0b5-4b1a-9c80-aa3a30b6586f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138247081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2138247081
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.448333836
Short name T626
Test name
Test status
Simulation time 259332460 ps
CPU time 3.32 seconds
Started Jul 05 05:22:35 PM PDT 24
Finished Jul 05 05:22:40 PM PDT 24
Peak memory 200380 kb
Host smart-327b5629-50c5-4307-822c-0329da66cf30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448333836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.448333836
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.438554321
Short name T142
Test name
Test status
Simulation time 412036490 ps
CPU time 4.02 seconds
Started Jul 05 05:22:34 PM PDT 24
Finished Jul 05 05:22:40 PM PDT 24
Peak memory 200356 kb
Host smart-b370bcdd-f4bf-419d-9b8f-41caf191f681
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438554321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.438554321
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1493801727
Short name T71
Test name
Test status
Simulation time 33612223 ps
CPU time 1.17 seconds
Started Jul 05 05:22:37 PM PDT 24
Finished Jul 05 05:22:40 PM PDT 24
Peak memory 200196 kb
Host smart-e63b4ad2-9e29-49fe-ab76-1c612e2ad454
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493801727 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1493801727
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2466263397
Short name T635
Test name
Test status
Simulation time 15913197 ps
CPU time 0.7 seconds
Started Jul 05 05:22:39 PM PDT 24
Finished Jul 05 05:22:41 PM PDT 24
Peak memory 198624 kb
Host smart-263deca1-ef9f-4201-83f6-39988afade93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466263397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2466263397
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.995169698
Short name T531
Test name
Test status
Simulation time 12819187 ps
CPU time 0.59 seconds
Started Jul 05 05:22:39 PM PDT 24
Finished Jul 05 05:22:40 PM PDT 24
Peak memory 195276 kb
Host smart-26fe23cc-8e9e-4d01-9f00-2b4831a8722b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995169698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.995169698
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3469133579
Short name T130
Test name
Test status
Simulation time 186259332 ps
CPU time 1.19 seconds
Started Jul 05 05:22:43 PM PDT 24
Finished Jul 05 05:22:44 PM PDT 24
Peak memory 198612 kb
Host smart-085e8d61-ad61-4745-a9d3-f6866dd01499
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469133579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3469133579
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2314832804
Short name T619
Test name
Test status
Simulation time 689493765 ps
CPU time 3.73 seconds
Started Jul 05 05:22:31 PM PDT 24
Finished Jul 05 05:22:35 PM PDT 24
Peak memory 200300 kb
Host smart-d4b3de81-8106-4365-97e9-7d5968b1ada9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314832804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2314832804
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3535629882
Short name T586
Test name
Test status
Simulation time 106263118 ps
CPU time 1.9 seconds
Started Jul 05 05:22:32 PM PDT 24
Finished Jul 05 05:22:35 PM PDT 24
Peak memory 200300 kb
Host smart-c9c9fcfe-aeff-4d7f-9b6e-cb690dd1eb62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535629882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3535629882
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2241913285
Short name T567
Test name
Test status
Simulation time 910088772 ps
CPU time 3.44 seconds
Started Jul 05 05:22:42 PM PDT 24
Finished Jul 05 05:22:46 PM PDT 24
Peak memory 216060 kb
Host smart-0cc9821c-a5e2-430f-89f8-70f3143984bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241913285 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2241913285
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1766161294
Short name T129
Test name
Test status
Simulation time 42546549 ps
CPU time 0.7 seconds
Started Jul 05 05:22:40 PM PDT 24
Finished Jul 05 05:22:42 PM PDT 24
Peak memory 198484 kb
Host smart-cf5bbfb1-f190-4b8e-9d01-a18a20a127b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766161294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1766161294
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3189397899
Short name T646
Test name
Test status
Simulation time 56347822 ps
CPU time 0.62 seconds
Started Jul 05 05:22:38 PM PDT 24
Finished Jul 05 05:22:40 PM PDT 24
Peak memory 195160 kb
Host smart-3708b0e2-422c-4116-82fa-6b083dfffd6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189397899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3189397899
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1847904832
Short name T605
Test name
Test status
Simulation time 75870303 ps
CPU time 1.62 seconds
Started Jul 05 05:22:37 PM PDT 24
Finished Jul 05 05:22:40 PM PDT 24
Peak memory 200080 kb
Host smart-e8d6cd4c-fba7-4410-812a-f63843decaa4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847904832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1847904832
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.4148670103
Short name T540
Test name
Test status
Simulation time 475359961 ps
CPU time 3.69 seconds
Started Jul 05 05:22:37 PM PDT 24
Finished Jul 05 05:22:42 PM PDT 24
Peak memory 200372 kb
Host smart-ad192a32-78c2-43f4-b51f-73c1d86359e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148670103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.4148670103
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2647810419
Short name T148
Test name
Test status
Simulation time 65174450 ps
CPU time 1.74 seconds
Started Jul 05 05:22:39 PM PDT 24
Finished Jul 05 05:22:42 PM PDT 24
Peak memory 200312 kb
Host smart-ccfc481c-94ce-4729-9b58-46cdec5d4857
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647810419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2647810419
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.640501085
Short name T587
Test name
Test status
Simulation time 428276511 ps
CPU time 2.55 seconds
Started Jul 05 05:22:38 PM PDT 24
Finished Jul 05 05:22:41 PM PDT 24
Peak memory 200304 kb
Host smart-cc3dac4d-4c85-4e9a-adcb-91fe1a95edb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640501085 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.640501085
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3491012963
Short name T603
Test name
Test status
Simulation time 110919912 ps
CPU time 0.96 seconds
Started Jul 05 05:22:39 PM PDT 24
Finished Jul 05 05:22:42 PM PDT 24
Peak memory 199980 kb
Host smart-eab09fa4-d40a-4387-8c3a-7e61a4ecf7f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491012963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3491012963
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1344877554
Short name T592
Test name
Test status
Simulation time 10996506 ps
CPU time 0.59 seconds
Started Jul 05 05:22:36 PM PDT 24
Finished Jul 05 05:22:38 PM PDT 24
Peak memory 195308 kb
Host smart-53c3ca3f-e6f6-4e79-ad86-a422b337853b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344877554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1344877554
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1356437003
Short name T631
Test name
Test status
Simulation time 34038524 ps
CPU time 1.53 seconds
Started Jul 05 05:22:38 PM PDT 24
Finished Jul 05 05:22:40 PM PDT 24
Peak memory 200080 kb
Host smart-02e3a6a8-c4ca-4089-b861-710a59f4c7ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356437003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1356437003
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3040871820
Short name T607
Test name
Test status
Simulation time 104420689 ps
CPU time 1.89 seconds
Started Jul 05 05:22:39 PM PDT 24
Finished Jul 05 05:22:42 PM PDT 24
Peak memory 200316 kb
Host smart-e3a850d4-f1b1-467b-a70d-ee2380a10aa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040871820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3040871820
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2467472498
Short name T641
Test name
Test status
Simulation time 255835408 ps
CPU time 4.11 seconds
Started Jul 05 05:22:39 PM PDT 24
Finished Jul 05 05:22:44 PM PDT 24
Peak memory 200232 kb
Host smart-3b452e97-7d53-4365-a413-64259404b435
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467472498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2467472498
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2310205673
Short name T589
Test name
Test status
Simulation time 203052850 ps
CPU time 1.56 seconds
Started Jul 05 05:23:12 PM PDT 24
Finished Jul 05 05:23:14 PM PDT 24
Peak memory 200324 kb
Host smart-87193d86-f9ff-46fc-91a5-699902babddf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310205673 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2310205673
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1291218352
Short name T597
Test name
Test status
Simulation time 253681981 ps
CPU time 0.79 seconds
Started Jul 05 05:22:37 PM PDT 24
Finished Jul 05 05:22:40 PM PDT 24
Peak memory 199796 kb
Host smart-f2a2ad3c-8b93-4218-be28-fa1c87005860
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291218352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1291218352
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1194140450
Short name T573
Test name
Test status
Simulation time 18643977 ps
CPU time 0.63 seconds
Started Jul 05 05:22:35 PM PDT 24
Finished Jul 05 05:22:37 PM PDT 24
Peak memory 195116 kb
Host smart-f287927d-b3fe-4248-8b8e-a14816c63241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194140450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1194140450
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1703430254
Short name T549
Test name
Test status
Simulation time 113301742 ps
CPU time 2.22 seconds
Started Jul 05 05:22:38 PM PDT 24
Finished Jul 05 05:22:41 PM PDT 24
Peak memory 200292 kb
Host smart-bc746b3b-6606-4163-9012-7b2b7fc4c15b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703430254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1703430254
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.977272315
Short name T615
Test name
Test status
Simulation time 647718936 ps
CPU time 3.08 seconds
Started Jul 05 05:22:39 PM PDT 24
Finished Jul 05 05:22:43 PM PDT 24
Peak memory 200372 kb
Host smart-2d82701a-9618-4bb5-a50d-97c0ef5a2b33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977272315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.977272315
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.397534812
Short name T618
Test name
Test status
Simulation time 198892401 ps
CPU time 1.06 seconds
Started Jul 05 05:22:47 PM PDT 24
Finished Jul 05 05:22:49 PM PDT 24
Peak memory 200028 kb
Host smart-cfbe2de8-ddce-423f-9b42-1d0976a24ff8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397534812 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.397534812
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3929601858
Short name T629
Test name
Test status
Simulation time 19311366 ps
CPU time 0.9 seconds
Started Jul 05 05:22:44 PM PDT 24
Finished Jul 05 05:22:46 PM PDT 24
Peak memory 200156 kb
Host smart-fceaf503-e5a7-4843-9814-5c96b8577129
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929601858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3929601858
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3224236968
Short name T645
Test name
Test status
Simulation time 42065662 ps
CPU time 0.64 seconds
Started Jul 05 05:22:44 PM PDT 24
Finished Jul 05 05:22:45 PM PDT 24
Peak memory 195276 kb
Host smart-eac85d3c-986a-449f-b9bb-352579c0308d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224236968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3224236968
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2676708340
Short name T642
Test name
Test status
Simulation time 137573781 ps
CPU time 1.84 seconds
Started Jul 05 05:23:12 PM PDT 24
Finished Jul 05 05:23:15 PM PDT 24
Peak memory 200224 kb
Host smart-e752f16a-552d-4fe1-871d-4b254bab0460
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676708340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2676708340
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.854394609
Short name T648
Test name
Test status
Simulation time 49142000 ps
CPU time 2.26 seconds
Started Jul 05 05:22:45 PM PDT 24
Finished Jul 05 05:22:48 PM PDT 24
Peak memory 200268 kb
Host smart-29b896ac-f268-4df6-bc96-40178c70ce9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854394609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.854394609
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.5639044
Short name T639
Test name
Test status
Simulation time 956346909 ps
CPU time 4.37 seconds
Started Jul 05 05:22:44 PM PDT 24
Finished Jul 05 05:22:49 PM PDT 24
Peak memory 200248 kb
Host smart-f05c578e-b7bc-43c8-a697-fc4decfef709
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5639044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.5639044
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2804871082
Short name T643
Test name
Test status
Simulation time 95110127 ps
CPU time 1.69 seconds
Started Jul 05 05:23:12 PM PDT 24
Finished Jul 05 05:23:14 PM PDT 24
Peak memory 200260 kb
Host smart-2386fcf2-0b77-460a-bb8f-7aa59c0550c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804871082 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2804871082
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3838081643
Short name T113
Test name
Test status
Simulation time 27088683 ps
CPU time 0.86 seconds
Started Jul 05 05:22:46 PM PDT 24
Finished Jul 05 05:22:47 PM PDT 24
Peak memory 199944 kb
Host smart-69dac3f9-7805-4c9e-a5b6-137d17ca9aab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838081643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3838081643
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3261601145
Short name T555
Test name
Test status
Simulation time 30513037 ps
CPU time 0.61 seconds
Started Jul 05 05:22:46 PM PDT 24
Finished Jul 05 05:22:47 PM PDT 24
Peak memory 195280 kb
Host smart-0f2fc4c8-2573-4797-90a9-94de9f9b336e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261601145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3261601145
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.739001221
Short name T131
Test name
Test status
Simulation time 58799822 ps
CPU time 1.23 seconds
Started Jul 05 05:30:39 PM PDT 24
Finished Jul 05 05:30:41 PM PDT 24
Peak memory 200312 kb
Host smart-da57f842-b155-4ecc-84bc-4a765e0c0f5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739001221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.739001221
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1597385533
Short name T577
Test name
Test status
Simulation time 157668762 ps
CPU time 3.02 seconds
Started Jul 05 05:22:44 PM PDT 24
Finished Jul 05 05:22:47 PM PDT 24
Peak memory 200240 kb
Host smart-490a69f3-2eaa-4b35-9fc0-61f888a0601f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597385533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1597385533
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1920471996
Short name T66
Test name
Test status
Simulation time 82962371 ps
CPU time 1.94 seconds
Started Jul 05 05:23:12 PM PDT 24
Finished Jul 05 05:23:15 PM PDT 24
Peak memory 200256 kb
Host smart-e50ae324-5a23-4a10-9190-17b5d13c86cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920471996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1920471996
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1130263103
Short name T537
Test name
Test status
Simulation time 598995846 ps
CPU time 5.68 seconds
Started Jul 05 05:21:57 PM PDT 24
Finished Jul 05 05:22:03 PM PDT 24
Peak memory 200148 kb
Host smart-0630af8e-a46c-4794-bb31-d0d2002b8feb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130263103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1130263103
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.377669881
Short name T559
Test name
Test status
Simulation time 113253723 ps
CPU time 5.25 seconds
Started Jul 05 05:21:58 PM PDT 24
Finished Jul 05 05:22:03 PM PDT 24
Peak memory 200292 kb
Host smart-5840fcb6-33ba-4e19-a8d6-eda8ff58fe58
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377669881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.377669881
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2430738038
Short name T124
Test name
Test status
Simulation time 40983573 ps
CPU time 0.99 seconds
Started Jul 05 05:21:58 PM PDT 24
Finished Jul 05 05:22:00 PM PDT 24
Peak memory 200112 kb
Host smart-35bf13cc-3201-40af-8af9-548cee7d8084
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430738038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2430738038
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1805171711
Short name T599
Test name
Test status
Simulation time 104728928 ps
CPU time 2.4 seconds
Started Jul 05 05:24:56 PM PDT 24
Finished Jul 05 05:24:59 PM PDT 24
Peak memory 200416 kb
Host smart-602226aa-ffe2-4fb6-b5b2-241a37e0080d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805171711 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1805171711
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.241997701
Short name T116
Test name
Test status
Simulation time 72032253 ps
CPU time 0.95 seconds
Started Jul 05 05:21:57 PM PDT 24
Finished Jul 05 05:21:59 PM PDT 24
Peak memory 200080 kb
Host smart-17452b96-55f0-4fe7-b23a-09cbdba94b3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241997701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.241997701
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.1289501263
Short name T623
Test name
Test status
Simulation time 38280268 ps
CPU time 0.59 seconds
Started Jul 05 05:21:56 PM PDT 24
Finished Jul 05 05:21:57 PM PDT 24
Peak memory 195204 kb
Host smart-38dd4792-60ae-4a3a-9d6a-555f8ae2da46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289501263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1289501263
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1278785706
Short name T127
Test name
Test status
Simulation time 157346012 ps
CPU time 1.1 seconds
Started Jul 05 05:21:57 PM PDT 24
Finished Jul 05 05:21:59 PM PDT 24
Peak memory 200048 kb
Host smart-17157815-e0fe-4112-808a-d1f41fa54630
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278785706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1278785706
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3561488027
Short name T552
Test name
Test status
Simulation time 222903319 ps
CPU time 3.34 seconds
Started Jul 05 05:21:51 PM PDT 24
Finished Jul 05 05:21:55 PM PDT 24
Peak memory 200308 kb
Host smart-1a6011f4-3864-432f-a576-8c81ab9ccf15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561488027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3561488027
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3992980223
Short name T67
Test name
Test status
Simulation time 86329661 ps
CPU time 1.9 seconds
Started Jul 05 05:21:59 PM PDT 24
Finished Jul 05 05:22:01 PM PDT 24
Peak memory 200344 kb
Host smart-78776002-55e5-42af-a526-9bf646c4ffed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992980223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3992980223
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.3348185763
Short name T591
Test name
Test status
Simulation time 29538384 ps
CPU time 0.59 seconds
Started Jul 05 05:22:45 PM PDT 24
Finished Jul 05 05:22:46 PM PDT 24
Peak memory 195196 kb
Host smart-a2daacf0-2b7c-4cf0-9474-fcd143d5d6ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348185763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.3348185763
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1312864284
Short name T628
Test name
Test status
Simulation time 32039587 ps
CPU time 0.59 seconds
Started Jul 05 05:22:46 PM PDT 24
Finished Jul 05 05:22:47 PM PDT 24
Peak memory 195212 kb
Host smart-d5c7f1dc-2ec2-4bb2-bb48-08ff2aa3d69f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312864284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1312864284
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.579610431
Short name T583
Test name
Test status
Simulation time 13465369 ps
CPU time 0.61 seconds
Started Jul 05 05:22:47 PM PDT 24
Finished Jul 05 05:22:48 PM PDT 24
Peak memory 195292 kb
Host smart-e80d9214-111f-4844-a8a2-184a9d01dcb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579610431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.579610431
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.642453246
Short name T604
Test name
Test status
Simulation time 99881209 ps
CPU time 0.59 seconds
Started Jul 05 05:22:43 PM PDT 24
Finished Jul 05 05:22:44 PM PDT 24
Peak memory 195556 kb
Host smart-596f0f4b-31e5-4f39-a0f5-9560d2194945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642453246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.642453246
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2010865588
Short name T553
Test name
Test status
Simulation time 48964906 ps
CPU time 0.63 seconds
Started Jul 05 05:23:12 PM PDT 24
Finished Jul 05 05:23:13 PM PDT 24
Peak memory 195212 kb
Host smart-50cab2b9-90da-4640-86d3-537c329dc86c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010865588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2010865588
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2828017784
Short name T530
Test name
Test status
Simulation time 83610908 ps
CPU time 0.68 seconds
Started Jul 05 05:23:12 PM PDT 24
Finished Jul 05 05:23:13 PM PDT 24
Peak memory 195144 kb
Host smart-5f1e3860-0b30-40bc-91ae-2725b5548a69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828017784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2828017784
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.316321012
Short name T609
Test name
Test status
Simulation time 18082324 ps
CPU time 0.63 seconds
Started Jul 05 05:23:12 PM PDT 24
Finished Jul 05 05:23:13 PM PDT 24
Peak memory 195232 kb
Host smart-a19e22f2-468a-4614-b4b2-a67377d6fcfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316321012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.316321012
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.965698883
Short name T550
Test name
Test status
Simulation time 22040520 ps
CPU time 0.6 seconds
Started Jul 05 05:22:59 PM PDT 24
Finished Jul 05 05:23:00 PM PDT 24
Peak memory 195204 kb
Host smart-028e9eeb-ed8b-49f0-b307-1a7689be3016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965698883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.965698883
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2514682441
Short name T542
Test name
Test status
Simulation time 13293324 ps
CPU time 0.6 seconds
Started Jul 05 05:22:51 PM PDT 24
Finished Jul 05 05:22:52 PM PDT 24
Peak memory 195164 kb
Host smart-790a3212-1ee2-48b7-ae2f-91d13d66243f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514682441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2514682441
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2574514259
Short name T578
Test name
Test status
Simulation time 29606097 ps
CPU time 0.55 seconds
Started Jul 05 05:22:50 PM PDT 24
Finished Jul 05 05:22:51 PM PDT 24
Peak memory 195100 kb
Host smart-20ace1e8-402e-4064-8b18-93ac9779fe0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574514259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2574514259
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3986189700
Short name T627
Test name
Test status
Simulation time 202280032 ps
CPU time 3.21 seconds
Started Jul 05 05:22:04 PM PDT 24
Finished Jul 05 05:22:08 PM PDT 24
Peak memory 200008 kb
Host smart-48781e30-ac48-4625-a8ba-2a50d4a088b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986189700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3986189700
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3535076455
Short name T651
Test name
Test status
Simulation time 6423053812 ps
CPU time 10.45 seconds
Started Jul 05 05:22:04 PM PDT 24
Finished Jul 05 05:22:16 PM PDT 24
Peak memory 199672 kb
Host smart-9df561e3-bdb9-4a73-b1e9-7500a25be090
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535076455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3535076455
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.4219557297
Short name T625
Test name
Test status
Simulation time 36722672 ps
CPU time 0.85 seconds
Started Jul 05 05:22:06 PM PDT 24
Finished Jul 05 05:22:08 PM PDT 24
Peak memory 199356 kb
Host smart-45bbddf8-9310-476f-ae97-a71cf842d72f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219557297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.4219557297
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1745530265
Short name T563
Test name
Test status
Simulation time 42104208 ps
CPU time 1.21 seconds
Started Jul 05 05:22:17 PM PDT 24
Finished Jul 05 05:22:19 PM PDT 24
Peak memory 200136 kb
Host smart-65a0c0cf-bcd9-4b1b-a9d4-5cc9bfca66ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745530265 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1745530265
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2866706401
Short name T114
Test name
Test status
Simulation time 55170412 ps
CPU time 0.83 seconds
Started Jul 05 05:22:05 PM PDT 24
Finished Jul 05 05:22:06 PM PDT 24
Peak memory 199748 kb
Host smart-dd7557e8-0c5d-419e-8f26-6dbac88dec4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866706401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2866706401
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1863599193
Short name T588
Test name
Test status
Simulation time 15996594 ps
CPU time 0.63 seconds
Started Jul 05 05:22:03 PM PDT 24
Finished Jul 05 05:22:04 PM PDT 24
Peak memory 195348 kb
Host smart-71b1206a-f211-41a1-a4f1-e3c4b611d484
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863599193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1863599193
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4095092361
Short name T656
Test name
Test status
Simulation time 816873973 ps
CPU time 1.79 seconds
Started Jul 05 05:22:01 PM PDT 24
Finished Jul 05 05:22:04 PM PDT 24
Peak memory 200184 kb
Host smart-c56ad7eb-6823-45b0-ab69-a68a1a719509
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095092361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.4095092361
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.983043439
Short name T579
Test name
Test status
Simulation time 82525079 ps
CPU time 1.8 seconds
Started Jul 05 05:22:03 PM PDT 24
Finished Jul 05 05:22:06 PM PDT 24
Peak memory 200240 kb
Host smart-1b391515-074e-40d2-b4e8-dc0429ee25ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983043439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.983043439
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2700299241
Short name T141
Test name
Test status
Simulation time 639525338 ps
CPU time 4.05 seconds
Started Jul 05 05:22:04 PM PDT 24
Finished Jul 05 05:22:09 PM PDT 24
Peak memory 200212 kb
Host smart-7d20b0a3-f9ba-4343-bd92-33712d9da8f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700299241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2700299241
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.4079701111
Short name T569
Test name
Test status
Simulation time 49260100 ps
CPU time 0.61 seconds
Started Jul 05 05:22:57 PM PDT 24
Finished Jul 05 05:22:58 PM PDT 24
Peak memory 195116 kb
Host smart-f9fad97b-bfc6-4605-8773-222e71a98339
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079701111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.4079701111
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.620260688
Short name T640
Test name
Test status
Simulation time 69080932 ps
CPU time 0.58 seconds
Started Jul 05 05:22:51 PM PDT 24
Finished Jul 05 05:22:52 PM PDT 24
Peak memory 195296 kb
Host smart-a9aa38be-e5d6-45e6-a941-27f6940ba27e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620260688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.620260688
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3705312274
Short name T543
Test name
Test status
Simulation time 49416707 ps
CPU time 0.63 seconds
Started Jul 05 05:22:57 PM PDT 24
Finished Jul 05 05:22:58 PM PDT 24
Peak memory 195232 kb
Host smart-2842ef33-5b70-48e9-a489-f7648f7cb09d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705312274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3705312274
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3577347650
Short name T608
Test name
Test status
Simulation time 12690539 ps
CPU time 0.6 seconds
Started Jul 05 05:22:59 PM PDT 24
Finished Jul 05 05:23:01 PM PDT 24
Peak memory 195128 kb
Host smart-1bc12ee0-3297-4563-87dd-34a11a57ad6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577347650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3577347650
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.2030401130
Short name T610
Test name
Test status
Simulation time 29570950 ps
CPU time 0.6 seconds
Started Jul 05 05:22:50 PM PDT 24
Finished Jul 05 05:22:51 PM PDT 24
Peak memory 195248 kb
Host smart-8549659e-cca4-4ec6-95dc-b9613f9d8f83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030401130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.2030401130
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1398066540
Short name T528
Test name
Test status
Simulation time 14460432 ps
CPU time 0.6 seconds
Started Jul 05 05:22:53 PM PDT 24
Finished Jul 05 05:22:54 PM PDT 24
Peak memory 195352 kb
Host smart-b7666d0c-c5fc-4292-ae7a-d2b83fd97938
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398066540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1398066540
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3402148952
Short name T650
Test name
Test status
Simulation time 14616204 ps
CPU time 0.61 seconds
Started Jul 05 05:23:00 PM PDT 24
Finished Jul 05 05:23:02 PM PDT 24
Peak memory 195208 kb
Host smart-b424bd82-41c8-48f7-b20f-f6e636084b0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402148952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3402148952
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.3106594787
Short name T644
Test name
Test status
Simulation time 58784589 ps
CPU time 0.6 seconds
Started Jul 05 05:22:52 PM PDT 24
Finished Jul 05 05:22:53 PM PDT 24
Peak memory 195212 kb
Host smart-0d2efb07-9256-4ff5-b7c3-0548fea0bce1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106594787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3106594787
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.117016521
Short name T654
Test name
Test status
Simulation time 23317221 ps
CPU time 0.57 seconds
Started Jul 05 05:22:58 PM PDT 24
Finished Jul 05 05:22:59 PM PDT 24
Peak memory 195180 kb
Host smart-17e0f67c-d09c-4ffb-97e0-02e86ea3c9d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117016521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.117016521
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3749912354
Short name T536
Test name
Test status
Simulation time 29566468 ps
CPU time 0.58 seconds
Started Jul 05 05:22:59 PM PDT 24
Finished Jul 05 05:23:00 PM PDT 24
Peak memory 195200 kb
Host smart-fb2724b5-f17f-4213-89ab-ecbc86268e76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749912354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3749912354
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2673442307
Short name T117
Test name
Test status
Simulation time 629708328 ps
CPU time 8.02 seconds
Started Jul 05 05:22:09 PM PDT 24
Finished Jul 05 05:22:18 PM PDT 24
Peak memory 200320 kb
Host smart-58496c2f-54e5-4655-a2cd-a12fd2a6c44b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673442307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2673442307
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1250184890
Short name T561
Test name
Test status
Simulation time 117343734 ps
CPU time 5.27 seconds
Started Jul 05 05:22:11 PM PDT 24
Finished Jul 05 05:22:17 PM PDT 24
Peak memory 200328 kb
Host smart-340a589b-5357-41fa-8c32-a4b9734d4245
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250184890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1250184890
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.312811176
Short name T636
Test name
Test status
Simulation time 72523149 ps
CPU time 0.98 seconds
Started Jul 05 05:22:10 PM PDT 24
Finished Jul 05 05:22:11 PM PDT 24
Peak memory 200096 kb
Host smart-ff451612-15d5-47cd-b028-148a0bd9d966
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312811176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.312811176
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1509196934
Short name T556
Test name
Test status
Simulation time 46764925 ps
CPU time 1.23 seconds
Started Jul 05 05:22:14 PM PDT 24
Finished Jul 05 05:22:16 PM PDT 24
Peak memory 200128 kb
Host smart-c8aed9fa-7906-462c-9ea9-4407faf9f425
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509196934 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1509196934
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2499850850
Short name T612
Test name
Test status
Simulation time 143631952 ps
CPU time 0.96 seconds
Started Jul 05 05:22:11 PM PDT 24
Finished Jul 05 05:22:13 PM PDT 24
Peak memory 200128 kb
Host smart-e1a5d151-64bb-4189-bdcf-5f2f0c78f99f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499850850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2499850850
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.4193661565
Short name T533
Test name
Test status
Simulation time 14934298 ps
CPU time 0.6 seconds
Started Jul 05 05:22:11 PM PDT 24
Finished Jul 05 05:22:12 PM PDT 24
Peak memory 195196 kb
Host smart-d8f16f8e-f069-480f-a2f9-695710abcb9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193661565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.4193661565
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.722050627
Short name T617
Test name
Test status
Simulation time 58042730 ps
CPU time 1.16 seconds
Started Jul 05 05:22:08 PM PDT 24
Finished Jul 05 05:22:10 PM PDT 24
Peak memory 200160 kb
Host smart-aa8894ce-e133-43c9-80aa-4f59d46a50c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722050627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_
outstanding.722050627
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1421933281
Short name T565
Test name
Test status
Simulation time 58823662 ps
CPU time 3.19 seconds
Started Jul 05 05:22:06 PM PDT 24
Finished Jul 05 05:22:10 PM PDT 24
Peak memory 200332 kb
Host smart-7ecfe5b0-e73a-4c6b-b179-aca3e49cc5a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421933281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1421933281
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2583926861
Short name T616
Test name
Test status
Simulation time 153964135 ps
CPU time 1.84 seconds
Started Jul 05 05:22:05 PM PDT 24
Finished Jul 05 05:22:07 PM PDT 24
Peak memory 200236 kb
Host smart-63b9a239-68e3-43bf-b883-1017b8ce9844
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583926861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2583926861
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3939965722
Short name T532
Test name
Test status
Simulation time 33061044 ps
CPU time 0.63 seconds
Started Jul 05 05:22:52 PM PDT 24
Finished Jul 05 05:22:53 PM PDT 24
Peak memory 195160 kb
Host smart-4ebe7dd1-9370-425b-9e4c-8021049697f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939965722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3939965722
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2739345554
Short name T590
Test name
Test status
Simulation time 36147494 ps
CPU time 0.62 seconds
Started Jul 05 05:22:52 PM PDT 24
Finished Jul 05 05:22:53 PM PDT 24
Peak memory 195316 kb
Host smart-ac2d156c-32e7-41d6-a0b6-cd0f310e7e40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739345554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2739345554
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1472579415
Short name T564
Test name
Test status
Simulation time 39556390 ps
CPU time 0.6 seconds
Started Jul 05 05:22:50 PM PDT 24
Finished Jul 05 05:22:51 PM PDT 24
Peak memory 195224 kb
Host smart-1e6c08e8-3fb3-45d4-a885-c9a86d0cabd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472579415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1472579415
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2758025956
Short name T541
Test name
Test status
Simulation time 15286607 ps
CPU time 0.6 seconds
Started Jul 05 05:22:59 PM PDT 24
Finished Jul 05 05:23:01 PM PDT 24
Peak memory 195116 kb
Host smart-8b51cb0d-d109-42a3-804e-b288ef4e0383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758025956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2758025956
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2109759263
Short name T638
Test name
Test status
Simulation time 24151200 ps
CPU time 0.64 seconds
Started Jul 05 05:23:00 PM PDT 24
Finished Jul 05 05:23:02 PM PDT 24
Peak memory 195368 kb
Host smart-899a850f-ee65-49a7-a6d1-d4626c3bc008
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109759263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2109759263
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.902800769
Short name T595
Test name
Test status
Simulation time 14405916 ps
CPU time 0.62 seconds
Started Jul 05 05:23:01 PM PDT 24
Finished Jul 05 05:23:02 PM PDT 24
Peak memory 195152 kb
Host smart-ca9f582e-c448-4652-a162-87f7db2259fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902800769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.902800769
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1107933112
Short name T551
Test name
Test status
Simulation time 43169084 ps
CPU time 0.58 seconds
Started Jul 05 05:23:00 PM PDT 24
Finished Jul 05 05:23:02 PM PDT 24
Peak memory 195168 kb
Host smart-4b128208-e1c9-4ffb-8b3f-4e06ce438107
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107933112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1107933112
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.4197247825
Short name T529
Test name
Test status
Simulation time 15611561 ps
CPU time 0.62 seconds
Started Jul 05 05:22:58 PM PDT 24
Finished Jul 05 05:23:00 PM PDT 24
Peak memory 195236 kb
Host smart-69fe90c9-b4b9-4a5e-9a63-fa94ba004c08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197247825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.4197247825
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1917387414
Short name T544
Test name
Test status
Simulation time 69693754 ps
CPU time 0.61 seconds
Started Jul 05 05:23:00 PM PDT 24
Finished Jul 05 05:23:02 PM PDT 24
Peak memory 195256 kb
Host smart-8547cc62-e4a9-4aaa-8d78-e7ca8006b7e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917387414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1917387414
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1740968945
Short name T637
Test name
Test status
Simulation time 14739509 ps
CPU time 0.63 seconds
Started Jul 05 05:22:58 PM PDT 24
Finished Jul 05 05:23:00 PM PDT 24
Peak memory 195360 kb
Host smart-e5332a20-59de-4344-9488-60df69d32a88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740968945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1740968945
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2887663462
Short name T580
Test name
Test status
Simulation time 50073661312 ps
CPU time 736.68 seconds
Started Jul 05 05:22:11 PM PDT 24
Finished Jul 05 05:34:28 PM PDT 24
Peak memory 216844 kb
Host smart-3925eec8-8ccd-42ff-bc0c-fbace5b45eed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887663462 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2887663462
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2413451366
Short name T606
Test name
Test status
Simulation time 19572754 ps
CPU time 0.95 seconds
Started Jul 05 05:22:11 PM PDT 24
Finished Jul 05 05:22:13 PM PDT 24
Peak memory 199964 kb
Host smart-72aefc38-9c86-4902-bab8-da0f64d39d08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413451366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2413451366
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2920326667
Short name T576
Test name
Test status
Simulation time 41376119 ps
CPU time 0.61 seconds
Started Jul 05 05:22:11 PM PDT 24
Finished Jul 05 05:22:12 PM PDT 24
Peak memory 195232 kb
Host smart-af86b4d0-c0ed-4c66-954f-35a36618cb76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920326667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2920326667
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3761554461
Short name T594
Test name
Test status
Simulation time 188940556 ps
CPU time 1.27 seconds
Started Jul 05 05:22:11 PM PDT 24
Finished Jul 05 05:22:12 PM PDT 24
Peak memory 199768 kb
Host smart-53f9f8c0-b2b6-4bff-9fc9-3ad9d28924de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761554461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3761554461
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.607990936
Short name T613
Test name
Test status
Simulation time 542804334 ps
CPU time 2.44 seconds
Started Jul 05 05:22:10 PM PDT 24
Finished Jul 05 05:22:13 PM PDT 24
Peak memory 200188 kb
Host smart-3c34cade-8a2f-4eb4-b937-27fa8c2b5881
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607990936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.607990936
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3194466615
Short name T147
Test name
Test status
Simulation time 58085171 ps
CPU time 1.87 seconds
Started Jul 05 05:22:13 PM PDT 24
Finished Jul 05 05:22:15 PM PDT 24
Peak memory 200300 kb
Host smart-1d325e75-6bec-48f6-8f75-dc048284c02d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194466615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3194466615
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.688008442
Short name T558
Test name
Test status
Simulation time 96799559 ps
CPU time 3.43 seconds
Started Jul 05 05:22:19 PM PDT 24
Finished Jul 05 05:22:23 PM PDT 24
Peak memory 215768 kb
Host smart-32384214-6e30-4cce-926e-fadda53961a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688008442 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.688008442
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1055257041
Short name T120
Test name
Test status
Simulation time 56053003 ps
CPU time 0.82 seconds
Started Jul 05 05:22:19 PM PDT 24
Finished Jul 05 05:22:21 PM PDT 24
Peak memory 199984 kb
Host smart-72cd3d86-0f1c-445c-946e-7b230598dd85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055257041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1055257041
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.378495931
Short name T632
Test name
Test status
Simulation time 29427793 ps
CPU time 0.62 seconds
Started Jul 05 05:22:20 PM PDT 24
Finished Jul 05 05:22:21 PM PDT 24
Peak memory 195332 kb
Host smart-39289e1f-0d49-4839-8aaa-8efb0b85b4e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378495931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.378495931
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1515113148
Short name T655
Test name
Test status
Simulation time 45273229 ps
CPU time 1.16 seconds
Started Jul 05 05:22:19 PM PDT 24
Finished Jul 05 05:22:21 PM PDT 24
Peak memory 198660 kb
Host smart-af9c09e0-7287-473e-87b8-5895d7d56cf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515113148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1515113148
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.233554779
Short name T545
Test name
Test status
Simulation time 1185397073 ps
CPU time 2.35 seconds
Started Jul 05 05:22:20 PM PDT 24
Finished Jul 05 05:22:23 PM PDT 24
Peak memory 200284 kb
Host smart-8d454ea9-4dc9-4a6a-876d-4a1550ecd540
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233554779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.233554779
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1773506156
Short name T145
Test name
Test status
Simulation time 232376149 ps
CPU time 4.39 seconds
Started Jul 05 05:22:20 PM PDT 24
Finished Jul 05 05:22:26 PM PDT 24
Peak memory 200296 kb
Host smart-f5b317e7-68d7-439e-9dca-1b728bc0f04c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773506156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1773506156
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2715206418
Short name T566
Test name
Test status
Simulation time 36467100 ps
CPU time 1.19 seconds
Started Jul 05 05:22:19 PM PDT 24
Finished Jul 05 05:22:22 PM PDT 24
Peak memory 200196 kb
Host smart-f3346583-cae5-470d-bc92-a2e05f06ba9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715206418 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2715206418
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3375732849
Short name T634
Test name
Test status
Simulation time 17819833 ps
CPU time 0.71 seconds
Started Jul 05 05:22:19 PM PDT 24
Finished Jul 05 05:22:20 PM PDT 24
Peak memory 198148 kb
Host smart-ebbe7e34-baee-43c8-86e0-7b93bf49d2d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375732849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3375732849
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1233707613
Short name T653
Test name
Test status
Simulation time 11106719 ps
CPU time 0.63 seconds
Started Jul 05 05:22:19 PM PDT 24
Finished Jul 05 05:22:20 PM PDT 24
Peak memory 195196 kb
Host smart-e3bdf815-dd97-4bf4-be6b-88aef2099a19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233707613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1233707613
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2853986993
Short name T546
Test name
Test status
Simulation time 146557959 ps
CPU time 2.31 seconds
Started Jul 05 05:22:18 PM PDT 24
Finished Jul 05 05:22:21 PM PDT 24
Peak memory 200360 kb
Host smart-717d22f7-bbe0-4d91-aa8d-98d1bdbe8743
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853986993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2853986993
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3595346948
Short name T538
Test name
Test status
Simulation time 249553845 ps
CPU time 2.31 seconds
Started Jul 05 05:22:17 PM PDT 24
Finished Jul 05 05:22:20 PM PDT 24
Peak memory 200320 kb
Host smart-4b1c6030-a3e6-4c55-80f4-4b107f64506e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595346948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3595346948
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3294418771
Short name T585
Test name
Test status
Simulation time 7164708430 ps
CPU time 98.55 seconds
Started Jul 05 05:22:25 PM PDT 24
Finished Jul 05 05:24:05 PM PDT 24
Peak memory 216144 kb
Host smart-7efa133c-3819-48b4-b736-b4be83766256
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294418771 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3294418771
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.346015416
Short name T121
Test name
Test status
Simulation time 35000207 ps
CPU time 0.97 seconds
Started Jul 05 05:22:27 PM PDT 24
Finished Jul 05 05:22:28 PM PDT 24
Peak memory 199788 kb
Host smart-451b94e0-7f30-4b45-9054-7faef16649ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346015416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.346015416
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3505564342
Short name T602
Test name
Test status
Simulation time 36823295 ps
CPU time 0.58 seconds
Started Jul 05 05:22:17 PM PDT 24
Finished Jul 05 05:22:19 PM PDT 24
Peak memory 195188 kb
Host smart-b7e656b9-ceba-4c75-b538-80cfb14f8050
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505564342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3505564342
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1788200695
Short name T575
Test name
Test status
Simulation time 149214273 ps
CPU time 2.39 seconds
Started Jul 05 05:22:25 PM PDT 24
Finished Jul 05 05:22:28 PM PDT 24
Peak memory 200308 kb
Host smart-27f847d4-9dfc-44ca-9487-c53cef6588fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788200695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1788200695
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3100574915
Short name T657
Test name
Test status
Simulation time 65122630 ps
CPU time 1.5 seconds
Started Jul 05 05:22:19 PM PDT 24
Finished Jul 05 05:22:21 PM PDT 24
Peak memory 200316 kb
Host smart-b9bcadf2-b84a-4499-98fa-93e92c7bd031
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100574915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3100574915
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.4289736648
Short name T621
Test name
Test status
Simulation time 103584651 ps
CPU time 2.88 seconds
Started Jul 05 05:22:19 PM PDT 24
Finished Jul 05 05:22:23 PM PDT 24
Peak memory 200284 kb
Host smart-05221cba-190d-4511-b495-73dd2bf5060f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289736648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.4289736648
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3497024034
Short name T649
Test name
Test status
Simulation time 42956428 ps
CPU time 1.29 seconds
Started Jul 05 05:22:26 PM PDT 24
Finished Jul 05 05:22:28 PM PDT 24
Peak memory 200368 kb
Host smart-03741df1-ebbc-4176-bc7c-9585c944b260
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497024034 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3497024034
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2897315835
Short name T118
Test name
Test status
Simulation time 141864958 ps
CPU time 0.82 seconds
Started Jul 05 05:22:25 PM PDT 24
Finished Jul 05 05:22:27 PM PDT 24
Peak memory 200076 kb
Host smart-cebab6af-ecd5-44bf-825c-9a1c38e805f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897315835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2897315835
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3243431503
Short name T539
Test name
Test status
Simulation time 71894916 ps
CPU time 0.65 seconds
Started Jul 05 05:22:24 PM PDT 24
Finished Jul 05 05:22:25 PM PDT 24
Peak memory 195196 kb
Host smart-b9c7b691-7a26-4b05-9dd0-411f630dc909
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243431503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3243431503
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2795924252
Short name T647
Test name
Test status
Simulation time 36301579 ps
CPU time 1.63 seconds
Started Jul 05 05:22:25 PM PDT 24
Finished Jul 05 05:22:28 PM PDT 24
Peak memory 200292 kb
Host smart-916a07fb-ceec-4347-807c-c5c1d0e4fe0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795924252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2795924252
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2347787936
Short name T547
Test name
Test status
Simulation time 90123852 ps
CPU time 2.33 seconds
Started Jul 05 05:22:26 PM PDT 24
Finished Jul 05 05:22:29 PM PDT 24
Peak memory 200252 kb
Host smart-3bed1001-a472-4b8a-8c0e-7daa81f813ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347787936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2347787936
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1082271263
Short name T140
Test name
Test status
Simulation time 184200358 ps
CPU time 2.93 seconds
Started Jul 05 05:22:25 PM PDT 24
Finished Jul 05 05:22:29 PM PDT 24
Peak memory 200200 kb
Host smart-bad3e22c-382f-4f55-baf2-081fac8912ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082271263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1082271263
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3669178537
Short name T304
Test name
Test status
Simulation time 71071855 ps
CPU time 0.61 seconds
Started Jul 05 05:45:22 PM PDT 24
Finished Jul 05 05:45:23 PM PDT 24
Peak memory 196816 kb
Host smart-19f815a5-685f-49b6-96a0-97b131488008
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669178537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3669178537
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2065122577
Short name T350
Test name
Test status
Simulation time 932628559 ps
CPU time 13.11 seconds
Started Jul 05 05:45:20 PM PDT 24
Finished Jul 05 05:45:34 PM PDT 24
Peak memory 200352 kb
Host smart-a93aba0e-559b-42ba-adbb-91390792e1e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2065122577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2065122577
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.526559419
Short name T473
Test name
Test status
Simulation time 2051689939 ps
CPU time 25.52 seconds
Started Jul 05 05:45:17 PM PDT 24
Finished Jul 05 05:45:43 PM PDT 24
Peak memory 200320 kb
Host smart-958df38f-7648-4722-966f-916ed1c1c8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526559419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.526559419
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.3120115190
Short name T335
Test name
Test status
Simulation time 77114441663 ps
CPU time 1563.9 seconds
Started Jul 05 05:45:21 PM PDT 24
Finished Jul 05 06:11:25 PM PDT 24
Peak memory 781832 kb
Host smart-6eefdbcf-9b73-4021-8d89-e0d12f1ba137
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3120115190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.3120115190
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1699057501
Short name T76
Test name
Test status
Simulation time 19296998243 ps
CPU time 118.48 seconds
Started Jul 05 05:45:17 PM PDT 24
Finished Jul 05 05:47:17 PM PDT 24
Peak memory 200360 kb
Host smart-31a93030-9806-4c62-9141-d41a88f9325a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699057501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1699057501
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3998254433
Short name T45
Test name
Test status
Simulation time 44165885820 ps
CPU time 123.92 seconds
Started Jul 05 05:45:20 PM PDT 24
Finished Jul 05 05:47:25 PM PDT 24
Peak memory 216692 kb
Host smart-161e5576-7c03-48f7-9ba7-344a816c8793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998254433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3998254433
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1722259606
Short name T62
Test name
Test status
Simulation time 75849850 ps
CPU time 0.98 seconds
Started Jul 05 05:45:17 PM PDT 24
Finished Jul 05 05:45:18 PM PDT 24
Peak memory 218304 kb
Host smart-ee26056d-c373-4b3c-a29c-f0eb342a8070
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722259606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1722259606
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.1603069897
Short name T362
Test name
Test status
Simulation time 1266839353 ps
CPU time 14.15 seconds
Started Jul 05 05:45:17 PM PDT 24
Finished Jul 05 05:45:32 PM PDT 24
Peak memory 200328 kb
Host smart-1fb61e00-cfb6-449e-b9bb-66565feda22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603069897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1603069897
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.295187724
Short name T87
Test name
Test status
Simulation time 57128650308 ps
CPU time 1134.64 seconds
Started Jul 05 05:45:20 PM PDT 24
Finished Jul 05 06:04:15 PM PDT 24
Peak memory 715392 kb
Host smart-a579841e-8651-4d1f-b500-e335e0ec5184
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295187724 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.295187724
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.4105026726
Short name T69
Test name
Test status
Simulation time 46755021688 ps
CPU time 3137.1 seconds
Started Jul 05 05:45:18 PM PDT 24
Finished Jul 05 06:37:36 PM PDT 24
Peak memory 755744 kb
Host smart-b26dd09a-0ca1-44ad-82b4-c1cc454fa43e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4105026726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.4105026726
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.3825282674
Short name T157
Test name
Test status
Simulation time 25697441346 ps
CPU time 64.54 seconds
Started Jul 05 05:45:22 PM PDT 24
Finished Jul 05 05:46:27 PM PDT 24
Peak memory 200304 kb
Host smart-1023ab4c-0188-4674-a9dd-577d36b9056c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3825282674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3825282674
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.3443885497
Short name T302
Test name
Test status
Simulation time 47677928402 ps
CPU time 60.97 seconds
Started Jul 05 05:45:20 PM PDT 24
Finished Jul 05 05:46:22 PM PDT 24
Peak memory 200368 kb
Host smart-f088e3e1-52cf-427a-bf00-b348ca0652f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3443885497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.3443885497
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.2971519989
Short name T480
Test name
Test status
Simulation time 11374890911 ps
CPU time 127.07 seconds
Started Jul 05 05:45:14 PM PDT 24
Finished Jul 05 05:47:21 PM PDT 24
Peak memory 200392 kb
Host smart-43ee1e77-2a49-49a5-87b5-a1a15f340104
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2971519989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.2971519989
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3202111887
Short name T317
Test name
Test status
Simulation time 75396045765 ps
CPU time 627.9 seconds
Started Jul 05 05:45:20 PM PDT 24
Finished Jul 05 05:55:48 PM PDT 24
Peak memory 200372 kb
Host smart-187d2270-530a-4c61-b37a-020f11a6b958
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3202111887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3202111887
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.3489179108
Short name T521
Test name
Test status
Simulation time 156742611801 ps
CPU time 2317.7 seconds
Started Jul 05 05:45:22 PM PDT 24
Finished Jul 05 06:24:00 PM PDT 24
Peak memory 216820 kb
Host smart-6ddc62cf-287a-40ff-917a-d8558d9f846a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3489179108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.3489179108
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.60325028
Short name T503
Test name
Test status
Simulation time 2183320601 ps
CPU time 46.56 seconds
Started Jul 05 05:45:18 PM PDT 24
Finished Jul 05 05:46:05 PM PDT 24
Peak memory 200412 kb
Host smart-7a99c612-5be2-4f31-bbe3-6396918af44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60325028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.60325028
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.4232523889
Short name T261
Test name
Test status
Simulation time 25758266 ps
CPU time 0.61 seconds
Started Jul 05 05:45:30 PM PDT 24
Finished Jul 05 05:45:31 PM PDT 24
Peak memory 195140 kb
Host smart-601f87dd-2ae6-4669-bce7-5db2288fc949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232523889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.4232523889
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2257750262
Short name T190
Test name
Test status
Simulation time 1205676045 ps
CPU time 68.3 seconds
Started Jul 05 05:45:18 PM PDT 24
Finished Jul 05 05:46:27 PM PDT 24
Peak memory 200236 kb
Host smart-c6d4fc9d-9134-47d1-9d93-d9a16ebb8d7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2257750262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2257750262
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.212168959
Short name T371
Test name
Test status
Simulation time 4454414678 ps
CPU time 825.38 seconds
Started Jul 05 05:45:15 PM PDT 24
Finished Jul 05 05:59:01 PM PDT 24
Peak memory 707352 kb
Host smart-1c65ab04-252c-4d6b-94f9-2f6f900d8392
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=212168959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.212168959
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3138532205
Short name T313
Test name
Test status
Simulation time 10824047476 ps
CPU time 79.52 seconds
Started Jul 05 05:45:17 PM PDT 24
Finished Jul 05 05:46:38 PM PDT 24
Peak memory 200240 kb
Host smart-86fe0d12-c236-4f55-b20c-aa5aa31e7307
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138532205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3138532205
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1658409302
Short name T252
Test name
Test status
Simulation time 6587118605 ps
CPU time 119.39 seconds
Started Jul 05 05:45:20 PM PDT 24
Finished Jul 05 05:47:20 PM PDT 24
Peak memory 200344 kb
Host smart-c24502ab-5ea9-4b7c-8f9d-c4790e393443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658409302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1658409302
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.4014468034
Short name T63
Test name
Test status
Simulation time 55323048 ps
CPU time 0.89 seconds
Started Jul 05 05:45:23 PM PDT 24
Finished Jul 05 05:45:24 PM PDT 24
Peak memory 218320 kb
Host smart-6c94704e-5eb9-40d0-a4e0-0cccdb449837
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014468034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.4014468034
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1635755981
Short name T394
Test name
Test status
Simulation time 219386493 ps
CPU time 5.32 seconds
Started Jul 05 05:45:19 PM PDT 24
Finished Jul 05 05:45:24 PM PDT 24
Peak memory 200300 kb
Host smart-cedf2e48-956c-4907-bd5d-08ac5c487869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635755981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1635755981
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.523875089
Short name T374
Test name
Test status
Simulation time 11985386688 ps
CPU time 468.49 seconds
Started Jul 05 05:45:27 PM PDT 24
Finished Jul 05 05:53:16 PM PDT 24
Peak memory 461604 kb
Host smart-b23e309b-0c7d-45a1-bea1-65dd72009c26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523875089 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.523875089
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.2132001954
Short name T13
Test name
Test status
Simulation time 28511186958 ps
CPU time 553.05 seconds
Started Jul 05 05:45:26 PM PDT 24
Finished Jul 05 05:54:39 PM PDT 24
Peak memory 208636 kb
Host smart-0942e13d-ada2-40ae-ab34-1d0aa84f75d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2132001954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.2132001954
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.3991339324
Short name T492
Test name
Test status
Simulation time 8679485371 ps
CPU time 68.38 seconds
Started Jul 05 05:45:28 PM PDT 24
Finished Jul 05 05:46:37 PM PDT 24
Peak memory 200380 kb
Host smart-30997354-a12e-4449-b51f-74db3688991d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3991339324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.3991339324
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.3949313123
Short name T412
Test name
Test status
Simulation time 11964274195 ps
CPU time 94.72 seconds
Started Jul 05 05:45:26 PM PDT 24
Finished Jul 05 05:47:01 PM PDT 24
Peak memory 200372 kb
Host smart-17f25736-fe7f-4f6d-82d2-4c2827138698
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3949313123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.3949313123
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.1399912316
Short name T363
Test name
Test status
Simulation time 111111683461 ps
CPU time 86.22 seconds
Started Jul 05 05:45:26 PM PDT 24
Finished Jul 05 05:46:53 PM PDT 24
Peak memory 200380 kb
Host smart-0d1d9442-5a5b-4253-94fa-d300fa64931a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1399912316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.1399912316
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1534482896
Short name T515
Test name
Test status
Simulation time 10212205284 ps
CPU time 547.1 seconds
Started Jul 05 05:45:16 PM PDT 24
Finished Jul 05 05:54:24 PM PDT 24
Peak memory 200376 kb
Host smart-5a1e369c-da8a-44b3-96fa-ff831b0a9a66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1534482896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1534482896
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.1172739044
Short name T475
Test name
Test status
Simulation time 753918281350 ps
CPU time 2637.33 seconds
Started Jul 05 05:50:49 PM PDT 24
Finished Jul 05 06:34:49 PM PDT 24
Peak memory 216164 kb
Host smart-2f7101c3-6efa-4934-9340-5e5521f42159
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1172739044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.1172739044
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.3134064731
Short name T240
Test name
Test status
Simulation time 566155955110 ps
CPU time 2390.51 seconds
Started Jul 05 05:45:26 PM PDT 24
Finished Jul 05 06:25:17 PM PDT 24
Peak memory 215988 kb
Host smart-f353823c-5909-4fb1-b0e1-b2a44414401a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3134064731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.3134064731
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3831647401
Short name T514
Test name
Test status
Simulation time 1361480116 ps
CPU time 18.7 seconds
Started Jul 05 05:45:20 PM PDT 24
Finished Jul 05 05:45:39 PM PDT 24
Peak memory 200320 kb
Host smart-bf7f77f0-4e5c-49a6-8371-d84f0ea5bcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831647401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3831647401
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.4055269374
Short name T22
Test name
Test status
Simulation time 4582623772 ps
CPU time 58.99 seconds
Started Jul 05 05:45:59 PM PDT 24
Finished Jul 05 05:46:59 PM PDT 24
Peak memory 208580 kb
Host smart-f2d73dec-7212-4858-87c7-846cefb192de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4055269374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.4055269374
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.887670504
Short name T155
Test name
Test status
Simulation time 115601535 ps
CPU time 5.95 seconds
Started Jul 05 05:45:52 PM PDT 24
Finished Jul 05 05:45:59 PM PDT 24
Peak memory 200304 kb
Host smart-aae3ebb5-6565-4e50-9e29-c8929886c223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887670504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.887670504
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.110149743
Short name T246
Test name
Test status
Simulation time 717925809 ps
CPU time 119.71 seconds
Started Jul 05 05:45:54 PM PDT 24
Finished Jul 05 05:47:55 PM PDT 24
Peak memory 434744 kb
Host smart-79fdd2f2-658f-48d0-a16f-d0291e3dc226
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=110149743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.110149743
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3604757082
Short name T469
Test name
Test status
Simulation time 2763131880 ps
CPU time 147.42 seconds
Started Jul 05 05:46:01 PM PDT 24
Finished Jul 05 05:48:30 PM PDT 24
Peak memory 200360 kb
Host smart-d4adbfe0-0bd6-451a-be2d-7224b044a1f8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604757082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3604757082
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2166403025
Short name T483
Test name
Test status
Simulation time 17776502986 ps
CPU time 62.11 seconds
Started Jul 05 05:45:53 PM PDT 24
Finished Jul 05 05:46:56 PM PDT 24
Peak memory 200356 kb
Host smart-e0193e9a-9119-4548-992f-ae9cac6e2566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166403025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2166403025
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1258105226
Short name T286
Test name
Test status
Simulation time 255221486 ps
CPU time 11.44 seconds
Started Jul 05 05:45:53 PM PDT 24
Finished Jul 05 05:46:05 PM PDT 24
Peak memory 200368 kb
Host smart-23ab215b-cbf0-4a46-8fa6-6ea92c448e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258105226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1258105226
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3281279167
Short name T456
Test name
Test status
Simulation time 19957880250 ps
CPU time 523.57 seconds
Started Jul 05 05:45:51 PM PDT 24
Finished Jul 05 05:54:35 PM PDT 24
Peak memory 465828 kb
Host smart-8195d359-77d6-4094-89be-c9383fe516b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281279167 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3281279167
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2585328227
Short name T448
Test name
Test status
Simulation time 999887635 ps
CPU time 38.9 seconds
Started Jul 05 05:45:50 PM PDT 24
Finished Jul 05 05:46:29 PM PDT 24
Peak memory 200336 kb
Host smart-c0559ec6-2966-498b-a21d-d1deb63f99cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585328227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2585328227
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2500169644
Short name T310
Test name
Test status
Simulation time 38819580 ps
CPU time 0.57 seconds
Started Jul 05 05:45:59 PM PDT 24
Finished Jul 05 05:46:01 PM PDT 24
Peak memory 195800 kb
Host smart-4f3da178-a6fe-4f24-a135-5828e6ec688c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500169644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2500169644
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.908430916
Short name T221
Test name
Test status
Simulation time 509830609 ps
CPU time 23.76 seconds
Started Jul 05 05:45:55 PM PDT 24
Finished Jul 05 05:46:19 PM PDT 24
Peak memory 200340 kb
Host smart-4e9828b6-8e38-4681-adf4-ece1140c12ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=908430916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.908430916
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.4071889177
Short name T333
Test name
Test status
Simulation time 3057145711 ps
CPU time 42.43 seconds
Started Jul 05 05:45:54 PM PDT 24
Finished Jul 05 05:46:37 PM PDT 24
Peak memory 200332 kb
Host smart-1577ce7d-7146-40eb-8cd1-e9a5c74cf3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071889177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.4071889177
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3336783113
Short name T269
Test name
Test status
Simulation time 9976031513 ps
CPU time 416.28 seconds
Started Jul 05 05:45:55 PM PDT 24
Finished Jul 05 05:52:52 PM PDT 24
Peak memory 689988 kb
Host smart-169acc44-2e76-4ee9-bfca-6675ca48ed23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3336783113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3336783113
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2904736119
Short name T288
Test name
Test status
Simulation time 126574288689 ps
CPU time 195.42 seconds
Started Jul 05 05:45:56 PM PDT 24
Finished Jul 05 05:49:12 PM PDT 24
Peak memory 200136 kb
Host smart-03d35141-0c76-4782-824d-695cca0c1c23
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904736119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2904736119
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.470530269
Short name T197
Test name
Test status
Simulation time 47142708541 ps
CPU time 137.98 seconds
Started Jul 05 05:46:01 PM PDT 24
Finished Jul 05 05:48:20 PM PDT 24
Peak memory 200528 kb
Host smart-b91c559c-c5b8-4854-9665-4c6dec33eafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470530269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.470530269
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1094177190
Short name T505
Test name
Test status
Simulation time 1785021132 ps
CPU time 7.86 seconds
Started Jul 05 05:45:51 PM PDT 24
Finished Jul 05 05:46:00 PM PDT 24
Peak memory 200364 kb
Host smart-a9ace52a-2af3-4ba3-b7c3-e786ecbb0241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094177190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1094177190
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2603990615
Short name T14
Test name
Test status
Simulation time 20022231854 ps
CPU time 100.17 seconds
Started Jul 05 05:45:53 PM PDT 24
Finished Jul 05 05:47:34 PM PDT 24
Peak memory 200656 kb
Host smart-d19be2dc-bd9f-48ab-8e3c-5789a63f82d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603990615 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2603990615
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.4167598612
Short name T449
Test name
Test status
Simulation time 10524490271 ps
CPU time 73.8 seconds
Started Jul 05 05:45:57 PM PDT 24
Finished Jul 05 05:47:11 PM PDT 24
Peak memory 200384 kb
Host smart-9658b1fc-7f1c-4666-a89c-a3ea9e5811d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167598612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.4167598612
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2701034880
Short name T259
Test name
Test status
Simulation time 13954989 ps
CPU time 0.56 seconds
Started Jul 05 05:45:58 PM PDT 24
Finished Jul 05 05:45:59 PM PDT 24
Peak memory 195068 kb
Host smart-da814ef3-81a8-4d72-85fd-f86a43e55e46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701034880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2701034880
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3049992213
Short name T312
Test name
Test status
Simulation time 300249596 ps
CPU time 17.99 seconds
Started Jul 05 05:45:55 PM PDT 24
Finished Jul 05 05:46:13 PM PDT 24
Peak memory 199932 kb
Host smart-a3945b41-7c40-4a44-bfab-f514e5a478d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3049992213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3049992213
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2658308288
Short name T500
Test name
Test status
Simulation time 281884383 ps
CPU time 7.46 seconds
Started Jul 05 05:45:55 PM PDT 24
Finished Jul 05 05:46:03 PM PDT 24
Peak memory 200312 kb
Host smart-aac33f93-057b-4f42-b612-f0a8b7739ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658308288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2658308288
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3393093661
Short name T139
Test name
Test status
Simulation time 1629615405 ps
CPU time 244.45 seconds
Started Jul 05 05:45:59 PM PDT 24
Finished Jul 05 05:50:05 PM PDT 24
Peak memory 593980 kb
Host smart-f118aa2c-a97c-48ad-adf1-1797affac84d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3393093661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3393093661
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.147068209
Short name T200
Test name
Test status
Simulation time 7202961375 ps
CPU time 191.76 seconds
Started Jul 05 05:45:52 PM PDT 24
Finished Jul 05 05:49:05 PM PDT 24
Peak memory 200348 kb
Host smart-d6c4f0ad-3db2-40ae-bebf-45b58aa5323e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147068209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.147068209
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2122790685
Short name T106
Test name
Test status
Simulation time 7353805351 ps
CPU time 104.31 seconds
Started Jul 05 05:45:55 PM PDT 24
Finished Jul 05 05:47:40 PM PDT 24
Peak memory 200052 kb
Host smart-791ae268-ed3a-4c37-bf5e-d544e818ddbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122790685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2122790685
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2605432028
Short name T184
Test name
Test status
Simulation time 762929422 ps
CPU time 3.87 seconds
Started Jul 05 05:45:56 PM PDT 24
Finished Jul 05 05:46:00 PM PDT 24
Peak memory 200096 kb
Host smart-dfc55abe-a942-4738-aea8-b2f062d6ecca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605432028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2605432028
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.4210812299
Short name T382
Test name
Test status
Simulation time 24590564191 ps
CPU time 1298.94 seconds
Started Jul 05 05:46:01 PM PDT 24
Finished Jul 05 06:07:41 PM PDT 24
Peak memory 707480 kb
Host smart-20bfbcf7-ac46-48ff-985f-7f14cc40ca5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210812299 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.4210812299
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1813441029
Short name T442
Test name
Test status
Simulation time 4096102620 ps
CPU time 18.22 seconds
Started Jul 05 05:45:50 PM PDT 24
Finished Jul 05 05:46:08 PM PDT 24
Peak memory 200436 kb
Host smart-75ec1bfa-07f6-49dc-b62e-e90d6cccb44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813441029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1813441029
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.938218319
Short name T375
Test name
Test status
Simulation time 12466686 ps
CPU time 0.6 seconds
Started Jul 05 05:45:58 PM PDT 24
Finished Jul 05 05:45:59 PM PDT 24
Peak memory 196236 kb
Host smart-bd7eb829-c27d-43eb-8f38-0f687dd9be34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938218319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.938218319
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.242315155
Short name T398
Test name
Test status
Simulation time 27008389 ps
CPU time 1.61 seconds
Started Jul 05 05:46:00 PM PDT 24
Finished Jul 05 05:46:02 PM PDT 24
Peak memory 200164 kb
Host smart-9f0a3667-0aaa-408e-8d0a-7dbd86ec41de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=242315155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.242315155
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1354832416
Short name T209
Test name
Test status
Simulation time 348412216 ps
CPU time 4.55 seconds
Started Jul 05 05:46:02 PM PDT 24
Finished Jul 05 05:46:08 PM PDT 24
Peak memory 200184 kb
Host smart-145b47c6-2ca8-4900-abff-d399f6813900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354832416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1354832416
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2028369869
Short name T245
Test name
Test status
Simulation time 8828360296 ps
CPU time 334.26 seconds
Started Jul 05 05:46:04 PM PDT 24
Finished Jul 05 05:51:39 PM PDT 24
Peak memory 479864 kb
Host smart-d6d19863-c674-419c-bb90-6466c0ac6c5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2028369869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2028369869
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1883766164
Short name T213
Test name
Test status
Simulation time 31540346960 ps
CPU time 88.77 seconds
Started Jul 05 05:46:02 PM PDT 24
Finished Jul 05 05:47:31 PM PDT 24
Peak memory 200360 kb
Host smart-e43f58b7-8f56-4927-8723-dd6b7d55b07e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883766164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1883766164
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.3938972852
Short name T90
Test name
Test status
Simulation time 30151394477 ps
CPU time 191.39 seconds
Started Jul 05 05:46:03 PM PDT 24
Finished Jul 05 05:49:16 PM PDT 24
Peak memory 200396 kb
Host smart-880470cf-4a05-4dfb-bcbb-08b834e4eedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938972852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3938972852
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2589962320
Short name T232
Test name
Test status
Simulation time 718523618 ps
CPU time 8.64 seconds
Started Jul 05 05:45:59 PM PDT 24
Finished Jul 05 05:46:09 PM PDT 24
Peak memory 200320 kb
Host smart-5bd96af3-7fa7-4beb-9395-7fe7e93e0909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589962320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2589962320
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1171446122
Short name T510
Test name
Test status
Simulation time 36137881647 ps
CPU time 504.04 seconds
Started Jul 05 05:45:57 PM PDT 24
Finished Jul 05 05:54:21 PM PDT 24
Peak memory 216756 kb
Host smart-9f2db5bb-5c61-4cbd-84a7-36f043d54fed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171446122 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1171446122
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1440802171
Short name T104
Test name
Test status
Simulation time 10941466889 ps
CPU time 96.21 seconds
Started Jul 05 05:46:03 PM PDT 24
Finished Jul 05 05:47:40 PM PDT 24
Peak memory 200356 kb
Host smart-4c2086cd-ccd2-423c-89c6-5d524314d0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440802171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1440802171
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.4230948746
Short name T367
Test name
Test status
Simulation time 32874945 ps
CPU time 0.59 seconds
Started Jul 05 05:46:01 PM PDT 24
Finished Jul 05 05:46:02 PM PDT 24
Peak memory 196152 kb
Host smart-0377adb6-3cff-454b-9b7e-265927e68a85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230948746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.4230948746
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1736814920
Short name T57
Test name
Test status
Simulation time 2885401181 ps
CPU time 83.4 seconds
Started Jul 05 05:46:02 PM PDT 24
Finished Jul 05 05:47:26 PM PDT 24
Peak memory 200372 kb
Host smart-fb7a1a64-390a-42bd-bea4-02a92f5554bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1736814920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1736814920
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2269323523
Short name T256
Test name
Test status
Simulation time 2443758951 ps
CPU time 29.66 seconds
Started Jul 05 05:45:58 PM PDT 24
Finished Jul 05 05:46:29 PM PDT 24
Peak memory 200392 kb
Host smart-fa71c9d3-b78e-4296-80b4-f4f94ca013a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269323523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2269323523
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3944916787
Short name T389
Test name
Test status
Simulation time 5635472395 ps
CPU time 1035.69 seconds
Started Jul 05 05:46:00 PM PDT 24
Finished Jul 05 06:03:17 PM PDT 24
Peak memory 726292 kb
Host smart-03cf05c3-1bc9-4c89-8e08-bb94c36efb2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3944916787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3944916787
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.2266986579
Short name T54
Test name
Test status
Simulation time 20210256387 ps
CPU time 178.55 seconds
Started Jul 05 05:46:01 PM PDT 24
Finished Jul 05 05:49:01 PM PDT 24
Peak memory 200364 kb
Host smart-19ba3a5e-c6c2-479f-9410-0915e9b0247d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266986579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.2266986579
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.3919725834
Short name T357
Test name
Test status
Simulation time 4340773442 ps
CPU time 116.6 seconds
Started Jul 05 05:45:58 PM PDT 24
Finished Jul 05 05:47:56 PM PDT 24
Peak memory 200336 kb
Host smart-56f440ea-f4dd-4dc7-acfb-32ba5890580c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919725834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.3919725834
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1215519671
Short name T409
Test name
Test status
Simulation time 454062644 ps
CPU time 6.27 seconds
Started Jul 05 05:46:01 PM PDT 24
Finished Jul 05 05:46:08 PM PDT 24
Peak memory 200328 kb
Host smart-080ebfd2-4b0a-466e-9aa7-c87b96dd7530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215519671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1215519671
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.1705277208
Short name T348
Test name
Test status
Simulation time 69237899755 ps
CPU time 2742.78 seconds
Started Jul 05 05:46:01 PM PDT 24
Finished Jul 05 06:31:45 PM PDT 24
Peak memory 791052 kb
Host smart-fe3eb195-ec9b-44c9-ac7a-9e573c58398b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705277208 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.1705277208
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.1043745170
Short name T218
Test name
Test status
Simulation time 4925403096 ps
CPU time 63.57 seconds
Started Jul 05 05:45:58 PM PDT 24
Finished Jul 05 05:47:02 PM PDT 24
Peak memory 200380 kb
Host smart-7b462b78-665b-417f-8521-eb997f60e449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043745170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1043745170
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3552768692
Short name T20
Test name
Test status
Simulation time 23030779 ps
CPU time 0.57 seconds
Started Jul 05 05:46:07 PM PDT 24
Finished Jul 05 05:46:09 PM PDT 24
Peak memory 195868 kb
Host smart-29edd111-443d-4600-80e8-b86b97f19b13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552768692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3552768692
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.284506221
Short name T196
Test name
Test status
Simulation time 518524333 ps
CPU time 30.27 seconds
Started Jul 05 05:45:58 PM PDT 24
Finished Jul 05 05:46:30 PM PDT 24
Peak memory 200220 kb
Host smart-16274669-cb4c-42ec-8eda-d152a1fc5f70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=284506221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.284506221
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3162856241
Short name T440
Test name
Test status
Simulation time 944843801 ps
CPU time 8.16 seconds
Started Jul 05 05:45:58 PM PDT 24
Finished Jul 05 05:46:08 PM PDT 24
Peak memory 200292 kb
Host smart-a0ae7212-dba2-47f0-ae75-9e7b04554bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162856241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3162856241
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.483170251
Short name T5
Test name
Test status
Simulation time 674633167 ps
CPU time 31.48 seconds
Started Jul 05 05:45:59 PM PDT 24
Finished Jul 05 05:46:31 PM PDT 24
Peak memory 244652 kb
Host smart-8506f439-3d8e-461c-9fb0-240aa79383ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=483170251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.483170251
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2109608317
Short name T23
Test name
Test status
Simulation time 17107923601 ps
CPU time 113.96 seconds
Started Jul 05 05:46:02 PM PDT 24
Finished Jul 05 05:47:57 PM PDT 24
Peak memory 200348 kb
Host smart-8788df9c-93ca-423b-97c9-c39972c20d60
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109608317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2109608317
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2771510400
Short name T216
Test name
Test status
Simulation time 2673702138 ps
CPU time 45.22 seconds
Started Jul 05 05:45:58 PM PDT 24
Finished Jul 05 05:46:44 PM PDT 24
Peak memory 200348 kb
Host smart-699399e5-b69c-49cf-8377-5224d5a24a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771510400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2771510400
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.383949330
Short name T153
Test name
Test status
Simulation time 824299272 ps
CPU time 9.91 seconds
Started Jul 05 05:46:01 PM PDT 24
Finished Jul 05 05:46:12 PM PDT 24
Peak memory 200312 kb
Host smart-5b80696d-9538-4f19-b6e7-c0e8250c06f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383949330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.383949330
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.369480610
Short name T395
Test name
Test status
Simulation time 11055175925 ps
CPU time 1450.42 seconds
Started Jul 05 05:46:06 PM PDT 24
Finished Jul 05 06:10:18 PM PDT 24
Peak memory 730296 kb
Host smart-1eca002f-6a57-4d77-a9d9-719a54dbc650
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369480610 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.369480610
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3771828376
Short name T27
Test name
Test status
Simulation time 37047135 ps
CPU time 0.78 seconds
Started Jul 05 05:45:59 PM PDT 24
Finished Jul 05 05:46:01 PM PDT 24
Peak memory 198088 kb
Host smart-4c3257c4-f7da-489f-b672-60379c320441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771828376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3771828376
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3875544820
Short name T413
Test name
Test status
Simulation time 16162593 ps
CPU time 0.59 seconds
Started Jul 05 05:46:06 PM PDT 24
Finished Jul 05 05:46:07 PM PDT 24
Peak memory 196864 kb
Host smart-49bf6e96-bc72-4f07-9517-5e95b059c93a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875544820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3875544820
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1433838982
Short name T330
Test name
Test status
Simulation time 4595901763 ps
CPU time 61.96 seconds
Started Jul 05 05:46:08 PM PDT 24
Finished Jul 05 05:47:11 PM PDT 24
Peak memory 200372 kb
Host smart-22bf8081-5587-41f2-b93a-910714b753e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1433838982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1433838982
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.1460341060
Short name T293
Test name
Test status
Simulation time 156199969 ps
CPU time 7.1 seconds
Started Jul 05 05:46:06 PM PDT 24
Finished Jul 05 05:46:14 PM PDT 24
Peak memory 200312 kb
Host smart-377dab0c-dc81-4a7b-a92c-65742c2e0752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460341060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.1460341060
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3437730335
Short name T165
Test name
Test status
Simulation time 1480833856 ps
CPU time 199.47 seconds
Started Jul 05 05:46:10 PM PDT 24
Finished Jul 05 05:49:30 PM PDT 24
Peak memory 416460 kb
Host smart-d54d71ac-b9cf-48ed-ae26-911e5bc866fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3437730335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3437730335
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.3767425715
Short name T447
Test name
Test status
Simulation time 17446983305 ps
CPU time 54.62 seconds
Started Jul 05 05:46:07 PM PDT 24
Finished Jul 05 05:47:03 PM PDT 24
Peak memory 200348 kb
Host smart-f781ab8c-70e2-4cd9-8c15-b2f0d7610a1b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767425715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3767425715
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1524105502
Short name T38
Test name
Test status
Simulation time 14914023688 ps
CPU time 119.29 seconds
Started Jul 05 05:46:06 PM PDT 24
Finished Jul 05 05:48:06 PM PDT 24
Peak memory 200440 kb
Host smart-7aafa412-e6ac-48e1-ae70-08adb971ed1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524105502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1524105502
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.588126169
Short name T436
Test name
Test status
Simulation time 116249541 ps
CPU time 5.56 seconds
Started Jul 05 05:46:08 PM PDT 24
Finished Jul 05 05:46:15 PM PDT 24
Peak memory 200300 kb
Host smart-d77b71d4-7f71-43eb-9fa3-a16eeb30f065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588126169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.588126169
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.755932078
Short name T499
Test name
Test status
Simulation time 19362784374 ps
CPU time 73.58 seconds
Started Jul 05 05:46:06 PM PDT 24
Finished Jul 05 05:47:20 PM PDT 24
Peak memory 200340 kb
Host smart-b7c84ca0-18dd-4dff-b30a-5c93b7b2f421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755932078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.755932078
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2331133129
Short name T464
Test name
Test status
Simulation time 33160784 ps
CPU time 0.58 seconds
Started Jul 05 05:49:32 PM PDT 24
Finished Jul 05 05:49:33 PM PDT 24
Peak memory 195164 kb
Host smart-e16fce34-5565-4c03-b609-be851734b508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331133129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2331133129
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2328536369
Short name T170
Test name
Test status
Simulation time 1701436645 ps
CPU time 86.18 seconds
Started Jul 05 05:46:08 PM PDT 24
Finished Jul 05 05:47:35 PM PDT 24
Peak memory 200328 kb
Host smart-00aca1b4-825a-44da-821d-d41a52e7adf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2328536369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2328536369
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.350210305
Short name T132
Test name
Test status
Simulation time 4376450089 ps
CPU time 55.32 seconds
Started Jul 05 05:46:08 PM PDT 24
Finished Jul 05 05:47:04 PM PDT 24
Peak memory 200352 kb
Host smart-5baef06f-0783-42b7-b2f0-09be77080ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350210305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.350210305
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.4098286351
Short name T273
Test name
Test status
Simulation time 6820855061 ps
CPU time 1215.71 seconds
Started Jul 05 05:46:06 PM PDT 24
Finished Jul 05 06:06:22 PM PDT 24
Peak memory 727068 kb
Host smart-a6d52fa2-e2c3-47c4-bdbd-5ccb2c857f8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4098286351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.4098286351
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1305110824
Short name T279
Test name
Test status
Simulation time 63912478087 ps
CPU time 213.76 seconds
Started Jul 05 05:46:06 PM PDT 24
Finished Jul 05 05:49:40 PM PDT 24
Peak memory 200360 kb
Host smart-539eb25e-9fea-4444-9d36-269f7c1a42ac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305110824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1305110824
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3041803766
Short name T376
Test name
Test status
Simulation time 4499855960 ps
CPU time 21.5 seconds
Started Jul 05 05:46:06 PM PDT 24
Finished Jul 05 05:46:28 PM PDT 24
Peak memory 200276 kb
Host smart-104483c1-2ed3-403e-87bb-d5dc2751caf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041803766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3041803766
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.941539993
Short name T297
Test name
Test status
Simulation time 54025813 ps
CPU time 0.67 seconds
Started Jul 05 05:46:08 PM PDT 24
Finished Jul 05 05:46:10 PM PDT 24
Peak memory 196884 kb
Host smart-a98ed02f-fd99-48c8-908d-ea2aea9132bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941539993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.941539993
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.4252135378
Short name T457
Test name
Test status
Simulation time 15764753271 ps
CPU time 161.81 seconds
Started Jul 05 05:46:07 PM PDT 24
Finished Jul 05 05:48:50 PM PDT 24
Peak memory 208544 kb
Host smart-532a323a-f9b2-4ab8-bb9d-36af6d629b4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252135378 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.4252135378
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.28848192
Short name T439
Test name
Test status
Simulation time 50312824129 ps
CPU time 49.37 seconds
Started Jul 05 05:46:06 PM PDT 24
Finished Jul 05 05:46:56 PM PDT 24
Peak memory 200384 kb
Host smart-eeeaf8a1-f740-4ffb-a6a9-3467f375e09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28848192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.28848192
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1831452572
Short name T490
Test name
Test status
Simulation time 13320382 ps
CPU time 0.6 seconds
Started Jul 05 05:46:14 PM PDT 24
Finished Jul 05 05:46:16 PM PDT 24
Peak memory 195948 kb
Host smart-7c8b8c5b-02e3-4c69-a19d-b3211e8d5f4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831452572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1831452572
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1980216014
Short name T237
Test name
Test status
Simulation time 1128662932 ps
CPU time 17.97 seconds
Started Jul 05 05:46:07 PM PDT 24
Finished Jul 05 05:46:26 PM PDT 24
Peak memory 200320 kb
Host smart-cc707ae1-2a51-4039-892d-0668e1ce3e00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1980216014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1980216014
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3578776355
Short name T411
Test name
Test status
Simulation time 2619640638 ps
CPU time 47.67 seconds
Started Jul 05 05:46:06 PM PDT 24
Finished Jul 05 05:46:55 PM PDT 24
Peak memory 200356 kb
Host smart-db764c39-8623-4fb9-b5e6-b813dae046d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578776355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3578776355
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3245123693
Short name T266
Test name
Test status
Simulation time 643975696 ps
CPU time 118.99 seconds
Started Jul 05 05:46:08 PM PDT 24
Finished Jul 05 05:48:08 PM PDT 24
Peak memory 456312 kb
Host smart-7c9381ac-b9b5-4add-bd7e-b23966a54fa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3245123693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3245123693
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1256983210
Short name T502
Test name
Test status
Simulation time 6044722195 ps
CPU time 165.36 seconds
Started Jul 05 05:46:04 PM PDT 24
Finished Jul 05 05:48:50 PM PDT 24
Peak memory 200320 kb
Host smart-f66657d2-3dc6-479e-9b33-1e070b36dbd6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256983210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1256983210
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.558051167
Short name T303
Test name
Test status
Simulation time 2442874978 ps
CPU time 22.25 seconds
Started Jul 05 05:46:07 PM PDT 24
Finished Jul 05 05:46:30 PM PDT 24
Peak memory 200332 kb
Host smart-36d5a937-c240-4d03-b6ae-1ba41faf5f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558051167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.558051167
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3410352081
Short name T496
Test name
Test status
Simulation time 1099235647 ps
CPU time 12.78 seconds
Started Jul 05 05:46:06 PM PDT 24
Finished Jul 05 05:46:19 PM PDT 24
Peak memory 200332 kb
Host smart-70716bc7-9d5c-4472-b50c-62a09cb23222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410352081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3410352081
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2103823007
Short name T26
Test name
Test status
Simulation time 25128187395 ps
CPU time 3819.75 seconds
Started Jul 05 05:46:14 PM PDT 24
Finished Jul 05 06:49:55 PM PDT 24
Peak memory 839452 kb
Host smart-fcc8dec5-0593-43ae-92c1-e7396a5b1723
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103823007 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2103823007
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.1795308013
Short name T268
Test name
Test status
Simulation time 41978956613 ps
CPU time 121.85 seconds
Started Jul 05 05:46:07 PM PDT 24
Finished Jul 05 05:48:10 PM PDT 24
Peak memory 200364 kb
Host smart-24b4dd9c-8c01-42a1-b386-39fbfbe7e136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795308013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1795308013
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.322248755
Short name T207
Test name
Test status
Simulation time 27302931 ps
CPU time 0.62 seconds
Started Jul 05 05:46:15 PM PDT 24
Finished Jul 05 05:46:17 PM PDT 24
Peak memory 196236 kb
Host smart-89e4a364-52a5-416a-934d-9bda22cda73d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322248755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.322248755
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3269179248
Short name T162
Test name
Test status
Simulation time 846033482 ps
CPU time 13.19 seconds
Started Jul 05 05:46:15 PM PDT 24
Finished Jul 05 05:46:29 PM PDT 24
Peak memory 200176 kb
Host smart-4e849ca1-83bc-4636-8945-1727d55c5b23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3269179248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3269179248
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.51940620
Short name T217
Test name
Test status
Simulation time 1900146631 ps
CPU time 34.49 seconds
Started Jul 05 05:46:14 PM PDT 24
Finished Jul 05 05:46:49 PM PDT 24
Peak memory 200332 kb
Host smart-b7b945bf-6e3b-48c1-a87d-1bcf5f8b9030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51940620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.51940620
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2873081736
Short name T332
Test name
Test status
Simulation time 672459034 ps
CPU time 103.6 seconds
Started Jul 05 05:46:15 PM PDT 24
Finished Jul 05 05:48:00 PM PDT 24
Peak memory 351492 kb
Host smart-bb50fde4-77fa-4da9-8bb7-2bb344c906ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2873081736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2873081736
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3684165143
Short name T299
Test name
Test status
Simulation time 24654180167 ps
CPU time 216.34 seconds
Started Jul 05 05:46:14 PM PDT 24
Finished Jul 05 05:49:51 PM PDT 24
Peak memory 200356 kb
Host smart-3fe46b00-e255-4488-972a-dbf22ff9529c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684165143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3684165143
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.4022480071
Short name T180
Test name
Test status
Simulation time 1511351977 ps
CPU time 38.59 seconds
Started Jul 05 05:46:19 PM PDT 24
Finished Jul 05 05:46:58 PM PDT 24
Peak memory 200328 kb
Host smart-22b63ac8-c7d5-4008-93e6-90df625e9f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022480071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.4022480071
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2594980695
Short name T51
Test name
Test status
Simulation time 846910866 ps
CPU time 14.28 seconds
Started Jul 05 05:46:15 PM PDT 24
Finished Jul 05 05:46:30 PM PDT 24
Peak memory 200372 kb
Host smart-1f947d6a-278b-4f23-9b4d-d970ad69e83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594980695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2594980695
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.659881054
Short name T50
Test name
Test status
Simulation time 350905230603 ps
CPU time 1909.18 seconds
Started Jul 05 05:46:18 PM PDT 24
Finished Jul 05 06:18:08 PM PDT 24
Peak memory 790356 kb
Host smart-f7b657b4-5522-4423-9936-08496bb9b8ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659881054 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.659881054
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.4003182318
Short name T227
Test name
Test status
Simulation time 9361043247 ps
CPU time 87.15 seconds
Started Jul 05 05:46:16 PM PDT 24
Finished Jul 05 05:47:44 PM PDT 24
Peak memory 200368 kb
Host smart-f6306f5f-e7c9-484a-ab54-32b954520c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003182318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.4003182318
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.2736041471
Short name T179
Test name
Test status
Simulation time 27572096 ps
CPU time 0.62 seconds
Started Jul 05 05:45:26 PM PDT 24
Finished Jul 05 05:45:27 PM PDT 24
Peak memory 196216 kb
Host smart-1da16ba3-3c2e-48c6-9a19-05e04871cf3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736041471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.2736041471
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.4160325941
Short name T175
Test name
Test status
Simulation time 2809676330 ps
CPU time 59.29 seconds
Started Jul 05 05:45:22 PM PDT 24
Finished Jul 05 05:46:22 PM PDT 24
Peak memory 200276 kb
Host smart-323e63b4-86e4-4af1-a2e5-72306d95f3fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4160325941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.4160325941
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.367458416
Short name T497
Test name
Test status
Simulation time 6164054744 ps
CPU time 43.24 seconds
Started Jul 05 05:45:25 PM PDT 24
Finished Jul 05 05:46:09 PM PDT 24
Peak memory 200340 kb
Host smart-60285837-b8e9-4e32-bbdd-43ce6dd3bbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367458416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.367458416
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.4133627145
Short name T408
Test name
Test status
Simulation time 3394146278 ps
CPU time 93.31 seconds
Started Jul 05 05:45:27 PM PDT 24
Finished Jul 05 05:47:01 PM PDT 24
Peak memory 351556 kb
Host smart-89b10885-af64-485c-b573-b46d094fe8c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4133627145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.4133627145
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.2758548273
Short name T331
Test name
Test status
Simulation time 20412440008 ps
CPU time 184.66 seconds
Started Jul 05 05:45:24 PM PDT 24
Finished Jul 05 05:48:30 PM PDT 24
Peak memory 200404 kb
Host smart-185bce07-6459-476e-a51f-08fb6a1c1ecd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758548273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.2758548273
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.535652168
Short name T285
Test name
Test status
Simulation time 2805608970 ps
CPU time 26.26 seconds
Started Jul 05 05:45:29 PM PDT 24
Finished Jul 05 05:45:56 PM PDT 24
Peak memory 200380 kb
Host smart-834eed0f-1c70-42c9-a2a0-51e2ebf2e57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535652168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.535652168
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_smoke.2751891424
Short name T334
Test name
Test status
Simulation time 1740422908 ps
CPU time 7.03 seconds
Started Jul 05 05:45:26 PM PDT 24
Finished Jul 05 05:45:33 PM PDT 24
Peak memory 200308 kb
Host smart-678d3eb5-2b9c-4e64-9097-ffda79cd2597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751891424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2751891424
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2710835476
Short name T193
Test name
Test status
Simulation time 2010154063 ps
CPU time 114.34 seconds
Started Jul 05 05:45:24 PM PDT 24
Finished Jul 05 05:47:19 PM PDT 24
Peak memory 200276 kb
Host smart-ee89acdd-cd73-4156-80cd-605cf8f7cde0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710835476 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2710835476
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.2927415421
Short name T24
Test name
Test status
Simulation time 82559602351 ps
CPU time 9539.81 seconds
Started Jul 05 05:45:26 PM PDT 24
Finished Jul 05 08:24:27 PM PDT 24
Peak memory 873244 kb
Host smart-d2cf0b87-9f08-46c2-b090-716cabc7553f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2927415421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.2927415421
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.2151668283
Short name T161
Test name
Test status
Simulation time 1178921171 ps
CPU time 45.64 seconds
Started Jul 05 05:45:24 PM PDT 24
Finished Jul 05 05:46:10 PM PDT 24
Peak memory 200364 kb
Host smart-e2d5952f-0848-4d16-b740-b79847140315
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2151668283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.2151668283
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.3668720151
Short name T49
Test name
Test status
Simulation time 6112027685 ps
CPU time 93.4 seconds
Started Jul 05 05:45:28 PM PDT 24
Finished Jul 05 05:47:01 PM PDT 24
Peak memory 200428 kb
Host smart-ba185ed3-9106-44e6-b4dc-ae9be28557ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3668720151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.3668720151
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.1538783350
Short name T210
Test name
Test status
Simulation time 11467908924 ps
CPU time 133.11 seconds
Started Jul 05 05:45:27 PM PDT 24
Finished Jul 05 05:47:40 PM PDT 24
Peak memory 200356 kb
Host smart-2b70b41e-ef0a-4cbf-aa12-6c255e9f5cde
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1538783350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.1538783350
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.1137155170
Short name T194
Test name
Test status
Simulation time 10304298143 ps
CPU time 535.84 seconds
Started Jul 05 05:45:26 PM PDT 24
Finished Jul 05 05:54:22 PM PDT 24
Peak memory 200412 kb
Host smart-19ba58ca-9144-420b-9a1f-e01fcc3e0d94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1137155170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.1137155170
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.1160447779
Short name T445
Test name
Test status
Simulation time 85189350287 ps
CPU time 2307.33 seconds
Started Jul 05 05:45:26 PM PDT 24
Finished Jul 05 06:23:54 PM PDT 24
Peak memory 208560 kb
Host smart-53e0ccf4-1134-4e9e-8cde-e10addcbc2f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1160447779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.1160447779
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.1330744562
Short name T152
Test name
Test status
Simulation time 78731805418 ps
CPU time 2179.02 seconds
Started Jul 05 05:45:28 PM PDT 24
Finished Jul 05 06:21:47 PM PDT 24
Peak memory 215916 kb
Host smart-22322547-5c16-44dc-8ab6-44c50de0c3ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1330744562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1330744562
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.4004965000
Short name T479
Test name
Test status
Simulation time 33915600076 ps
CPU time 127.71 seconds
Started Jul 05 05:45:27 PM PDT 24
Finished Jul 05 05:47:36 PM PDT 24
Peak memory 200364 kb
Host smart-975f6017-3806-4925-81ef-6f40d40ea648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004965000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.4004965000
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.808319425
Short name T405
Test name
Test status
Simulation time 15086530 ps
CPU time 0.59 seconds
Started Jul 05 05:46:16 PM PDT 24
Finished Jul 05 05:46:17 PM PDT 24
Peak memory 196200 kb
Host smart-7268fc66-339b-458a-823a-2b6db3e4f98a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808319425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.808319425
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2773617314
Short name T341
Test name
Test status
Simulation time 3296483724 ps
CPU time 47.41 seconds
Started Jul 05 05:46:14 PM PDT 24
Finished Jul 05 05:47:02 PM PDT 24
Peak memory 200360 kb
Host smart-f6c86430-888b-4041-af48-a30d827ac85a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2773617314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2773617314
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3039945035
Short name T281
Test name
Test status
Simulation time 224267518 ps
CPU time 4.64 seconds
Started Jul 05 05:46:14 PM PDT 24
Finished Jul 05 05:46:20 PM PDT 24
Peak memory 200276 kb
Host smart-e8c9ffed-0f03-4781-8126-19f74bd33ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039945035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3039945035
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.1036944482
Short name T235
Test name
Test status
Simulation time 11513401934 ps
CPU time 859.68 seconds
Started Jul 05 05:46:13 PM PDT 24
Finished Jul 05 06:00:33 PM PDT 24
Peak memory 630760 kb
Host smart-1a93015c-fca0-46be-b74e-cb3d57b24b6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1036944482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.1036944482
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.740585432
Short name T177
Test name
Test status
Simulation time 112828396814 ps
CPU time 195.1 seconds
Started Jul 05 05:46:14 PM PDT 24
Finished Jul 05 05:49:30 PM PDT 24
Peak memory 200356 kb
Host smart-dd0d56da-321d-4d23-96c1-813988fbddd4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740585432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.740585432
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3741752845
Short name T470
Test name
Test status
Simulation time 28623908679 ps
CPU time 123.92 seconds
Started Jul 05 05:46:17 PM PDT 24
Finished Jul 05 05:48:21 PM PDT 24
Peak memory 200336 kb
Host smart-babcf7d9-8495-46bd-8fbc-7213e3529653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741752845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3741752845
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.2602607483
Short name T272
Test name
Test status
Simulation time 366043676 ps
CPU time 6.45 seconds
Started Jul 05 05:46:15 PM PDT 24
Finished Jul 05 05:46:23 PM PDT 24
Peak memory 200320 kb
Host smart-6078f5c2-9d9a-4cb2-ba98-876bc36a6b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602607483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.2602607483
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.307977776
Short name T82
Test name
Test status
Simulation time 29512379841 ps
CPU time 380.86 seconds
Started Jul 05 05:46:14 PM PDT 24
Finished Jul 05 05:52:36 PM PDT 24
Peak memory 201060 kb
Host smart-282609dc-6382-4fa0-99b6-0b68da321dc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307977776 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.307977776
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.227964189
Short name T305
Test name
Test status
Simulation time 453762203 ps
CPU time 8.31 seconds
Started Jul 05 05:46:11 PM PDT 24
Finished Jul 05 05:46:20 PM PDT 24
Peak memory 200360 kb
Host smart-926f06b2-5f45-492b-be5f-cb5a75f52cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227964189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.227964189
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1096129718
Short name T28
Test name
Test status
Simulation time 11876482 ps
CPU time 0.58 seconds
Started Jul 05 05:46:18 PM PDT 24
Finished Jul 05 05:46:19 PM PDT 24
Peak memory 195172 kb
Host smart-8ccd1857-7ee4-4bae-8fe4-d62564b62d30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096129718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1096129718
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.927119340
Short name T96
Test name
Test status
Simulation time 4481436715 ps
CPU time 48.7 seconds
Started Jul 05 05:46:16 PM PDT 24
Finished Jul 05 05:47:06 PM PDT 24
Peak memory 200336 kb
Host smart-7705d198-9a78-4822-aa74-09d820be8e91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=927119340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.927119340
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1627385963
Short name T315
Test name
Test status
Simulation time 749436786 ps
CPU time 39.24 seconds
Started Jul 05 05:46:20 PM PDT 24
Finished Jul 05 05:47:00 PM PDT 24
Peak memory 200224 kb
Host smart-4e128f55-e30a-4b0a-a7b7-7eb6892866c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627385963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1627385963
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.4269828222
Short name T318
Test name
Test status
Simulation time 1788038506 ps
CPU time 316.21 seconds
Started Jul 05 05:46:22 PM PDT 24
Finished Jul 05 05:51:39 PM PDT 24
Peak memory 612260 kb
Host smart-76ae3b26-bf04-48ec-9b01-5074f70fe536
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4269828222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.4269828222
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3647475713
Short name T390
Test name
Test status
Simulation time 63257782260 ps
CPU time 217.41 seconds
Started Jul 05 05:46:18 PM PDT 24
Finished Jul 05 05:49:55 PM PDT 24
Peak memory 200352 kb
Host smart-b62f16c4-68ff-46ff-9656-b42e67d6084a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647475713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3647475713
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.869215279
Short name T501
Test name
Test status
Simulation time 55651476913 ps
CPU time 200.23 seconds
Started Jul 05 05:46:17 PM PDT 24
Finished Jul 05 05:49:37 PM PDT 24
Peak memory 208548 kb
Host smart-15ff855c-05cd-44b3-88fd-55e38e808f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869215279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.869215279
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1626755858
Short name T396
Test name
Test status
Simulation time 618000726 ps
CPU time 3.1 seconds
Started Jul 05 05:46:19 PM PDT 24
Finished Jul 05 05:46:23 PM PDT 24
Peak memory 200296 kb
Host smart-2d25fd1a-107e-4b0c-ba98-7897122ba747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626755858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1626755858
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2953680495
Short name T373
Test name
Test status
Simulation time 297256549516 ps
CPU time 1444.77 seconds
Started Jul 05 05:46:20 PM PDT 24
Finished Jul 05 06:10:25 PM PDT 24
Peak memory 709092 kb
Host smart-43cc1459-1894-4003-8298-7491d8c0acc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953680495 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2953680495
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1937399643
Short name T167
Test name
Test status
Simulation time 9168566987 ps
CPU time 156.32 seconds
Started Jul 05 05:46:21 PM PDT 24
Finished Jul 05 05:48:58 PM PDT 24
Peak memory 200356 kb
Host smart-89765b87-80c8-4bb6-b578-7065740b6080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937399643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1937399643
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.412735846
Short name T370
Test name
Test status
Simulation time 25908968 ps
CPU time 0.63 seconds
Started Jul 05 05:46:23 PM PDT 24
Finished Jul 05 05:46:24 PM PDT 24
Peak memory 196212 kb
Host smart-51a9e001-1051-47dc-928f-73ccbc22e261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412735846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.412735846
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.408348068
Short name T326
Test name
Test status
Simulation time 7032392525 ps
CPU time 61.18 seconds
Started Jul 05 05:46:21 PM PDT 24
Finished Jul 05 05:47:23 PM PDT 24
Peak memory 200336 kb
Host smart-a50eff00-04b5-4eb8-99a5-07f694fc7c0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=408348068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.408348068
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.3798430780
Short name T231
Test name
Test status
Simulation time 2536418546 ps
CPU time 17.15 seconds
Started Jul 05 05:46:19 PM PDT 24
Finished Jul 05 05:46:37 PM PDT 24
Peak memory 200380 kb
Host smart-54e29567-91ef-432e-bfcd-a6edd47031c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798430780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3798430780
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1306664487
Short name T386
Test name
Test status
Simulation time 15657195253 ps
CPU time 799.74 seconds
Started Jul 05 05:46:18 PM PDT 24
Finished Jul 05 05:59:38 PM PDT 24
Peak memory 706872 kb
Host smart-d4d8e9ca-f64e-4851-90d8-3fc01bcf66f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1306664487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1306664487
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.4164442457
Short name T486
Test name
Test status
Simulation time 11414291261 ps
CPU time 97.48 seconds
Started Jul 05 05:46:19 PM PDT 24
Finished Jul 05 05:47:57 PM PDT 24
Peak memory 200412 kb
Host smart-dc2bf8f1-e067-42fd-8f37-135b8e57beda
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164442457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.4164442457
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3112133673
Short name T214
Test name
Test status
Simulation time 16798199962 ps
CPU time 219.52 seconds
Started Jul 05 05:46:21 PM PDT 24
Finished Jul 05 05:50:01 PM PDT 24
Peak memory 200296 kb
Host smart-b6b8ba01-263b-4611-bf63-f6402cff7ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112133673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3112133673
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1875639361
Short name T37
Test name
Test status
Simulation time 4242917350 ps
CPU time 14.71 seconds
Started Jul 05 05:46:21 PM PDT 24
Finished Jul 05 05:46:36 PM PDT 24
Peak memory 200308 kb
Host smart-531fcd0c-14c7-4a56-b6a1-518d8f833086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875639361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1875639361
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1642831105
Short name T85
Test name
Test status
Simulation time 549044512263 ps
CPU time 3983.09 seconds
Started Jul 05 05:46:22 PM PDT 24
Finished Jul 05 06:52:46 PM PDT 24
Peak memory 820932 kb
Host smart-843093b5-95f4-4a77-b316-19fc5eeeb614
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642831105 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1642831105
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.779497983
Short name T495
Test name
Test status
Simulation time 5871995442 ps
CPU time 82.5 seconds
Started Jul 05 05:46:19 PM PDT 24
Finished Jul 05 05:47:42 PM PDT 24
Peak memory 200260 kb
Host smart-cc68e8cb-1370-4a2d-9d17-4787be098a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779497983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.779497983
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2221441882
Short name T64
Test name
Test status
Simulation time 15987804 ps
CPU time 0.6 seconds
Started Jul 05 05:46:28 PM PDT 24
Finished Jul 05 05:46:29 PM PDT 24
Peak memory 196192 kb
Host smart-243db7e6-746d-4f36-bb17-62e17666cc61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221441882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2221441882
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.301255696
Short name T205
Test name
Test status
Simulation time 1578371297 ps
CPU time 87.54 seconds
Started Jul 05 05:46:20 PM PDT 24
Finished Jul 05 05:47:48 PM PDT 24
Peak memory 200348 kb
Host smart-dd28cd47-15e2-43ee-9924-cba8c8530aeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=301255696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.301255696
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.3180982879
Short name T103
Test name
Test status
Simulation time 3700909254 ps
CPU time 24.68 seconds
Started Jul 05 05:46:18 PM PDT 24
Finished Jul 05 05:46:43 PM PDT 24
Peak memory 200392 kb
Host smart-1201725b-2035-49f2-b656-31b898f0f427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180982879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.3180982879
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1933687437
Short name T48
Test name
Test status
Simulation time 999531237 ps
CPU time 51.49 seconds
Started Jul 05 05:46:21 PM PDT 24
Finished Jul 05 05:47:14 PM PDT 24
Peak memory 310064 kb
Host smart-af435faa-2b0f-416e-9700-8af656c0e1ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1933687437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1933687437
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2610107738
Short name T46
Test name
Test status
Simulation time 9744548206 ps
CPU time 179.51 seconds
Started Jul 05 05:46:20 PM PDT 24
Finished Jul 05 05:49:20 PM PDT 24
Peak memory 200356 kb
Host smart-2d2ae698-26c7-4722-917a-616d6eb69a41
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610107738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2610107738
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3848647129
Short name T322
Test name
Test status
Simulation time 2627196708 ps
CPU time 74.02 seconds
Started Jul 05 05:46:20 PM PDT 24
Finished Jul 05 05:47:34 PM PDT 24
Peak memory 200376 kb
Host smart-99ab1a79-1bce-4807-a9da-3ab975c7b82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848647129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3848647129
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3449143075
Short name T287
Test name
Test status
Simulation time 1199672142 ps
CPU time 14.93 seconds
Started Jul 05 05:46:20 PM PDT 24
Finished Jul 05 05:46:35 PM PDT 24
Peak memory 200320 kb
Host smart-176b96eb-3921-404e-98d7-2f25c8594e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449143075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3449143075
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3267933337
Short name T364
Test name
Test status
Simulation time 4293960209 ps
CPU time 283.16 seconds
Started Jul 05 05:46:34 PM PDT 24
Finished Jul 05 05:51:18 PM PDT 24
Peak memory 485536 kb
Host smart-37cf31cd-328e-492c-9888-f91fee8d230b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267933337 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3267933337
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.578779420
Short name T29
Test name
Test status
Simulation time 18527402825 ps
CPU time 26.43 seconds
Started Jul 05 05:46:20 PM PDT 24
Finished Jul 05 05:46:47 PM PDT 24
Peak memory 200384 kb
Host smart-c6483c25-14c8-40af-8469-fb17e31d4d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578779420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.578779420
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.1680017777
Short name T102
Test name
Test status
Simulation time 21936500 ps
CPU time 0.58 seconds
Started Jul 05 05:46:28 PM PDT 24
Finished Jul 05 05:46:29 PM PDT 24
Peak memory 196116 kb
Host smart-b567cc40-37a7-42d6-9558-50a485873f84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680017777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1680017777
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2894558971
Short name T6
Test name
Test status
Simulation time 1491350704 ps
CPU time 84.56 seconds
Started Jul 05 05:46:26 PM PDT 24
Finished Jul 05 05:47:51 PM PDT 24
Peak memory 200316 kb
Host smart-d146bfdc-83a9-4c6d-bd04-a8f2368a93c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2894558971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2894558971
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.4067103103
Short name T361
Test name
Test status
Simulation time 6917575227 ps
CPU time 52.58 seconds
Started Jul 05 05:46:28 PM PDT 24
Finished Jul 05 05:47:21 PM PDT 24
Peak memory 200424 kb
Host smart-e47322ad-2837-465a-8a5a-7fc74fcf73aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067103103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.4067103103
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.4005392392
Short name T453
Test name
Test status
Simulation time 13466354991 ps
CPU time 413.82 seconds
Started Jul 05 05:46:28 PM PDT 24
Finished Jul 05 05:53:23 PM PDT 24
Peak memory 461260 kb
Host smart-df61a435-7004-4d07-9295-64cba8b3cd29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4005392392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.4005392392
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.475937693
Short name T98
Test name
Test status
Simulation time 12317304572 ps
CPU time 187.38 seconds
Started Jul 05 05:46:29 PM PDT 24
Finished Jul 05 05:49:37 PM PDT 24
Peak memory 200312 kb
Host smart-fb217623-3adb-476b-81da-d75d78f78437
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475937693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.475937693
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1632948726
Short name T257
Test name
Test status
Simulation time 16870360594 ps
CPU time 53.92 seconds
Started Jul 05 05:46:33 PM PDT 24
Finished Jul 05 05:47:28 PM PDT 24
Peak memory 200348 kb
Host smart-7c4444e7-8e6d-4223-aa73-f8b98edf2c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632948726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1632948726
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.4025073718
Short name T487
Test name
Test status
Simulation time 1971998086 ps
CPU time 7.64 seconds
Started Jul 05 05:46:27 PM PDT 24
Finished Jul 05 05:46:36 PM PDT 24
Peak memory 200304 kb
Host smart-c40b324f-4595-4553-a010-645ac4f138c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025073718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.4025073718
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2340374094
Short name T366
Test name
Test status
Simulation time 134519662006 ps
CPU time 1847.13 seconds
Started Jul 05 05:46:28 PM PDT 24
Finished Jul 05 06:17:16 PM PDT 24
Peak memory 729064 kb
Host smart-05dc12d4-fc97-483d-a9ab-dd2378d896e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340374094 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2340374094
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2327029665
Short name T241
Test name
Test status
Simulation time 5856032749 ps
CPU time 79.54 seconds
Started Jul 05 05:46:28 PM PDT 24
Finished Jul 05 05:47:48 PM PDT 24
Peak memory 200416 kb
Host smart-0a275505-f9bd-4d19-809e-59d0a7d08f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327029665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2327029665
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3942780143
Short name T454
Test name
Test status
Simulation time 43932241 ps
CPU time 0.62 seconds
Started Jul 05 05:46:36 PM PDT 24
Finished Jul 05 05:46:38 PM PDT 24
Peak memory 196212 kb
Host smart-9b68765b-d6f7-4e1e-ae08-40cf34206edf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942780143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3942780143
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1365844722
Short name T199
Test name
Test status
Simulation time 7364656154 ps
CPU time 85.63 seconds
Started Jul 05 05:46:27 PM PDT 24
Finished Jul 05 05:47:54 PM PDT 24
Peak memory 200376 kb
Host smart-06f44a65-cf68-4572-9340-d282240b57d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1365844722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1365844722
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.2577422955
Short name T443
Test name
Test status
Simulation time 4156198561 ps
CPU time 28.14 seconds
Started Jul 05 05:46:33 PM PDT 24
Finished Jul 05 05:47:02 PM PDT 24
Peak memory 200344 kb
Host smart-d24327be-3c98-42ef-bfcf-131e56aa8ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577422955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.2577422955
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.134618031
Short name T91
Test name
Test status
Simulation time 6300189455 ps
CPU time 1098.92 seconds
Started Jul 05 05:46:28 PM PDT 24
Finished Jul 05 06:04:49 PM PDT 24
Peak memory 721576 kb
Host smart-355dc993-7812-4dcb-919c-a90ce46fd54b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=134618031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.134618031
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2141274360
Short name T192
Test name
Test status
Simulation time 13178789768 ps
CPU time 165.39 seconds
Started Jul 05 05:46:29 PM PDT 24
Finished Jul 05 05:49:15 PM PDT 24
Peak memory 200356 kb
Host smart-bb55298f-3bce-4688-93e4-a3a705248d78
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141274360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2141274360
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1109977872
Short name T462
Test name
Test status
Simulation time 9462287842 ps
CPU time 87.84 seconds
Started Jul 05 05:46:30 PM PDT 24
Finished Jul 05 05:47:58 PM PDT 24
Peak memory 200420 kb
Host smart-a30f75af-3089-4e8f-8b35-948114e6d753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109977872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1109977872
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1988440630
Short name T43
Test name
Test status
Simulation time 1401695426 ps
CPU time 13.47 seconds
Started Jul 05 05:46:27 PM PDT 24
Finished Jul 05 05:46:42 PM PDT 24
Peak memory 200368 kb
Host smart-0d940eaa-66cb-4453-a904-3795c32bbfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988440630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1988440630
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2175976780
Short name T86
Test name
Test status
Simulation time 186365817261 ps
CPU time 2704.68 seconds
Started Jul 05 05:46:28 PM PDT 24
Finished Jul 05 06:31:34 PM PDT 24
Peak memory 747044 kb
Host smart-3ade50fb-0f4d-473d-b071-7a6a5b040996
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175976780 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2175976780
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2187038965
Short name T2
Test name
Test status
Simulation time 6686957760 ps
CPU time 86.08 seconds
Started Jul 05 05:46:28 PM PDT 24
Finished Jul 05 05:47:56 PM PDT 24
Peak memory 200360 kb
Host smart-12d50942-26a7-4b03-a199-de4a1927fab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187038965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2187038965
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3759822146
Short name T247
Test name
Test status
Simulation time 42320165 ps
CPU time 0.57 seconds
Started Jul 05 05:46:37 PM PDT 24
Finished Jul 05 05:46:39 PM PDT 24
Peak memory 196000 kb
Host smart-c16123fd-0edf-4ba4-8dc2-d2497ff07a5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759822146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3759822146
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.2170416795
Short name T417
Test name
Test status
Simulation time 658035005 ps
CPU time 33.76 seconds
Started Jul 05 05:46:34 PM PDT 24
Finished Jul 05 05:47:08 PM PDT 24
Peak memory 200336 kb
Host smart-37bade4f-04e0-436a-b43c-afab19e74268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170416795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.2170416795
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3375357206
Short name T168
Test name
Test status
Simulation time 13883783968 ps
CPU time 1340.76 seconds
Started Jul 05 05:46:35 PM PDT 24
Finished Jul 05 06:08:57 PM PDT 24
Peak memory 749364 kb
Host smart-c1404c85-82df-49f8-a023-a1455743ef78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3375357206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3375357206
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2450623390
Short name T206
Test name
Test status
Simulation time 162946961 ps
CPU time 4.81 seconds
Started Jul 05 05:46:37 PM PDT 24
Finished Jul 05 05:46:43 PM PDT 24
Peak memory 200240 kb
Host smart-149243b1-1043-4f00-8c97-f4274820a957
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450623390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2450623390
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.4143108494
Short name T316
Test name
Test status
Simulation time 13440596258 ps
CPU time 177.34 seconds
Started Jul 05 05:46:35 PM PDT 24
Finished Jul 05 05:49:33 PM PDT 24
Peak memory 200336 kb
Host smart-d15f4b40-aab0-456c-903c-95d8419080c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143108494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.4143108494
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3840072009
Short name T291
Test name
Test status
Simulation time 92301385 ps
CPU time 2.15 seconds
Started Jul 05 05:46:34 PM PDT 24
Finished Jul 05 05:46:37 PM PDT 24
Peak memory 200296 kb
Host smart-b60689f7-e45e-4051-924f-9c0269faaf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840072009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3840072009
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3693092781
Short name T308
Test name
Test status
Simulation time 118066249198 ps
CPU time 194.34 seconds
Started Jul 05 05:46:34 PM PDT 24
Finished Jul 05 05:49:49 PM PDT 24
Peak memory 208576 kb
Host smart-8a74f52c-d408-4df0-8bd3-1b20377acdda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693092781 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3693092781
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.677294604
Short name T263
Test name
Test status
Simulation time 1899638748 ps
CPU time 86.21 seconds
Started Jul 05 05:46:30 PM PDT 24
Finished Jul 05 05:47:57 PM PDT 24
Peak memory 200236 kb
Host smart-c5edc7a8-c393-43e3-bdb8-e552c2251de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677294604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.677294604
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.477710635
Short name T292
Test name
Test status
Simulation time 14999392 ps
CPU time 0.63 seconds
Started Jul 05 05:46:34 PM PDT 24
Finished Jul 05 05:46:36 PM PDT 24
Peak memory 195816 kb
Host smart-5793bf77-3971-45f7-bcb2-5ae60a17c354
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477710635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.477710635
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2595439338
Short name T260
Test name
Test status
Simulation time 1955792640 ps
CPU time 26.74 seconds
Started Jul 05 05:46:33 PM PDT 24
Finished Jul 05 05:47:00 PM PDT 24
Peak memory 200212 kb
Host smart-a8b2a30c-253e-44d3-b60e-4e38355c49b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2595439338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2595439338
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.544993225
Short name T354
Test name
Test status
Simulation time 632138721 ps
CPU time 5.1 seconds
Started Jul 05 05:46:32 PM PDT 24
Finished Jul 05 05:46:38 PM PDT 24
Peak memory 200316 kb
Host smart-bc41b06b-e2fa-4d9b-9649-5aeaf2ea64da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544993225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.544993225
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3248470535
Short name T34
Test name
Test status
Simulation time 25087762068 ps
CPU time 1231.93 seconds
Started Jul 05 05:46:34 PM PDT 24
Finished Jul 05 06:07:07 PM PDT 24
Peak memory 720812 kb
Host smart-ee8cbb9a-b612-4613-8e39-35b71e2856be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3248470535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3248470535
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1051512600
Short name T35
Test name
Test status
Simulation time 189717925 ps
CPU time 2.86 seconds
Started Jul 05 05:46:33 PM PDT 24
Finished Jul 05 05:46:37 PM PDT 24
Peak memory 200216 kb
Host smart-0c5b543d-caf8-457e-bfab-c25fdf7a7176
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051512600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1051512600
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3964176325
Short name T105
Test name
Test status
Simulation time 2642991153 ps
CPU time 35.05 seconds
Started Jul 05 05:46:37 PM PDT 24
Finished Jul 05 05:47:13 PM PDT 24
Peak memory 200292 kb
Host smart-86233b63-ca4c-4697-978b-b55dda84966d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964176325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3964176325
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1297527058
Short name T10
Test name
Test status
Simulation time 390748188 ps
CPU time 4.42 seconds
Started Jul 05 05:46:34 PM PDT 24
Finished Jul 05 05:46:39 PM PDT 24
Peak memory 200332 kb
Host smart-366d0a18-a795-40b0-a98e-5f2f88d22cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297527058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1297527058
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.760032867
Short name T110
Test name
Test status
Simulation time 643765912494 ps
CPU time 3678.56 seconds
Started Jul 05 05:46:35 PM PDT 24
Finished Jul 05 06:47:55 PM PDT 24
Peak memory 804188 kb
Host smart-28fabb76-3fe5-4110-be78-00dbcb3ce545
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760032867 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.760032867
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.52905554
Short name T258
Test name
Test status
Simulation time 20220843465 ps
CPU time 80.98 seconds
Started Jul 05 05:46:34 PM PDT 24
Finished Jul 05 05:47:55 PM PDT 24
Peak memory 200352 kb
Host smart-c57ae185-8f2e-4a48-a29c-eb14354bebd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52905554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.52905554
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.376174015
Short name T356
Test name
Test status
Simulation time 12750441 ps
CPU time 0.62 seconds
Started Jul 05 05:46:42 PM PDT 24
Finished Jul 05 05:46:43 PM PDT 24
Peak memory 196228 kb
Host smart-a0614743-436b-4f32-b8a4-00a310933072
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376174015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.376174015
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3929115118
Short name T392
Test name
Test status
Simulation time 1425739545 ps
CPU time 83.61 seconds
Started Jul 05 05:46:41 PM PDT 24
Finished Jul 05 05:48:06 PM PDT 24
Peak memory 200296 kb
Host smart-83a75e47-5de7-4f9b-bfc7-7418c8420a73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3929115118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3929115118
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1597051988
Short name T468
Test name
Test status
Simulation time 8665613276 ps
CPU time 28.17 seconds
Started Jul 05 05:46:43 PM PDT 24
Finished Jul 05 05:47:11 PM PDT 24
Peak memory 200336 kb
Host smart-4daad716-e296-4934-883f-116b818b49d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597051988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1597051988
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.351621976
Short name T467
Test name
Test status
Simulation time 43024631261 ps
CPU time 836.9 seconds
Started Jul 05 05:46:41 PM PDT 24
Finished Jul 05 06:00:39 PM PDT 24
Peak memory 726668 kb
Host smart-74d7c97f-e7b0-42c3-9068-2061abfd527a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=351621976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.351621976
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3444498000
Short name T446
Test name
Test status
Simulation time 4344042242 ps
CPU time 206.08 seconds
Started Jul 05 05:46:42 PM PDT 24
Finished Jul 05 05:50:08 PM PDT 24
Peak memory 200236 kb
Host smart-ce659a9b-5c4c-4a72-b89f-b4e23f656d87
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444498000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3444498000
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.869532291
Short name T39
Test name
Test status
Simulation time 3839325330 ps
CPU time 46.66 seconds
Started Jul 05 05:46:41 PM PDT 24
Finished Jul 05 05:47:28 PM PDT 24
Peak memory 216584 kb
Host smart-30c6d7b1-798e-4891-879e-44a811fa476f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869532291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.869532291
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1163628708
Short name T202
Test name
Test status
Simulation time 1374954594 ps
CPU time 11.33 seconds
Started Jul 05 05:46:41 PM PDT 24
Finished Jul 05 05:46:53 PM PDT 24
Peak memory 200312 kb
Host smart-b5f991bd-5181-4db9-aa46-aad63eef9b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163628708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1163628708
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3294090217
Short name T422
Test name
Test status
Simulation time 33772535226 ps
CPU time 1879.02 seconds
Started Jul 05 05:46:42 PM PDT 24
Finished Jul 05 06:18:02 PM PDT 24
Peak memory 772256 kb
Host smart-09ea90ac-bb7f-4afb-8aa8-2ca6d2b545a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294090217 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3294090217
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.587383918
Short name T294
Test name
Test status
Simulation time 610709746 ps
CPU time 29.25 seconds
Started Jul 05 05:46:41 PM PDT 24
Finished Jul 05 05:47:11 PM PDT 24
Peak memory 200320 kb
Host smart-107271c7-00cb-43fe-a318-d2c799ca9c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587383918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.587383918
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3368029098
Short name T414
Test name
Test status
Simulation time 70499535 ps
CPU time 0.6 seconds
Started Jul 05 05:46:41 PM PDT 24
Finished Jul 05 05:46:43 PM PDT 24
Peak memory 196232 kb
Host smart-acea1a86-d123-48de-a37b-db306f658612
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368029098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3368029098
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.716057572
Short name T463
Test name
Test status
Simulation time 2211532131 ps
CPU time 66.78 seconds
Started Jul 05 05:46:43 PM PDT 24
Finished Jul 05 05:47:50 PM PDT 24
Peak memory 200332 kb
Host smart-01099cdc-f3a9-4583-bbdb-625cd01cb151
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=716057572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.716057572
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2154815616
Short name T262
Test name
Test status
Simulation time 27844130235 ps
CPU time 60.29 seconds
Started Jul 05 05:46:40 PM PDT 24
Finished Jul 05 05:47:41 PM PDT 24
Peak memory 200372 kb
Host smart-7cd69772-33bf-4757-900b-41d70281769e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154815616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2154815616
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1687064114
Short name T518
Test name
Test status
Simulation time 839677010 ps
CPU time 154.96 seconds
Started Jul 05 05:46:42 PM PDT 24
Finished Jul 05 05:49:18 PM PDT 24
Peak memory 572456 kb
Host smart-0fb56e58-8815-444e-82ba-32e44b81b593
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1687064114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1687064114
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2990137095
Short name T347
Test name
Test status
Simulation time 755991798 ps
CPU time 43.56 seconds
Started Jul 05 05:46:41 PM PDT 24
Finished Jul 05 05:47:26 PM PDT 24
Peak memory 200252 kb
Host smart-e139df23-cb77-472a-b984-b2dd2207c6fe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990137095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2990137095
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3791393270
Short name T276
Test name
Test status
Simulation time 3410829416 ps
CPU time 149.57 seconds
Started Jul 05 05:46:45 PM PDT 24
Finished Jul 05 05:49:15 PM PDT 24
Peak memory 200368 kb
Host smart-4ee313b4-91de-4327-a208-17ad113e1658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791393270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3791393270
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1495640332
Short name T271
Test name
Test status
Simulation time 785331228 ps
CPU time 5.37 seconds
Started Jul 05 05:46:45 PM PDT 24
Finished Jul 05 05:46:51 PM PDT 24
Peak memory 200268 kb
Host smart-818470c7-79a3-45ce-9a2d-0bf3f5840b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495640332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1495640332
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2311762393
Short name T407
Test name
Test status
Simulation time 131230043496 ps
CPU time 1625.08 seconds
Started Jul 05 05:46:45 PM PDT 24
Finished Jul 05 06:13:50 PM PDT 24
Peak memory 692924 kb
Host smart-77103b9a-e8f7-423c-aedb-6d1c0528c3ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311762393 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2311762393
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1512133752
Short name T97
Test name
Test status
Simulation time 5106453269 ps
CPU time 45.41 seconds
Started Jul 05 05:46:45 PM PDT 24
Finished Jul 05 05:47:31 PM PDT 24
Peak memory 200380 kb
Host smart-11b9f102-7050-4371-993a-67ffe3560a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512133752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1512133752
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.262609494
Short name T171
Test name
Test status
Simulation time 13767539 ps
CPU time 0.6 seconds
Started Jul 05 05:45:31 PM PDT 24
Finished Jul 05 05:45:32 PM PDT 24
Peak memory 196876 kb
Host smart-ac947437-bc90-49b8-abe0-e1f732bad7dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262609494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.262609494
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3912825042
Short name T95
Test name
Test status
Simulation time 149625080 ps
CPU time 5.36 seconds
Started Jul 05 05:45:31 PM PDT 24
Finished Jul 05 05:45:36 PM PDT 24
Peak memory 200216 kb
Host smart-f08ce62d-6ee8-4632-988d-c324bc49a434
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3912825042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3912825042
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.2491377419
Short name T416
Test name
Test status
Simulation time 1926312973 ps
CPU time 26.49 seconds
Started Jul 05 05:45:30 PM PDT 24
Finished Jul 05 05:45:57 PM PDT 24
Peak memory 200324 kb
Host smart-1fc8ed48-7e8d-4d93-a1ea-e09e0efdfc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491377419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2491377419
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3478780643
Short name T211
Test name
Test status
Simulation time 22517305652 ps
CPU time 392.42 seconds
Started Jul 05 05:45:31 PM PDT 24
Finished Jul 05 05:52:04 PM PDT 24
Peak memory 609552 kb
Host smart-5183e7d0-7b89-4d0b-990f-16306ae13783
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3478780643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3478780643
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3201184554
Short name T7
Test name
Test status
Simulation time 10406396977 ps
CPU time 49.21 seconds
Started Jul 05 05:45:33 PM PDT 24
Finished Jul 05 05:46:22 PM PDT 24
Peak memory 200404 kb
Host smart-db72576c-7512-450c-8f13-c4b9e988d143
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201184554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3201184554
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1150774581
Short name T471
Test name
Test status
Simulation time 1991732113 ps
CPU time 81.41 seconds
Started Jul 05 05:45:25 PM PDT 24
Finished Jul 05 05:46:47 PM PDT 24
Peak memory 200260 kb
Host smart-7d8f5783-93c1-4d51-bd65-fcb9bc207ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150774581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1150774581
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1989811645
Short name T61
Test name
Test status
Simulation time 36749271 ps
CPU time 0.84 seconds
Started Jul 05 05:45:27 PM PDT 24
Finished Jul 05 05:45:29 PM PDT 24
Peak memory 218464 kb
Host smart-ae89bf5a-0670-4a0f-b1e8-7517ea829fc1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989811645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1989811645
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.661621368
Short name T512
Test name
Test status
Simulation time 2719925060 ps
CPU time 8.49 seconds
Started Jul 05 05:45:22 PM PDT 24
Finished Jul 05 05:45:31 PM PDT 24
Peak memory 200356 kb
Host smart-63a91e04-74e3-40a3-ada3-0f58cbae12a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661621368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.661621368
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.562580945
Short name T360
Test name
Test status
Simulation time 109490524482 ps
CPU time 1452.18 seconds
Started Jul 05 05:45:32 PM PDT 24
Finished Jul 05 06:09:45 PM PDT 24
Peak memory 697224 kb
Host smart-34ca45d7-e7b8-415c-9324-d81abb02abd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562580945 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.562580945
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.2565974825
Short name T18
Test name
Test status
Simulation time 47468193463 ps
CPU time 360.28 seconds
Started Jul 05 05:45:32 PM PDT 24
Finished Jul 05 05:51:33 PM PDT 24
Peak memory 476140 kb
Host smart-12dd3b33-c621-41d5-b0f4-1594e9b874c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2565974825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.2565974825
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.1723677683
Short name T253
Test name
Test status
Simulation time 17137516015 ps
CPU time 68.17 seconds
Started Jul 05 05:45:31 PM PDT 24
Finished Jul 05 05:46:40 PM PDT 24
Peak memory 200416 kb
Host smart-3a8a3b86-0e95-42e7-b067-50dba03b9049
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1723677683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.1723677683
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.4214572437
Short name T474
Test name
Test status
Simulation time 4662054550 ps
CPU time 60.43 seconds
Started Jul 05 05:45:32 PM PDT 24
Finished Jul 05 05:46:33 PM PDT 24
Peak memory 200368 kb
Host smart-45ac1911-e6e5-40dc-9add-ac4e8e2e7921
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4214572437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.4214572437
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.631608402
Short name T353
Test name
Test status
Simulation time 4882444146 ps
CPU time 77.43 seconds
Started Jul 05 05:45:30 PM PDT 24
Finished Jul 05 05:46:48 PM PDT 24
Peak memory 200380 kb
Host smart-ce3bc5e4-26ff-44c2-b8e2-594038164594
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=631608402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.631608402
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.1352202427
Short name T455
Test name
Test status
Simulation time 49426119073 ps
CPU time 658.67 seconds
Started Jul 05 05:45:33 PM PDT 24
Finished Jul 05 05:56:32 PM PDT 24
Peak memory 200424 kb
Host smart-8348d283-a863-4b67-afa7-2aec3e2b83e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1352202427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.1352202427
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.3503263677
Short name T401
Test name
Test status
Simulation time 78738894404 ps
CPU time 2134.85 seconds
Started Jul 05 05:45:33 PM PDT 24
Finished Jul 05 06:21:09 PM PDT 24
Peak memory 216324 kb
Host smart-d2590dbc-42b7-4019-aca1-3a34409eb844
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3503263677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.3503263677
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.446893507
Short name T349
Test name
Test status
Simulation time 769464601502 ps
CPU time 2410.62 seconds
Started Jul 05 05:45:28 PM PDT 24
Finished Jul 05 06:25:40 PM PDT 24
Peak memory 216244 kb
Host smart-4c8da387-173c-458c-8ed3-fef5354280e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=446893507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.446893507
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.336351910
Short name T111
Test name
Test status
Simulation time 1387541052 ps
CPU time 57.77 seconds
Started Jul 05 05:45:32 PM PDT 24
Finished Jul 05 05:46:30 PM PDT 24
Peak memory 200320 kb
Host smart-00b5a72a-8b5e-45da-b6d4-b738837eface
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336351910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.336351910
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.4129280312
Short name T450
Test name
Test status
Simulation time 45778627 ps
CPU time 0.6 seconds
Started Jul 05 05:46:47 PM PDT 24
Finished Jul 05 05:46:47 PM PDT 24
Peak memory 196200 kb
Host smart-a72b0437-ae19-4db8-bb2c-c47dda3ee5e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129280312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.4129280312
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1785198204
Short name T203
Test name
Test status
Simulation time 6524792522 ps
CPU time 84.08 seconds
Started Jul 05 05:46:45 PM PDT 24
Finished Jul 05 05:48:10 PM PDT 24
Peak memory 200368 kb
Host smart-2319d5df-ab32-4999-9c18-4b641c80eec4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1785198204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1785198204
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.106943382
Short name T230
Test name
Test status
Simulation time 3068559247 ps
CPU time 56.04 seconds
Started Jul 05 05:46:39 PM PDT 24
Finished Jul 05 05:47:36 PM PDT 24
Peak memory 200384 kb
Host smart-c3c02084-6ae7-420c-8b89-1cca9e40e5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106943382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.106943382
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1108551678
Short name T282
Test name
Test status
Simulation time 4273410337 ps
CPU time 798.03 seconds
Started Jul 05 05:46:42 PM PDT 24
Finished Jul 05 06:00:00 PM PDT 24
Peak memory 735112 kb
Host smart-af68bf3b-20e3-47cd-98c2-dca494d0930a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1108551678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1108551678
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1539077268
Short name T384
Test name
Test status
Simulation time 30892136428 ps
CPU time 119.39 seconds
Started Jul 05 05:46:41 PM PDT 24
Finished Jul 05 05:48:41 PM PDT 24
Peak memory 200260 kb
Host smart-1c650f38-c86b-4d56-b471-287282b944fd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539077268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1539077268
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1126839053
Short name T183
Test name
Test status
Simulation time 13631730665 ps
CPU time 64.44 seconds
Started Jul 05 05:46:43 PM PDT 24
Finished Jul 05 05:47:48 PM PDT 24
Peak memory 200416 kb
Host smart-ced6d1e4-2049-4846-9de4-596331749ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126839053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1126839053
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.741339431
Short name T151
Test name
Test status
Simulation time 79355822 ps
CPU time 1.39 seconds
Started Jul 05 05:46:43 PM PDT 24
Finished Jul 05 05:46:45 PM PDT 24
Peak memory 200244 kb
Host smart-f4948e47-15dd-41ea-b5e7-5009beaa6f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741339431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.741339431
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.197247575
Short name T59
Test name
Test status
Simulation time 38953557871 ps
CPU time 1421.58 seconds
Started Jul 05 05:46:51 PM PDT 24
Finished Jul 05 06:10:33 PM PDT 24
Peak memory 767848 kb
Host smart-29e441dd-28ea-402e-bbdc-5bfa43ccde28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197247575 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.197247575
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2388766281
Short name T107
Test name
Test status
Simulation time 7770473521 ps
CPU time 89.97 seconds
Started Jul 05 05:46:50 PM PDT 24
Finished Jul 05 05:48:21 PM PDT 24
Peak memory 200332 kb
Host smart-4f4b891e-9cd2-45f1-9de8-6db0124d251b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388766281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2388766281
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2550738600
Short name T477
Test name
Test status
Simulation time 41188930 ps
CPU time 0.57 seconds
Started Jul 05 05:46:48 PM PDT 24
Finished Jul 05 05:46:49 PM PDT 24
Peak memory 195808 kb
Host smart-4318dba9-62f0-49b6-8c77-de6e784381df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550738600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2550738600
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3828621578
Short name T189
Test name
Test status
Simulation time 1897345414 ps
CPU time 110.51 seconds
Started Jul 05 05:46:49 PM PDT 24
Finished Jul 05 05:48:40 PM PDT 24
Peak memory 200304 kb
Host smart-ebdd73b5-9c07-4192-bd74-2c45e7379e1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3828621578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3828621578
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2404862817
Short name T250
Test name
Test status
Simulation time 1716429433 ps
CPU time 48.7 seconds
Started Jul 05 05:46:49 PM PDT 24
Finished Jul 05 05:47:38 PM PDT 24
Peak memory 200340 kb
Host smart-139d6aab-0e89-498b-acb6-be21d78a3d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404862817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2404862817
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.4088585158
Short name T415
Test name
Test status
Simulation time 3906560490 ps
CPU time 717.99 seconds
Started Jul 05 05:46:49 PM PDT 24
Finished Jul 05 05:58:47 PM PDT 24
Peak memory 733672 kb
Host smart-b382c35f-f6a6-42c4-978d-ccdddb1bfbe6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4088585158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.4088585158
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.2483283278
Short name T79
Test name
Test status
Simulation time 2494477263 ps
CPU time 36.4 seconds
Started Jul 05 05:46:48 PM PDT 24
Finished Jul 05 05:47:25 PM PDT 24
Peak memory 200400 kb
Host smart-eb8b68b0-a083-4ce4-87da-f357a50a6fca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483283278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.2483283278
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.2600801824
Short name T239
Test name
Test status
Simulation time 5035718892 ps
CPU time 66.69 seconds
Started Jul 05 05:46:50 PM PDT 24
Finished Jul 05 05:47:57 PM PDT 24
Peak memory 200352 kb
Host smart-035acf4f-e230-41b2-9a39-9f874ec474ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600801824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2600801824
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.1834770107
Short name T430
Test name
Test status
Simulation time 798412106 ps
CPU time 2.38 seconds
Started Jul 05 05:46:50 PM PDT 24
Finished Jul 05 05:46:53 PM PDT 24
Peak memory 200316 kb
Host smart-458f9337-4314-4f6f-bfa4-ae951a16ca29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834770107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.1834770107
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.493051911
Short name T298
Test name
Test status
Simulation time 11598271381 ps
CPU time 64.36 seconds
Started Jul 05 05:46:48 PM PDT 24
Finished Jul 05 05:47:53 PM PDT 24
Peak memory 200368 kb
Host smart-251da7d7-3b30-4d0e-ab1b-75605407b8d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493051911 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.493051911
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.284529131
Short name T423
Test name
Test status
Simulation time 5906364012 ps
CPU time 17.06 seconds
Started Jul 05 05:46:51 PM PDT 24
Finished Jul 05 05:47:08 PM PDT 24
Peak memory 200372 kb
Host smart-48a9fe14-a545-47fb-8ac2-cf23aecae88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284529131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.284529131
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.125201336
Short name T1
Test name
Test status
Simulation time 35712187 ps
CPU time 0.59 seconds
Started Jul 05 05:46:59 PM PDT 24
Finished Jul 05 05:47:00 PM PDT 24
Peak memory 195188 kb
Host smart-336b3857-8106-42c0-ab42-5cb21027f24e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125201336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.125201336
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3158603695
Short name T243
Test name
Test status
Simulation time 3743561134 ps
CPU time 27.15 seconds
Started Jul 05 05:46:49 PM PDT 24
Finished Jul 05 05:47:17 PM PDT 24
Peak memory 200392 kb
Host smart-36897bac-7542-4225-9092-50695eb8dc78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3158603695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3158603695
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3360792341
Short name T138
Test name
Test status
Simulation time 1777053192 ps
CPU time 16.01 seconds
Started Jul 05 05:46:51 PM PDT 24
Finished Jul 05 05:47:07 PM PDT 24
Peak memory 200320 kb
Host smart-4eefed2e-489d-4b5d-9f35-6e0d6075afac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360792341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3360792341
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.375290022
Short name T340
Test name
Test status
Simulation time 2409862344 ps
CPU time 378.85 seconds
Started Jul 05 05:46:49 PM PDT 24
Finished Jul 05 05:53:09 PM PDT 24
Peak memory 620856 kb
Host smart-49055a91-3f51-4b31-a825-270a84298970
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=375290022 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.375290022
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1403782571
Short name T523
Test name
Test status
Simulation time 697710190 ps
CPU time 12.09 seconds
Started Jul 05 05:46:48 PM PDT 24
Finished Jul 05 05:47:01 PM PDT 24
Peak memory 200180 kb
Host smart-340ae0fb-83e5-4fe1-a84b-5c2befadd027
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403782571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1403782571
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1030134311
Short name T275
Test name
Test status
Simulation time 3299255467 ps
CPU time 28.21 seconds
Started Jul 05 05:46:49 PM PDT 24
Finished Jul 05 05:47:17 PM PDT 24
Peak memory 200384 kb
Host smart-c173146f-363e-41ab-bffb-d9e1f93b853b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030134311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1030134311
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.584332367
Short name T149
Test name
Test status
Simulation time 154823943 ps
CPU time 7.52 seconds
Started Jul 05 05:46:50 PM PDT 24
Finished Jul 05 05:46:57 PM PDT 24
Peak memory 200332 kb
Host smart-dab1d094-647e-46d5-9276-fa0d13507de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584332367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.584332367
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.821995950
Short name T83
Test name
Test status
Simulation time 146375293737 ps
CPU time 1381.06 seconds
Started Jul 05 05:46:57 PM PDT 24
Finished Jul 05 06:09:59 PM PDT 24
Peak memory 744524 kb
Host smart-4b67edb2-3bd1-461d-afb0-db1009ced395
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821995950 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.821995950
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.2789669811
Short name T278
Test name
Test status
Simulation time 41531843416 ps
CPU time 105.54 seconds
Started Jul 05 05:46:48 PM PDT 24
Finished Jul 05 05:48:33 PM PDT 24
Peak memory 200360 kb
Host smart-fabe8f25-9078-4906-a16a-8f42d936fde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789669811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2789669811
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.3868843159
Short name T254
Test name
Test status
Simulation time 11057101 ps
CPU time 0.59 seconds
Started Jul 05 05:46:56 PM PDT 24
Finished Jul 05 05:46:57 PM PDT 24
Peak memory 195876 kb
Host smart-e808a196-6d67-41ca-bbaa-0fb9e7c2cc7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868843159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3868843159
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.1680395647
Short name T451
Test name
Test status
Simulation time 808527136 ps
CPU time 47.71 seconds
Started Jul 05 05:46:59 PM PDT 24
Finished Jul 05 05:47:47 PM PDT 24
Peak memory 200372 kb
Host smart-e23debe8-3a90-4dfd-9550-579a065df8ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1680395647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1680395647
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1905687525
Short name T283
Test name
Test status
Simulation time 757090325 ps
CPU time 21.14 seconds
Started Jul 05 05:47:10 PM PDT 24
Finished Jul 05 05:47:31 PM PDT 24
Peak memory 200312 kb
Host smart-7eb92281-fd04-43fa-a397-68e2653091f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905687525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1905687525
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_error.1239735396
Short name T516
Test name
Test status
Simulation time 8497926736 ps
CPU time 113.57 seconds
Started Jul 05 05:46:58 PM PDT 24
Finished Jul 05 05:48:52 PM PDT 24
Peak memory 200404 kb
Host smart-dff56b59-ed63-430c-95fc-564d7ae9603b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239735396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1239735396
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3257314705
Short name T101
Test name
Test status
Simulation time 2262816694 ps
CPU time 117.59 seconds
Started Jul 05 05:47:10 PM PDT 24
Finished Jul 05 05:49:08 PM PDT 24
Peak memory 200432 kb
Host smart-0750a50c-1ada-49fe-b9e9-3fb75fe03ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257314705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3257314705
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1054437881
Short name T174
Test name
Test status
Simulation time 3016484526 ps
CPU time 10.36 seconds
Started Jul 05 05:47:00 PM PDT 24
Finished Jul 05 05:47:11 PM PDT 24
Peak memory 200376 kb
Host smart-963419e3-6d24-486d-9956-bcc6a2999935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054437881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1054437881
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.1284200404
Short name T485
Test name
Test status
Simulation time 121958037586 ps
CPU time 1605.94 seconds
Started Jul 05 05:46:59 PM PDT 24
Finished Jul 05 06:13:46 PM PDT 24
Peak memory 438424 kb
Host smart-7725fee8-7b48-48f5-94ef-d99fbbc55f95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284200404 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1284200404
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2418559707
Short name T504
Test name
Test status
Simulation time 2840786452 ps
CPU time 143.92 seconds
Started Jul 05 05:46:58 PM PDT 24
Finished Jul 05 05:49:23 PM PDT 24
Peak memory 200376 kb
Host smart-70d92c04-f402-4af6-a858-663977e7d0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418559707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2418559707
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3974398678
Short name T319
Test name
Test status
Simulation time 14300709 ps
CPU time 0.64 seconds
Started Jul 05 05:46:58 PM PDT 24
Finished Jul 05 05:46:59 PM PDT 24
Peak memory 196100 kb
Host smart-705fef38-0d0e-4829-9216-4400992aea96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974398678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3974398678
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1849625178
Short name T461
Test name
Test status
Simulation time 94586360 ps
CPU time 5.45 seconds
Started Jul 05 05:46:57 PM PDT 24
Finished Jul 05 05:47:03 PM PDT 24
Peak memory 200256 kb
Host smart-47d4ee14-525c-4afa-8466-c664dbf5fcd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1849625178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1849625178
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2148207924
Short name T156
Test name
Test status
Simulation time 2523917280 ps
CPU time 35.11 seconds
Started Jul 05 05:46:56 PM PDT 24
Finished Jul 05 05:47:32 PM PDT 24
Peak memory 200304 kb
Host smart-079379eb-4eb6-4c82-9028-0d3ce53493b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148207924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2148207924
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.2895498637
Short name T441
Test name
Test status
Simulation time 2359545680 ps
CPU time 410.09 seconds
Started Jul 05 05:47:01 PM PDT 24
Finished Jul 05 05:53:52 PM PDT 24
Peak memory 676492 kb
Host smart-6bd77601-850e-428c-aba3-f4c8ff8b6477
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2895498637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2895498637
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.753824977
Short name T186
Test name
Test status
Simulation time 18708336564 ps
CPU time 87.94 seconds
Started Jul 05 05:47:00 PM PDT 24
Finished Jul 05 05:48:28 PM PDT 24
Peak memory 200360 kb
Host smart-40bd04b0-5dbe-4557-9d1b-0ffc1e7926c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753824977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.753824977
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.2527694879
Short name T327
Test name
Test status
Simulation time 12668907902 ps
CPU time 168.88 seconds
Started Jul 05 05:47:02 PM PDT 24
Finished Jul 05 05:49:51 PM PDT 24
Peak memory 200380 kb
Host smart-6b8d9165-95e4-4057-a546-1368d6deba03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527694879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.2527694879
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3073297054
Short name T182
Test name
Test status
Simulation time 630040538 ps
CPU time 4.2 seconds
Started Jul 05 05:47:10 PM PDT 24
Finished Jul 05 05:47:14 PM PDT 24
Peak memory 200364 kb
Host smart-76f35d82-2395-4ce9-8caf-d53fe816b500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073297054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3073297054
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1985390657
Short name T355
Test name
Test status
Simulation time 28645625733 ps
CPU time 497.24 seconds
Started Jul 05 05:46:56 PM PDT 24
Finished Jul 05 05:55:13 PM PDT 24
Peak memory 200364 kb
Host smart-c889d3b4-8dd9-4ad6-b2d9-0750a998e816
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985390657 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1985390657
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2045362822
Short name T460
Test name
Test status
Simulation time 14432919078 ps
CPU time 21.91 seconds
Started Jul 05 05:46:58 PM PDT 24
Finished Jul 05 05:47:20 PM PDT 24
Peak memory 200356 kb
Host smart-643719c4-257c-4ed5-8a87-c6c4a62c4f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045362822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2045362822
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3929357138
Short name T337
Test name
Test status
Simulation time 11904321 ps
CPU time 0.61 seconds
Started Jul 05 05:47:12 PM PDT 24
Finished Jul 05 05:47:13 PM PDT 24
Peak memory 196880 kb
Host smart-1080ee8f-7ab4-45b5-9d6e-4402334f051f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929357138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3929357138
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2830996045
Short name T47
Test name
Test status
Simulation time 710232883 ps
CPU time 40.49 seconds
Started Jul 05 05:46:58 PM PDT 24
Finished Jul 05 05:47:39 PM PDT 24
Peak memory 200300 kb
Host smart-6a043f1b-a6eb-4b4d-bfec-ade6f71abcd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2830996045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2830996045
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.101693815
Short name T509
Test name
Test status
Simulation time 722011619 ps
CPU time 11.61 seconds
Started Jul 05 05:47:05 PM PDT 24
Finished Jul 05 05:47:18 PM PDT 24
Peak memory 200328 kb
Host smart-37009c03-1a70-4bf8-a58c-35bfa1b3a3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101693815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.101693815
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1740826438
Short name T133
Test name
Test status
Simulation time 5900694883 ps
CPU time 1042.33 seconds
Started Jul 05 05:46:57 PM PDT 24
Finished Jul 05 06:04:20 PM PDT 24
Peak memory 694880 kb
Host smart-4fd7b64c-0a11-4cb1-b8e0-7f0dea5d3b40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1740826438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1740826438
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1593600418
Short name T56
Test name
Test status
Simulation time 6696310832 ps
CPU time 97.23 seconds
Started Jul 05 05:47:06 PM PDT 24
Finished Jul 05 05:48:43 PM PDT 24
Peak memory 200332 kb
Host smart-4f5339ec-4491-410e-a7ca-d228de1ee734
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593600418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1593600418
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.251914302
Short name T73
Test name
Test status
Simulation time 6122434722 ps
CPU time 9.96 seconds
Started Jul 05 05:46:58 PM PDT 24
Finished Jul 05 05:47:08 PM PDT 24
Peak memory 200352 kb
Host smart-da549842-abce-44a6-9356-48e2f5fddb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251914302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.251914302
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3323495227
Short name T77
Test name
Test status
Simulation time 2226777175 ps
CPU time 9.74 seconds
Started Jul 05 05:47:01 PM PDT 24
Finished Jul 05 05:47:11 PM PDT 24
Peak memory 200368 kb
Host smart-82a6548f-bc3c-46d6-9ad6-7759e28e0de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323495227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3323495227
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.614438641
Short name T290
Test name
Test status
Simulation time 199750848894 ps
CPU time 838.82 seconds
Started Jul 05 05:47:12 PM PDT 24
Finished Jul 05 06:01:12 PM PDT 24
Peak memory 200380 kb
Host smart-75d6ea71-4406-4f03-b3a8-8877cd58b69e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614438641 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.614438641
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.576978721
Short name T380
Test name
Test status
Simulation time 9247325898 ps
CPU time 104.37 seconds
Started Jul 05 05:47:09 PM PDT 24
Finished Jul 05 05:48:53 PM PDT 24
Peak memory 200420 kb
Host smart-c2b0e98f-a49a-4b63-9c4a-e3ee34fbb484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576978721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.576978721
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3474653848
Short name T508
Test name
Test status
Simulation time 14747768 ps
CPU time 0.65 seconds
Started Jul 05 05:47:11 PM PDT 24
Finished Jul 05 05:47:12 PM PDT 24
Peak memory 196888 kb
Host smart-468bd799-cd24-47b8-9162-8dcd54796fa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474653848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3474653848
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3574074444
Short name T251
Test name
Test status
Simulation time 468694128 ps
CPU time 13.38 seconds
Started Jul 05 05:47:07 PM PDT 24
Finished Jul 05 05:47:21 PM PDT 24
Peak memory 200316 kb
Host smart-6e0b1dba-b698-4456-a4ad-374cbdc44e01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3574074444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3574074444
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.3292628243
Short name T524
Test name
Test status
Simulation time 11599717982 ps
CPU time 46.19 seconds
Started Jul 05 05:47:05 PM PDT 24
Finished Jul 05 05:47:52 PM PDT 24
Peak memory 200376 kb
Host smart-f7f74f6b-9e4f-49f2-be67-b6182cee1bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292628243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3292628243
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2251370293
Short name T300
Test name
Test status
Simulation time 3812417412 ps
CPU time 587.07 seconds
Started Jul 05 05:47:05 PM PDT 24
Finished Jul 05 05:56:53 PM PDT 24
Peak memory 468620 kb
Host smart-0a6e2de0-c98d-4f87-803f-5d68bcbebf25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2251370293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2251370293
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.177815711
Short name T55
Test name
Test status
Simulation time 53222437071 ps
CPU time 137.99 seconds
Started Jul 05 05:47:11 PM PDT 24
Finished Jul 05 05:49:29 PM PDT 24
Peak memory 200332 kb
Host smart-fa0b8344-129c-47e8-9dda-98c6e38a3327
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177815711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.177815711
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1637245716
Short name T306
Test name
Test status
Simulation time 2406647357 ps
CPU time 30.77 seconds
Started Jul 05 05:47:11 PM PDT 24
Finished Jul 05 05:47:42 PM PDT 24
Peak memory 200384 kb
Host smart-75440b31-622b-4073-898f-09fe7160a471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637245716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1637245716
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2089026007
Short name T368
Test name
Test status
Simulation time 280276889 ps
CPU time 12.3 seconds
Started Jul 05 05:47:05 PM PDT 24
Finished Jul 05 05:47:18 PM PDT 24
Peak memory 200244 kb
Host smart-b818153f-56af-4061-9d51-5f30c8039f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089026007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2089026007
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2271475727
Short name T44
Test name
Test status
Simulation time 20294099503 ps
CPU time 2299.71 seconds
Started Jul 05 05:47:05 PM PDT 24
Finished Jul 05 06:25:26 PM PDT 24
Peak memory 778364 kb
Host smart-07bf43ec-db15-47fb-872e-53eaed0c3e1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271475727 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2271475727
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1599940263
Short name T137
Test name
Test status
Simulation time 3965503641 ps
CPU time 86.14 seconds
Started Jul 05 05:47:05 PM PDT 24
Finished Jul 05 05:48:32 PM PDT 24
Peak memory 200288 kb
Host smart-e19762a7-b6d4-419a-b408-79909e2784a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599940263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1599940263
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2132843011
Short name T402
Test name
Test status
Simulation time 10712575 ps
CPU time 0.56 seconds
Started Jul 05 05:47:12 PM PDT 24
Finished Jul 05 05:47:13 PM PDT 24
Peak memory 195172 kb
Host smart-8474a421-29cc-47b4-9dd7-7332eb2a3081
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132843011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2132843011
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.4227858321
Short name T233
Test name
Test status
Simulation time 1192648931 ps
CPU time 60.64 seconds
Started Jul 05 05:47:04 PM PDT 24
Finished Jul 05 05:48:05 PM PDT 24
Peak memory 200332 kb
Host smart-44245450-8c4c-4be3-a137-1e857db73980
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4227858321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.4227858321
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.453759605
Short name T265
Test name
Test status
Simulation time 55180176358 ps
CPU time 38.55 seconds
Started Jul 05 05:47:10 PM PDT 24
Finished Jul 05 05:47:49 PM PDT 24
Peak memory 216000 kb
Host smart-0d2f3198-eb7d-46e9-9813-4df05d8e4a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453759605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.453759605
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2517327440
Short name T324
Test name
Test status
Simulation time 764353770 ps
CPU time 24.57 seconds
Started Jul 05 05:47:08 PM PDT 24
Finished Jul 05 05:47:33 PM PDT 24
Peak memory 243760 kb
Host smart-203f5d10-809f-4b2c-a616-ec81a9e21fb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2517327440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2517327440
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3379215897
Short name T185
Test name
Test status
Simulation time 12088315501 ps
CPU time 184.4 seconds
Started Jul 05 05:47:06 PM PDT 24
Finished Jul 05 05:50:11 PM PDT 24
Peak memory 200352 kb
Host smart-83b9b399-1af7-4f7f-b727-47513027658d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379215897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3379215897
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.4043324230
Short name T387
Test name
Test status
Simulation time 1838931715 ps
CPU time 24.52 seconds
Started Jul 05 05:47:12 PM PDT 24
Finished Jul 05 05:47:37 PM PDT 24
Peak memory 200312 kb
Host smart-7ba2c195-037d-4fd5-808f-c3f33eb3e4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043324230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.4043324230
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2668681421
Short name T187
Test name
Test status
Simulation time 162322959 ps
CPU time 2.95 seconds
Started Jul 05 05:47:05 PM PDT 24
Finished Jul 05 05:47:08 PM PDT 24
Peak memory 200276 kb
Host smart-4f68e763-3570-4429-8568-d97584319ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668681421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2668681421
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2751051536
Short name T494
Test name
Test status
Simulation time 19532664523 ps
CPU time 1059.25 seconds
Started Jul 05 05:47:06 PM PDT 24
Finished Jul 05 06:04:46 PM PDT 24
Peak memory 200368 kb
Host smart-f1edf348-24b3-4085-8510-2520ef64f244
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751051536 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2751051536
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3730584400
Short name T391
Test name
Test status
Simulation time 4789008628 ps
CPU time 83.61 seconds
Started Jul 05 05:47:06 PM PDT 24
Finished Jul 05 05:48:30 PM PDT 24
Peak memory 200316 kb
Host smart-d099faae-fb26-4838-9c4c-5dff084ab44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730584400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3730584400
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2813537241
Short name T452
Test name
Test status
Simulation time 13448321 ps
CPU time 0.58 seconds
Started Jul 05 05:47:04 PM PDT 24
Finished Jul 05 05:47:05 PM PDT 24
Peak memory 195088 kb
Host smart-b6a7fc68-fcfa-4773-9799-752520eae7fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813537241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2813537241
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.4159202629
Short name T314
Test name
Test status
Simulation time 4041885421 ps
CPU time 54.02 seconds
Started Jul 05 05:47:12 PM PDT 24
Finished Jul 05 05:48:07 PM PDT 24
Peak memory 200388 kb
Host smart-338c93eb-7c47-4c7a-9e56-7a39f9d38ae1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4159202629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.4159202629
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.312651751
Short name T228
Test name
Test status
Simulation time 2004662074 ps
CPU time 50.89 seconds
Started Jul 05 05:47:07 PM PDT 24
Finished Jul 05 05:47:58 PM PDT 24
Peak memory 200316 kb
Host smart-f30157ce-3141-4001-b327-9c72e2e21114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312651751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.312651751
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3904410751
Short name T437
Test name
Test status
Simulation time 20152312921 ps
CPU time 775.53 seconds
Started Jul 05 05:47:05 PM PDT 24
Finished Jul 05 06:00:01 PM PDT 24
Peak memory 640660 kb
Host smart-9ccb7aab-a4fb-4d75-bd3b-a0aec8883067
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3904410751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3904410751
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3085735282
Short name T428
Test name
Test status
Simulation time 16513382585 ps
CPU time 76.8 seconds
Started Jul 05 05:47:07 PM PDT 24
Finished Jul 05 05:48:24 PM PDT 24
Peak memory 200360 kb
Host smart-08365a2d-caf4-41c9-8319-c2ee3e2c5612
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085735282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3085735282
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3040679786
Short name T399
Test name
Test status
Simulation time 485428384 ps
CPU time 28.08 seconds
Started Jul 05 05:47:10 PM PDT 24
Finished Jul 05 05:47:39 PM PDT 24
Peak memory 200356 kb
Host smart-7cb951f4-197a-43a2-a5aa-9a8c2d48ad74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040679786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3040679786
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1171822784
Short name T150
Test name
Test status
Simulation time 191366033 ps
CPU time 3.93 seconds
Started Jul 05 05:47:01 PM PDT 24
Finished Jul 05 05:47:06 PM PDT 24
Peak memory 200292 kb
Host smart-9b29d369-5fa0-4d8c-8092-2bdbd9da76ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171822784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1171822784
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.2901084756
Short name T33
Test name
Test status
Simulation time 17351522866 ps
CPU time 3007.46 seconds
Started Jul 05 05:47:11 PM PDT 24
Finished Jul 05 06:37:19 PM PDT 24
Peak memory 820576 kb
Host smart-f6b31501-7a4b-404c-b51d-ac1a8228dc6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901084756 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2901084756
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2471598260
Short name T108
Test name
Test status
Simulation time 6275300245 ps
CPU time 110.22 seconds
Started Jul 05 05:47:07 PM PDT 24
Finished Jul 05 05:48:58 PM PDT 24
Peak memory 200284 kb
Host smart-977167f9-dee5-4680-b8be-ad12ebd34289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471598260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2471598260
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3913355288
Short name T432
Test name
Test status
Simulation time 36440933 ps
CPU time 0.6 seconds
Started Jul 05 05:47:15 PM PDT 24
Finished Jul 05 05:47:16 PM PDT 24
Peak memory 196180 kb
Host smart-c67bbdef-2545-4999-86e6-a9b5aef480cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913355288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3913355288
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2139772536
Short name T476
Test name
Test status
Simulation time 2925050521 ps
CPU time 33.17 seconds
Started Jul 05 05:47:04 PM PDT 24
Finished Jul 05 05:47:38 PM PDT 24
Peak memory 200252 kb
Host smart-933ba9b3-64fe-47ef-8371-b47c7441ae6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2139772536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2139772536
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3281323417
Short name T158
Test name
Test status
Simulation time 2647904107 ps
CPU time 35.29 seconds
Started Jul 05 05:47:17 PM PDT 24
Finished Jul 05 05:47:53 PM PDT 24
Peak memory 200428 kb
Host smart-d4059d60-6a38-4b48-b4dc-ee9c720f51bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281323417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3281323417
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.850941241
Short name T295
Test name
Test status
Simulation time 6602068444 ps
CPU time 676.19 seconds
Started Jul 05 05:47:17 PM PDT 24
Finished Jul 05 05:58:34 PM PDT 24
Peak memory 720824 kb
Host smart-9836bd77-199e-47f4-9cf8-469d1b50d106
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=850941241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.850941241
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.2068672926
Short name T169
Test name
Test status
Simulation time 2470060519 ps
CPU time 10.23 seconds
Started Jul 05 05:47:12 PM PDT 24
Finished Jul 05 05:47:23 PM PDT 24
Peak memory 200352 kb
Host smart-822c4302-c982-452c-8cda-27e8375be5bd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068672926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.2068672926
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.4078265071
Short name T517
Test name
Test status
Simulation time 14001984495 ps
CPU time 66 seconds
Started Jul 05 05:47:03 PM PDT 24
Finished Jul 05 05:48:10 PM PDT 24
Peak memory 200420 kb
Host smart-a7433d84-7d6f-4c53-84fd-62bc431a2a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078265071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.4078265071
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1700848072
Short name T309
Test name
Test status
Simulation time 513717560 ps
CPU time 6.92 seconds
Started Jul 05 05:47:04 PM PDT 24
Finished Jul 05 05:47:12 PM PDT 24
Peak memory 200316 kb
Host smart-06f3cdcc-cf6a-478c-ba40-96e46c68a880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700848072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1700848072
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2308546744
Short name T135
Test name
Test status
Simulation time 4417048584 ps
CPU time 253.78 seconds
Started Jul 05 05:47:14 PM PDT 24
Finished Jul 05 05:51:29 PM PDT 24
Peak memory 233792 kb
Host smart-020d23bc-52f5-4889-9e7e-8caae3bfe669
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308546744 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2308546744
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2668554283
Short name T511
Test name
Test status
Simulation time 1677763031 ps
CPU time 76.68 seconds
Started Jul 05 05:47:15 PM PDT 24
Finished Jul 05 05:48:32 PM PDT 24
Peak memory 200320 kb
Host smart-15b096cb-cd27-4e85-890c-810f57b58b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668554283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2668554283
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.582903984
Short name T421
Test name
Test status
Simulation time 27278322 ps
CPU time 0.57 seconds
Started Jul 05 05:45:39 PM PDT 24
Finished Jul 05 05:45:40 PM PDT 24
Peak memory 195196 kb
Host smart-7f339b25-01ba-4bbd-b79a-0aade0c44b15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582903984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.582903984
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.634218583
Short name T176
Test name
Test status
Simulation time 3019885646 ps
CPU time 41.87 seconds
Started Jul 05 05:45:33 PM PDT 24
Finished Jul 05 05:46:15 PM PDT 24
Peak memory 200372 kb
Host smart-b5231c41-705a-4ef0-b209-46c7b3160cb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=634218583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.634218583
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2192444045
Short name T42
Test name
Test status
Simulation time 3738156608 ps
CPU time 6.83 seconds
Started Jul 05 05:45:32 PM PDT 24
Finished Jul 05 05:45:39 PM PDT 24
Peak memory 200400 kb
Host smart-a6f006e8-a448-44d9-8d92-6835efd2e372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192444045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2192444045
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3301962433
Short name T224
Test name
Test status
Simulation time 9568401552 ps
CPU time 871.85 seconds
Started Jul 05 05:45:31 PM PDT 24
Finished Jul 05 06:00:03 PM PDT 24
Peak memory 731876 kb
Host smart-b6ac3dfe-e239-444e-a031-09b5b3e373d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3301962433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3301962433
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3232912925
Short name T244
Test name
Test status
Simulation time 11699646104 ps
CPU time 103.07 seconds
Started Jul 05 05:45:34 PM PDT 24
Finished Jul 05 05:47:18 PM PDT 24
Peak memory 200388 kb
Host smart-79602301-7dbc-4d4c-9517-3834d7cd05b2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232912925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3232912925
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2049158187
Short name T425
Test name
Test status
Simulation time 1376186144 ps
CPU time 75.81 seconds
Started Jul 05 05:45:34 PM PDT 24
Finished Jul 05 05:46:51 PM PDT 24
Peak memory 200340 kb
Host smart-7ab46bf5-20d9-49eb-8efb-e1d020f1328d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049158187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2049158187
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2888634038
Short name T60
Test name
Test status
Simulation time 42678054 ps
CPU time 0.8 seconds
Started Jul 05 05:45:38 PM PDT 24
Finished Jul 05 05:45:39 PM PDT 24
Peak memory 218416 kb
Host smart-da362dcc-9f9c-4ac4-ab72-7674808a4769
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888634038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2888634038
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.11691036
Short name T381
Test name
Test status
Simulation time 3528823163 ps
CPU time 9.93 seconds
Started Jul 05 05:45:34 PM PDT 24
Finished Jul 05 05:45:44 PM PDT 24
Peak memory 200384 kb
Host smart-c14c75a1-0316-4242-9059-3f548feebec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11691036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.11691036
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2384793157
Short name T154
Test name
Test status
Simulation time 15948045505 ps
CPU time 1799.28 seconds
Started Jul 05 05:45:39 PM PDT 24
Finished Jul 05 06:15:39 PM PDT 24
Peak memory 765056 kb
Host smart-c1da2b1d-47cb-4250-9d8d-2d30b036f29e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384793157 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2384793157
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.1338282566
Short name T12
Test name
Test status
Simulation time 30164206034 ps
CPU time 491.76 seconds
Started Jul 05 05:45:38 PM PDT 24
Finished Jul 05 05:53:50 PM PDT 24
Peak memory 506472 kb
Host smart-c9110f22-ae98-421b-8f6d-1a371c13573e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1338282566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.1338282566
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.305279214
Short name T345
Test name
Test status
Simulation time 10809205405 ps
CPU time 42.68 seconds
Started Jul 05 05:45:38 PM PDT 24
Finished Jul 05 05:46:21 PM PDT 24
Peak memory 200372 kb
Host smart-e5f1fb29-4a7e-49c1-82a9-064fcb70ddda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=305279214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.305279214
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.206681062
Short name T488
Test name
Test status
Simulation time 9576532159 ps
CPU time 93.63 seconds
Started Jul 05 05:45:39 PM PDT 24
Finished Jul 05 05:47:14 PM PDT 24
Peak memory 200424 kb
Host smart-3bfdd927-eab6-44f2-b30a-0d9c247c4748
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=206681062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.206681062
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.928359655
Short name T526
Test name
Test status
Simulation time 9407120517 ps
CPU time 75.57 seconds
Started Jul 05 05:45:38 PM PDT 24
Finished Jul 05 05:46:53 PM PDT 24
Peak memory 200384 kb
Host smart-09b40050-ad47-4d25-ad76-f060f06fa346
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=928359655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.928359655
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.3627123745
Short name T323
Test name
Test status
Simulation time 9441418340 ps
CPU time 513.85 seconds
Started Jul 05 05:45:33 PM PDT 24
Finished Jul 05 05:54:07 PM PDT 24
Peak memory 200384 kb
Host smart-42a25a56-3bf4-483d-8ee9-4695d249f18e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3627123745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.3627123745
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.3657278451
Short name T52
Test name
Test status
Simulation time 41432081103 ps
CPU time 2208.02 seconds
Started Jul 05 05:45:32 PM PDT 24
Finished Jul 05 06:22:20 PM PDT 24
Peak memory 215836 kb
Host smart-f83b02c6-65ae-4f59-a9b1-1ce4574016f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3657278451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.3657278451
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.792061045
Short name T438
Test name
Test status
Simulation time 187271924518 ps
CPU time 2581.4 seconds
Started Jul 05 05:45:36 PM PDT 24
Finished Jul 05 06:28:38 PM PDT 24
Peak memory 215900 kb
Host smart-8db0db16-a166-4149-9018-6324086ca60c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=792061045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.792061045
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.737695573
Short name T427
Test name
Test status
Simulation time 2004808057 ps
CPU time 51.22 seconds
Started Jul 05 05:45:33 PM PDT 24
Finished Jul 05 05:46:25 PM PDT 24
Peak memory 200268 kb
Host smart-687185ac-cf78-4e20-b713-49cc8c5fc4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737695573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.737695573
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2774574364
Short name T459
Test name
Test status
Simulation time 22005266 ps
CPU time 0.6 seconds
Started Jul 05 05:47:13 PM PDT 24
Finished Jul 05 05:47:15 PM PDT 24
Peak memory 196144 kb
Host smart-e2aa0b13-13ab-40f8-9142-f9e9ce492dba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774574364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2774574364
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1093702858
Short name T419
Test name
Test status
Simulation time 1853391763 ps
CPU time 105.85 seconds
Started Jul 05 05:47:14 PM PDT 24
Finished Jul 05 05:49:01 PM PDT 24
Peak memory 200336 kb
Host smart-23ad0d84-cb52-43a4-8fa3-72291d7bcd41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1093702858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1093702858
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1469442626
Short name T274
Test name
Test status
Simulation time 454567344 ps
CPU time 3.67 seconds
Started Jul 05 05:47:14 PM PDT 24
Finished Jul 05 05:47:18 PM PDT 24
Peak memory 200324 kb
Host smart-8a601932-2f39-4bbc-a6fc-68e4fbccfb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469442626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1469442626
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2384672539
Short name T212
Test name
Test status
Simulation time 2640248066 ps
CPU time 489.65 seconds
Started Jul 05 05:47:12 PM PDT 24
Finished Jul 05 05:55:22 PM PDT 24
Peak memory 678088 kb
Host smart-2f208ad9-6b5b-4da2-ba3b-5d9b1ea64b34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2384672539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2384672539
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.3517976485
Short name T204
Test name
Test status
Simulation time 10577533939 ps
CPU time 127.57 seconds
Started Jul 05 05:47:14 PM PDT 24
Finished Jul 05 05:49:22 PM PDT 24
Peak memory 200356 kb
Host smart-059991b1-f703-4aea-87fe-91a8aeb4ded8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517976485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3517976485
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.382928487
Short name T301
Test name
Test status
Simulation time 27924467225 ps
CPU time 102.87 seconds
Started Jul 05 05:47:13 PM PDT 24
Finished Jul 05 05:48:57 PM PDT 24
Peak memory 208504 kb
Host smart-32dc60ab-c7e9-4971-b970-af8dded243fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382928487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.382928487
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1828664320
Short name T493
Test name
Test status
Simulation time 246425966 ps
CPU time 4.6 seconds
Started Jul 05 05:47:14 PM PDT 24
Finished Jul 05 05:47:19 PM PDT 24
Peak memory 200320 kb
Host smart-7ff2c08d-75b7-42d8-b3ea-28c07e5ea7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828664320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1828664320
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2216210167
Short name T84
Test name
Test status
Simulation time 315014802732 ps
CPU time 957 seconds
Started Jul 05 05:47:12 PM PDT 24
Finished Jul 05 06:03:10 PM PDT 24
Peak memory 200368 kb
Host smart-c5d046fa-86bf-4db2-a518-f30c8dac0076
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216210167 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2216210167
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.701654778
Short name T92
Test name
Test status
Simulation time 8621887617 ps
CPU time 35.8 seconds
Started Jul 05 05:47:13 PM PDT 24
Finished Jul 05 05:47:49 PM PDT 24
Peak memory 200356 kb
Host smart-598b9ad6-a4c7-4a92-ba9a-71f11bf81813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701654778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.701654778
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.4081160842
Short name T307
Test name
Test status
Simulation time 14501859 ps
CPU time 0.6 seconds
Started Jul 05 05:47:13 PM PDT 24
Finished Jul 05 05:47:14 PM PDT 24
Peak memory 196168 kb
Host smart-22e852ea-52c5-40e5-a62c-8872ee8771b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081160842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.4081160842
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.245243810
Short name T220
Test name
Test status
Simulation time 5973020240 ps
CPU time 101.15 seconds
Started Jul 05 05:47:14 PM PDT 24
Finished Jul 05 05:48:56 PM PDT 24
Peak memory 208668 kb
Host smart-b251df00-942b-4a83-bf23-02687e53e27c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=245243810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.245243810
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3249532931
Short name T491
Test name
Test status
Simulation time 83150209 ps
CPU time 1.19 seconds
Started Jul 05 05:47:14 PM PDT 24
Finished Jul 05 05:47:16 PM PDT 24
Peak memory 200256 kb
Host smart-f19ce30a-ad78-42fb-850f-5ef4ec66881e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249532931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3249532931
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1153441824
Short name T388
Test name
Test status
Simulation time 5076564098 ps
CPU time 725.86 seconds
Started Jul 05 05:47:13 PM PDT 24
Finished Jul 05 05:59:20 PM PDT 24
Peak memory 637380 kb
Host smart-6704ac54-aa5b-4e89-9c0b-656ff2a85d80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1153441824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1153441824
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3386063140
Short name T267
Test name
Test status
Simulation time 10644753014 ps
CPU time 139.9 seconds
Started Jul 05 05:47:15 PM PDT 24
Finished Jul 05 05:49:35 PM PDT 24
Peak memory 200384 kb
Host smart-9b9710bf-1607-4ef2-aa6c-c16ec3c6115f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386063140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3386063140
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.2385897234
Short name T284
Test name
Test status
Simulation time 102852616398 ps
CPU time 95.52 seconds
Started Jul 05 05:47:13 PM PDT 24
Finished Jul 05 05:48:50 PM PDT 24
Peak memory 200544 kb
Host smart-92e5b4b8-2b67-42a9-8954-640a228776b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385897234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2385897234
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.95416132
Short name T198
Test name
Test status
Simulation time 3018012462 ps
CPU time 10.1 seconds
Started Jul 05 05:47:16 PM PDT 24
Finished Jul 05 05:47:27 PM PDT 24
Peak memory 200384 kb
Host smart-cf002d6b-7a81-4a3b-b21a-e0892f9f393c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95416132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.95416132
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.962217515
Short name T88
Test name
Test status
Simulation time 80920360516 ps
CPU time 2797.66 seconds
Started Jul 05 05:47:10 PM PDT 24
Finished Jul 05 06:33:49 PM PDT 24
Peak memory 817668 kb
Host smart-765a98b4-b6fc-4d72-9298-a5b333bc4cc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962217515 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.962217515
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.117393208
Short name T172
Test name
Test status
Simulation time 22962072493 ps
CPU time 101.69 seconds
Started Jul 05 05:47:15 PM PDT 24
Finished Jul 05 05:48:57 PM PDT 24
Peak memory 200308 kb
Host smart-76e41f4b-6e80-464c-8628-3df97e7eae9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117393208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.117393208
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.4147718276
Short name T320
Test name
Test status
Simulation time 43623763 ps
CPU time 0.59 seconds
Started Jul 05 05:47:21 PM PDT 24
Finished Jul 05 05:47:22 PM PDT 24
Peak memory 195752 kb
Host smart-f1fe1fed-6969-478a-b98e-67fa4abeb369
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147718276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.4147718276
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2685520369
Short name T424
Test name
Test status
Simulation time 4534897379 ps
CPU time 83.6 seconds
Started Jul 05 05:47:15 PM PDT 24
Finished Jul 05 05:48:39 PM PDT 24
Peak memory 200432 kb
Host smart-9a5d6535-afec-4e3c-9195-25902cf9fd0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2685520369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2685520369
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.157700277
Short name T359
Test name
Test status
Simulation time 435722828 ps
CPU time 8.12 seconds
Started Jul 05 05:47:13 PM PDT 24
Finished Jul 05 05:47:22 PM PDT 24
Peak memory 200276 kb
Host smart-90f30ca5-d4b6-4a0c-89e8-6c4bb8c4eedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157700277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.157700277
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.161851720
Short name T397
Test name
Test status
Simulation time 75329656 ps
CPU time 0.78 seconds
Started Jul 05 05:47:15 PM PDT 24
Finished Jul 05 05:47:16 PM PDT 24
Peak memory 208372 kb
Host smart-0ebb1137-384d-4af0-89ef-213333c448bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=161851720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.161851720
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1471811467
Short name T435
Test name
Test status
Simulation time 19693283337 ps
CPU time 171.39 seconds
Started Jul 05 05:47:23 PM PDT 24
Finished Jul 05 05:50:14 PM PDT 24
Peak memory 200356 kb
Host smart-8d8da050-1629-4e68-b47b-3aaad4b95779
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471811467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1471811467
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1320166588
Short name T410
Test name
Test status
Simulation time 9279077157 ps
CPU time 166.33 seconds
Started Jul 05 05:47:12 PM PDT 24
Finished Jul 05 05:49:59 PM PDT 24
Peak memory 200356 kb
Host smart-f3bf4ad7-04b3-4da2-8b6c-d0d3a7528edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320166588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1320166588
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3656281358
Short name T215
Test name
Test status
Simulation time 436100504 ps
CPU time 3.83 seconds
Started Jul 05 05:47:13 PM PDT 24
Finished Jul 05 05:47:18 PM PDT 24
Peak memory 200364 kb
Host smart-1fc71be1-5c92-4297-9478-43f393e3ed50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656281358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3656281358
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2412008205
Short name T482
Test name
Test status
Simulation time 376887609 ps
CPU time 19.5 seconds
Started Jul 05 05:47:25 PM PDT 24
Finished Jul 05 05:47:45 PM PDT 24
Peak memory 200348 kb
Host smart-c3025022-9aa4-42c8-952f-4035d706747f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412008205 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2412008205
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.2171055791
Short name T236
Test name
Test status
Simulation time 10752432199 ps
CPU time 137.65 seconds
Started Jul 05 05:47:17 PM PDT 24
Finished Jul 05 05:49:35 PM PDT 24
Peak memory 200296 kb
Host smart-62603b9e-fdf2-4cd8-8c91-3c0f17f6530e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171055791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.2171055791
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1322993764
Short name T434
Test name
Test status
Simulation time 13226786 ps
CPU time 0.59 seconds
Started Jul 05 05:47:21 PM PDT 24
Finished Jul 05 05:47:23 PM PDT 24
Peak memory 195176 kb
Host smart-2373872c-d11f-4c93-8835-f8d876634e5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322993764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1322993764
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1138174237
Short name T31
Test name
Test status
Simulation time 1417659925 ps
CPU time 75.85 seconds
Started Jul 05 05:47:25 PM PDT 24
Finished Jul 05 05:48:41 PM PDT 24
Peak memory 200320 kb
Host smart-6b6ec046-56fc-49ec-8374-37a006bb3e14
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1138174237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1138174237
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3434867318
Short name T36
Test name
Test status
Simulation time 14255487617 ps
CPU time 51 seconds
Started Jul 05 05:47:27 PM PDT 24
Finished Jul 05 05:48:19 PM PDT 24
Peak memory 200444 kb
Host smart-5ef406fa-984f-45b6-869b-a63a6f556ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434867318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3434867318
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.3106361685
Short name T465
Test name
Test status
Simulation time 15365878690 ps
CPU time 595.03 seconds
Started Jul 05 05:47:27 PM PDT 24
Finished Jul 05 05:57:23 PM PDT 24
Peak memory 701984 kb
Host smart-6211255c-2fd1-4f5f-8fd2-8ad4577c5773
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3106361685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3106361685
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.2412802676
Short name T74
Test name
Test status
Simulation time 129097932267 ps
CPU time 197.9 seconds
Started Jul 05 05:47:23 PM PDT 24
Finished Jul 05 05:50:42 PM PDT 24
Peak memory 200360 kb
Host smart-3eed0397-487c-4320-a8ea-b932e9904528
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412802676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2412802676
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1765169981
Short name T466
Test name
Test status
Simulation time 3070629707 ps
CPU time 175.47 seconds
Started Jul 05 05:47:22 PM PDT 24
Finished Jul 05 05:50:18 PM PDT 24
Peak memory 200372 kb
Host smart-d8558eae-64ab-49af-8d0a-22b03e42200d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765169981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1765169981
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1792210656
Short name T513
Test name
Test status
Simulation time 1167022376 ps
CPU time 3.97 seconds
Started Jul 05 05:47:22 PM PDT 24
Finished Jul 05 05:47:26 PM PDT 24
Peak memory 200332 kb
Host smart-6f23cba5-8c08-4c8b-8afc-227971bb7bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792210656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1792210656
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1094735067
Short name T94
Test name
Test status
Simulation time 42313236300 ps
CPU time 685.99 seconds
Started Jul 05 05:47:27 PM PDT 24
Finished Jul 05 05:58:53 PM PDT 24
Peak memory 339124 kb
Host smart-f14fccc6-98c0-4d9d-a358-f8abdc9799ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094735067 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1094735067
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2481709851
Short name T109
Test name
Test status
Simulation time 9540473916 ps
CPU time 62.78 seconds
Started Jul 05 05:47:24 PM PDT 24
Finished Jul 05 05:48:27 PM PDT 24
Peak memory 200356 kb
Host smart-f7000895-ff5e-4bfa-91f6-b4ac46ab336a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481709851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2481709851
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3603435415
Short name T159
Test name
Test status
Simulation time 31645960 ps
CPU time 0.6 seconds
Started Jul 05 05:47:26 PM PDT 24
Finished Jul 05 05:47:27 PM PDT 24
Peak memory 196216 kb
Host smart-4fc84353-45e5-44e2-b2f3-60bdf3319c9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603435415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3603435415
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2180096028
Short name T30
Test name
Test status
Simulation time 1810400973 ps
CPU time 29.89 seconds
Started Jul 05 05:47:22 PM PDT 24
Finished Jul 05 05:47:52 PM PDT 24
Peak memory 200324 kb
Host smart-45e93dfc-f665-4920-8fd7-71fafcb48fab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2180096028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2180096028
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3596398997
Short name T365
Test name
Test status
Simulation time 225459575 ps
CPU time 6.1 seconds
Started Jul 05 05:47:25 PM PDT 24
Finished Jul 05 05:47:32 PM PDT 24
Peak memory 200336 kb
Host smart-f6d0911c-ca0a-406d-8b4b-d7167db710ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596398997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3596398997
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1760251102
Short name T80
Test name
Test status
Simulation time 550967534 ps
CPU time 29 seconds
Started Jul 05 05:47:18 PM PDT 24
Finished Jul 05 05:47:47 PM PDT 24
Peak memory 300048 kb
Host smart-cba6067a-b8d7-462d-818d-af9925271852
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1760251102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1760251102
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1889387214
Short name T99
Test name
Test status
Simulation time 7075541400 ps
CPU time 114.19 seconds
Started Jul 05 05:47:26 PM PDT 24
Finished Jul 05 05:49:21 PM PDT 24
Peak memory 200356 kb
Host smart-a5f50300-9a19-4726-8b2e-ca9c7ac471e6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889387214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1889387214
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2577797133
Short name T385
Test name
Test status
Simulation time 7249996220 ps
CPU time 63.66 seconds
Started Jul 05 05:47:22 PM PDT 24
Finished Jul 05 05:48:26 PM PDT 24
Peak memory 200328 kb
Host smart-04a0bbf9-8bda-4efd-915c-59e18d135ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577797133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2577797133
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.1321182094
Short name T420
Test name
Test status
Simulation time 1084135622 ps
CPU time 11.59 seconds
Started Jul 05 05:47:27 PM PDT 24
Finished Jul 05 05:47:39 PM PDT 24
Peak memory 200332 kb
Host smart-c6a2e5f1-0a18-446a-84b1-5a57d7a3920d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321182094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1321182094
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.871931770
Short name T81
Test name
Test status
Simulation time 1264834738874 ps
CPU time 1108.16 seconds
Started Jul 05 05:47:21 PM PDT 24
Finished Jul 05 06:05:50 PM PDT 24
Peak memory 200392 kb
Host smart-48969497-1566-43dd-abb6-986919d9b744
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871931770 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.871931770
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.294577520
Short name T372
Test name
Test status
Simulation time 6099868151 ps
CPU time 63.09 seconds
Started Jul 05 05:47:22 PM PDT 24
Finished Jul 05 05:48:26 PM PDT 24
Peak memory 200384 kb
Host smart-8e7982af-8cbe-4821-9f1c-5bec527da304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294577520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.294577520
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.44784736
Short name T208
Test name
Test status
Simulation time 14457844 ps
CPU time 0.6 seconds
Started Jul 05 05:47:29 PM PDT 24
Finished Jul 05 05:47:30 PM PDT 24
Peak memory 195068 kb
Host smart-a69e9e35-2cf8-4155-9848-9f94fcf0735b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44784736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.44784736
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3508459800
Short name T93
Test name
Test status
Simulation time 3364422604 ps
CPU time 99.79 seconds
Started Jul 05 05:47:21 PM PDT 24
Finished Jul 05 05:49:01 PM PDT 24
Peak memory 208616 kb
Host smart-54bf71bf-869c-4db1-9425-4e945bdba13d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3508459800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3508459800
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2743187599
Short name T344
Test name
Test status
Simulation time 8982897184 ps
CPU time 60.4 seconds
Started Jul 05 05:47:26 PM PDT 24
Finished Jul 05 05:48:27 PM PDT 24
Peak memory 216788 kb
Host smart-51b75c09-e2b1-4884-bf67-90cd5d3d5296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743187599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2743187599
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2925031634
Short name T481
Test name
Test status
Simulation time 2579706179 ps
CPU time 241.26 seconds
Started Jul 05 05:47:28 PM PDT 24
Finished Jul 05 05:51:30 PM PDT 24
Peak memory 599956 kb
Host smart-e61587f0-d74c-44fe-b2ff-7ff982ce2ea8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2925031634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2925031634
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1584057421
Short name T383
Test name
Test status
Simulation time 4009887693 ps
CPU time 34.39 seconds
Started Jul 05 05:47:25 PM PDT 24
Finished Jul 05 05:48:00 PM PDT 24
Peak memory 200356 kb
Host smart-377ed104-5095-4e3d-95f3-99620bad64ac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584057421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1584057421
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1865916767
Short name T166
Test name
Test status
Simulation time 5017075130 ps
CPU time 89.31 seconds
Started Jul 05 05:47:20 PM PDT 24
Finished Jul 05 05:48:50 PM PDT 24
Peak memory 208588 kb
Host smart-c4c7f491-020c-47e2-babe-8f1494eaa139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865916767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1865916767
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3436144207
Short name T342
Test name
Test status
Simulation time 583291036 ps
CPU time 10.2 seconds
Started Jul 05 05:47:27 PM PDT 24
Finished Jul 05 05:47:38 PM PDT 24
Peak memory 200320 kb
Host smart-d7807e8a-249d-4f30-a3fb-e51ff14f1060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436144207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3436144207
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.234082245
Short name T431
Test name
Test status
Simulation time 14334742129 ps
CPU time 1032.81 seconds
Started Jul 05 05:47:28 PM PDT 24
Finished Jul 05 06:04:41 PM PDT 24
Peak memory 670268 kb
Host smart-10d0bf7b-c19a-4fdb-851c-a89689024e8a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234082245 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.234082245
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3762376157
Short name T328
Test name
Test status
Simulation time 37686090203 ps
CPU time 87.54 seconds
Started Jul 05 05:47:31 PM PDT 24
Finished Jul 05 05:48:59 PM PDT 24
Peak memory 199860 kb
Host smart-e1b0e6ae-df00-42e2-90bd-8f604e3ed38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762376157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3762376157
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3145837510
Short name T41
Test name
Test status
Simulation time 33283850 ps
CPU time 0.61 seconds
Started Jul 05 05:47:31 PM PDT 24
Finished Jul 05 05:47:32 PM PDT 24
Peak memory 196828 kb
Host smart-1a952bba-830e-46b3-8b5c-99bcaef1a29f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145837510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3145837510
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.4173575914
Short name T32
Test name
Test status
Simulation time 2157882725 ps
CPU time 65.65 seconds
Started Jul 05 05:47:29 PM PDT 24
Finished Jul 05 05:48:35 PM PDT 24
Peak memory 200400 kb
Host smart-55e0dc07-8e2e-4653-a5eb-5f26d089f1d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4173575914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.4173575914
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.79227546
Short name T195
Test name
Test status
Simulation time 366827869 ps
CPU time 10.07 seconds
Started Jul 05 05:47:27 PM PDT 24
Finished Jul 05 05:47:37 PM PDT 24
Peak memory 200268 kb
Host smart-bd2a1b31-6685-4222-b399-0b96189ac3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79227546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.79227546
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3314249959
Short name T418
Test name
Test status
Simulation time 532514911 ps
CPU time 28.62 seconds
Started Jul 05 05:47:30 PM PDT 24
Finished Jul 05 05:47:59 PM PDT 24
Peak memory 258532 kb
Host smart-7b40de3e-1453-4f4a-b54c-af602c9a012d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3314249959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3314249959
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.353290654
Short name T329
Test name
Test status
Simulation time 7868568174 ps
CPU time 90.78 seconds
Started Jul 05 05:47:27 PM PDT 24
Finished Jul 05 05:48:59 PM PDT 24
Peak memory 200264 kb
Host smart-833988e6-0e7c-473c-bb31-9293e9bdcab0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353290654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.353290654
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2312464121
Short name T9
Test name
Test status
Simulation time 1930141254 ps
CPU time 108.74 seconds
Started Jul 05 05:47:31 PM PDT 24
Finished Jul 05 05:49:20 PM PDT 24
Peak memory 200268 kb
Host smart-e0e18afc-1e75-497c-a924-a10ba8e02ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312464121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2312464121
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3318878685
Short name T181
Test name
Test status
Simulation time 936559438 ps
CPU time 14.56 seconds
Started Jul 05 05:47:27 PM PDT 24
Finished Jul 05 05:47:42 PM PDT 24
Peak memory 200292 kb
Host smart-c6625951-7f24-428d-b05d-b923f9319d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318878685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3318878685
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.746107167
Short name T478
Test name
Test status
Simulation time 17762421800 ps
CPU time 165.51 seconds
Started Jul 05 05:47:27 PM PDT 24
Finished Jul 05 05:50:14 PM PDT 24
Peak memory 208544 kb
Host smart-2d613546-098e-4564-a3fe-389e098fe92c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746107167 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.746107167
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.3010146576
Short name T336
Test name
Test status
Simulation time 5918311815 ps
CPU time 76.4 seconds
Started Jul 05 05:47:29 PM PDT 24
Finished Jul 05 05:48:46 PM PDT 24
Peak memory 200400 kb
Host smart-cfbbec9b-5564-43b4-88e4-2a221054109e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010146576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.3010146576
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2456884407
Short name T242
Test name
Test status
Simulation time 39992224 ps
CPU time 0.58 seconds
Started Jul 05 05:47:27 PM PDT 24
Finished Jul 05 05:47:28 PM PDT 24
Peak memory 195852 kb
Host smart-e2bb96d9-ae98-41e9-a652-c3907095485b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456884407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2456884407
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.3524268578
Short name T358
Test name
Test status
Simulation time 459063974 ps
CPU time 23.96 seconds
Started Jul 05 05:47:29 PM PDT 24
Finished Jul 05 05:47:53 PM PDT 24
Peak memory 200364 kb
Host smart-794989ca-67c5-44a7-a57f-ce9222dc014d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3524268578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3524268578
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1085633077
Short name T289
Test name
Test status
Simulation time 157532809 ps
CPU time 1.67 seconds
Started Jul 05 05:47:29 PM PDT 24
Finished Jul 05 05:47:31 PM PDT 24
Peak memory 200320 kb
Host smart-be05137b-a407-44e1-a795-5728d0caed2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085633077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1085633077
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1646088654
Short name T72
Test name
Test status
Simulation time 3835071761 ps
CPU time 721.44 seconds
Started Jul 05 05:47:26 PM PDT 24
Finished Jul 05 05:59:28 PM PDT 24
Peak memory 671436 kb
Host smart-054f2d05-21ee-44e6-8266-7eb49c93e381
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1646088654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1646088654
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1602195157
Short name T339
Test name
Test status
Simulation time 1747640568 ps
CPU time 48.44 seconds
Started Jul 05 05:47:31 PM PDT 24
Finished Jul 05 05:48:20 PM PDT 24
Peak memory 200232 kb
Host smart-7f728395-926d-4714-bb28-ba72196bf227
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602195157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1602195157
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1325558219
Short name T53
Test name
Test status
Simulation time 13172927400 ps
CPU time 135.65 seconds
Started Jul 05 05:47:26 PM PDT 24
Finished Jul 05 05:49:42 PM PDT 24
Peak memory 200356 kb
Host smart-cabeabd5-29b7-4c7a-94f9-3753da45c470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325558219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1325558219
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.4109711271
Short name T226
Test name
Test status
Simulation time 357423197 ps
CPU time 8.1 seconds
Started Jul 05 05:47:31 PM PDT 24
Finished Jul 05 05:47:40 PM PDT 24
Peak memory 199972 kb
Host smart-37ef4254-aba6-4a96-8211-492e7fb74ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109711271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.4109711271
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.210604427
Short name T134
Test name
Test status
Simulation time 52215488188 ps
CPU time 580.58 seconds
Started Jul 05 05:47:31 PM PDT 24
Finished Jul 05 05:57:12 PM PDT 24
Peak memory 200372 kb
Host smart-125a7b0a-4a52-4df5-bf06-293694b95a18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210604427 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.210604427
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1661316908
Short name T378
Test name
Test status
Simulation time 9916844813 ps
CPU time 35.45 seconds
Started Jul 05 05:47:27 PM PDT 24
Finished Jul 05 05:48:03 PM PDT 24
Peak memory 200384 kb
Host smart-c2f14c7c-5f07-46d1-aa2f-66f031a253a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661316908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1661316908
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.256234255
Short name T188
Test name
Test status
Simulation time 14352970 ps
CPU time 0.61 seconds
Started Jul 05 05:47:34 PM PDT 24
Finished Jul 05 05:47:35 PM PDT 24
Peak memory 196884 kb
Host smart-b729c3f7-d969-459e-8a1c-c1f865fb8e8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256234255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.256234255
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.303954474
Short name T343
Test name
Test status
Simulation time 2310025424 ps
CPU time 68.63 seconds
Started Jul 05 05:47:43 PM PDT 24
Finished Jul 05 05:48:52 PM PDT 24
Peak memory 200376 kb
Host smart-80aecba3-88b8-4b30-bc8f-846a7e8fbe98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=303954474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.303954474
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3411905698
Short name T173
Test name
Test status
Simulation time 11374456643 ps
CPU time 67.3 seconds
Started Jul 05 05:47:34 PM PDT 24
Finished Jul 05 05:48:42 PM PDT 24
Peak memory 200352 kb
Host smart-8e62c031-9037-4caf-9537-aecbe577aaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411905698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3411905698
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1978718819
Short name T429
Test name
Test status
Simulation time 5371329306 ps
CPU time 198.62 seconds
Started Jul 05 05:47:33 PM PDT 24
Finished Jul 05 05:50:52 PM PDT 24
Peak memory 623636 kb
Host smart-c9493a51-cb97-42bf-8d5d-35e96773fd17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1978718819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1978718819
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.2545314807
Short name T201
Test name
Test status
Simulation time 23851966949 ps
CPU time 183.84 seconds
Started Jul 05 05:47:33 PM PDT 24
Finished Jul 05 05:50:37 PM PDT 24
Peak memory 200388 kb
Host smart-74449ec0-b3a5-4e1d-b732-e77b65c4eb66
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545314807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2545314807
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1362146792
Short name T400
Test name
Test status
Simulation time 2900479906 ps
CPU time 167.23 seconds
Started Jul 05 05:47:31 PM PDT 24
Finished Jul 05 05:50:19 PM PDT 24
Peak memory 200016 kb
Host smart-6eb81cd3-abdd-42e9-93c8-7635122f23f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362146792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1362146792
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3947336901
Short name T75
Test name
Test status
Simulation time 366012937 ps
CPU time 4.92 seconds
Started Jul 05 05:47:27 PM PDT 24
Finished Jul 05 05:47:33 PM PDT 24
Peak memory 200316 kb
Host smart-d24257d5-c4c2-4eed-804f-20c13b165ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947336901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3947336901
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.487024713
Short name T352
Test name
Test status
Simulation time 5227283644 ps
CPU time 272.48 seconds
Started Jul 05 05:47:35 PM PDT 24
Finished Jul 05 05:52:08 PM PDT 24
Peak memory 200368 kb
Host smart-f180aec2-981f-457a-aa7e-1abfb8f838b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487024713 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.487024713
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.704382783
Short name T219
Test name
Test status
Simulation time 399857485 ps
CPU time 5.29 seconds
Started Jul 05 05:47:33 PM PDT 24
Finished Jul 05 05:47:39 PM PDT 24
Peak memory 200300 kb
Host smart-848e36e9-6e87-4212-9332-946e2ac150cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704382783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.704382783
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1374083606
Short name T498
Test name
Test status
Simulation time 12934152 ps
CPU time 0.61 seconds
Started Jul 05 05:47:38 PM PDT 24
Finished Jul 05 05:47:39 PM PDT 24
Peak memory 195840 kb
Host smart-3b82746e-0f49-4f1c-9ca1-b0e753ef12b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374083606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1374083606
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.4259813698
Short name T89
Test name
Test status
Simulation time 581015698 ps
CPU time 34.28 seconds
Started Jul 05 05:47:37 PM PDT 24
Finished Jul 05 05:48:11 PM PDT 24
Peak memory 200244 kb
Host smart-84ba1835-16a7-42ba-8ecd-b47bb97f94a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4259813698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.4259813698
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1820468323
Short name T58
Test name
Test status
Simulation time 13910503337 ps
CPU time 48.07 seconds
Started Jul 05 05:47:38 PM PDT 24
Finished Jul 05 05:48:26 PM PDT 24
Peak memory 200376 kb
Host smart-6800d6cc-9842-4880-8fca-d4c2706622ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820468323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1820468323
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.4070603372
Short name T223
Test name
Test status
Simulation time 3230902230 ps
CPU time 652.71 seconds
Started Jul 05 05:47:36 PM PDT 24
Finished Jul 05 05:58:29 PM PDT 24
Peak memory 747856 kb
Host smart-dd0c35b2-8fff-47fd-9e69-77aa8fb441fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4070603372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.4070603372
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.4278263261
Short name T519
Test name
Test status
Simulation time 6060430271 ps
CPU time 71.48 seconds
Started Jul 05 05:47:43 PM PDT 24
Finished Jul 05 05:48:55 PM PDT 24
Peak memory 200308 kb
Host smart-70964ffb-bfd0-4d5a-afec-0d22a4cc8095
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278263261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.4278263261
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2616924617
Short name T178
Test name
Test status
Simulation time 32358541736 ps
CPU time 141.22 seconds
Started Jul 05 05:47:34 PM PDT 24
Finished Jul 05 05:49:55 PM PDT 24
Peak memory 200356 kb
Host smart-fe08e44f-391f-4db6-95dd-150a8b01e8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616924617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2616924617
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2926380047
Short name T506
Test name
Test status
Simulation time 293566238 ps
CPU time 12.6 seconds
Started Jul 05 05:47:35 PM PDT 24
Finished Jul 05 05:47:48 PM PDT 24
Peak memory 200312 kb
Host smart-7519db58-a1b7-4f55-91a8-98d1298f4f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926380047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2926380047
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.935490093
Short name T277
Test name
Test status
Simulation time 63693909583 ps
CPU time 129.48 seconds
Started Jul 05 05:47:34 PM PDT 24
Finished Jul 05 05:49:43 PM PDT 24
Peak memory 200332 kb
Host smart-ab7979a8-43f4-43c7-9393-cc3c713261d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935490093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.935490093
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1769779606
Short name T164
Test name
Test status
Simulation time 12020034 ps
CPU time 0.55 seconds
Started Jul 05 05:45:41 PM PDT 24
Finished Jul 05 05:45:41 PM PDT 24
Peak memory 195192 kb
Host smart-6b3c9f1e-d1d3-4e03-b1c4-a4523f221856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769779606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1769779606
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1216326508
Short name T222
Test name
Test status
Simulation time 135894101 ps
CPU time 8.03 seconds
Started Jul 05 05:45:41 PM PDT 24
Finished Jul 05 05:45:50 PM PDT 24
Peak memory 200300 kb
Host smart-470198c0-d07e-4255-a8d3-07f88d646a76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1216326508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1216326508
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1111401459
Short name T338
Test name
Test status
Simulation time 5353580115 ps
CPU time 57.84 seconds
Started Jul 05 05:45:39 PM PDT 24
Finished Jul 05 05:46:37 PM PDT 24
Peak memory 200396 kb
Host smart-0b460385-50ea-47fe-b2d3-5faa37d906a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111401459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1111401459
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3782151657
Short name T369
Test name
Test status
Simulation time 7345404693 ps
CPU time 1580.8 seconds
Started Jul 05 05:45:38 PM PDT 24
Finished Jul 05 06:11:59 PM PDT 24
Peak memory 696092 kb
Host smart-794b04e4-3bbf-46f9-bb9a-80339d0a18bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3782151657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3782151657
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1247425143
Short name T458
Test name
Test status
Simulation time 54858396390 ps
CPU time 72.19 seconds
Started Jul 05 05:45:37 PM PDT 24
Finished Jul 05 05:46:50 PM PDT 24
Peak memory 200364 kb
Host smart-a27c04c7-9809-4a25-8e05-53d70d861609
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247425143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1247425143
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3720136589
Short name T40
Test name
Test status
Simulation time 64631642202 ps
CPU time 204.12 seconds
Started Jul 05 05:45:39 PM PDT 24
Finished Jul 05 05:49:03 PM PDT 24
Peak memory 200404 kb
Host smart-bd36ca6d-d837-4e4a-8e03-dda12b243f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720136589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3720136589
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.765158701
Short name T351
Test name
Test status
Simulation time 396450581 ps
CPU time 13.97 seconds
Started Jul 05 05:45:39 PM PDT 24
Finished Jul 05 05:45:54 PM PDT 24
Peak memory 200380 kb
Host smart-e1359e2a-b8cc-4f7d-aa6a-3e7b89d571a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765158701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.765158701
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3561251780
Short name T249
Test name
Test status
Simulation time 3809284112 ps
CPU time 64.4 seconds
Started Jul 05 05:45:41 PM PDT 24
Finished Jul 05 05:46:46 PM PDT 24
Peak memory 200372 kb
Host smart-c317e277-dc0f-49e3-87c3-83d60ee76705
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561251780 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3561251780
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.1211672220
Short name T17
Test name
Test status
Simulation time 122058874818 ps
CPU time 1770.99 seconds
Started Jul 05 05:45:37 PM PDT 24
Finished Jul 05 06:15:09 PM PDT 24
Peak memory 434504 kb
Host smart-ab8e015d-3324-41c1-8668-6a193eabfe89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1211672220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.1211672220
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2181881821
Short name T489
Test name
Test status
Simulation time 30690516396 ps
CPU time 96.99 seconds
Started Jul 05 05:45:37 PM PDT 24
Finished Jul 05 05:47:15 PM PDT 24
Peak memory 200424 kb
Host smart-5aee7e9f-2164-46ab-8ea9-d60022457c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181881821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2181881821
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2281265388
Short name T433
Test name
Test status
Simulation time 11916661 ps
CPU time 0.55 seconds
Started Jul 05 05:45:46 PM PDT 24
Finished Jul 05 05:45:47 PM PDT 24
Peak memory 195088 kb
Host smart-6f7388e5-56b3-412a-82d5-3f870f5be1e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281265388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2281265388
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.1618461133
Short name T238
Test name
Test status
Simulation time 638042969 ps
CPU time 38.25 seconds
Started Jul 05 05:45:40 PM PDT 24
Finished Jul 05 05:46:19 PM PDT 24
Peak memory 200312 kb
Host smart-632bd239-30fd-4737-af2c-b7708491f228
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1618461133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1618461133
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3518931141
Short name T229
Test name
Test status
Simulation time 3221685133 ps
CPU time 58.51 seconds
Started Jul 05 05:45:43 PM PDT 24
Finished Jul 05 05:46:41 PM PDT 24
Peak memory 200268 kb
Host smart-b1c27e3a-99bd-45a3-ab25-ba0af988c1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518931141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3518931141
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.183555244
Short name T325
Test name
Test status
Simulation time 2032595312 ps
CPU time 316.3 seconds
Started Jul 05 05:45:44 PM PDT 24
Finished Jul 05 05:51:01 PM PDT 24
Peak memory 648792 kb
Host smart-fdec6e3d-6e4e-4e4b-af55-364ae0055584
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=183555244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.183555244
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.212899905
Short name T444
Test name
Test status
Simulation time 4553752260 ps
CPU time 74.68 seconds
Started Jul 05 05:45:45 PM PDT 24
Finished Jul 05 05:47:01 PM PDT 24
Peak memory 200300 kb
Host smart-c254485c-c4db-4abd-8735-4ac59df707c8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212899905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.212899905
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.4068701799
Short name T248
Test name
Test status
Simulation time 72608384542 ps
CPU time 154.39 seconds
Started Jul 05 05:45:41 PM PDT 24
Finished Jul 05 05:48:16 PM PDT 24
Peak memory 200384 kb
Host smart-a7055369-6e9b-402b-94a1-d65968c99a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068701799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.4068701799
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1512592612
Short name T264
Test name
Test status
Simulation time 265880103 ps
CPU time 6.52 seconds
Started Jul 05 05:45:42 PM PDT 24
Finished Jul 05 05:45:49 PM PDT 24
Peak memory 200360 kb
Host smart-8a68df3d-f197-4310-9636-e8444bb6b24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512592612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1512592612
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2624946389
Short name T225
Test name
Test status
Simulation time 58897020475 ps
CPU time 1835.09 seconds
Started Jul 05 05:45:45 PM PDT 24
Finished Jul 05 06:16:22 PM PDT 24
Peak memory 792924 kb
Host smart-d57392ec-911b-459b-8fcd-50b54711ade9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624946389 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2624946389
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.2263814208
Short name T70
Test name
Test status
Simulation time 195934912052 ps
CPU time 6487.02 seconds
Started Jul 05 05:45:51 PM PDT 24
Finished Jul 05 07:33:59 PM PDT 24
Peak memory 894640 kb
Host smart-7d37cfe1-0b27-42cb-8d94-31f4563554f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2263814208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.2263814208
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.417875442
Short name T377
Test name
Test status
Simulation time 7921393553 ps
CPU time 26.96 seconds
Started Jul 05 05:45:45 PM PDT 24
Finished Jul 05 05:46:13 PM PDT 24
Peak memory 200380 kb
Host smart-03c761d3-c536-4736-b457-78f6b369865c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417875442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.417875442
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1291381625
Short name T163
Test name
Test status
Simulation time 37694828 ps
CPU time 0.63 seconds
Started Jul 05 05:45:43 PM PDT 24
Finished Jul 05 05:45:44 PM PDT 24
Peak memory 196884 kb
Host smart-6cdd6918-975c-4a44-93c3-5d35706bb319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291381625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1291381625
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3072984562
Short name T472
Test name
Test status
Simulation time 1332666964 ps
CPU time 73.93 seconds
Started Jul 05 05:45:47 PM PDT 24
Finished Jul 05 05:47:02 PM PDT 24
Peak memory 200356 kb
Host smart-9096f069-eb97-49ca-9bb9-31c7129649cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3072984562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3072984562
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.4232648151
Short name T280
Test name
Test status
Simulation time 1008228773 ps
CPU time 14.4 seconds
Started Jul 05 05:45:45 PM PDT 24
Finished Jul 05 05:45:59 PM PDT 24
Peak memory 200336 kb
Host smart-792eb575-59e8-45ce-90d9-b143e96ca1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232648151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.4232648151
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.45358763
Short name T346
Test name
Test status
Simulation time 2676256262 ps
CPU time 191.84 seconds
Started Jul 05 05:45:45 PM PDT 24
Finished Jul 05 05:48:58 PM PDT 24
Peak memory 457348 kb
Host smart-40917652-3fc4-49b9-90e5-8af22f69cfd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=45358763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.45358763
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1585990130
Short name T296
Test name
Test status
Simulation time 13418864344 ps
CPU time 232.36 seconds
Started Jul 05 05:45:47 PM PDT 24
Finished Jul 05 05:49:40 PM PDT 24
Peak memory 200412 kb
Host smart-124c4ff7-a6d0-4ab7-a820-6aa03306ebc1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585990130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1585990130
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.417631040
Short name T403
Test name
Test status
Simulation time 1941409869 ps
CPU time 106.68 seconds
Started Jul 05 05:45:45 PM PDT 24
Finished Jul 05 05:47:33 PM PDT 24
Peak memory 200564 kb
Host smart-e5ac52c2-12f7-4574-93b1-f24083dc3aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417631040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.417631040
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3967380395
Short name T522
Test name
Test status
Simulation time 88507271 ps
CPU time 0.8 seconds
Started Jul 05 05:45:48 PM PDT 24
Finished Jul 05 05:45:49 PM PDT 24
Peak memory 198160 kb
Host smart-f6d83385-7dba-4192-a4a6-168dff0aa05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967380395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3967380395
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.874656889
Short name T379
Test name
Test status
Simulation time 554784777552 ps
CPU time 1488.15 seconds
Started Jul 05 05:45:44 PM PDT 24
Finished Jul 05 06:10:32 PM PDT 24
Peak memory 661812 kb
Host smart-1d2f0cf6-0d9b-41a4-83cb-7bc99e9f90ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874656889 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.874656889
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2754958035
Short name T136
Test name
Test status
Simulation time 5334648756 ps
CPU time 61.54 seconds
Started Jul 05 05:45:47 PM PDT 24
Finished Jul 05 05:46:49 PM PDT 24
Peak memory 200424 kb
Host smart-4e870e77-856d-46a7-a373-7985b370eddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754958035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2754958035
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3408427965
Short name T406
Test name
Test status
Simulation time 46175642 ps
CPU time 0.59 seconds
Started Jul 05 05:45:46 PM PDT 24
Finished Jul 05 05:45:47 PM PDT 24
Peak memory 196220 kb
Host smart-23255635-ced5-4a1b-a703-87c40d1c5380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408427965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3408427965
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.107089931
Short name T484
Test name
Test status
Simulation time 1302738885 ps
CPU time 35.28 seconds
Started Jul 05 05:45:53 PM PDT 24
Finished Jul 05 05:46:29 PM PDT 24
Peak memory 200340 kb
Host smart-901063c3-74fa-423b-b70a-98faddee894a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107089931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.107089931
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.966203029
Short name T311
Test name
Test status
Simulation time 10065447002 ps
CPU time 418.66 seconds
Started Jul 05 05:45:43 PM PDT 24
Finished Jul 05 05:52:42 PM PDT 24
Peak memory 656048 kb
Host smart-1aa6d2f1-29fd-4ca0-85e6-008a8b33bd0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=966203029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.966203029
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.4168367160
Short name T404
Test name
Test status
Simulation time 4678911346 ps
CPU time 60.47 seconds
Started Jul 05 05:45:46 PM PDT 24
Finished Jul 05 05:46:47 PM PDT 24
Peak memory 200348 kb
Host smart-49f2c082-95cc-4b99-a8ba-5c9e2462f84a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168367160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.4168367160
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.525606140
Short name T234
Test name
Test status
Simulation time 2110121775 ps
CPU time 57.38 seconds
Started Jul 05 05:45:45 PM PDT 24
Finished Jul 05 05:46:44 PM PDT 24
Peak memory 200200 kb
Host smart-b2d83644-3fe4-458e-8385-6f8a271e2f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525606140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.525606140
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.2918426991
Short name T191
Test name
Test status
Simulation time 1100304370 ps
CPU time 14.03 seconds
Started Jul 05 05:45:48 PM PDT 24
Finished Jul 05 05:46:02 PM PDT 24
Peak memory 200352 kb
Host smart-49262cd6-cad9-479b-80a0-f57321975d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918426991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2918426991
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3996285596
Short name T426
Test name
Test status
Simulation time 46024980136 ps
CPU time 147.43 seconds
Started Jul 05 05:45:46 PM PDT 24
Finished Jul 05 05:48:14 PM PDT 24
Peak memory 200360 kb
Host smart-55772ed1-13aa-4ee2-b1bb-a2816ddc229d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996285596 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3996285596
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1264589788
Short name T393
Test name
Test status
Simulation time 4887144190 ps
CPU time 59.67 seconds
Started Jul 05 05:45:52 PM PDT 24
Finished Jul 05 05:46:52 PM PDT 24
Peak memory 200384 kb
Host smart-93b3fe56-a594-40d3-87ad-c190170c64d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264589788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1264589788
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1630360083
Short name T321
Test name
Test status
Simulation time 14334828 ps
CPU time 0.59 seconds
Started Jul 05 05:45:51 PM PDT 24
Finished Jul 05 05:45:52 PM PDT 24
Peak memory 196232 kb
Host smart-206e98f5-de3f-42ae-a0b6-8fbdb18ff282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630360083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1630360083
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1295651778
Short name T525
Test name
Test status
Simulation time 3390013026 ps
CPU time 52.19 seconds
Started Jul 05 05:45:54 PM PDT 24
Finished Jul 05 05:46:46 PM PDT 24
Peak memory 200344 kb
Host smart-af9e6b5b-1804-43e8-bc2e-1a35f2e7136b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1295651778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1295651778
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.521283823
Short name T8
Test name
Test status
Simulation time 2105782071 ps
CPU time 37 seconds
Started Jul 05 05:45:51 PM PDT 24
Finished Jul 05 05:46:29 PM PDT 24
Peak memory 200364 kb
Host smart-8f269623-7b38-4df2-9099-8b446b86e1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521283823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.521283823
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.409391482
Short name T527
Test name
Test status
Simulation time 14567975175 ps
CPU time 579 seconds
Started Jul 05 05:45:54 PM PDT 24
Finished Jul 05 05:55:33 PM PDT 24
Peak memory 715652 kb
Host smart-2b9d2872-2047-42c4-bfd2-1ecf3dbdd8ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=409391482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.409391482
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2516602969
Short name T520
Test name
Test status
Simulation time 6241793715 ps
CPU time 171.14 seconds
Started Jul 05 05:46:00 PM PDT 24
Finished Jul 05 05:48:52 PM PDT 24
Peak memory 200412 kb
Host smart-65607c1d-4105-4b92-adcf-60ee80f69787
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516602969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2516602969
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2923433574
Short name T507
Test name
Test status
Simulation time 32075133125 ps
CPU time 35.73 seconds
Started Jul 05 05:45:55 PM PDT 24
Finished Jul 05 05:46:32 PM PDT 24
Peak memory 200376 kb
Host smart-258c5c47-0e77-4ce7-accc-dfc20012d7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923433574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2923433574
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1190846144
Short name T255
Test name
Test status
Simulation time 35942595 ps
CPU time 1.7 seconds
Started Jul 05 05:45:44 PM PDT 24
Finished Jul 05 05:45:46 PM PDT 24
Peak memory 200292 kb
Host smart-c71b6590-e485-4652-b480-1ac999898e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190846144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1190846144
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3162157204
Short name T270
Test name
Test status
Simulation time 31637733519 ps
CPU time 384.93 seconds
Started Jul 05 05:45:53 PM PDT 24
Finished Jul 05 05:52:18 PM PDT 24
Peak memory 603900 kb
Host smart-599c7c73-1fff-493a-ba1e-26d5c1c947ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162157204 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3162157204
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.6225046
Short name T78
Test name
Test status
Simulation time 1498521002 ps
CPU time 78.71 seconds
Started Jul 05 05:45:52 PM PDT 24
Finished Jul 05 05:47:12 PM PDT 24
Peak memory 200252 kb
Host smart-2cebfdbd-e52d-488f-a69a-a2bc804b0778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6225046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.6225046
Directory /workspace/9.hmac_wipe_secret/latest
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