Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	17617194	1			T1	17996		T2	3634		T3	3397
all_values[1]	17617194	1			T1	17996		T2	3634		T3	3397
all_values[2]	17617194	1			T1	17996		T2	3634		T3	3397

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

197468

1

T4

4

T18

802

T5

31

auto[1]

52654114

1

T1

53988

T2

10902

T3

10191

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44904128

1

T1

47839

T2

9252

T3

8138

auto[1]

7947454

1

T1

6149

T2

1650

T3

2053

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	84180	1			T4	2		T5	5		T61	4
all_values[0]	auto[0]	auto[1]	334	1			T5	4		T37	4		T105	2
all_values[0]	auto[1]	auto[0]	17513053	1			T1	17974		T2	3600		T3	3376
all_values[0]	auto[1]	auto[1]	19627	1			T1	22		T2	34		T3	21
all_values[1]	auto[0]	auto[0]	66794	1			T4	2		T18	802		T5	9
all_values[1]	auto[0]	auto[1]	169	1			T5	3		T38	1		T21	1
all_values[1]	auto[1]	auto[0]	17549887	1			T1	17996		T2	3634		T3	3397
all_values[1]	auto[1]	auto[1]	344	1			T5	3		T7	3		T20	7
all_values[2]	auto[0]	auto[0]	23793	1			T5	5		T6	209		T39	2
all_values[2]	auto[0]	auto[1]	22198	1			T5	5		T6	676		T39	641
all_values[2]	auto[1]	auto[0]	9666421	1			T1	11869		T2	2018		T3	1365
all_values[2]	auto[1]	auto[1]	7904782	1			T1	6127		T2	1616		T3	2032