Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

155734

1

T1

14

T2

1726

T3

1276

auto[1]

158994

1

T1

26

T2

1252

T3

1766

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	120891	1			T1	16		T2	1390		T3	798
len_1026_2046	8048	1			T1	1		T2	51		T3	248
len_514_1022	4423	1			T2	25		T3	8		T5	13
len_2_510	4000	1			T2	14		T3	438		T5	11
len_2056	151	1			T37	2		T7	4		T20	3
len_2048	314	1			T1	1		T2	1		T3	1
len_2040	379	1			T5	3		T37	2		T21	1
len_1032	144	1			T7	1		T21	1		T117	2
len_1024	1995	1			T1	1		T2	1		T3	3
len_1016	227	1			T5	2		T37	4		T7	3
len_520	227	1			T5	3		T20	3		T21	5
len_512	433	1			T2	4		T3	2		T4	1
len_504	414	1			T5	4		T118	3		T7	6
len_8	1004	1			T5	4		T61	10		T10	10
len_0	14715	1			T1	1		T2	3		T3	23

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

161

1

T1

1

T5

7

T10

2

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	60170	1			T1	4		T2	808		T3	245
auto[0]	len_1026_2046	3940	1			T1	1		T2	39		T3	10
auto[0]	len_514_1022	2293	1			T2	9		T3	6		T5	3
auto[0]	len_2_510	2390	1			T2	5		T3	374		T5	1
auto[0]	len_2056	82	1			T37	1		T7	2		T38	1
auto[0]	len_2048	176	1			T1	1		T2	1		T37	2
auto[0]	len_2040	292	1			T37	2		T117	1		T63	1
auto[0]	len_1032	73	1			T117	1		T9	2		T119	2
auto[0]	len_1024	329	1			T3	2		T5	4		T105	2
auto[0]	len_1016	140	1			T37	3		T7	1		T20	3
auto[0]	len_520	104	1			T5	2		T20	3		T21	1
auto[0]	len_512	265	1			T2	1		T3	1		T4	1
auto[0]	len_504	323	1			T118	3		T7	4		T20	203
auto[0]	len_8	23	1			T5	1		T120	1		T104	1
auto[0]	len_0	7268	1			T1	1		T4	3		T18	1
auto[1]	len_2050_plus	60721	1			T1	12		T2	582		T3	553
auto[1]	len_1026_2046	4108	1			T2	12		T3	238		T4	1
auto[1]	len_514_1022	2130	1			T2	16		T3	2		T5	10
auto[1]	len_2_510	1610	1			T2	9		T3	64		T5	10
auto[1]	len_2056	69	1			T37	1		T7	2		T20	3
auto[1]	len_2048	138	1			T3	1		T5	3		T37	2
auto[1]	len_2040	87	1			T5	3		T21	1		T63	2
auto[1]	len_1032	71	1			T7	1		T21	1		T117	1
auto[1]	len_1024	1666	1			T1	1		T2	1		T3	1
auto[1]	len_1016	87	1			T5	2		T37	1		T7	2
auto[1]	len_520	123	1			T5	1		T21	4		T63	7
auto[1]	len_512	168	1			T2	3		T3	1		T5	3
auto[1]	len_504	91	1			T5	4		T7	2		T20	12
auto[1]	len_8	981	1			T5	3		T61	10		T10	10
auto[1]	len_0	7447	1			T2	3		T3	23		T4	2

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

86

1

T1

1

T5

1

T7

1

auto[1]

len_upper

75

1

T5

6

T10

2

T121

2