Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4487041 1 T1 4322 T2 4571 T3 2906
auto[1] 2863453 1 T1 4631 T2 1562 T3 3303


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2891908 1 T1 5001 T2 2173 T3 3534
auto[1] 4458586 1 T1 3952 T2 3960 T3 2675


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3278495 1 T1 3201 T2 3576 T3 2508
auto[1] 4071999 1 T1 5752 T2 2557 T3 3701


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4439864 1 T1 3576 T2 3075 T3 3004
auto[1] 2910630 1 T1 5377 T2 3058 T3 3205


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 6473659 1 T1 8707 T2 5808 T3 5908
fifo_depth[1] 127174 1 T1 147 T2 44 T3 31
fifo_depth[2] 105589 1 T1 66 T2 135 T3 56
fifo_depth[3] 87395 1 T1 29 T2 26 T3 37
fifo_depth[4] 80737 1 T1 4 T2 84 T3 74
fifo_depth[5] 62429 1 T2 12 T3 27 T4 305
fifo_depth[6] 50611 1 T2 19 T3 28 T4 234
fifo_depth[7] 33269 1 T2 2 T3 12 T4 134


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 876835 1 T1 246 T2 325 T3 301
auto[1] 6473659 1 T1 8707 T2 5808 T3 5908


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7328842 1 T1 8953 T2 6133 T3 6209
auto[1] 21652 1 T7 133 T20 336 T21 79


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 45322 1 T1 16 T2 129 T4 104
auto[0] auto[0] auto[0] auto[0] auto[1] 36947 1 T1 12 T3 36 T4 241
auto[0] auto[0] auto[0] auto[1] auto[0] 47619 1 T1 3 T3 2 T4 625
auto[0] auto[0] auto[0] auto[1] auto[1] 45628 1 T1 24 T2 4 T3 24
auto[0] auto[0] auto[1] auto[0] auto[0] 187752 1 T3 103 T4 130 T6 345
auto[0] auto[0] auto[1] auto[0] auto[1] 40471 1 T1 3 T2 83 T37 50
auto[0] auto[0] auto[1] auto[1] auto[0] 39797 1 T2 61 T5 1 T6 251
auto[0] auto[0] auto[1] auto[1] auto[1] 41005 1 T1 13 T2 3 T4 210
auto[0] auto[1] auto[0] auto[0] auto[0] 48180 1 T1 17 T3 49 T4 239
auto[0] auto[1] auto[0] auto[0] auto[1] 44921 1 T1 11 T2 9 T3 26
auto[0] auto[1] auto[0] auto[1] auto[0] 42675 1 T1 31 T2 3 T6 171
auto[0] auto[1] auto[0] auto[1] auto[1] 50067 1 T1 53 T2 5 T4 86
auto[0] auto[1] auto[1] auto[0] auto[0] 54372 1 T2 2 T3 60 T4 14
auto[0] auto[1] auto[1] auto[0] auto[1] 53979 1 T2 26 T3 1 T5 72
auto[0] auto[1] auto[1] auto[1] auto[0] 51438 1 T4 147 T5 13 T6 54
auto[0] auto[1] auto[1] auto[1] auto[1] 46662 1 T1 63 T4 88 T5 3
auto[1] auto[0] auto[0] auto[0] auto[0] 173313 1 T1 1681 T2 1089 T3 3
auto[1] auto[0] auto[0] auto[0] auto[1] 176764 1 T1 299 T2 329 T3 135
auto[1] auto[0] auto[0] auto[1] auto[0] 176327 1 T1 41 T2 267 T3 345
auto[1] auto[0] auto[0] auto[1] auto[1] 197509 1 T1 393 T2 50 T3 187
auto[1] auto[0] auto[1] auto[0] auto[0] 1539535 1 T2 127 T3 250 T4 317
auto[1] auto[0] auto[1] auto[0] auto[1] 170874 1 T1 40 T2 605 T5 118
auto[1] auto[0] auto[1] auto[1] auto[0] 166053 1 T2 745 T3 1363 T4 1
auto[1] auto[0] auto[1] auto[1] auto[1] 193579 1 T1 676 T2 84 T3 60
auto[1] auto[1] auto[0] auto[0] auto[0] 480808 1 T1 281 T2 58 T3 253
auto[1] auto[1] auto[0] auto[0] auto[1] 442579 1 T1 440 T2 75 T3 1583
auto[1] auto[1] auto[0] auto[1] auto[0] 430288 1 T1 789 T2 113 T3 92
auto[1] auto[1] auto[0] auto[1] auto[1] 452961 1 T1 910 T2 42 T3 799
auto[1] auto[1] auto[1] auto[0] auto[0] 492021 1 T1 717 T2 432 T3 256
auto[1] auto[1] auto[1] auto[0] auto[1] 499203 1 T1 805 T2 1607 T3 151
auto[1] auto[1] auto[1] auto[1] auto[0] 464364 1 T2 49 T3 228 T4 1464
auto[1] auto[1] auto[1] auto[1] auto[1] 417481 1 T1 1635 T2 136 T3 203


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 214046 1 T1 1697 T2 1218 T3 3
auto[0] auto[0] auto[0] auto[0] auto[1] 212371 1 T1 311 T2 329 T3 171
auto[0] auto[0] auto[0] auto[1] auto[0] 222796 1 T1 44 T2 267 T3 347
auto[0] auto[0] auto[0] auto[1] auto[1] 241625 1 T1 417 T2 54 T3 211
auto[0] auto[0] auto[1] auto[0] auto[0] 1726156 1 T2 127 T3 353 T4 447
auto[0] auto[0] auto[1] auto[0] auto[1] 210549 1 T1 43 T2 688 T5 118
auto[0] auto[0] auto[1] auto[1] auto[0] 203802 1 T2 806 T3 1363 T4 1
auto[0] auto[0] auto[1] auto[1] auto[1] 233712 1 T1 689 T2 87 T3 60
auto[0] auto[1] auto[0] auto[0] auto[0] 528251 1 T1 298 T2 58 T3 302
auto[0] auto[1] auto[0] auto[0] auto[1] 487009 1 T1 451 T2 84 T3 1609
auto[0] auto[1] auto[0] auto[1] auto[0] 472084 1 T1 820 T2 116 T3 92
auto[0] auto[1] auto[0] auto[1] auto[1] 502230 1 T1 963 T2 47 T3 799
auto[0] auto[1] auto[1] auto[0] auto[0] 546245 1 T1 717 T2 434 T3 316
auto[0] auto[1] auto[1] auto[0] auto[1] 550647 1 T1 805 T2 1633 T3 152
auto[0] auto[1] auto[1] auto[1] auto[0] 514173 1 T2 49 T3 228 T4 1611
auto[0] auto[1] auto[1] auto[1] auto[1] 463146 1 T1 1698 T2 136 T3 203
auto[1] auto[0] auto[0] auto[0] auto[0] 4589 1 T9 44 T123 52 T12 373
auto[1] auto[0] auto[0] auto[0] auto[1] 1340 1 T9 16 T124 3 T125 187
auto[1] auto[0] auto[0] auto[1] auto[0] 1150 1 T7 22 T21 62 T103 14
auto[1] auto[0] auto[0] auto[1] auto[1] 1512 1 T20 18 T9 668 T124 6
auto[1] auto[0] auto[1] auto[0] auto[0] 1131 1 T7 43 T20 52 T9 15
auto[1] auto[0] auto[1] auto[0] auto[1] 796 1 T7 1 T20 236 T103 1
auto[1] auto[0] auto[1] auto[1] auto[0] 2048 1 T21 4 T103 10 T9 9
auto[1] auto[0] auto[1] auto[1] auto[1] 872 1 T7 10 T20 7 T21 1
auto[1] auto[1] auto[0] auto[0] auto[0] 737 1 T7 9 T21 6 T125 69
auto[1] auto[1] auto[0] auto[0] auto[1] 491 1 T7 6 T9 44 T125 64
auto[1] auto[1] auto[0] auto[1] auto[0] 879 1 T20 3 T21 6 T9 17
auto[1] auto[1] auto[0] auto[1] auto[1] 798 1 T7 1 T20 12 T9 64
auto[1] auto[1] auto[1] auto[0] auto[0] 148 1 T7 40 T125 1 T77 2
auto[1] auto[1] auto[1] auto[0] auto[1] 2535 1 T20 8 T9 41 T124 7
auto[1] auto[1] auto[1] auto[1] auto[0] 1629 1 T7 1 T125 1 T76 401
auto[1] auto[1] auto[1] auto[1] auto[1] 997 1 T9 10 T124 390 T76 32


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 173313 1 T1 1681 T2 1089 T3 3
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 176764 1 T1 299 T2 329 T3 135
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 176327 1 T1 41 T2 267 T3 345
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 197509 1 T1 393 T2 50 T3 187
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1539535 1 T2 127 T3 250 T4 317
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 170874 1 T1 40 T2 605 T5 118
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 166053 1 T2 745 T3 1363 T4 1
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 193579 1 T1 676 T2 84 T3 60
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 480808 1 T1 281 T2 58 T3 253
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 442579 1 T1 440 T2 75 T3 1583
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 430288 1 T1 789 T2 113 T3 92
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 452961 1 T1 910 T2 42 T3 799
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 492021 1 T1 717 T2 432 T3 256
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 499203 1 T1 805 T2 1607 T3 151
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 464364 1 T2 49 T3 228 T4 1464
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 417481 1 T1 1635 T2 136 T3 203
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 3835 1 T1 10 T2 11 T4 18
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 3677 1 T1 7 T3 1 T4 42
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 4340 1 T1 3 T4 107 T23 5
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 4334 1 T1 15 T3 6 T4 65
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 46311 1 T3 7 T4 22 T6 60
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 3772 1 T1 1 T2 19 T37 35
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 3554 1 T2 2 T5 1 T6 43
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 3941 1 T1 7 T4 30 T6 5
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 6763 1 T1 5 T3 10 T4 29
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 6179 1 T1 6 T2 2 T3 1
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 5557 1 T1 19 T2 3 T6 25
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 6279 1 T1 34 T2 2 T4 12
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 8361 1 T2 1 T3 6 T4 2
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 6985 1 T2 4 T5 35 T6 20
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 6614 1 T4 19 T5 2 T6 8
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 6672 1 T1 40 T4 18 T5 1
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 3448 1 T1 5 T2 72 T4 15
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 3078 1 T1 5 T3 8 T4 37
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 4059 1 T4 123 T37 5 T126 7
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 3554 1 T1 6 T2 2 T3 4
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 35366 1 T3 25 T4 18 T6 62
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 3136 1 T1 2 T2 23 T37 8
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 2964 1 T2 30 T6 46 T37 18
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 3443 1 T1 5 T4 27 T6 8
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 6015 1 T1 5 T3 8 T4 39
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 5377 1 T1 3 T2 2 T3 1
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 4508 1 T1 4 T6 29 T23 4
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 5548 1 T1 14 T2 1 T4 15
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 7469 1 T2 1 T3 10 T4 3
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 5974 1 T2 4 T5 30 T6 26
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 5789 1 T4 22 T5 5 T6 8
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 5861 1 T1 17 T4 11 T5 2
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 2696 1 T1 1 T2 6 T4 12
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 2344 1 T4 40 T6 35 T37 3
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 3075 1 T4 108 T37 2 T126 7
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 2738 1 T1 2 T3 6 T4 44
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 27837 1 T3 10 T4 30 T6 51
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 2321 1 T2 14 T37 5 T7 77
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 2322 1 T2 1 T6 42 T37 7
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 2791 1 T4 46 T6 6 T37 5
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 5316 1 T1 6 T3 10 T4 33
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 4795 1 T1 2 T2 2 T3 2
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 3966 1 T1 7 T6 30 T37 5
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 5056 1 T1 5 T4 7 T37 3
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 6232 1 T3 9 T4 1 T5 2
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 5227 1 T2 3 T5 5 T6 17
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 5326 1 T4 20 T6 8 T10 76
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 5353 1 T1 6 T4 18 T37 1
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2868 1 T2 35 T4 18 T126 12
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 2531 1 T3 10 T4 47 T5 6
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 3575 1 T4 108 T37 1 T126 5
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 2845 1 T1 1 T2 1 T3 4
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 20276 1 T3 22 T4 21 T6 49
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 2385 1 T2 18 T37 1 T7 67
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 2394 1 T2 18 T6 38 T37 4
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 3178 1 T1 1 T2 1 T4 49
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 5051 1 T1 1 T3 10 T4 29
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 4602 1 T2 1 T3 22 T6 32
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 3978 1 T1 1 T6 22 T37 2
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 5020 1 T4 11 T37 2 T10 77
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 6185 1 T3 6 T4 4 T7 116
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 5334 1 T2 10 T5 2 T6 15
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 5350 1 T4 22 T5 3 T6 6
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 5165 1 T4 12 T10 70 T7 96
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 2104 1 T2 2 T4 14 T126 10
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 1656 1 T4 28 T6 29 T7 9
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 2401 1 T4 84 T126 5 T7 14
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 2113 1 T3 2 T4 51 T7 30
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 14119 1 T3 11 T4 21 T6 46
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 1975 1 T2 4 T37 1 T7 57
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1943 1 T2 1 T6 37 T7 26
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 2005 1 T2 1 T4 22 T6 9
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 4360 1 T3 6 T4 37 T37 1
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 4038 1 T2 1 T6 34 T118 1
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 3244 1 T6 28 T10 82 T7 55
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 4459 1 T2 1 T4 15 T10 62
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 4780 1 T3 8 T4 1 T7 93
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 4437 1 T2 2 T6 15 T10 102
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 4476 1 T4 18 T6 10 T10 81
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 4319 1 T4 14 T10 68 T7 96
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1584 1 T2 1 T4 9 T126 5
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1761 1 T3 9 T4 26 T6 16
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 2317 1 T3 1 T4 63 T126 5
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1682 1 T2 1 T3 1 T4 44
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 9703 1 T3 10 T4 8 T6 40
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1786 1 T2 3 T7 46 T20 4
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1486 1 T2 8 T6 23 T7 24
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 2222 1 T2 1 T4 25 T6 8
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 3485 1 T3 2 T4 28 T37 1
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 3167 1 T2 1 T6 30 T118 1
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 2887 1 T6 15 T10 78 T7 51
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 3503 1 T2 1 T4 6 T10 36
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3855 1 T3 5 T4 1 T7 83
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 4109 1 T2 3 T6 11 T10 85
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 3497 1 T4 15 T5 1 T6 5
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 3567 1 T4 9 T10 48 T7 86
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 1075 1 T2 1 T4 6 T126 4
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 1108 1 T4 13 T6 9 T7 2
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 1290 1 T4 19 T126 3 T7 8
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 1208 1 T4 40 T7 13 T20 26
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 5968 1 T3 4 T4 5 T6 24
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 1328 1 T2 1 T102 1 T7 33
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 1101 1 T6 13 T7 7 T20 30
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 1235 1 T4 8 T6 6 T7 103
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 2456 1 T3 2 T4 22 T7 34
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 2132 1 T6 15 T118 1 T7 91
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 2022 1 T6 13 T10 35 T7 39
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 2462 1 T4 8 T10 33 T126 2
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2511 1 T3 6 T7 65 T20 28
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 2725 1 T6 14 T10 63 T7 10
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 2393 1 T4 9 T6 1 T10 47
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 2255 1 T4 4 T10 43 T7 56

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