Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	17617194	1			T1	17996		T2	3634		T3	3397
all_pins[1]	17617194	1			T1	17996		T2	3634		T3	3397
all_pins[2]	17617194	1			T1	17996		T2	3634		T3	3397

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	44925869	1			T1	47838		T2	9249		T3	8138
values[0x1]	7925713	1			T1	6150		T2	1653		T3	2053
transitions[0x0=>0x1]	7925534	1			T1	6150		T2	1653		T3	2053
transitions[0x1=>0x0]	7925548	1			T1	6150		T2	1653		T3	2053

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	17596646	1			T1	17973		T2	3597		T3	3376
all_pins[0]	values[0x1]	20548	1			T1	23		T2	37		T3	21
all_pins[0]	transitions[0x0=>0x1]	20473	1			T1	23		T2	37		T3	21
all_pins[0]	transitions[0x1=>0x0]	7904721	1			T1	6127		T2	1616		T3	2032
all_pins[1]	values[0x0]	17616811	1			T1	17996		T2	3634		T3	3397
all_pins[1]	values[0x1]	383	1			T5	3		T7	3		T20	8
all_pins[1]	transitions[0x0=>0x1]	333	1			T5	3		T7	3		T20	7
all_pins[1]	transitions[0x1=>0x0]	20498	1			T1	23		T2	37		T3	21
all_pins[2]	values[0x0]	9712412	1			T1	11869		T2	2018		T3	1365
all_pins[2]	values[0x1]	7904782	1			T1	6127		T2	1616		T3	2032
all_pins[2]	transitions[0x0=>0x1]	7904728	1			T1	6127		T2	1616		T3	2032
all_pins[2]	transitions[0x1=>0x0]	329	1			T5	1		T7	3		T20	8