Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 919 1 T5 14 T20 4 T38 18
all_values[1] 919 1 T5 14 T20 4 T38 18
all_values[2] 919 1 T5 14 T20 4 T38 18


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1368 1 T5 19 T20 2 T38 30
auto[1] 1389 1 T5 23 T20 10 T38 24


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 998 1 T5 10 T20 6 T38 25
auto[1] 1759 1 T5 32 T20 6 T38 29


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1574 1 T5 20 T20 9 T38 33
auto[1] 1183 1 T5 22 T20 3 T38 21


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 165 1 T5 2 T38 5 T63 3
all_values[0] auto[0] auto[0] auto[1] 82 1 T5 3 T38 1 T21 2
all_values[0] auto[0] auto[1] auto[0] 200 1 T5 3 T20 2 T38 6
all_values[0] auto[0] auto[1] auto[1] 83 1 T20 1 T21 2 T12 1
all_values[0] auto[1] auto[0] auto[1] 187 1 T38 3 T21 1 T63 1
all_values[0] auto[1] auto[1] auto[1] 202 1 T5 6 T20 1 T38 3
all_values[1] auto[0] auto[0] auto[0] 158 1 T5 1 T38 6 T21 1
all_values[1] auto[0] auto[0] auto[1] 112 1 T5 4 T38 1 T21 1
all_values[1] auto[0] auto[1] auto[0] 146 1 T5 2 T20 2 T38 2
all_values[1] auto[0] auto[1] auto[1] 114 1 T5 1 T20 1 T38 3
all_values[1] auto[1] auto[0] auto[1] 190 1 T5 1 T38 3 T63 3
all_values[1] auto[1] auto[1] auto[1] 199 1 T5 5 T20 1 T38 3
all_values[2] auto[0] auto[0] auto[0] 166 1 T5 1 T38 2 T63 1
all_values[2] auto[0] auto[0] auto[1] 95 1 T5 1 T20 1 T38 2
all_values[2] auto[0] auto[1] auto[0] 163 1 T5 1 T20 2 T38 4
all_values[2] auto[0] auto[1] auto[1] 90 1 T5 1 T38 1 T21 2
all_values[2] auto[1] auto[0] auto[1] 213 1 T5 6 T20 1 T38 7
all_values[2] auto[1] auto[1] auto[1] 192 1 T5 4 T38 2 T21 4


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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