Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4389	1			T1	5		T2	11		T3	3
sha2_none	4195	1			T1	2		T2	8		T3	4
sha2_512	7690	1			T1	8		T2	10		T3	12
sha2_384	7097	1			T1	8		T2	12		T3	6
sha2_256	6402	1			T1	6		T2	7		T3	6

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18348

1

T1

13

T2

28

T3

18

auto[1]

11804

1

T1

16

T2

20

T3

14

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11461

1

T1

19

T2

22

T3

13

auto[1]

18691

1

T1

10

T2

26

T3

19

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

15641

1

T1

16

T2

23

T3

17

disabled

14511

1

T1

13

T2

25

T3

15

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4810	1			T1	7		T2	8		T3	13
key_none	7384	1			T1	3		T2	7		T3	5
key_1024	4375	1			T1	3		T2	5		T3	5
key_512	3775	1			T1	2		T2	7		T3	2
key_384	3513	1			T1	1		T2	11		T3	5
key_256	3164	1			T1	4		T2	4		T4	6
key_128	3038	1			T1	9		T2	6		T3	2

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18746

1

T1

12

T2

24

T3

17

auto[1]

11406

1

T1

17

T2

24

T3

15

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

29944

1

T1

29

T2

48

T3

32

disabled

208

1

T7

7

T20

8

T38

4

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1573

1

T1

1

T2

1

T3

1

enabled

auto[0]

auto[0]

auto[1]

1534

1

T1

2

T2

2

T3

2

enabled

auto[0]

auto[1]

auto[0]

1721

1

T1

4

T2

5

T3

1

enabled

auto[0]

auto[1]

auto[1]

1587

1

T1

2

T2

2

T3

1

enabled

auto[1]

auto[0]

auto[0]

4249

1

T1

2

T2

5

T3

4

enabled

auto[1]

auto[0]

auto[1]

1616

1

T1

1

T2

5

T3

4

enabled

auto[1]

auto[1]

auto[0]

1764

1

T2

1

T3

2

T4

5

enabled

auto[1]

auto[1]

auto[1]

1597

1

T1

4

T2

2

T3

2

disabled

auto[0]

auto[0]

auto[0]

1207

1

T1

4

T2

5

T3

1

disabled

auto[0]

auto[0]

auto[1]

1220

1

T1

2

T2

3

T3

2

disabled

auto[0]

auto[1]

auto[0]

1279

1

T1

1

T2

2

T3

3

disabled

auto[0]

auto[1]

auto[1]

1340

1

T1

3

T2

2

T3

2

disabled

auto[1]

auto[0]

auto[0]

5719

1

T2

1

T3

4

T4

3

disabled

auto[1]

auto[0]

auto[1]

1230

1

T1

1

T2

6

T5

2

disabled

auto[1]

auto[1]

auto[0]

1234

1

T2

4

T3

1

T4

1

disabled

auto[1]

auto[1]

auto[1]

1282

1

T1

2

T2

2

T3

2

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

15559

1

T1

16

T2

23

T3

17

enabled

disabled

82

1

T7

3

T20

4

T38

1

disabled

disabled

126

1

T7

4

T20

4

T38

3

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

14385

1

T1

13

T2

25

T3

15

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1223	1			T1	2		T2	1		T3	1
key_invalid	sha2_none	852	1			T2	2		T3	1		T4	3
key_invalid	sha2_512	869	1			T1	2		T2	2		T3	7
key_invalid	sha2_384	865	1			T1	1		T2	1		T3	2
key_invalid	sha2_256	902	1			T1	2		T2	2		T3	2
key_none	sha2_invalid	545	1			T1	1		T2	1		T4	2
key_none	sha2_none	567	1			T2	2		T3	1		T5	2
key_none	sha2_512	2538	1			T1	1		T2	1		T3	1
key_none	sha2_384	2139	1			T2	3		T3	1		T4	1
key_none	sha2_256	1538	1			T1	1		T3	2		T4	1
key_1024	sha2_invalid	511	1			T3	1		T5	1		T23	2
key_1024	sha2_none	570	1			T1	1		T4	1		T6	2
key_1024	sha2_512	1732	1			T2	2		T3	1		T4	3
key_1024	sha2_384	945	1			T1	1		T2	1		T3	1
key_512	sha2_invalid	513	1			T2	2		T5	4		T6	1
key_512	sha2_none	593	1			T3	1		T5	3		T6	1
key_512	sha2_512	628	1			T1	1		T3	1		T4	1
key_512	sha2_384	1194	1			T2	2		T4	4		T5	1
key_512	sha2_256	810	1			T1	1		T2	3		T4	1
key_384	sha2_invalid	520	1			T2	6		T3	1		T4	2
key_384	sha2_none	579	1			T2	2		T4	2		T5	3
key_384	sha2_512	609	1			T2	1		T3	1		T4	1
key_384	sha2_384	643	1			T1	1		T2	2		T3	2
key_384	sha2_256	1111	1			T3	1		T6	1		T37	2
key_256	sha2_invalid	502	1			T4	1		T5	2		T6	2
key_256	sha2_none	489	1			T2	2		T4	1		T5	4
key_256	sha2_512	645	1			T1	1		T4	2		T18	1
key_256	sha2_384	672	1			T1	3		T2	2		T4	1
key_256	sha2_256	809	1			T4	1		T18	1		T5	7
key_128	sha2_invalid	552	1			T1	2		T2	1		T4	1
key_128	sha2_none	525	1			T1	1		T3	1		T4	1
key_128	sha2_512	644	1			T1	3		T2	4		T3	1
key_128	sha2_384	633	1			T1	2		T2	1		T5	2
key_128	sha2_256	635	1			T1	1		T4	1		T5	5

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

579

1

T1

1

T2

2

T3

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1223	1			T1	2		T2	1		T3	1
key_invalid	sha2_none	852	1			T2	2		T3	1		T4	3
key_invalid	sha2_512	869	1			T1	2		T2	2		T3	7
key_invalid	sha2_384	865	1			T1	1		T2	1		T3	2
key_invalid	sha2_256	902	1			T1	2		T2	2		T3	2
key_none	sha2_invalid	545	1			T1	1		T2	1		T4	2
key_none	sha2_none	567	1			T2	2		T3	1		T5	2
key_none	sha2_512	2538	1			T1	1		T2	1		T3	1
key_none	sha2_384	2139	1			T2	3		T3	1		T4	1
key_none	sha2_256	1538	1			T1	1		T3	2		T4	1
key_1024	sha2_invalid	511	1			T3	1		T5	1		T23	2
key_1024	sha2_none	570	1			T1	1		T4	1		T6	2
key_1024	sha2_512	1732	1			T2	2		T3	1		T4	3
key_1024	sha2_384	945	1			T1	1		T2	1		T3	1
key_1024	sha2_256	579	1			T1	1		T2	2		T3	1
key_512	sha2_invalid	513	1			T2	2		T5	4		T6	1
key_512	sha2_none	593	1			T3	1		T5	3		T6	1
key_512	sha2_512	628	1			T1	1		T3	1		T4	1
key_512	sha2_384	1194	1			T2	2		T4	4		T5	1
key_512	sha2_256	810	1			T1	1		T2	3		T4	1
key_384	sha2_invalid	520	1			T2	6		T3	1		T4	2
key_384	sha2_none	579	1			T2	2		T4	2		T5	3
key_384	sha2_512	609	1			T2	1		T3	1		T4	1
key_384	sha2_384	643	1			T1	1		T2	2		T3	2
key_384	sha2_256	1111	1			T3	1		T6	1		T37	2
key_256	sha2_invalid	502	1			T4	1		T5	2		T6	2
key_256	sha2_none	489	1			T2	2		T4	1		T5	4
key_256	sha2_512	645	1			T1	1		T4	2		T18	1
key_256	sha2_384	672	1			T1	3		T2	2		T4	1
key_256	sha2_256	809	1			T4	1		T18	1		T5	7
key_128	sha2_invalid	552	1			T1	2		T2	1		T4	1
key_128	sha2_none	525	1			T1	1		T3	1		T4	1
key_128	sha2_512	644	1			T1	3		T2	4		T3	1
key_128	sha2_384	633	1			T1	2		T2	1		T5	2
key_128	sha2_256	635	1			T1	1		T4	1		T5	5