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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.51 95.26 97.22 100.00 94.12 98.12 97.97 99.85


Total test records in report: 659
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T537 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2616387632 Jul 06 07:02:26 PM PDT 24 Jul 06 07:02:28 PM PDT 24 19863019 ps
T96 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.446310192 Jul 06 07:01:38 PM PDT 24 Jul 06 07:01:40 PM PDT 24 257607490 ps
T79 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2943971206 Jul 06 07:01:45 PM PDT 24 Jul 06 07:01:55 PM PDT 24 463847544 ps
T538 /workspace/coverage/cover_reg_top/2.hmac_intr_test.3745380728 Jul 06 07:01:37 PM PDT 24 Jul 06 07:01:39 PM PDT 24 102787294 ps
T80 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1231153188 Jul 06 07:02:10 PM PDT 24 Jul 06 07:02:12 PM PDT 24 28942970 ps
T539 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1766027650 Jul 06 07:02:15 PM PDT 24 Jul 06 07:02:16 PM PDT 24 51965408 ps
T88 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3163451387 Jul 06 07:01:36 PM PDT 24 Jul 06 07:01:43 PM PDT 24 355968087 ps
T97 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2382985043 Jul 06 07:01:59 PM PDT 24 Jul 06 07:02:01 PM PDT 24 100114236 ps
T540 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3990442181 Jul 06 07:02:10 PM PDT 24 Jul 06 07:02:12 PM PDT 24 210255740 ps
T541 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1086335387 Jul 06 07:02:19 PM PDT 24 Jul 06 07:02:20 PM PDT 24 12396616 ps
T542 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3627970830 Jul 06 07:02:21 PM PDT 24 Jul 06 07:02:22 PM PDT 24 110049767 ps
T543 /workspace/coverage/cover_reg_top/40.hmac_intr_test.4002561919 Jul 06 07:02:24 PM PDT 24 Jul 06 07:02:25 PM PDT 24 41372300 ps
T54 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2570026970 Jul 06 07:01:59 PM PDT 24 Jul 06 07:02:01 PM PDT 24 647415722 ps
T544 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3735428104 Jul 06 07:02:16 PM PDT 24 Jul 06 07:02:19 PM PDT 24 142090079 ps
T545 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2053141252 Jul 06 07:02:13 PM PDT 24 Jul 06 07:02:15 PM PDT 24 18779881 ps
T546 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2635325620 Jul 06 07:01:35 PM PDT 24 Jul 06 07:01:36 PM PDT 24 34682845 ps
T547 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3895530059 Jul 06 07:02:21 PM PDT 24 Jul 06 07:02:23 PM PDT 24 159723605 ps
T548 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1932822567 Jul 06 07:01:42 PM PDT 24 Jul 06 07:01:46 PM PDT 24 90376048 ps
T549 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.393646934 Jul 06 07:02:02 PM PDT 24 Jul 06 07:02:03 PM PDT 24 51627492 ps
T550 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.584672252 Jul 06 07:02:00 PM PDT 24 Jul 06 07:02:02 PM PDT 24 52957768 ps
T551 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3438957654 Jul 06 07:02:14 PM PDT 24 Jul 06 07:02:15 PM PDT 24 38850905 ps
T552 /workspace/coverage/cover_reg_top/42.hmac_intr_test.4132279533 Jul 06 07:02:19 PM PDT 24 Jul 06 07:02:20 PM PDT 24 47632100 ps
T553 /workspace/coverage/cover_reg_top/6.hmac_intr_test.485053538 Jul 06 07:01:47 PM PDT 24 Jul 06 07:01:48 PM PDT 24 12525280 ps
T55 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.213455041 Jul 06 07:01:41 PM PDT 24 Jul 06 07:01:45 PM PDT 24 395790778 ps
T554 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3616765202 Jul 06 07:02:14 PM PDT 24 Jul 06 07:02:15 PM PDT 24 40543397 ps
T98 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3162473387 Jul 06 07:02:13 PM PDT 24 Jul 06 07:02:16 PM PDT 24 579782169 ps
T555 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1267842801 Jul 06 07:02:12 PM PDT 24 Jul 06 07:02:14 PM PDT 24 61987627 ps
T556 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3597420762 Jul 06 07:02:17 PM PDT 24 Jul 06 07:02:20 PM PDT 24 223665164 ps
T99 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.296770362 Jul 06 07:02:06 PM PDT 24 Jul 06 07:02:08 PM PDT 24 35918450 ps
T557 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3382005565 Jul 06 07:01:59 PM PDT 24 Jul 06 07:02:00 PM PDT 24 71844320 ps
T56 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2192509771 Jul 06 07:02:13 PM PDT 24 Jul 06 07:02:19 PM PDT 24 1046980966 ps
T106 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2397604984 Jul 06 07:01:36 PM PDT 24 Jul 06 07:01:39 PM PDT 24 96704298 ps
T109 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1419748160 Jul 06 07:01:53 PM PDT 24 Jul 06 07:01:58 PM PDT 24 230704787 ps
T558 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3521091081 Jul 06 07:01:45 PM PDT 24 Jul 06 07:01:47 PM PDT 24 26939909 ps
T100 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1330962167 Jul 06 07:02:13 PM PDT 24 Jul 06 07:02:16 PM PDT 24 139770663 ps
T559 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3870615728 Jul 06 07:01:53 PM PDT 24 Jul 06 07:01:54 PM PDT 24 39304413 ps
T101 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2358858357 Jul 06 07:02:11 PM PDT 24 Jul 06 07:02:13 PM PDT 24 52689196 ps
T560 /workspace/coverage/cover_reg_top/9.hmac_intr_test.983618674 Jul 06 07:01:52 PM PDT 24 Jul 06 07:01:54 PM PDT 24 174606574 ps
T561 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1765941310 Jul 06 07:01:58 PM PDT 24 Jul 06 07:02:00 PM PDT 24 308045017 ps
T107 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3938471853 Jul 06 07:01:52 PM PDT 24 Jul 06 07:01:57 PM PDT 24 126493261 ps
T562 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2672377128 Jul 06 07:02:08 PM PDT 24 Jul 06 07:02:11 PM PDT 24 76084068 ps
T563 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2610214697 Jul 06 07:02:20 PM PDT 24 Jul 06 07:02:21 PM PDT 24 13298664 ps
T564 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2145603647 Jul 06 07:01:46 PM PDT 24 Jul 06 07:01:50 PM PDT 24 477850994 ps
T565 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.920560936 Jul 06 07:02:06 PM PDT 24 Jul 06 07:02:09 PM PDT 24 101712785 ps
T81 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3296302740 Jul 06 07:01:53 PM PDT 24 Jul 06 07:01:55 PM PDT 24 16194007 ps
T566 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3758415908 Jul 06 07:01:35 PM PDT 24 Jul 06 07:01:37 PM PDT 24 216005391 ps
T567 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3545144758 Jul 06 07:02:16 PM PDT 24 Jul 06 07:02:18 PM PDT 24 27396200 ps
T115 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2110609339 Jul 06 07:01:38 PM PDT 24 Jul 06 07:01:42 PM PDT 24 1500179362 ps
T568 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2770748009 Jul 06 07:02:45 PM PDT 24 Jul 06 07:02:47 PM PDT 24 51646346 ps
T569 /workspace/coverage/cover_reg_top/34.hmac_intr_test.487601212 Jul 06 07:02:22 PM PDT 24 Jul 06 07:02:24 PM PDT 24 100804107 ps
T82 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1214644566 Jul 06 07:01:36 PM PDT 24 Jul 06 07:01:40 PM PDT 24 72974502 ps
T570 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2107066502 Jul 06 07:02:16 PM PDT 24 Jul 06 07:02:18 PM PDT 24 40173176 ps
T83 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3598739101 Jul 06 07:01:40 PM PDT 24 Jul 06 07:01:41 PM PDT 24 35974435 ps
T571 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2397197100 Jul 06 07:01:54 PM PDT 24 Jul 06 07:01:57 PM PDT 24 315284264 ps
T572 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1637239506 Jul 06 07:02:07 PM PDT 24 Jul 06 07:02:09 PM PDT 24 146056378 ps
T84 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.4131684844 Jul 06 07:02:18 PM PDT 24 Jul 06 07:02:19 PM PDT 24 31345978 ps
T573 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3113868541 Jul 06 07:02:10 PM PDT 24 Jul 06 07:02:14 PM PDT 24 786655318 ps
T574 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3629343655 Jul 06 07:01:34 PM PDT 24 Jul 06 07:01:35 PM PDT 24 44599912 ps
T110 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1809044593 Jul 06 07:01:53 PM PDT 24 Jul 06 07:01:56 PM PDT 24 96710992 ps
T575 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.11838501 Jul 06 07:02:01 PM PDT 24 Jul 06 07:02:04 PM PDT 24 120625051 ps
T576 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2482595948 Jul 06 07:01:34 PM PDT 24 Jul 06 07:01:41 PM PDT 24 2417690465 ps
T85 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3076993616 Jul 06 07:02:00 PM PDT 24 Jul 06 07:02:01 PM PDT 24 42616086 ps
T577 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2653598222 Jul 06 07:01:46 PM PDT 24 Jul 06 07:01:50 PM PDT 24 37088294 ps
T578 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2242743136 Jul 06 07:01:51 PM PDT 24 Jul 06 07:01:54 PM PDT 24 172673283 ps
T579 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.4112657499 Jul 06 07:01:53 PM PDT 24 Jul 06 07:01:57 PM PDT 24 828418848 ps
T580 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3304465313 Jul 06 07:02:06 PM PDT 24 Jul 06 07:02:09 PM PDT 24 417556312 ps
T581 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.163066398 Jul 06 07:01:45 PM PDT 24 Jul 06 07:01:51 PM PDT 24 1653944441 ps
T582 /workspace/coverage/cover_reg_top/27.hmac_intr_test.936258507 Jul 06 07:02:12 PM PDT 24 Jul 06 07:02:13 PM PDT 24 49636927 ps
T583 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1365742154 Jul 06 07:01:52 PM PDT 24 Jul 06 07:01:54 PM PDT 24 44102076 ps
T584 /workspace/coverage/cover_reg_top/18.hmac_intr_test.586213721 Jul 06 07:02:14 PM PDT 24 Jul 06 07:02:15 PM PDT 24 11940319 ps
T585 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2307317956 Jul 06 07:02:12 PM PDT 24 Jul 06 07:02:14 PM PDT 24 42799668 ps
T86 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1278059456 Jul 06 07:01:37 PM PDT 24 Jul 06 07:01:39 PM PDT 24 26751972 ps
T586 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1436272756 Jul 06 07:02:19 PM PDT 24 Jul 06 07:02:20 PM PDT 24 36584730 ps
T587 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1826351781 Jul 06 07:01:47 PM PDT 24 Jul 06 07:01:50 PM PDT 24 100390413 ps
T588 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2909385198 Jul 06 07:02:08 PM PDT 24 Jul 06 07:02:10 PM PDT 24 46459896 ps
T589 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3410041978 Jul 06 07:02:07 PM PDT 24 Jul 06 07:02:10 PM PDT 24 195669283 ps
T590 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3015010521 Jul 06 07:02:23 PM PDT 24 Jul 06 07:02:25 PM PDT 24 25724000 ps
T591 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.4164096568 Jul 06 07:02:08 PM PDT 24 Jul 06 07:02:11 PM PDT 24 62061761 ps
T592 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.967946290 Jul 06 07:02:02 PM PDT 24 Jul 06 07:02:07 PM PDT 24 708491762 ps
T87 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1812200803 Jul 06 07:01:35 PM PDT 24 Jul 06 07:01:36 PM PDT 24 52449366 ps
T593 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2603406439 Jul 06 07:01:45 PM PDT 24 Jul 06 07:01:47 PM PDT 24 43725803 ps
T113 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1132987487 Jul 06 07:01:43 PM PDT 24 Jul 06 07:01:47 PM PDT 24 183528101 ps
T594 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1439949155 Jul 06 07:02:00 PM PDT 24 Jul 06 07:02:01 PM PDT 24 43324367 ps
T595 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.582933660 Jul 06 07:01:40 PM PDT 24 Jul 06 07:01:41 PM PDT 24 22499291 ps
T596 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2056623575 Jul 06 07:02:25 PM PDT 24 Jul 06 07:02:27 PM PDT 24 46323154 ps
T597 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.44772239 Jul 06 07:01:40 PM PDT 24 Jul 06 07:01:43 PM PDT 24 412922156 ps
T598 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1853993701 Jul 06 07:02:14 PM PDT 24 Jul 06 07:02:16 PM PDT 24 12282730 ps
T599 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2622129462 Jul 06 07:01:53 PM PDT 24 Jul 06 07:16:05 PM PDT 24 620077145127 ps
T600 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1294839193 Jul 06 07:01:40 PM PDT 24 Jul 06 07:01:42 PM PDT 24 44549123 ps
T601 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3534594363 Jul 06 07:02:26 PM PDT 24 Jul 06 07:02:27 PM PDT 24 10809004 ps
T114 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2293980593 Jul 06 07:02:12 PM PDT 24 Jul 06 07:02:17 PM PDT 24 161427946 ps
T602 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2709077678 Jul 06 07:01:54 PM PDT 24 Jul 06 07:01:56 PM PDT 24 13430845 ps
T603 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1088814721 Jul 06 07:01:39 PM PDT 24 Jul 06 07:01:42 PM PDT 24 177449208 ps
T89 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1388769971 Jul 06 07:02:00 PM PDT 24 Jul 06 07:02:01 PM PDT 24 39547127 ps
T111 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2065569996 Jul 06 07:02:09 PM PDT 24 Jul 06 07:02:13 PM PDT 24 125249157 ps
T604 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.99050192 Jul 06 07:02:03 PM PDT 24 Jul 06 07:02:07 PM PDT 24 51581144 ps
T605 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2971360812 Jul 06 07:01:47 PM PDT 24 Jul 06 07:01:49 PM PDT 24 76898998 ps
T606 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4067953875 Jul 06 07:01:45 PM PDT 24 Jul 06 07:10:01 PM PDT 24 48519614119 ps
T607 /workspace/coverage/cover_reg_top/49.hmac_intr_test.14098926 Jul 06 07:02:21 PM PDT 24 Jul 06 07:02:22 PM PDT 24 37599833 ps
T608 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3458406109 Jul 06 07:01:33 PM PDT 24 Jul 06 07:01:45 PM PDT 24 740880449 ps
T90 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.772403937 Jul 06 07:01:34 PM PDT 24 Jul 06 07:01:44 PM PDT 24 2206272563 ps
T609 /workspace/coverage/cover_reg_top/47.hmac_intr_test.1454991742 Jul 06 07:02:21 PM PDT 24 Jul 06 07:02:22 PM PDT 24 45925556 ps
T610 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3546679630 Jul 06 07:02:10 PM PDT 24 Jul 06 07:02:12 PM PDT 24 181407585 ps
T91 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1066185811 Jul 06 07:01:42 PM PDT 24 Jul 06 07:01:49 PM PDT 24 1668027077 ps
T611 /workspace/coverage/cover_reg_top/15.hmac_intr_test.21642419 Jul 06 07:02:10 PM PDT 24 Jul 06 07:02:12 PM PDT 24 19982548 ps
T612 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1679826412 Jul 06 07:01:52 PM PDT 24 Jul 06 07:01:53 PM PDT 24 28118442 ps
T613 /workspace/coverage/cover_reg_top/20.hmac_intr_test.815076585 Jul 06 07:02:15 PM PDT 24 Jul 06 07:02:16 PM PDT 24 43008086 ps
T614 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1458771627 Jul 06 07:02:20 PM PDT 24 Jul 06 07:02:22 PM PDT 24 19205176 ps
T615 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1246285945 Jul 06 07:01:36 PM PDT 24 Jul 06 07:01:37 PM PDT 24 57951462 ps
T616 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2992137711 Jul 06 07:02:06 PM PDT 24 Jul 06 07:02:09 PM PDT 24 37669148 ps
T617 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.65883434 Jul 06 07:01:41 PM PDT 24 Jul 06 07:01:53 PM PDT 24 733091203 ps
T108 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.98966720 Jul 06 07:02:03 PM PDT 24 Jul 06 07:02:06 PM PDT 24 809246888 ps
T93 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3894002039 Jul 06 07:01:53 PM PDT 24 Jul 06 07:01:55 PM PDT 24 31443912 ps
T618 /workspace/coverage/cover_reg_top/41.hmac_intr_test.786700978 Jul 06 07:02:22 PM PDT 24 Jul 06 07:02:23 PM PDT 24 30513734 ps
T619 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1461318153 Jul 06 07:01:44 PM PDT 24 Jul 06 07:01:49 PM PDT 24 499357643 ps
T620 /workspace/coverage/cover_reg_top/0.hmac_intr_test.3562944029 Jul 06 07:01:33 PM PDT 24 Jul 06 07:01:35 PM PDT 24 15143740 ps
T116 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.538097610 Jul 06 07:02:00 PM PDT 24 Jul 06 07:02:02 PM PDT 24 328009603 ps
T621 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3817395222 Jul 06 07:02:01 PM PDT 24 Jul 06 07:02:05 PM PDT 24 218143307 ps
T92 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.400144248 Jul 06 07:01:44 PM PDT 24 Jul 06 07:01:45 PM PDT 24 103088979 ps
T112 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.199485919 Jul 06 07:01:46 PM PDT 24 Jul 06 07:01:49 PM PDT 24 95058146 ps
T622 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3039158347 Jul 06 07:01:40 PM PDT 24 Jul 06 07:01:41 PM PDT 24 164844072 ps
T623 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.914232823 Jul 06 07:01:46 PM PDT 24 Jul 06 07:01:50 PM PDT 24 168018248 ps
T624 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.786180386 Jul 06 07:01:33 PM PDT 24 Jul 06 07:01:43 PM PDT 24 1760052922 ps
T625 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3282020442 Jul 06 07:01:37 PM PDT 24 Jul 06 07:01:38 PM PDT 24 69173007 ps
T626 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3774054942 Jul 06 07:02:00 PM PDT 24 Jul 06 07:02:04 PM PDT 24 75519476 ps
T627 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2219152275 Jul 06 07:01:41 PM PDT 24 Jul 06 07:01:42 PM PDT 24 15434630 ps
T628 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1602345799 Jul 06 07:02:25 PM PDT 24 Jul 06 07:02:26 PM PDT 24 40592021 ps
T629 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2847777992 Jul 06 07:01:37 PM PDT 24 Jul 06 07:01:40 PM PDT 24 122209084 ps
T630 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.312980333 Jul 06 07:01:39 PM PDT 24 Jul 06 07:01:41 PM PDT 24 58043212 ps
T631 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.321533933 Jul 06 07:02:06 PM PDT 24 Jul 06 07:02:08 PM PDT 24 17865615 ps
T632 /workspace/coverage/cover_reg_top/14.hmac_intr_test.4262939815 Jul 06 07:02:10 PM PDT 24 Jul 06 07:02:11 PM PDT 24 58486757 ps
T633 /workspace/coverage/cover_reg_top/48.hmac_intr_test.754176802 Jul 06 07:02:21 PM PDT 24 Jul 06 07:02:22 PM PDT 24 34362221 ps
T634 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1309787875 Jul 06 07:02:26 PM PDT 24 Jul 06 07:02:28 PM PDT 24 11890192 ps
T635 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2810860626 Jul 06 07:02:07 PM PDT 24 Jul 06 07:02:09 PM PDT 24 39849524 ps
T57 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.722917160 Jul 06 07:01:38 PM PDT 24 Jul 06 07:01:43 PM PDT 24 464938808 ps
T636 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1993204103 Jul 06 07:01:46 PM PDT 24 Jul 06 07:01:48 PM PDT 24 14561189 ps
T637 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1343534589 Jul 06 07:02:01 PM PDT 24 Jul 06 07:02:03 PM PDT 24 177463427 ps
T638 /workspace/coverage/cover_reg_top/3.hmac_intr_test.760265491 Jul 06 07:01:41 PM PDT 24 Jul 06 07:01:42 PM PDT 24 21035648 ps
T639 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2376776741 Jul 06 07:01:53 PM PDT 24 Jul 06 07:01:56 PM PDT 24 283097041 ps
T640 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3415105355 Jul 06 07:01:35 PM PDT 24 Jul 06 07:01:39 PM PDT 24 593753509 ps
T641 /workspace/coverage/cover_reg_top/10.hmac_intr_test.2423117150 Jul 06 07:02:00 PM PDT 24 Jul 06 07:02:02 PM PDT 24 15219444 ps
T642 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1546685682 Jul 06 07:01:52 PM PDT 24 Jul 06 07:01:56 PM PDT 24 52282406 ps
T643 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1132420905 Jul 06 07:02:11 PM PDT 24 Jul 06 07:02:16 PM PDT 24 370276176 ps
T644 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3711868105 Jul 06 07:01:53 PM PDT 24 Jul 06 07:01:56 PM PDT 24 238367461 ps
T645 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3237443702 Jul 06 07:02:10 PM PDT 24 Jul 06 07:02:13 PM PDT 24 88792414 ps
T646 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1087667636 Jul 06 07:02:20 PM PDT 24 Jul 06 07:02:21 PM PDT 24 12384679 ps
T647 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1745820523 Jul 06 07:02:20 PM PDT 24 Jul 06 07:02:22 PM PDT 24 91691252 ps
T648 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3556446166 Jul 06 07:02:13 PM PDT 24 Jul 06 07:02:14 PM PDT 24 13402482 ps
T649 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1751804410 Jul 06 07:01:59 PM PDT 24 Jul 06 07:02:02 PM PDT 24 160682053 ps
T650 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3171786719 Jul 06 07:02:11 PM PDT 24 Jul 06 07:02:13 PM PDT 24 40487137 ps
T651 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3575484782 Jul 06 07:02:06 PM PDT 24 Jul 06 07:02:08 PM PDT 24 52770231 ps
T652 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1547239013 Jul 06 07:01:36 PM PDT 24 Jul 06 07:01:40 PM PDT 24 95979985 ps
T653 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2172982430 Jul 06 07:02:10 PM PDT 24 Jul 06 07:02:13 PM PDT 24 278899308 ps
T654 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3161680465 Jul 06 07:02:12 PM PDT 24 Jul 06 07:02:15 PM PDT 24 94914525 ps
T655 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3088813676 Jul 06 07:01:40 PM PDT 24 Jul 06 07:01:44 PM PDT 24 1384260392 ps
T656 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2129319590 Jul 06 07:01:41 PM PDT 24 Jul 06 07:01:42 PM PDT 24 12543314 ps
T657 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4217798055 Jul 06 07:01:33 PM PDT 24 Jul 06 07:01:36 PM PDT 24 628968193 ps
T658 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1189973627 Jul 06 07:01:35 PM PDT 24 Jul 06 07:01:37 PM PDT 24 27411812 ps
T659 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2941373303 Jul 06 07:01:36 PM PDT 24 Jul 06 07:01:38 PM PDT 24 35547617 ps

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.313350748
Short name T5
Test name
Test status
Simulation time 37198786601 ps
CPU time 577.22 seconds
Started Jul 06 07:10:54 PM PDT 24
Finished Jul 06 07:20:33 PM PDT 24
Peak memory 636316 kb
Host smart-c0a5e57a-5b0d-4a8c-bd9d-6c4a08c118e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=313350748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.313350748
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.687623749
Short name T7
Test name
Test status
Simulation time 21781445643 ps
CPU time 2196.69 seconds
Started Jul 06 07:11:12 PM PDT 24
Finished Jul 06 07:47:51 PM PDT 24
Peak memory 748432 kb
Host smart-36a59bca-1181-4f6c-bdf2-5dc0ff003c0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=687623749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.687623749
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.hmac_long_msg.84730669
Short name T4
Test name
Test status
Simulation time 2977264895 ps
CPU time 169.01 seconds
Started Jul 06 07:12:54 PM PDT 24
Finished Jul 06 07:15:45 PM PDT 24
Peak memory 200436 kb
Host smart-8d8c3328-bdd2-4ec2-9ddf-ea9f68f7886c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84730669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.84730669
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1419748160
Short name T109
Test name
Test status
Simulation time 230704787 ps
CPU time 4.5 seconds
Started Jul 06 07:01:53 PM PDT 24
Finished Jul 06 07:01:58 PM PDT 24
Peak memory 200300 kb
Host smart-10cbf59e-c7e2-4ff6-a069-b4e4a27b0b62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419748160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1419748160
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.1178143260
Short name T36
Test name
Test status
Simulation time 64041534096 ps
CPU time 1885.85 seconds
Started Jul 06 07:11:08 PM PDT 24
Finished Jul 06 07:42:36 PM PDT 24
Peak memory 723368 kb
Host smart-5632ec18-e42d-436a-a249-b7fe5b8b8cbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1178143260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.1178143260
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1687179338
Short name T12
Test name
Test status
Simulation time 22394053934 ps
CPU time 1881.79 seconds
Started Jul 06 07:11:06 PM PDT 24
Finished Jul 06 07:42:29 PM PDT 24
Peak memory 716208 kb
Host smart-e92b89ca-d164-4f5c-9c7c-e890b1e735e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687179338 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1687179338
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_alert_test.3971660837
Short name T73
Test name
Test status
Simulation time 52691821 ps
CPU time 0.61 seconds
Started Jul 06 07:12:12 PM PDT 24
Finished Jul 06 07:12:14 PM PDT 24
Peak memory 196008 kb
Host smart-c2be8218-8b6f-458d-988a-fb5b6c948819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971660837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.3971660837
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2642504402
Short name T78
Test name
Test status
Simulation time 14739060 ps
CPU time 0.8 seconds
Started Jul 06 07:02:17 PM PDT 24
Finished Jul 06 07:02:18 PM PDT 24
Peak memory 200152 kb
Host smart-8456aa04-b82e-46c5-9a72-c1102e7832f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642504402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2642504402
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2231913981
Short name T44
Test name
Test status
Simulation time 272840779 ps
CPU time 0.91 seconds
Started Jul 06 07:10:48 PM PDT 24
Finished Jul 06 07:10:50 PM PDT 24
Peak memory 218312 kb
Host smart-6e63b39a-1fa2-497f-a010-d67e52f3b033
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231913981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2231913981
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/7.hmac_stress_all.398645940
Short name T9
Test name
Test status
Simulation time 71191804204 ps
CPU time 2075.51 seconds
Started Jul 06 07:11:13 PM PDT 24
Finished Jul 06 07:45:50 PM PDT 24
Peak memory 739468 kb
Host smart-bc1dde42-92cf-413e-a47f-4d5c722151a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398645940 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.398645940
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_stress_all.2404114115
Short name T63
Test name
Test status
Simulation time 34124512093 ps
CPU time 1006.04 seconds
Started Jul 06 07:13:47 PM PDT 24
Finished Jul 06 07:31:17 PM PDT 24
Peak memory 497680 kb
Host smart-02643180-516b-44ba-82c5-6bd5520ee704
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404114115 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.2404114115
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3938471853
Short name T107
Test name
Test status
Simulation time 126493261 ps
CPU time 4.04 seconds
Started Jul 06 07:01:52 PM PDT 24
Finished Jul 06 07:01:57 PM PDT 24
Peak memory 200296 kb
Host smart-50025f83-32ff-42e1-8673-aa90e857ced6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938471853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3938471853
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2065569996
Short name T111
Test name
Test status
Simulation time 125249157 ps
CPU time 2.98 seconds
Started Jul 06 07:02:09 PM PDT 24
Finished Jul 06 07:02:13 PM PDT 24
Peak memory 200264 kb
Host smart-1b0f2950-e2ad-4934-90f2-3f01caa58f5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065569996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2065569996
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2110609339
Short name T115
Test name
Test status
Simulation time 1500179362 ps
CPU time 3.17 seconds
Started Jul 06 07:01:38 PM PDT 24
Finished Jul 06 07:01:42 PM PDT 24
Peak memory 200284 kb
Host smart-1366a0f6-8a16-4023-b327-df7d089dee2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110609339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2110609339
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.722917160
Short name T57
Test name
Test status
Simulation time 464938808 ps
CPU time 4.33 seconds
Started Jul 06 07:01:38 PM PDT 24
Finished Jul 06 07:01:43 PM PDT 24
Peak memory 200204 kb
Host smart-eabf1894-4b88-4aab-9512-da88830e3000
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722917160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.722917160
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.786180386
Short name T624
Test name
Test status
Simulation time 1760052922 ps
CPU time 8.9 seconds
Started Jul 06 07:01:33 PM PDT 24
Finished Jul 06 07:01:43 PM PDT 24
Peak memory 199672 kb
Host smart-fa5b93b6-f526-4621-b50e-731bd2896996
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786180386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.786180386
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3163451387
Short name T88
Test name
Test status
Simulation time 355968087 ps
CPU time 5.74 seconds
Started Jul 06 07:01:36 PM PDT 24
Finished Jul 06 07:01:43 PM PDT 24
Peak memory 200360 kb
Host smart-f4fc1af8-0e7e-4afa-a783-383320fe71ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163451387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3163451387
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1812200803
Short name T87
Test name
Test status
Simulation time 52449366 ps
CPU time 0.72 seconds
Started Jul 06 07:01:35 PM PDT 24
Finished Jul 06 07:01:36 PM PDT 24
Peak memory 198300 kb
Host smart-f942de30-7f9f-4c4d-966b-74f885c30e4d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812200803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1812200803
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1088814721
Short name T603
Test name
Test status
Simulation time 177449208 ps
CPU time 2.39 seconds
Started Jul 06 07:01:39 PM PDT 24
Finished Jul 06 07:01:42 PM PDT 24
Peak memory 200616 kb
Host smart-6e637553-baa1-4d36-8c1e-8d22fb486b53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088814721 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1088814721
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3282020442
Short name T625
Test name
Test status
Simulation time 69173007 ps
CPU time 0.72 seconds
Started Jul 06 07:01:37 PM PDT 24
Finished Jul 06 07:01:38 PM PDT 24
Peak memory 198336 kb
Host smart-9de57d0e-7ea9-49bb-8d44-7383819903ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282020442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3282020442
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3562944029
Short name T620
Test name
Test status
Simulation time 15143740 ps
CPU time 0.61 seconds
Started Jul 06 07:01:33 PM PDT 24
Finished Jul 06 07:01:35 PM PDT 24
Peak memory 195240 kb
Host smart-9c838907-d6d0-410f-bff3-a9b3f0e86f57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562944029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3562944029
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2941373303
Short name T659
Test name
Test status
Simulation time 35547617 ps
CPU time 1.63 seconds
Started Jul 06 07:01:36 PM PDT 24
Finished Jul 06 07:01:38 PM PDT 24
Peak memory 200380 kb
Host smart-6cf0fa29-1079-4a68-b155-7e71099baf06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941373303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2941373303
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2847777992
Short name T629
Test name
Test status
Simulation time 122209084 ps
CPU time 2.36 seconds
Started Jul 06 07:01:37 PM PDT 24
Finished Jul 06 07:01:40 PM PDT 24
Peak memory 200276 kb
Host smart-192ee412-5e3f-4dfa-99a1-ae88c51931b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847777992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2847777992
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.772403937
Short name T90
Test name
Test status
Simulation time 2206272563 ps
CPU time 9 seconds
Started Jul 06 07:01:34 PM PDT 24
Finished Jul 06 07:01:44 PM PDT 24
Peak memory 200424 kb
Host smart-e838e1fc-6f03-405d-9330-22264cfdd811
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772403937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.772403937
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2482595948
Short name T576
Test name
Test status
Simulation time 2417690465 ps
CPU time 6.55 seconds
Started Jul 06 07:01:34 PM PDT 24
Finished Jul 06 07:01:41 PM PDT 24
Peak memory 200388 kb
Host smart-4e9b8a2a-b2a0-43a6-9b04-bebf41cde71a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482595948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2482595948
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3629343655
Short name T574
Test name
Test status
Simulation time 44599912 ps
CPU time 0.85 seconds
Started Jul 06 07:01:34 PM PDT 24
Finished Jul 06 07:01:35 PM PDT 24
Peak memory 199740 kb
Host smart-3c223f33-c9b7-4814-9a4a-a63aa24369fb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629343655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3629343655
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3758415908
Short name T566
Test name
Test status
Simulation time 216005391 ps
CPU time 1.41 seconds
Started Jul 06 07:01:35 PM PDT 24
Finished Jul 06 07:01:37 PM PDT 24
Peak memory 200264 kb
Host smart-4ea19be8-100f-4ba3-972b-a2913693c099
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758415908 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.3758415908
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1278059456
Short name T86
Test name
Test status
Simulation time 26751972 ps
CPU time 0.85 seconds
Started Jul 06 07:01:37 PM PDT 24
Finished Jul 06 07:01:39 PM PDT 24
Peak memory 200096 kb
Host smart-6ad489ff-cab6-4857-a6b4-7ecbff5eb6d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278059456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1278059456
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2635325620
Short name T546
Test name
Test status
Simulation time 34682845 ps
CPU time 0.62 seconds
Started Jul 06 07:01:35 PM PDT 24
Finished Jul 06 07:01:36 PM PDT 24
Peak memory 195316 kb
Host smart-ddc0a2ec-c16d-46ae-936d-d550fef9a77a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635325620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2635325620
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.4217798055
Short name T657
Test name
Test status
Simulation time 628968193 ps
CPU time 2.29 seconds
Started Jul 06 07:01:33 PM PDT 24
Finished Jul 06 07:01:36 PM PDT 24
Peak memory 200540 kb
Host smart-6c889f26-2b48-4cff-8f7c-f75af7c3a8f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217798055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.4217798055
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3415105355
Short name T640
Test name
Test status
Simulation time 593753509 ps
CPU time 3.05 seconds
Started Jul 06 07:01:35 PM PDT 24
Finished Jul 06 07:01:39 PM PDT 24
Peak memory 200304 kb
Host smart-efe995a4-11b9-4260-9915-03b77e6a46eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415105355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3415105355
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2397604984
Short name T106
Test name
Test status
Simulation time 96704298 ps
CPU time 1.99 seconds
Started Jul 06 07:01:36 PM PDT 24
Finished Jul 06 07:01:39 PM PDT 24
Peak memory 200372 kb
Host smart-726b879f-febe-4e5b-96b6-666fe098d889
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397604984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2397604984
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3817395222
Short name T621
Test name
Test status
Simulation time 218143307 ps
CPU time 3.29 seconds
Started Jul 06 07:02:01 PM PDT 24
Finished Jul 06 07:02:05 PM PDT 24
Peak memory 208556 kb
Host smart-1554d197-b28e-4f2d-aeaf-d35093cb086e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817395222 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3817395222
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.584672252
Short name T550
Test name
Test status
Simulation time 52957768 ps
CPU time 0.73 seconds
Started Jul 06 07:02:00 PM PDT 24
Finished Jul 06 07:02:02 PM PDT 24
Peak memory 198556 kb
Host smart-ac7ef38e-4912-40aa-85dc-3658c9df9f3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584672252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.584672252
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.2423117150
Short name T641
Test name
Test status
Simulation time 15219444 ps
CPU time 0.67 seconds
Started Jul 06 07:02:00 PM PDT 24
Finished Jul 06 07:02:02 PM PDT 24
Peak memory 195124 kb
Host smart-10fe1f68-f330-47e0-978d-e567288d7445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423117150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.2423117150
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1343534589
Short name T637
Test name
Test status
Simulation time 177463427 ps
CPU time 2.15 seconds
Started Jul 06 07:02:01 PM PDT 24
Finished Jul 06 07:02:03 PM PDT 24
Peak memory 200232 kb
Host smart-4351b6ea-a514-493f-8907-3c88965c9d51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343534589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1343534589
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3774054942
Short name T626
Test name
Test status
Simulation time 75519476 ps
CPU time 3.98 seconds
Started Jul 06 07:02:00 PM PDT 24
Finished Jul 06 07:02:04 PM PDT 24
Peak memory 200380 kb
Host smart-c1ba4781-c991-4113-8bfe-9164f3b0db81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774054942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3774054942
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1765941310
Short name T561
Test name
Test status
Simulation time 308045017 ps
CPU time 1.92 seconds
Started Jul 06 07:01:58 PM PDT 24
Finished Jul 06 07:02:00 PM PDT 24
Peak memory 200376 kb
Host smart-ae8a4143-dc15-427d-a38e-5f3bc374d1b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765941310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1765941310
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.11838501
Short name T575
Test name
Test status
Simulation time 120625051 ps
CPU time 2.15 seconds
Started Jul 06 07:02:01 PM PDT 24
Finished Jul 06 07:02:04 PM PDT 24
Peak memory 200352 kb
Host smart-83179b72-02db-4cfb-aef5-0df7dec8d9c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11838501 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.11838501
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3076993616
Short name T85
Test name
Test status
Simulation time 42616086 ps
CPU time 0.94 seconds
Started Jul 06 07:02:00 PM PDT 24
Finished Jul 06 07:02:01 PM PDT 24
Peak memory 200132 kb
Host smart-0914ef2d-ffae-4cb9-9539-0ff7efb909ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076993616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3076993616
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2053141252
Short name T545
Test name
Test status
Simulation time 18779881 ps
CPU time 0.62 seconds
Started Jul 06 07:02:13 PM PDT 24
Finished Jul 06 07:02:15 PM PDT 24
Peak memory 195364 kb
Host smart-93cbb042-1944-4cf3-88d0-b9953d10b159
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053141252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2053141252
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2382985043
Short name T97
Test name
Test status
Simulation time 100114236 ps
CPU time 1.18 seconds
Started Jul 06 07:01:59 PM PDT 24
Finished Jul 06 07:02:01 PM PDT 24
Peak memory 200396 kb
Host smart-7c271b38-3a0b-480c-b99b-9cf448e09347
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382985043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2382985043
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2117582404
Short name T536
Test name
Test status
Simulation time 29307832 ps
CPU time 1.39 seconds
Started Jul 06 07:01:59 PM PDT 24
Finished Jul 06 07:02:01 PM PDT 24
Peak memory 200400 kb
Host smart-b08ab843-47bd-4d78-bff8-20cd280d9d93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117582404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2117582404
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.538097610
Short name T116
Test name
Test status
Simulation time 328009603 ps
CPU time 1.84 seconds
Started Jul 06 07:02:00 PM PDT 24
Finished Jul 06 07:02:02 PM PDT 24
Peak memory 200368 kb
Host smart-c82e4e99-948f-446d-8b4d-80f0f30de6d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538097610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.538097610
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3382005565
Short name T557
Test name
Test status
Simulation time 71844320 ps
CPU time 1.16 seconds
Started Jul 06 07:01:59 PM PDT 24
Finished Jul 06 07:02:00 PM PDT 24
Peak memory 200220 kb
Host smart-2045ca9f-be99-4ca0-9aac-b051d31fd376
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382005565 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3382005565
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1388769971
Short name T89
Test name
Test status
Simulation time 39547127 ps
CPU time 0.81 seconds
Started Jul 06 07:02:00 PM PDT 24
Finished Jul 06 07:02:01 PM PDT 24
Peak memory 199344 kb
Host smart-00f41e08-08de-4fb5-b165-6a96048182cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388769971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1388769971
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1439949155
Short name T594
Test name
Test status
Simulation time 43324367 ps
CPU time 0.59 seconds
Started Jul 06 07:02:00 PM PDT 24
Finished Jul 06 07:02:01 PM PDT 24
Peak memory 195172 kb
Host smart-9a758e33-a377-4f83-b93f-c75acca715f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439949155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1439949155
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1751804410
Short name T649
Test name
Test status
Simulation time 160682053 ps
CPU time 2.66 seconds
Started Jul 06 07:01:59 PM PDT 24
Finished Jul 06 07:02:02 PM PDT 24
Peak memory 200232 kb
Host smart-9bc86abb-d727-45fa-a8fc-b75452a646c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751804410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1751804410
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.967946290
Short name T592
Test name
Test status
Simulation time 708491762 ps
CPU time 4.4 seconds
Started Jul 06 07:02:02 PM PDT 24
Finished Jul 06 07:02:07 PM PDT 24
Peak memory 200272 kb
Host smart-49032335-2954-4702-aa19-7a06d0961fc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967946290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.967946290
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.98966720
Short name T108
Test name
Test status
Simulation time 809246888 ps
CPU time 3.2 seconds
Started Jul 06 07:02:03 PM PDT 24
Finished Jul 06 07:02:06 PM PDT 24
Peak memory 200304 kb
Host smart-a9f3fcdb-b163-4ce8-98c5-37ad32098645
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98966720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.98966720
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3990442181
Short name T540
Test name
Test status
Simulation time 210255740 ps
CPU time 1.19 seconds
Started Jul 06 07:02:10 PM PDT 24
Finished Jul 06 07:02:12 PM PDT 24
Peak memory 200120 kb
Host smart-c47c63bf-60d2-4e19-aa25-a83e277625c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990442181 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3990442181
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3171786719
Short name T650
Test name
Test status
Simulation time 40487137 ps
CPU time 0.98 seconds
Started Jul 06 07:02:11 PM PDT 24
Finished Jul 06 07:02:13 PM PDT 24
Peak memory 200084 kb
Host smart-4577a2df-e611-4c64-8803-306be9afcc75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171786719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3171786719
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2909385198
Short name T588
Test name
Test status
Simulation time 46459896 ps
CPU time 0.62 seconds
Started Jul 06 07:02:08 PM PDT 24
Finished Jul 06 07:02:10 PM PDT 24
Peak memory 195220 kb
Host smart-51ab03e7-1cb9-4cef-ba44-065caeda9f76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909385198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2909385198
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.296770362
Short name T99
Test name
Test status
Simulation time 35918450 ps
CPU time 1.65 seconds
Started Jul 06 07:02:06 PM PDT 24
Finished Jul 06 07:02:08 PM PDT 24
Peak memory 200304 kb
Host smart-18891aab-a7a3-42b1-a78f-5a9315158f47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296770362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr
_outstanding.296770362
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.99050192
Short name T604
Test name
Test status
Simulation time 51581144 ps
CPU time 2.78 seconds
Started Jul 06 07:02:03 PM PDT 24
Finished Jul 06 07:02:07 PM PDT 24
Peak memory 200396 kb
Host smart-851346ad-9116-4189-9b79-1595fd9f43e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99050192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.99050192
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2570026970
Short name T54
Test name
Test status
Simulation time 647415722 ps
CPU time 1.9 seconds
Started Jul 06 07:01:59 PM PDT 24
Finished Jul 06 07:02:01 PM PDT 24
Peak memory 200348 kb
Host smart-99c77137-868f-4b5c-ac4c-3884050c9686
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570026970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2570026970
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2992137711
Short name T616
Test name
Test status
Simulation time 37669148 ps
CPU time 2.2 seconds
Started Jul 06 07:02:06 PM PDT 24
Finished Jul 06 07:02:09 PM PDT 24
Peak memory 200532 kb
Host smart-5835b7ac-32e9-47ab-a383-fde8c6e45746
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992137711 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2992137711
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.321533933
Short name T631
Test name
Test status
Simulation time 17865615 ps
CPU time 0.91 seconds
Started Jul 06 07:02:06 PM PDT 24
Finished Jul 06 07:02:08 PM PDT 24
Peak memory 199768 kb
Host smart-08f5b087-d95c-4e5e-9459-2ddee01a24c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321533933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.321533933
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.4262939815
Short name T632
Test name
Test status
Simulation time 58486757 ps
CPU time 0.58 seconds
Started Jul 06 07:02:10 PM PDT 24
Finished Jul 06 07:02:11 PM PDT 24
Peak memory 195192 kb
Host smart-d422c6b0-c805-46da-8fdb-e23fc1aeb4c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262939815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.4262939815
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1349520617
Short name T94
Test name
Test status
Simulation time 36772531 ps
CPU time 1.7 seconds
Started Jul 06 07:02:07 PM PDT 24
Finished Jul 06 07:02:09 PM PDT 24
Peak memory 200328 kb
Host smart-1444b8e9-e1cb-4247-9503-1eec380b515c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349520617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1349520617
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3575484782
Short name T651
Test name
Test status
Simulation time 52770231 ps
CPU time 1.61 seconds
Started Jul 06 07:02:06 PM PDT 24
Finished Jul 06 07:02:08 PM PDT 24
Peak memory 200376 kb
Host smart-11ab08b1-f519-442f-bd0e-d1bf910368ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575484782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3575484782
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3410041978
Short name T589
Test name
Test status
Simulation time 195669283 ps
CPU time 1.91 seconds
Started Jul 06 07:02:07 PM PDT 24
Finished Jul 06 07:02:10 PM PDT 24
Peak memory 200324 kb
Host smart-9d421386-141a-496c-a1d7-2cd23c532c07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410041978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3410041978
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3304465313
Short name T580
Test name
Test status
Simulation time 417556312 ps
CPU time 2.27 seconds
Started Jul 06 07:02:06 PM PDT 24
Finished Jul 06 07:02:09 PM PDT 24
Peak memory 200368 kb
Host smart-2c935fe7-3b7e-4204-a2c3-58d1d8f2079d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304465313 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3304465313
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1231153188
Short name T80
Test name
Test status
Simulation time 28942970 ps
CPU time 0.82 seconds
Started Jul 06 07:02:10 PM PDT 24
Finished Jul 06 07:02:12 PM PDT 24
Peak memory 199760 kb
Host smart-6df742dd-265a-4ad8-ba62-6a78eaf911cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231153188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1231153188
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.21642419
Short name T611
Test name
Test status
Simulation time 19982548 ps
CPU time 0.65 seconds
Started Jul 06 07:02:10 PM PDT 24
Finished Jul 06 07:02:12 PM PDT 24
Peak memory 195268 kb
Host smart-b82064b0-9617-4b45-a1c1-157a6afe2abb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21642419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.21642419
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2358858357
Short name T101
Test name
Test status
Simulation time 52689196 ps
CPU time 1.17 seconds
Started Jul 06 07:02:11 PM PDT 24
Finished Jul 06 07:02:13 PM PDT 24
Peak memory 198876 kb
Host smart-6d91019e-6454-4a8b-8c65-9ac9a646a6b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358858357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2358858357
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.4164096568
Short name T591
Test name
Test status
Simulation time 62061761 ps
CPU time 1.61 seconds
Started Jul 06 07:02:08 PM PDT 24
Finished Jul 06 07:02:11 PM PDT 24
Peak memory 200296 kb
Host smart-4ce3edd5-edbd-4a92-bce5-b22d911b4956
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164096568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.4164096568
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3113868541
Short name T573
Test name
Test status
Simulation time 786655318 ps
CPU time 3.05 seconds
Started Jul 06 07:02:10 PM PDT 24
Finished Jul 06 07:02:14 PM PDT 24
Peak memory 200300 kb
Host smart-2066ceb3-45d8-46a7-b694-9eb1493d407c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113868541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3113868541
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1637239506
Short name T572
Test name
Test status
Simulation time 146056378 ps
CPU time 1.19 seconds
Started Jul 06 07:02:07 PM PDT 24
Finished Jul 06 07:02:09 PM PDT 24
Peak memory 200156 kb
Host smart-cd6c190f-31a8-4686-9079-24265e38321b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637239506 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1637239506
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3546679630
Short name T610
Test name
Test status
Simulation time 181407585 ps
CPU time 0.8 seconds
Started Jul 06 07:02:10 PM PDT 24
Finished Jul 06 07:02:12 PM PDT 24
Peak memory 199544 kb
Host smart-3b4e437c-78ca-4b35-8758-45c46f700fa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546679630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3546679630
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2810860626
Short name T635
Test name
Test status
Simulation time 39849524 ps
CPU time 0.6 seconds
Started Jul 06 07:02:07 PM PDT 24
Finished Jul 06 07:02:09 PM PDT 24
Peak memory 195228 kb
Host smart-7bab21fa-5de0-4819-b608-83a9d2a6f459
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810860626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2810860626
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2672377128
Short name T562
Test name
Test status
Simulation time 76084068 ps
CPU time 1.79 seconds
Started Jul 06 07:02:08 PM PDT 24
Finished Jul 06 07:02:11 PM PDT 24
Peak memory 200384 kb
Host smart-7817b4b1-a7c2-4783-903a-c4736145287e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672377128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.2672377128
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.2172982430
Short name T653
Test name
Test status
Simulation time 278899308 ps
CPU time 2.16 seconds
Started Jul 06 07:02:10 PM PDT 24
Finished Jul 06 07:02:13 PM PDT 24
Peak memory 200284 kb
Host smart-1311fbaa-b072-4591-b276-454a703a6c68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172982430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.2172982430
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.920560936
Short name T565
Test name
Test status
Simulation time 101712785 ps
CPU time 2.02 seconds
Started Jul 06 07:02:06 PM PDT 24
Finished Jul 06 07:02:09 PM PDT 24
Peak memory 200356 kb
Host smart-0a56ba0e-a776-4122-bc69-a242de9d4461
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920560936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.920560936
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3015010521
Short name T590
Test name
Test status
Simulation time 25724000 ps
CPU time 1.43 seconds
Started Jul 06 07:02:23 PM PDT 24
Finished Jul 06 07:02:25 PM PDT 24
Peak memory 200304 kb
Host smart-8ed6d793-d960-4f5e-9149-c354d1af355b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015010521 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3015010521
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.4131684844
Short name T84
Test name
Test status
Simulation time 31345978 ps
CPU time 0.93 seconds
Started Jul 06 07:02:18 PM PDT 24
Finished Jul 06 07:02:19 PM PDT 24
Peak memory 199916 kb
Host smart-d1990338-0fa3-4a9f-8ab4-6e4b0a97b522
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131684844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.4131684844
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1267842801
Short name T555
Test name
Test status
Simulation time 61987627 ps
CPU time 0.61 seconds
Started Jul 06 07:02:12 PM PDT 24
Finished Jul 06 07:02:14 PM PDT 24
Peak memory 195308 kb
Host smart-a5366c8f-a95d-49bb-9f12-6b7a2dc8d930
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267842801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1267842801
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3861451738
Short name T95
Test name
Test status
Simulation time 47474538 ps
CPU time 1.12 seconds
Started Jul 06 07:02:12 PM PDT 24
Finished Jul 06 07:02:15 PM PDT 24
Peak memory 200300 kb
Host smart-906680a9-6c1e-4d6d-a7b6-e0ff8e6424a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861451738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3861451738
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3237443702
Short name T645
Test name
Test status
Simulation time 88792414 ps
CPU time 1.58 seconds
Started Jul 06 07:02:10 PM PDT 24
Finished Jul 06 07:02:13 PM PDT 24
Peak memory 200304 kb
Host smart-38d9278c-9240-49ac-a4d2-c51dccc197d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237443702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3237443702
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3735428104
Short name T544
Test name
Test status
Simulation time 142090079 ps
CPU time 1.71 seconds
Started Jul 06 07:02:16 PM PDT 24
Finished Jul 06 07:02:19 PM PDT 24
Peak memory 200052 kb
Host smart-c6cd4995-4643-4b78-8dd5-d0e56f71822c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735428104 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3735428104
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.586213721
Short name T584
Test name
Test status
Simulation time 11940319 ps
CPU time 0.66 seconds
Started Jul 06 07:02:14 PM PDT 24
Finished Jul 06 07:02:15 PM PDT 24
Peak memory 195216 kb
Host smart-e8dcec92-6922-4698-b85c-6f3bade9612b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586213721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.586213721
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3162473387
Short name T98
Test name
Test status
Simulation time 579782169 ps
CPU time 2.4 seconds
Started Jul 06 07:02:13 PM PDT 24
Finished Jul 06 07:02:16 PM PDT 24
Peak memory 200292 kb
Host smart-720f4213-1f25-4a0f-92c0-df7cf9a8e026
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162473387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3162473387
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.3597420762
Short name T556
Test name
Test status
Simulation time 223665164 ps
CPU time 3.03 seconds
Started Jul 06 07:02:17 PM PDT 24
Finished Jul 06 07:02:20 PM PDT 24
Peak memory 200364 kb
Host smart-d10ee1a8-61c7-4692-aee5-d74c321eb70f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597420762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.3597420762
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2293980593
Short name T114
Test name
Test status
Simulation time 161427946 ps
CPU time 3.23 seconds
Started Jul 06 07:02:12 PM PDT 24
Finished Jul 06 07:02:17 PM PDT 24
Peak memory 200284 kb
Host smart-b0ec8d48-74bb-40eb-9ba5-a194b07b4ca9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293980593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2293980593
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3161680465
Short name T654
Test name
Test status
Simulation time 94914525 ps
CPU time 2.44 seconds
Started Jul 06 07:02:12 PM PDT 24
Finished Jul 06 07:02:15 PM PDT 24
Peak memory 200372 kb
Host smart-4e4432cb-a53d-49af-ab70-74352455d919
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161680465 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3161680465
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3438957654
Short name T551
Test name
Test status
Simulation time 38850905 ps
CPU time 0.7 seconds
Started Jul 06 07:02:14 PM PDT 24
Finished Jul 06 07:02:15 PM PDT 24
Peak memory 198100 kb
Host smart-b82838b0-8167-41f2-ac67-d66baf6a8ec2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438957654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3438957654
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1853993701
Short name T598
Test name
Test status
Simulation time 12282730 ps
CPU time 0.59 seconds
Started Jul 06 07:02:14 PM PDT 24
Finished Jul 06 07:02:16 PM PDT 24
Peak memory 195120 kb
Host smart-002dadb2-ccef-4278-8bc4-bbfb9c2ce2db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853993701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1853993701
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1330962167
Short name T100
Test name
Test status
Simulation time 139770663 ps
CPU time 2.46 seconds
Started Jul 06 07:02:13 PM PDT 24
Finished Jul 06 07:02:16 PM PDT 24
Peak memory 200376 kb
Host smart-61c15058-bf6d-486d-bdc3-362fa0acf8d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330962167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1330962167
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1132420905
Short name T643
Test name
Test status
Simulation time 370276176 ps
CPU time 3.25 seconds
Started Jul 06 07:02:11 PM PDT 24
Finished Jul 06 07:02:16 PM PDT 24
Peak memory 200328 kb
Host smart-66c4c409-61eb-4856-a43c-80bf372da973
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132420905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1132420905
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2192509771
Short name T56
Test name
Test status
Simulation time 1046980966 ps
CPU time 4.76 seconds
Started Jul 06 07:02:13 PM PDT 24
Finished Jul 06 07:02:19 PM PDT 24
Peak memory 200316 kb
Host smart-1de03b06-2e2e-45ce-a2e5-8e4e47f538ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192509771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2192509771
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1214644566
Short name T82
Test name
Test status
Simulation time 72974502 ps
CPU time 3.16 seconds
Started Jul 06 07:01:36 PM PDT 24
Finished Jul 06 07:01:40 PM PDT 24
Peak memory 200340 kb
Host smart-3f03e416-22fe-46ad-87bd-808c3a549c3d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214644566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1214644566
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3458406109
Short name T608
Test name
Test status
Simulation time 740880449 ps
CPU time 10.65 seconds
Started Jul 06 07:01:33 PM PDT 24
Finished Jul 06 07:01:45 PM PDT 24
Peak memory 200380 kb
Host smart-f1f6b509-107c-40bf-ab52-d5be6cc783a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458406109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3458406109
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1246285945
Short name T615
Test name
Test status
Simulation time 57951462 ps
CPU time 0.86 seconds
Started Jul 06 07:01:36 PM PDT 24
Finished Jul 06 07:01:37 PM PDT 24
Peak memory 200128 kb
Host smart-7d3143e3-f87c-4130-a492-3796cb9dcf72
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246285945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1246285945
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.1294839193
Short name T600
Test name
Test status
Simulation time 44549123 ps
CPU time 1.49 seconds
Started Jul 06 07:01:40 PM PDT 24
Finished Jul 06 07:01:42 PM PDT 24
Peak memory 200388 kb
Host smart-7628078b-19c0-494e-9f3d-4daad527092f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294839193 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.1294839193
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1189973627
Short name T658
Test name
Test status
Simulation time 27411812 ps
CPU time 0.84 seconds
Started Jul 06 07:01:35 PM PDT 24
Finished Jul 06 07:01:37 PM PDT 24
Peak memory 199860 kb
Host smart-004cfd12-2954-4dab-83d7-09ffbd9c1467
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189973627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1189973627
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3745380728
Short name T538
Test name
Test status
Simulation time 102787294 ps
CPU time 0.6 seconds
Started Jul 06 07:01:37 PM PDT 24
Finished Jul 06 07:01:39 PM PDT 24
Peak memory 195220 kb
Host smart-c4f317b6-4879-489d-8f6d-52a18abff918
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745380728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3745380728
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.446310192
Short name T96
Test name
Test status
Simulation time 257607490 ps
CPU time 1.91 seconds
Started Jul 06 07:01:38 PM PDT 24
Finished Jul 06 07:01:40 PM PDT 24
Peak memory 200224 kb
Host smart-f52f69c5-a4a1-4f07-9ed9-ac51d9e42304
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446310192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.446310192
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1547239013
Short name T652
Test name
Test status
Simulation time 95979985 ps
CPU time 3.78 seconds
Started Jul 06 07:01:36 PM PDT 24
Finished Jul 06 07:01:40 PM PDT 24
Peak memory 200328 kb
Host smart-e0a9fe8c-5a92-41f4-baa9-b025ad2238a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547239013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1547239013
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.815076585
Short name T613
Test name
Test status
Simulation time 43008086 ps
CPU time 0.58 seconds
Started Jul 06 07:02:15 PM PDT 24
Finished Jul 06 07:02:16 PM PDT 24
Peak memory 195200 kb
Host smart-f33defea-6f6b-44cf-a0c9-123894dd048c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815076585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.815076585
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3556446166
Short name T648
Test name
Test status
Simulation time 13402482 ps
CPU time 0.62 seconds
Started Jul 06 07:02:13 PM PDT 24
Finished Jul 06 07:02:14 PM PDT 24
Peak memory 195256 kb
Host smart-3e21b4fc-22ae-42d4-91c5-c1b5f5eb72ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556446166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3556446166
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3616765202
Short name T554
Test name
Test status
Simulation time 40543397 ps
CPU time 0.58 seconds
Started Jul 06 07:02:14 PM PDT 24
Finished Jul 06 07:02:15 PM PDT 24
Peak memory 195140 kb
Host smart-bc00d795-a8cc-4936-baa3-c0fe336a2595
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616765202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3616765202
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2107066502
Short name T570
Test name
Test status
Simulation time 40173176 ps
CPU time 0.57 seconds
Started Jul 06 07:02:16 PM PDT 24
Finished Jul 06 07:02:18 PM PDT 24
Peak memory 194956 kb
Host smart-76e145c0-a91e-438a-a83f-39a16236db37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107066502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2107066502
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1766027650
Short name T539
Test name
Test status
Simulation time 51965408 ps
CPU time 0.61 seconds
Started Jul 06 07:02:15 PM PDT 24
Finished Jul 06 07:02:16 PM PDT 24
Peak memory 195216 kb
Host smart-c028bf3b-dbbd-4741-b4d2-292285a5c021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766027650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1766027650
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2307317956
Short name T585
Test name
Test status
Simulation time 42799668 ps
CPU time 0.59 seconds
Started Jul 06 07:02:12 PM PDT 24
Finished Jul 06 07:02:14 PM PDT 24
Peak memory 195336 kb
Host smart-30ba441d-0bfc-44ec-b049-7531985a1de5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307317956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2307317956
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3545144758
Short name T567
Test name
Test status
Simulation time 27396200 ps
CPU time 0.59 seconds
Started Jul 06 07:02:16 PM PDT 24
Finished Jul 06 07:02:18 PM PDT 24
Peak memory 195172 kb
Host smart-a4a37883-4635-4777-958b-f03674964d12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545144758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3545144758
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.936258507
Short name T582
Test name
Test status
Simulation time 49636927 ps
CPU time 0.61 seconds
Started Jul 06 07:02:12 PM PDT 24
Finished Jul 06 07:02:13 PM PDT 24
Peak memory 195280 kb
Host smart-81ed2aff-c852-4bde-bba6-ee792bf0ba6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936258507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.936258507
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2770748009
Short name T568
Test name
Test status
Simulation time 51646346 ps
CPU time 0.6 seconds
Started Jul 06 07:02:45 PM PDT 24
Finished Jul 06 07:02:47 PM PDT 24
Peak memory 195356 kb
Host smart-5597e47b-187a-4907-a0aa-4d52945d5acb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770748009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2770748009
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.228383846
Short name T535
Test name
Test status
Simulation time 43837403 ps
CPU time 0.61 seconds
Started Jul 06 07:02:22 PM PDT 24
Finished Jul 06 07:02:23 PM PDT 24
Peak memory 195384 kb
Host smart-d8667541-4ef8-4da4-9be3-81d8c1e5b4ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228383846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.228383846
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1066185811
Short name T91
Test name
Test status
Simulation time 1668027077 ps
CPU time 6.38 seconds
Started Jul 06 07:01:42 PM PDT 24
Finished Jul 06 07:01:49 PM PDT 24
Peak memory 200320 kb
Host smart-3039d17e-beba-41b2-9726-59d79c987f5c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066185811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1066185811
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.65883434
Short name T617
Test name
Test status
Simulation time 733091203 ps
CPU time 10.71 seconds
Started Jul 06 07:01:41 PM PDT 24
Finished Jul 06 07:01:53 PM PDT 24
Peak memory 200328 kb
Host smart-df270805-cb4d-4864-b34c-2359141d11ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65883434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.65883434
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3039158347
Short name T622
Test name
Test status
Simulation time 164844072 ps
CPU time 0.89 seconds
Started Jul 06 07:01:40 PM PDT 24
Finished Jul 06 07:01:41 PM PDT 24
Peak memory 200044 kb
Host smart-e6651dd4-327d-40c3-81af-36bc301d9a15
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039158347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3039158347
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.1932822567
Short name T548
Test name
Test status
Simulation time 90376048 ps
CPU time 2.43 seconds
Started Jul 06 07:01:42 PM PDT 24
Finished Jul 06 07:01:46 PM PDT 24
Peak memory 200372 kb
Host smart-92a61100-c9c6-49c4-a815-8b0ff7134d27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932822567 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.1932822567
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.582933660
Short name T595
Test name
Test status
Simulation time 22499291 ps
CPU time 0.81 seconds
Started Jul 06 07:01:40 PM PDT 24
Finished Jul 06 07:01:41 PM PDT 24
Peak memory 199976 kb
Host smart-a1c83f0e-1ad4-4cba-afb4-f26a988766d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582933660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.582933660
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.760265491
Short name T638
Test name
Test status
Simulation time 21035648 ps
CPU time 0.61 seconds
Started Jul 06 07:01:41 PM PDT 24
Finished Jul 06 07:01:42 PM PDT 24
Peak memory 195192 kb
Host smart-1ec5c920-761a-4e75-b0a3-387797a0098f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760265491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.760265491
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.44772239
Short name T597
Test name
Test status
Simulation time 412922156 ps
CPU time 2.33 seconds
Started Jul 06 07:01:40 PM PDT 24
Finished Jul 06 07:01:43 PM PDT 24
Peak memory 200140 kb
Host smart-210825a8-1c0b-41f8-974f-b2f35d6fe12d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44772239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_o
utstanding.44772239
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.312980333
Short name T630
Test name
Test status
Simulation time 58043212 ps
CPU time 1.4 seconds
Started Jul 06 07:01:39 PM PDT 24
Finished Jul 06 07:01:41 PM PDT 24
Peak memory 200332 kb
Host smart-1db0fb32-c5cd-4d88-88dc-ba036c42d809
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312980333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.312980333
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.213455041
Short name T55
Test name
Test status
Simulation time 395790778 ps
CPU time 3.04 seconds
Started Jul 06 07:01:41 PM PDT 24
Finished Jul 06 07:01:45 PM PDT 24
Peak memory 200376 kb
Host smart-c3304520-50b1-421e-9670-7632fd6df002
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213455041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.213455041
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1602345799
Short name T628
Test name
Test status
Simulation time 40592021 ps
CPU time 0.6 seconds
Started Jul 06 07:02:25 PM PDT 24
Finished Jul 06 07:02:26 PM PDT 24
Peak memory 195292 kb
Host smart-3f2eef2c-a5b8-4546-a9bf-dfa483aa021c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602345799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1602345799
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1086335387
Short name T541
Test name
Test status
Simulation time 12396616 ps
CPU time 0.56 seconds
Started Jul 06 07:02:19 PM PDT 24
Finished Jul 06 07:02:20 PM PDT 24
Peak memory 195208 kb
Host smart-88960111-2562-4b78-bcdf-bb56ff53ad9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086335387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1086335387
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1745820523
Short name T647
Test name
Test status
Simulation time 91691252 ps
CPU time 0.59 seconds
Started Jul 06 07:02:20 PM PDT 24
Finished Jul 06 07:02:22 PM PDT 24
Peak memory 195240 kb
Host smart-5bad989d-4bba-4b03-987a-f8baf5278fc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745820523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1745820523
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2616387632
Short name T537
Test name
Test status
Simulation time 19863019 ps
CPU time 0.6 seconds
Started Jul 06 07:02:26 PM PDT 24
Finished Jul 06 07:02:28 PM PDT 24
Peak memory 195344 kb
Host smart-793d976b-b11e-4601-8019-fe8ec6933056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616387632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2616387632
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.487601212
Short name T569
Test name
Test status
Simulation time 100804107 ps
CPU time 0.62 seconds
Started Jul 06 07:02:22 PM PDT 24
Finished Jul 06 07:02:24 PM PDT 24
Peak memory 195184 kb
Host smart-e0fe8bc0-7d1c-402d-ac47-5a40ce1168a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487601212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.487601212
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1436272756
Short name T586
Test name
Test status
Simulation time 36584730 ps
CPU time 0.64 seconds
Started Jul 06 07:02:19 PM PDT 24
Finished Jul 06 07:02:20 PM PDT 24
Peak memory 195136 kb
Host smart-62d16cd6-457d-4fe9-9e43-757bf83b15e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436272756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1436272756
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1309787875
Short name T634
Test name
Test status
Simulation time 11890192 ps
CPU time 0.61 seconds
Started Jul 06 07:02:26 PM PDT 24
Finished Jul 06 07:02:28 PM PDT 24
Peak memory 195240 kb
Host smart-99fd5f56-50e1-4a43-b00c-d4cad884d5ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309787875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1309787875
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2056623575
Short name T596
Test name
Test status
Simulation time 46323154 ps
CPU time 0.59 seconds
Started Jul 06 07:02:25 PM PDT 24
Finished Jul 06 07:02:27 PM PDT 24
Peak memory 195328 kb
Host smart-c92ba21f-b1ae-46ca-81d3-f09d7313a13c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056623575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2056623575
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3895530059
Short name T547
Test name
Test status
Simulation time 159723605 ps
CPU time 0.58 seconds
Started Jul 06 07:02:21 PM PDT 24
Finished Jul 06 07:02:23 PM PDT 24
Peak memory 195176 kb
Host smart-e871edd4-fed8-40c4-a13f-a485b5b5e8ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895530059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3895530059
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1458771627
Short name T614
Test name
Test status
Simulation time 19205176 ps
CPU time 0.63 seconds
Started Jul 06 07:02:20 PM PDT 24
Finished Jul 06 07:02:22 PM PDT 24
Peak memory 195260 kb
Host smart-4ac306b4-0898-407d-9bea-8a3f318f1fda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458771627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1458771627
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2943971206
Short name T79
Test name
Test status
Simulation time 463847544 ps
CPU time 9.02 seconds
Started Jul 06 07:01:45 PM PDT 24
Finished Jul 06 07:01:55 PM PDT 24
Peak memory 200236 kb
Host smart-4414d491-dc30-4f20-baea-2bb698cae987
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943971206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2943971206
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.163066398
Short name T581
Test name
Test status
Simulation time 1653944441 ps
CPU time 6.27 seconds
Started Jul 06 07:01:45 PM PDT 24
Finished Jul 06 07:01:51 PM PDT 24
Peak memory 200372 kb
Host smart-4ea26255-5572-4e24-8bb8-9c7a071623e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163066398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.163066398
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.3598739101
Short name T83
Test name
Test status
Simulation time 35974435 ps
CPU time 1 seconds
Started Jul 06 07:01:40 PM PDT 24
Finished Jul 06 07:01:41 PM PDT 24
Peak memory 200168 kb
Host smart-d6aa07d5-8dac-4388-a070-448fb2a81ea3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598739101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.3598739101
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1336669576
Short name T534
Test name
Test status
Simulation time 191060259 ps
CPU time 1.78 seconds
Started Jul 06 07:01:46 PM PDT 24
Finished Jul 06 07:01:49 PM PDT 24
Peak memory 200388 kb
Host smart-cc22345f-2ac7-443e-8d31-8ff70020a374
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336669576 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1336669576
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2219152275
Short name T627
Test name
Test status
Simulation time 15434630 ps
CPU time 0.83 seconds
Started Jul 06 07:01:41 PM PDT 24
Finished Jul 06 07:01:42 PM PDT 24
Peak memory 199652 kb
Host smart-12938d83-3382-48ae-8375-a59b56acdea8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219152275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2219152275
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2129319590
Short name T656
Test name
Test status
Simulation time 12543314 ps
CPU time 0.6 seconds
Started Jul 06 07:01:41 PM PDT 24
Finished Jul 06 07:01:42 PM PDT 24
Peak memory 195240 kb
Host smart-25421288-320b-4d3d-8859-bffee9f9663d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129319590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2129319590
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2603406439
Short name T593
Test name
Test status
Simulation time 43725803 ps
CPU time 1.2 seconds
Started Jul 06 07:01:45 PM PDT 24
Finished Jul 06 07:01:47 PM PDT 24
Peak memory 198928 kb
Host smart-96d92961-9d4e-4cb5-87e5-243f8ff0dedc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603406439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2603406439
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3088813676
Short name T655
Test name
Test status
Simulation time 1384260392 ps
CPU time 2.95 seconds
Started Jul 06 07:01:40 PM PDT 24
Finished Jul 06 07:01:44 PM PDT 24
Peak memory 200316 kb
Host smart-d1cdd321-b904-4069-876a-3298f18f9ca8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088813676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3088813676
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1132987487
Short name T113
Test name
Test status
Simulation time 183528101 ps
CPU time 3.06 seconds
Started Jul 06 07:01:43 PM PDT 24
Finished Jul 06 07:01:47 PM PDT 24
Peak memory 200292 kb
Host smart-611ee53e-9f73-4467-830c-71cdc7b890e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132987487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1132987487
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.4002561919
Short name T543
Test name
Test status
Simulation time 41372300 ps
CPU time 0.62 seconds
Started Jul 06 07:02:24 PM PDT 24
Finished Jul 06 07:02:25 PM PDT 24
Peak memory 195212 kb
Host smart-66d6cfdf-f4e1-48f8-a7f5-ed594641b726
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002561919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.4002561919
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.786700978
Short name T618
Test name
Test status
Simulation time 30513734 ps
CPU time 0.61 seconds
Started Jul 06 07:02:22 PM PDT 24
Finished Jul 06 07:02:23 PM PDT 24
Peak memory 195320 kb
Host smart-28b641f3-d970-4cab-9702-135fd95dcc2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786700978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.786700978
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.4132279533
Short name T552
Test name
Test status
Simulation time 47632100 ps
CPU time 0.56 seconds
Started Jul 06 07:02:19 PM PDT 24
Finished Jul 06 07:02:20 PM PDT 24
Peak memory 195220 kb
Host smart-ce7d08d5-4240-480e-9d39-5226bf92d18f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132279533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.4132279533
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1087667636
Short name T646
Test name
Test status
Simulation time 12384679 ps
CPU time 0.56 seconds
Started Jul 06 07:02:20 PM PDT 24
Finished Jul 06 07:02:21 PM PDT 24
Peak memory 195192 kb
Host smart-9b1180f8-a88c-4a48-a8ba-b4b6bb2b0a94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087667636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1087667636
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2610214697
Short name T563
Test name
Test status
Simulation time 13298664 ps
CPU time 0.6 seconds
Started Jul 06 07:02:20 PM PDT 24
Finished Jul 06 07:02:21 PM PDT 24
Peak memory 195248 kb
Host smart-b98e641d-6607-441c-98ee-963b48de16a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610214697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2610214697
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3627970830
Short name T542
Test name
Test status
Simulation time 110049767 ps
CPU time 0.58 seconds
Started Jul 06 07:02:21 PM PDT 24
Finished Jul 06 07:02:22 PM PDT 24
Peak memory 195280 kb
Host smart-680d0282-bff1-4411-84a6-133179a7aad1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627970830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3627970830
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3534594363
Short name T601
Test name
Test status
Simulation time 10809004 ps
CPU time 0.6 seconds
Started Jul 06 07:02:26 PM PDT 24
Finished Jul 06 07:02:27 PM PDT 24
Peak memory 195212 kb
Host smart-7b5dc225-aa7b-483a-b960-b08485fcaad0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534594363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3534594363
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1454991742
Short name T609
Test name
Test status
Simulation time 45925556 ps
CPU time 0.6 seconds
Started Jul 06 07:02:21 PM PDT 24
Finished Jul 06 07:02:22 PM PDT 24
Peak memory 195308 kb
Host smart-2a85934f-7903-4c27-900b-7e95372abe36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454991742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1454991742
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.754176802
Short name T633
Test name
Test status
Simulation time 34362221 ps
CPU time 0.61 seconds
Started Jul 06 07:02:21 PM PDT 24
Finished Jul 06 07:02:22 PM PDT 24
Peak memory 195256 kb
Host smart-e826156e-fd0e-4da8-94ba-2f166cbf3178
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754176802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.754176802
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.14098926
Short name T607
Test name
Test status
Simulation time 37599833 ps
CPU time 0.58 seconds
Started Jul 06 07:02:21 PM PDT 24
Finished Jul 06 07:02:22 PM PDT 24
Peak memory 195300 kb
Host smart-fe52f1ad-d056-4121-b67f-e465482092f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14098926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.14098926
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4067953875
Short name T606
Test name
Test status
Simulation time 48519614119 ps
CPU time 495.66 seconds
Started Jul 06 07:01:45 PM PDT 24
Finished Jul 06 07:10:01 PM PDT 24
Peak memory 215888 kb
Host smart-47f6f993-0146-4606-b056-731b409b4044
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067953875 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.4067953875
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1993204103
Short name T636
Test name
Test status
Simulation time 14561189 ps
CPU time 0.79 seconds
Started Jul 06 07:01:46 PM PDT 24
Finished Jul 06 07:01:48 PM PDT 24
Peak memory 199728 kb
Host smart-dba1178d-febe-4d92-a629-49f21be3df4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993204103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1993204103
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3521091081
Short name T558
Test name
Test status
Simulation time 26939909 ps
CPU time 0.58 seconds
Started Jul 06 07:01:45 PM PDT 24
Finished Jul 06 07:01:47 PM PDT 24
Peak memory 195224 kb
Host smart-e5e57ed5-44c9-4d2e-8221-46ab8a4a6950
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521091081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3521091081
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2971360812
Short name T605
Test name
Test status
Simulation time 76898998 ps
CPU time 1.71 seconds
Started Jul 06 07:01:47 PM PDT 24
Finished Jul 06 07:01:49 PM PDT 24
Peak memory 200356 kb
Host smart-ff9e9597-7993-4006-98df-c59763a15e56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971360812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2971360812
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1461318153
Short name T619
Test name
Test status
Simulation time 499357643 ps
CPU time 4.5 seconds
Started Jul 06 07:01:44 PM PDT 24
Finished Jul 06 07:01:49 PM PDT 24
Peak memory 200600 kb
Host smart-cbf7f96c-e17a-4428-b1b2-be2f64f6f480
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461318153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1461318153
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1826351781
Short name T587
Test name
Test status
Simulation time 100390413 ps
CPU time 1.85 seconds
Started Jul 06 07:01:47 PM PDT 24
Finished Jul 06 07:01:50 PM PDT 24
Peak memory 200292 kb
Host smart-61f2e670-7f8f-473e-b14e-980edef6b290
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826351781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1826351781
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2653598222
Short name T577
Test name
Test status
Simulation time 37088294 ps
CPU time 2.3 seconds
Started Jul 06 07:01:46 PM PDT 24
Finished Jul 06 07:01:50 PM PDT 24
Peak memory 216672 kb
Host smart-b4adca4d-d718-4bbd-9a19-1f3cf2383819
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653598222 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2653598222
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.400144248
Short name T92
Test name
Test status
Simulation time 103088979 ps
CPU time 0.77 seconds
Started Jul 06 07:01:44 PM PDT 24
Finished Jul 06 07:01:45 PM PDT 24
Peak memory 199800 kb
Host smart-e6e4cba0-0ca9-4ed1-a977-ae5a34e66555
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400144248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.400144248
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.485053538
Short name T553
Test name
Test status
Simulation time 12525280 ps
CPU time 0.63 seconds
Started Jul 06 07:01:47 PM PDT 24
Finished Jul 06 07:01:48 PM PDT 24
Peak memory 195288 kb
Host smart-e8ca9276-fc81-4e1f-a868-3b7a00c7bd6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485053538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.485053538
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.914232823
Short name T623
Test name
Test status
Simulation time 168018248 ps
CPU time 2.18 seconds
Started Jul 06 07:01:46 PM PDT 24
Finished Jul 06 07:01:50 PM PDT 24
Peak memory 200268 kb
Host smart-b29596d2-233e-4330-a0a4-d70143d19fb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914232823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.914232823
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2145603647
Short name T564
Test name
Test status
Simulation time 477850994 ps
CPU time 2.64 seconds
Started Jul 06 07:01:46 PM PDT 24
Finished Jul 06 07:01:50 PM PDT 24
Peak memory 200308 kb
Host smart-c26b38a1-77a1-4d24-9733-daaf297c6875
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145603647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2145603647
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.199485919
Short name T112
Test name
Test status
Simulation time 95058146 ps
CPU time 1.87 seconds
Started Jul 06 07:01:46 PM PDT 24
Finished Jul 06 07:01:49 PM PDT 24
Peak memory 200292 kb
Host smart-e802a150-a1d6-40e6-8b93-ed5480d3fb48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199485919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.199485919
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2622129462
Short name T599
Test name
Test status
Simulation time 620077145127 ps
CPU time 851.16 seconds
Started Jul 06 07:01:53 PM PDT 24
Finished Jul 06 07:16:05 PM PDT 24
Peak memory 225032 kb
Host smart-5202406f-615a-4aa0-82c0-f92bd8a82aad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622129462 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2622129462
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3296302740
Short name T81
Test name
Test status
Simulation time 16194007 ps
CPU time 0.85 seconds
Started Jul 06 07:01:53 PM PDT 24
Finished Jul 06 07:01:55 PM PDT 24
Peak memory 199768 kb
Host smart-64e37d99-9a04-493a-aa34-a02da5f2c308
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296302740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3296302740
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1679826412
Short name T612
Test name
Test status
Simulation time 28118442 ps
CPU time 0.58 seconds
Started Jul 06 07:01:52 PM PDT 24
Finished Jul 06 07:01:53 PM PDT 24
Peak memory 195236 kb
Host smart-64e00fa0-3952-437d-8b54-f7c0457d1098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679826412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1679826412
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1365742154
Short name T583
Test name
Test status
Simulation time 44102076 ps
CPU time 1.14 seconds
Started Jul 06 07:01:52 PM PDT 24
Finished Jul 06 07:01:54 PM PDT 24
Peak memory 200276 kb
Host smart-24d6c285-ef79-41ce-b9e2-a4503c6306f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365742154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1365742154
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2242743136
Short name T578
Test name
Test status
Simulation time 172673283 ps
CPU time 1.99 seconds
Started Jul 06 07:01:51 PM PDT 24
Finished Jul 06 07:01:54 PM PDT 24
Peak memory 200228 kb
Host smart-3bcbe34b-8a6a-4166-b5de-65c1c28924db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242743136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2242743136
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.4112657499
Short name T579
Test name
Test status
Simulation time 828418848 ps
CPU time 2.47 seconds
Started Jul 06 07:01:53 PM PDT 24
Finished Jul 06 07:01:57 PM PDT 24
Peak memory 200300 kb
Host smart-f97db7a3-b566-4714-a516-83eb4ea55f39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112657499 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.4112657499
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2709077678
Short name T602
Test name
Test status
Simulation time 13430845 ps
CPU time 0.68 seconds
Started Jul 06 07:01:54 PM PDT 24
Finished Jul 06 07:01:56 PM PDT 24
Peak memory 198256 kb
Host smart-bb672cc8-d043-4b40-a7dd-0bbe0791e345
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709077678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2709077678
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3870615728
Short name T559
Test name
Test status
Simulation time 39304413 ps
CPU time 0.59 seconds
Started Jul 06 07:01:53 PM PDT 24
Finished Jul 06 07:01:54 PM PDT 24
Peak memory 195188 kb
Host smart-a79040db-9078-40a4-858b-dd14fef32617
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870615728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3870615728
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2397197100
Short name T571
Test name
Test status
Simulation time 315284264 ps
CPU time 1.74 seconds
Started Jul 06 07:01:54 PM PDT 24
Finished Jul 06 07:01:57 PM PDT 24
Peak memory 200268 kb
Host smart-a056fd41-891f-463b-8b6e-7d38ca347ec6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397197100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2397197100
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1546685682
Short name T642
Test name
Test status
Simulation time 52282406 ps
CPU time 2.88 seconds
Started Jul 06 07:01:52 PM PDT 24
Finished Jul 06 07:01:56 PM PDT 24
Peak memory 200308 kb
Host smart-712f021b-5871-4123-b967-f34075d8f8ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546685682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1546685682
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.393646934
Short name T549
Test name
Test status
Simulation time 51627492 ps
CPU time 1.27 seconds
Started Jul 06 07:02:02 PM PDT 24
Finished Jul 06 07:02:03 PM PDT 24
Peak memory 200108 kb
Host smart-771a07ba-8ce2-4695-bddc-b78f94df0ef8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393646934 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.393646934
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.3894002039
Short name T93
Test name
Test status
Simulation time 31443912 ps
CPU time 0.87 seconds
Started Jul 06 07:01:53 PM PDT 24
Finished Jul 06 07:01:55 PM PDT 24
Peak memory 200096 kb
Host smart-92064a4c-1cb9-4987-a5e5-5e21010e6a04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894002039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.3894002039
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.983618674
Short name T560
Test name
Test status
Simulation time 174606574 ps
CPU time 0.63 seconds
Started Jul 06 07:01:52 PM PDT 24
Finished Jul 06 07:01:54 PM PDT 24
Peak memory 195292 kb
Host smart-bf4debaf-a54b-472f-9cd4-a554fac52eda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983618674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.983618674
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2376776741
Short name T639
Test name
Test status
Simulation time 283097041 ps
CPU time 2.4 seconds
Started Jul 06 07:01:53 PM PDT 24
Finished Jul 06 07:01:56 PM PDT 24
Peak memory 200364 kb
Host smart-b7c83531-52e6-4db0-b049-7b05df99d2e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376776741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2376776741
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3711868105
Short name T644
Test name
Test status
Simulation time 238367461 ps
CPU time 2.86 seconds
Started Jul 06 07:01:53 PM PDT 24
Finished Jul 06 07:01:56 PM PDT 24
Peak memory 200292 kb
Host smart-c971ba98-5455-4eb6-902c-cec0be997fca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711868105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3711868105
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1809044593
Short name T110
Test name
Test status
Simulation time 96710992 ps
CPU time 1.82 seconds
Started Jul 06 07:01:53 PM PDT 24
Finished Jul 06 07:01:56 PM PDT 24
Peak memory 200308 kb
Host smart-80933b58-d64b-4e71-84cb-6c1f7160cdf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809044593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1809044593
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2001631744
Short name T180
Test name
Test status
Simulation time 49286584 ps
CPU time 0.65 seconds
Started Jul 06 07:10:49 PM PDT 24
Finished Jul 06 07:10:50 PM PDT 24
Peak memory 196152 kb
Host smart-4d6e95e3-d155-4683-a538-076d5d73972c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001631744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2001631744
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2684552970
Short name T426
Test name
Test status
Simulation time 636150457 ps
CPU time 37.19 seconds
Started Jul 06 07:10:44 PM PDT 24
Finished Jul 06 07:11:23 PM PDT 24
Peak memory 200308 kb
Host smart-1d379630-24db-4b25-9c8c-34a921661715
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2684552970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2684552970
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3823707062
Short name T268
Test name
Test status
Simulation time 172947584 ps
CPU time 8.79 seconds
Started Jul 06 07:10:43 PM PDT 24
Finished Jul 06 07:10:54 PM PDT 24
Peak memory 200296 kb
Host smart-01d48483-db95-4657-a242-0d9177c2dd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823707062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3823707062
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.147851923
Short name T341
Test name
Test status
Simulation time 1168216988 ps
CPU time 116.59 seconds
Started Jul 06 07:10:42 PM PDT 24
Finished Jul 06 07:12:41 PM PDT 24
Peak memory 555136 kb
Host smart-aeeab77c-1310-4ac9-a09b-c6f6b6eb8cd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=147851923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.147851923
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.3170944399
Short name T314
Test name
Test status
Simulation time 45585031335 ps
CPU time 189.6 seconds
Started Jul 06 07:10:48 PM PDT 24
Finished Jul 06 07:13:59 PM PDT 24
Peak memory 200380 kb
Host smart-09951e84-8353-493b-8933-97dc8d9e5e32
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170944399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.3170944399
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1302126775
Short name T195
Test name
Test status
Simulation time 4850420112 ps
CPU time 130.7 seconds
Started Jul 06 07:10:42 PM PDT 24
Finished Jul 06 07:12:55 PM PDT 24
Peak memory 200416 kb
Host smart-87b600f4-69ce-4078-a4ba-62831f88f96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302126775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1302126775
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.3082834486
Short name T169
Test name
Test status
Simulation time 319945637 ps
CPU time 13.05 seconds
Started Jul 06 07:10:50 PM PDT 24
Finished Jul 06 07:11:05 PM PDT 24
Peak memory 200260 kb
Host smart-8650a13e-52a2-4ae4-9b30-05c3c3a89078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082834486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3082834486
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.314885304
Short name T527
Test name
Test status
Simulation time 8779868949 ps
CPU time 247.94 seconds
Started Jul 06 07:10:49 PM PDT 24
Finished Jul 06 07:14:58 PM PDT 24
Peak memory 216780 kb
Host smart-552a1a33-2fa8-43ae-b54e-460d6d5a27b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314885304 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.314885304
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.3334164634
Short name T60
Test name
Test status
Simulation time 21749505180 ps
CPU time 376.49 seconds
Started Jul 06 07:10:47 PM PDT 24
Finished Jul 06 07:17:04 PM PDT 24
Peak memory 336156 kb
Host smart-145c03f8-a2a7-4f9e-99a9-a186ea64a9b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3334164634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.3334164634
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.3591559428
Short name T491
Test name
Test status
Simulation time 12607846561 ps
CPU time 47.03 seconds
Started Jul 06 07:10:49 PM PDT 24
Finished Jul 06 07:11:37 PM PDT 24
Peak memory 200364 kb
Host smart-f4ee7ede-6789-4209-8654-5bfaf0eeef9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3591559428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3591559428
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.1916087990
Short name T335
Test name
Test status
Simulation time 4782287473 ps
CPU time 95.52 seconds
Started Jul 06 07:10:49 PM PDT 24
Finished Jul 06 07:12:26 PM PDT 24
Peak memory 200432 kb
Host smart-b80d1f83-5b00-4dd2-b2fc-a958624bea44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1916087990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.1916087990
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.242629268
Short name T171
Test name
Test status
Simulation time 3200696240 ps
CPU time 129.66 seconds
Started Jul 06 07:10:50 PM PDT 24
Finished Jul 06 07:13:01 PM PDT 24
Peak memory 200376 kb
Host smart-8b6bd1de-31a5-4fe3-bf9a-b05547292c13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=242629268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.242629268
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.2069385184
Short name T460
Test name
Test status
Simulation time 9568061208 ps
CPU time 549.28 seconds
Started Jul 06 07:10:45 PM PDT 24
Finished Jul 06 07:19:56 PM PDT 24
Peak memory 200384 kb
Host smart-24207d93-18e2-4871-86b7-c276ae489d7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2069385184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.2069385184
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.456091387
Short name T300
Test name
Test status
Simulation time 442872701010 ps
CPU time 2487.94 seconds
Started Jul 06 07:10:49 PM PDT 24
Finished Jul 06 07:52:21 PM PDT 24
Peak memory 216436 kb
Host smart-9a79fe16-9d99-4e4e-887a-d83404824a65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=456091387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.456091387
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.1785602960
Short name T480
Test name
Test status
Simulation time 825087120755 ps
CPU time 2665.7 seconds
Started Jul 06 07:10:50 PM PDT 24
Finished Jul 06 07:55:19 PM PDT 24
Peak memory 216652 kb
Host smart-67e9c0b5-83ae-4e7c-9526-628ee6294f65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1785602960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.1785602960
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.157709451
Short name T309
Test name
Test status
Simulation time 2672935744 ps
CPU time 51.21 seconds
Started Jul 06 07:10:44 PM PDT 24
Finished Jul 06 07:11:37 PM PDT 24
Peak memory 200396 kb
Host smart-2dd17fbe-fc9c-4b67-b065-f01f6db0169a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157709451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.157709451
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1915103400
Short name T371
Test name
Test status
Simulation time 32772325 ps
CPU time 0.6 seconds
Started Jul 06 07:10:55 PM PDT 24
Finished Jul 06 07:10:57 PM PDT 24
Peak memory 195200 kb
Host smart-b16adce6-2be2-4499-898e-ac1f42012205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915103400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1915103400
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.1086961640
Short name T338
Test name
Test status
Simulation time 1120914381 ps
CPU time 71.15 seconds
Started Jul 06 07:10:47 PM PDT 24
Finished Jul 06 07:11:59 PM PDT 24
Peak memory 200280 kb
Host smart-88b278be-615c-42a3-ab54-42db52aba171
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1086961640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.1086961640
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3588405969
Short name T304
Test name
Test status
Simulation time 4090581771 ps
CPU time 73.87 seconds
Started Jul 06 07:10:47 PM PDT 24
Finished Jul 06 07:12:02 PM PDT 24
Peak memory 200380 kb
Host smart-3622811d-931b-48a3-abce-42c1adf70b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588405969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3588405969
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2888063055
Short name T223
Test name
Test status
Simulation time 9697179380 ps
CPU time 237.34 seconds
Started Jul 06 07:10:50 PM PDT 24
Finished Jul 06 07:14:49 PM PDT 24
Peak memory 624608 kb
Host smart-51b584bb-692e-4adb-baf7-6c50eae79939
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2888063055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2888063055
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.2808727270
Short name T235
Test name
Test status
Simulation time 43319690806 ps
CPU time 59.8 seconds
Started Jul 06 07:13:33 PM PDT 24
Finished Jul 06 07:14:57 PM PDT 24
Peak memory 200340 kb
Host smart-dd7f93ec-63c9-4650-af62-92086ddf820e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808727270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2808727270
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.633321607
Short name T210
Test name
Test status
Simulation time 2632866445 ps
CPU time 37.42 seconds
Started Jul 06 07:10:49 PM PDT 24
Finished Jul 06 07:11:28 PM PDT 24
Peak memory 200372 kb
Host smart-16cf0b71-41d8-47d7-98ae-ec514fb62187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633321607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.633321607
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3918286672
Short name T42
Test name
Test status
Simulation time 86575592 ps
CPU time 0.96 seconds
Started Jul 06 07:11:00 PM PDT 24
Finished Jul 06 07:11:03 PM PDT 24
Peak memory 218240 kb
Host smart-5e2764b1-7587-4b37-9823-25dfb10e7194
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918286672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3918286672
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3297184127
Short name T471
Test name
Test status
Simulation time 1243140868 ps
CPU time 15.12 seconds
Started Jul 06 07:10:47 PM PDT 24
Finished Jul 06 07:11:03 PM PDT 24
Peak memory 200248 kb
Host smart-6c3cb9a7-0a96-4aea-a6d7-9f493c458e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297184127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3297184127
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3447452591
Short name T222
Test name
Test status
Simulation time 72508882175 ps
CPU time 966.46 seconds
Started Jul 06 07:10:49 PM PDT 24
Finished Jul 06 07:26:56 PM PDT 24
Peak memory 200348 kb
Host smart-cab29046-9771-4eca-9307-08106c9759b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447452591 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3447452591
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3900081936
Short name T11
Test name
Test status
Simulation time 108871536951 ps
CPU time 1022.45 seconds
Started Jul 06 07:10:56 PM PDT 24
Finished Jul 06 07:27:59 PM PDT 24
Peak memory 577928 kb
Host smart-485fdcf3-9813-4354-973d-5371802d7b5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3900081936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3900081936
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.74559334
Short name T130
Test name
Test status
Simulation time 3008761959 ps
CPU time 66.81 seconds
Started Jul 06 07:10:49 PM PDT 24
Finished Jul 06 07:11:57 PM PDT 24
Peak memory 200388 kb
Host smart-fac9550b-5573-4847-8ea1-bafb5b7ca867
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=74559334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.74559334
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.1266568071
Short name T155
Test name
Test status
Simulation time 2423745310 ps
CPU time 95.83 seconds
Started Jul 06 07:10:50 PM PDT 24
Finished Jul 06 07:12:27 PM PDT 24
Peak memory 200316 kb
Host smart-c15e1033-1e8b-450e-81b2-a7e9720fc68c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1266568071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.1266568071
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.3456123744
Short name T446
Test name
Test status
Simulation time 43894583201 ps
CPU time 120.99 seconds
Started Jul 06 07:10:48 PM PDT 24
Finished Jul 06 07:12:49 PM PDT 24
Peak memory 200372 kb
Host smart-2ff853d6-4dc8-473d-92a0-93e7d626e6b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3456123744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.3456123744
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.294725564
Short name T412
Test name
Test status
Simulation time 8980746151 ps
CPU time 503.89 seconds
Started Jul 06 07:10:49 PM PDT 24
Finished Jul 06 07:19:14 PM PDT 24
Peak memory 200368 kb
Host smart-44bd8a51-3df9-4a70-a465-4a7c5ed9967e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=294725564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.294725564
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.282548452
Short name T296
Test name
Test status
Simulation time 167504079122 ps
CPU time 2499.43 seconds
Started Jul 06 07:10:49 PM PDT 24
Finished Jul 06 07:52:30 PM PDT 24
Peak memory 216404 kb
Host smart-ff6e4f48-5b97-40d4-83fc-9bcb3c3131bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=282548452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.282548452
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.2974540117
Short name T344
Test name
Test status
Simulation time 573035880788 ps
CPU time 2674.4 seconds
Started Jul 06 07:10:51 PM PDT 24
Finished Jul 06 07:55:27 PM PDT 24
Peak memory 215816 kb
Host smart-3d2226f4-2c32-4839-9ef0-40dc47d1d195
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2974540117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2974540117
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.4052615550
Short name T492
Test name
Test status
Simulation time 2696791214 ps
CPU time 98.43 seconds
Started Jul 06 07:10:50 PM PDT 24
Finished Jul 06 07:12:30 PM PDT 24
Peak memory 200340 kb
Host smart-eeee8d2b-1fbf-4c5c-9775-4e6e5af26b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052615550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.4052615550
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2163834596
Short name T281
Test name
Test status
Simulation time 22990769 ps
CPU time 0.59 seconds
Started Jul 06 07:11:18 PM PDT 24
Finished Jul 06 07:11:19 PM PDT 24
Peak memory 195164 kb
Host smart-0e43f7d3-c873-4aa7-9abc-9544e8f14d5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163834596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2163834596
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2784620853
Short name T303
Test name
Test status
Simulation time 1605869696 ps
CPU time 91.26 seconds
Started Jul 06 07:11:13 PM PDT 24
Finished Jul 06 07:12:46 PM PDT 24
Peak memory 200308 kb
Host smart-463a8242-f1dc-41fa-b162-fdb959f650d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2784620853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2784620853
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1642327095
Short name T423
Test name
Test status
Simulation time 1486929768 ps
CPU time 19.55 seconds
Started Jul 06 07:11:19 PM PDT 24
Finished Jul 06 07:11:40 PM PDT 24
Peak memory 200328 kb
Host smart-f77b4e47-53c7-4dff-acc3-b2c4440f6786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642327095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1642327095
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2356884913
Short name T515
Test name
Test status
Simulation time 1712066412 ps
CPU time 299.74 seconds
Started Jul 06 07:11:13 PM PDT 24
Finished Jul 06 07:16:14 PM PDT 24
Peak memory 595972 kb
Host smart-f070de9f-e62f-4d54-934f-926ba8e28fdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2356884913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2356884913
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.4038068632
Short name T495
Test name
Test status
Simulation time 41164568893 ps
CPU time 58.87 seconds
Started Jul 06 07:11:17 PM PDT 24
Finished Jul 06 07:12:17 PM PDT 24
Peak memory 200400 kb
Host smart-8d2e9915-04cc-4e8e-b5e8-1d0e00e1a529
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038068632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.4038068632
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3968687210
Short name T46
Test name
Test status
Simulation time 388222805 ps
CPU time 23.36 seconds
Started Jul 06 07:11:13 PM PDT 24
Finished Jul 06 07:11:38 PM PDT 24
Peak memory 200316 kb
Host smart-bc67c98e-1bf8-494b-aae9-2c21fc0126d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968687210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3968687210
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.589980202
Short name T493
Test name
Test status
Simulation time 443999441 ps
CPU time 14.18 seconds
Started Jul 06 07:11:13 PM PDT 24
Finished Jul 06 07:11:29 PM PDT 24
Peak memory 200340 kb
Host smart-6b592723-0f37-4e11-ba28-c31e6771575b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589980202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.589980202
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3449860631
Short name T417
Test name
Test status
Simulation time 14754164774 ps
CPU time 967.41 seconds
Started Jul 06 07:11:18 PM PDT 24
Finished Jul 06 07:27:27 PM PDT 24
Peak memory 706032 kb
Host smart-764fb44d-d957-4bf0-99bc-068131f33cff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449860631 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3449860631
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.3775412912
Short name T177
Test name
Test status
Simulation time 25735648281 ps
CPU time 90.68 seconds
Started Jul 06 07:11:20 PM PDT 24
Finished Jul 06 07:12:51 PM PDT 24
Peak memory 200352 kb
Host smart-911137ff-166b-4389-ba68-d375e3916bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775412912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3775412912
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2092078785
Short name T203
Test name
Test status
Simulation time 20852371 ps
CPU time 0.59 seconds
Started Jul 06 07:11:27 PM PDT 24
Finished Jul 06 07:11:29 PM PDT 24
Peak memory 195820 kb
Host smart-19794a54-9517-4bdf-a4b6-189a21659387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092078785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2092078785
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.261800863
Short name T516
Test name
Test status
Simulation time 5837034464 ps
CPU time 85.51 seconds
Started Jul 06 07:11:18 PM PDT 24
Finished Jul 06 07:12:44 PM PDT 24
Peak memory 200348 kb
Host smart-8af51d17-d9fd-45c0-afb4-1ef651a819d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=261800863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.261800863
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1778137404
Short name T442
Test name
Test status
Simulation time 6322256033 ps
CPU time 82.51 seconds
Started Jul 06 07:11:18 PM PDT 24
Finished Jul 06 07:12:42 PM PDT 24
Peak memory 208504 kb
Host smart-cd596a0e-98e8-438d-a5f5-b3836613190b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778137404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1778137404
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.251671930
Short name T410
Test name
Test status
Simulation time 26974192892 ps
CPU time 1672.18 seconds
Started Jul 06 07:11:20 PM PDT 24
Finished Jul 06 07:39:13 PM PDT 24
Peak memory 776104 kb
Host smart-b6a74bd9-d19b-41f6-9ec6-4d3b47967b48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=251671930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.251671930
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2995535133
Short name T311
Test name
Test status
Simulation time 15066153871 ps
CPU time 187.32 seconds
Started Jul 06 07:11:26 PM PDT 24
Finished Jul 06 07:14:35 PM PDT 24
Peak memory 200360 kb
Host smart-6207f5a8-94dc-48cc-aeca-59cfac1faad5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995535133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2995535133
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2149799506
Short name T481
Test name
Test status
Simulation time 31863103445 ps
CPU time 141.25 seconds
Started Jul 06 07:11:20 PM PDT 24
Finished Jul 06 07:13:42 PM PDT 24
Peak memory 200360 kb
Host smart-7399478c-20c6-4055-a03d-d35a5d9f695f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149799506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2149799506
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1954828882
Short name T305
Test name
Test status
Simulation time 120295615 ps
CPU time 5.4 seconds
Started Jul 06 07:11:19 PM PDT 24
Finished Jul 06 07:11:25 PM PDT 24
Peak memory 200312 kb
Host smart-f8c74d55-5c63-4a35-995d-3a8ff3b068a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954828882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1954828882
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1653441161
Short name T404
Test name
Test status
Simulation time 16223654926 ps
CPU time 3005.72 seconds
Started Jul 06 07:11:24 PM PDT 24
Finished Jul 06 08:01:31 PM PDT 24
Peak memory 796636 kb
Host smart-518c994b-2de1-44d9-855b-f9a702ee0a4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653441161 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1653441161
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2208804047
Short name T267
Test name
Test status
Simulation time 1201510283 ps
CPU time 52.04 seconds
Started Jul 06 07:11:25 PM PDT 24
Finished Jul 06 07:12:19 PM PDT 24
Peak memory 200236 kb
Host smart-1b8dcad1-cded-43fc-8d7c-0492ab171019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208804047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2208804047
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3168275817
Short name T217
Test name
Test status
Simulation time 16403505 ps
CPU time 0.63 seconds
Started Jul 06 07:11:26 PM PDT 24
Finished Jul 06 07:11:29 PM PDT 24
Peak memory 196188 kb
Host smart-bf9cd68b-861b-451f-a41d-bbc5d1687f6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168275817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3168275817
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.680890513
Short name T408
Test name
Test status
Simulation time 1483166732 ps
CPU time 88.26 seconds
Started Jul 06 07:11:26 PM PDT 24
Finished Jul 06 07:12:55 PM PDT 24
Peak memory 200284 kb
Host smart-9d69f2f1-4820-4298-bb91-b60715083c00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=680890513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.680890513
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1421125787
Short name T502
Test name
Test status
Simulation time 13144644075 ps
CPU time 65.51 seconds
Started Jul 06 07:11:25 PM PDT 24
Finished Jul 06 07:12:33 PM PDT 24
Peak memory 200400 kb
Host smart-ab60f8ca-f587-4516-833d-ba2bae9b2d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421125787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1421125787
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2135817579
Short name T30
Test name
Test status
Simulation time 4930225000 ps
CPU time 1060.64 seconds
Started Jul 06 07:11:25 PM PDT 24
Finished Jul 06 07:29:07 PM PDT 24
Peak memory 746204 kb
Host smart-94ebed68-013b-468d-aef0-6b0b8c1a3976
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2135817579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2135817579
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1397857140
Short name T380
Test name
Test status
Simulation time 2638276555 ps
CPU time 144.93 seconds
Started Jul 06 07:11:25 PM PDT 24
Finished Jul 06 07:13:51 PM PDT 24
Peak memory 200356 kb
Host smart-860e7a42-c3a7-400f-aafb-c10ea1346187
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397857140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1397857140
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.2151011947
Short name T413
Test name
Test status
Simulation time 3459587959 ps
CPU time 47.03 seconds
Started Jul 06 07:11:26 PM PDT 24
Finished Jul 06 07:12:14 PM PDT 24
Peak memory 200432 kb
Host smart-66121f55-13fe-44da-8d03-6f4c4bf39cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151011947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.2151011947
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2668743115
Short name T308
Test name
Test status
Simulation time 1564917279 ps
CPU time 11.84 seconds
Started Jul 06 07:11:25 PM PDT 24
Finished Jul 06 07:11:38 PM PDT 24
Peak memory 200276 kb
Host smart-3de699af-5831-40f4-9a69-218ba29f188a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668743115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2668743115
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3602663796
Short name T519
Test name
Test status
Simulation time 17440923404 ps
CPU time 226.15 seconds
Started Jul 06 07:11:25 PM PDT 24
Finished Jul 06 07:15:12 PM PDT 24
Peak memory 200372 kb
Host smart-e85a648d-bb76-49b2-8ea1-770a785342f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602663796 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3602663796
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3222149169
Short name T486
Test name
Test status
Simulation time 7030394936 ps
CPU time 92.84 seconds
Started Jul 06 07:11:26 PM PDT 24
Finished Jul 06 07:13:01 PM PDT 24
Peak memory 200396 kb
Host smart-11128eb8-fa31-47ef-a6eb-b1bd6250d5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222149169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3222149169
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1889775170
Short name T224
Test name
Test status
Simulation time 50322731 ps
CPU time 0.55 seconds
Started Jul 06 07:11:24 PM PDT 24
Finished Jul 06 07:11:25 PM PDT 24
Peak memory 195196 kb
Host smart-b931a079-82a1-4ab6-bb34-2f51652d9ef5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889775170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1889775170
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.846069548
Short name T8
Test name
Test status
Simulation time 1204600548 ps
CPU time 62.26 seconds
Started Jul 06 07:11:26 PM PDT 24
Finished Jul 06 07:12:30 PM PDT 24
Peak memory 200372 kb
Host smart-ef9c6ece-5065-4705-9995-07138d049d53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=846069548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.846069548
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1075097453
Short name T312
Test name
Test status
Simulation time 59351126100 ps
CPU time 66.89 seconds
Started Jul 06 07:11:27 PM PDT 24
Finished Jul 06 07:12:35 PM PDT 24
Peak memory 200300 kb
Host smart-5fd7c59e-b089-423d-a8d3-5cd450eb9fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075097453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1075097453
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1021366427
Short name T51
Test name
Test status
Simulation time 88267941341 ps
CPU time 964.25 seconds
Started Jul 06 07:11:26 PM PDT 24
Finished Jul 06 07:27:32 PM PDT 24
Peak memory 743212 kb
Host smart-a1ba45b7-de2e-446c-8422-609b0494b23e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1021366427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1021366427
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.478135899
Short name T156
Test name
Test status
Simulation time 7172223150 ps
CPU time 97.69 seconds
Started Jul 06 07:11:26 PM PDT 24
Finished Jul 06 07:13:05 PM PDT 24
Peak memory 200380 kb
Host smart-2bd29b5a-15e6-49d8-825d-fc93a07243c3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478135899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.478135899
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.29429084
Short name T143
Test name
Test status
Simulation time 12311711722 ps
CPU time 215.25 seconds
Started Jul 06 07:11:27 PM PDT 24
Finished Jul 06 07:15:04 PM PDT 24
Peak memory 208628 kb
Host smart-c7f0f4c1-bcb7-47f7-a799-7d677596f213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29429084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.29429084
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3377304461
Short name T117
Test name
Test status
Simulation time 584812615 ps
CPU time 10.13 seconds
Started Jul 06 07:11:28 PM PDT 24
Finished Jul 06 07:11:39 PM PDT 24
Peak memory 200304 kb
Host smart-a384cf44-0136-4aa1-bef2-82df406e345c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377304461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3377304461
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1107462911
Short name T477
Test name
Test status
Simulation time 13111154429 ps
CPU time 1382.53 seconds
Started Jul 06 07:11:25 PM PDT 24
Finished Jul 06 07:34:30 PM PDT 24
Peak memory 726756 kb
Host smart-38d88d77-da74-49cc-9c5d-025cd4f327b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107462911 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1107462911
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.4229059426
Short name T316
Test name
Test status
Simulation time 10001307592 ps
CPU time 148.07 seconds
Started Jul 06 07:11:24 PM PDT 24
Finished Jul 06 07:13:54 PM PDT 24
Peak memory 200392 kb
Host smart-2a002310-62cf-4360-9d15-9b5585c59913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229059426 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.4229059426
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1056021347
Short name T402
Test name
Test status
Simulation time 16297393 ps
CPU time 0.62 seconds
Started Jul 06 07:11:28 PM PDT 24
Finished Jul 06 07:11:30 PM PDT 24
Peak memory 196184 kb
Host smart-d16fda1b-528d-47b5-8c76-8cd93c15d06e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056021347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1056021347
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2658236958
Short name T32
Test name
Test status
Simulation time 17692249850 ps
CPU time 110.46 seconds
Started Jul 06 07:11:25 PM PDT 24
Finished Jul 06 07:13:17 PM PDT 24
Peak memory 208600 kb
Host smart-68001231-cfb7-4008-9175-b7c4a8555a52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2658236958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2658236958
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.1435219322
Short name T2
Test name
Test status
Simulation time 35189016348 ps
CPU time 78.05 seconds
Started Jul 06 07:11:24 PM PDT 24
Finished Jul 06 07:12:43 PM PDT 24
Peak memory 200356 kb
Host smart-613ef2cc-ff88-4ebb-9499-0bc8fd79b1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435219322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1435219322
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1544469323
Short name T439
Test name
Test status
Simulation time 5066659453 ps
CPU time 432.67 seconds
Started Jul 06 07:11:26 PM PDT 24
Finished Jul 06 07:18:40 PM PDT 24
Peak memory 488432 kb
Host smart-8ed00285-602f-484f-b5d1-db8d1174b1ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1544469323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1544469323
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.140061166
Short name T198
Test name
Test status
Simulation time 83156710 ps
CPU time 4.74 seconds
Started Jul 06 07:11:26 PM PDT 24
Finished Jul 06 07:11:33 PM PDT 24
Peak memory 200240 kb
Host smart-91c9f9aa-440d-41f7-889f-6eede559fc3d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140061166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.140061166
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1292687776
Short name T69
Test name
Test status
Simulation time 25370277270 ps
CPU time 74.5 seconds
Started Jul 06 07:11:25 PM PDT 24
Finished Jul 06 07:12:41 PM PDT 24
Peak memory 200440 kb
Host smart-a55a295f-fc4b-452f-9f6d-72bbf6cfc4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292687776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1292687776
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3775563092
Short name T382
Test name
Test status
Simulation time 830564434 ps
CPU time 9.45 seconds
Started Jul 06 07:11:28 PM PDT 24
Finished Jul 06 07:11:38 PM PDT 24
Peak memory 200224 kb
Host smart-25e34215-ee15-4713-8df9-f4c838797d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775563092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3775563092
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.501074288
Short name T383
Test name
Test status
Simulation time 10058756745 ps
CPU time 307.03 seconds
Started Jul 06 07:11:27 PM PDT 24
Finished Jul 06 07:16:36 PM PDT 24
Peak memory 607260 kb
Host smart-b8e79e40-737d-4a0b-93f2-70832bda90c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501074288 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.501074288
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2129153746
Short name T250
Test name
Test status
Simulation time 1986089230 ps
CPU time 86.37 seconds
Started Jul 06 07:11:26 PM PDT 24
Finished Jul 06 07:12:54 PM PDT 24
Peak memory 200280 kb
Host smart-5503170e-8c7b-42dc-90d1-408bcd2c5037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129153746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2129153746
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3309156898
Short name T184
Test name
Test status
Simulation time 96857220 ps
CPU time 0.59 seconds
Started Jul 06 07:11:33 PM PDT 24
Finished Jul 06 07:11:35 PM PDT 24
Peak memory 196216 kb
Host smart-ffaf7742-cce9-4c73-84ea-c5c00fac3e95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309156898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3309156898
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3158953994
Short name T533
Test name
Test status
Simulation time 2359840245 ps
CPU time 66.79 seconds
Started Jul 06 07:11:26 PM PDT 24
Finished Jul 06 07:12:34 PM PDT 24
Peak memory 200396 kb
Host smart-910f4cf2-71da-4f4a-8bb7-e838ec887f8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3158953994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3158953994
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3670466474
Short name T388
Test name
Test status
Simulation time 4953717216 ps
CPU time 68.64 seconds
Started Jul 06 07:11:24 PM PDT 24
Finished Jul 06 07:12:34 PM PDT 24
Peak memory 200392 kb
Host smart-85535ab2-18ce-4130-9fe7-4154560f108d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670466474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3670466474
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.71791447
Short name T414
Test name
Test status
Simulation time 975326708 ps
CPU time 86.26 seconds
Started Jul 06 07:11:25 PM PDT 24
Finished Jul 06 07:12:53 PM PDT 24
Peak memory 317580 kb
Host smart-5fb6da3b-3a93-421e-a672-f95f94596684
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=71791447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.71791447
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2081694693
Short name T258
Test name
Test status
Simulation time 19957470805 ps
CPU time 256.73 seconds
Started Jul 06 07:11:25 PM PDT 24
Finished Jul 06 07:15:44 PM PDT 24
Peak memory 200408 kb
Host smart-254a78b4-6789-440a-94bf-86b9891de24a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081694693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2081694693
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.416481740
Short name T355
Test name
Test status
Simulation time 6779532056 ps
CPU time 40.16 seconds
Started Jul 06 07:11:26 PM PDT 24
Finished Jul 06 07:12:08 PM PDT 24
Peak memory 200392 kb
Host smart-c56fc926-bc66-436d-994f-d7ef5ab69d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416481740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.416481740
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.2885439024
Short name T291
Test name
Test status
Simulation time 72880191 ps
CPU time 1.76 seconds
Started Jul 06 07:11:25 PM PDT 24
Finished Jul 06 07:11:28 PM PDT 24
Peak memory 200256 kb
Host smart-94dd53ee-9109-4272-8a86-1d7bdfd1b531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885439024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.2885439024
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2946569882
Short name T214
Test name
Test status
Simulation time 33314827245 ps
CPU time 99.75 seconds
Started Jul 06 07:11:34 PM PDT 24
Finished Jul 06 07:13:15 PM PDT 24
Peak memory 216540 kb
Host smart-3b346c74-df43-4a12-839b-04d621d9fe47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946569882 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2946569882
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.4195066555
Short name T75
Test name
Test status
Simulation time 16924378195 ps
CPU time 106.47 seconds
Started Jul 06 07:11:32 PM PDT 24
Finished Jul 06 07:13:20 PM PDT 24
Peak memory 200320 kb
Host smart-9e1cba8e-6c3c-40ae-a6a7-8deec80ea621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195066555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.4195066555
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.1474963650
Short name T62
Test name
Test status
Simulation time 18679474 ps
CPU time 0.58 seconds
Started Jul 06 07:11:39 PM PDT 24
Finished Jul 06 07:11:40 PM PDT 24
Peak memory 195856 kb
Host smart-ad2264b4-eb54-4a88-94b7-f3d1dd17fd46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474963650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1474963650
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.912196218
Short name T135
Test name
Test status
Simulation time 2649373593 ps
CPU time 45.87 seconds
Started Jul 06 07:11:31 PM PDT 24
Finished Jul 06 07:12:18 PM PDT 24
Peak memory 200324 kb
Host smart-09b11428-c16d-4bd6-ba64-b796a3812e73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=912196218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.912196218
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2208667017
Short name T441
Test name
Test status
Simulation time 3210860678 ps
CPU time 65.41 seconds
Started Jul 06 07:11:33 PM PDT 24
Finished Jul 06 07:12:40 PM PDT 24
Peak memory 200388 kb
Host smart-9523bbf3-f88e-409b-b77c-5319f8206c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208667017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2208667017
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.54816130
Short name T197
Test name
Test status
Simulation time 38677777 ps
CPU time 0.66 seconds
Started Jul 06 07:11:32 PM PDT 24
Finished Jul 06 07:11:34 PM PDT 24
Peak memory 198604 kb
Host smart-b8d3859e-f29c-4648-b49f-b3f8275f7bbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=54816130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.54816130
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.3569556935
Short name T425
Test name
Test status
Simulation time 269390878 ps
CPU time 16.76 seconds
Started Jul 06 07:11:30 PM PDT 24
Finished Jul 06 07:11:48 PM PDT 24
Peak memory 200300 kb
Host smart-bdb441ca-065b-43c0-a26e-4c9644f4a2ba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569556935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3569556935
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2396357246
Short name T403
Test name
Test status
Simulation time 2473569644 ps
CPU time 23.74 seconds
Started Jul 06 07:11:31 PM PDT 24
Finished Jul 06 07:11:55 PM PDT 24
Peak memory 200312 kb
Host smart-2eaa623b-0596-4439-a4ef-cc9f875a6584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396357246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2396357246
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.3486476770
Short name T283
Test name
Test status
Simulation time 255842963 ps
CPU time 3.41 seconds
Started Jul 06 07:11:32 PM PDT 24
Finished Jul 06 07:11:36 PM PDT 24
Peak memory 200288 kb
Host smart-7f1a1f7e-363c-40e5-b269-05b6acaf202d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486476770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3486476770
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.464458385
Short name T387
Test name
Test status
Simulation time 17513622955 ps
CPU time 438.81 seconds
Started Jul 06 07:11:33 PM PDT 24
Finished Jul 06 07:18:53 PM PDT 24
Peak memory 200376 kb
Host smart-94744f76-fe3c-443f-9ae5-c590ad14688a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464458385 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.464458385
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.426835644
Short name T453
Test name
Test status
Simulation time 1408208083 ps
CPU time 55.7 seconds
Started Jul 06 07:11:32 PM PDT 24
Finished Jul 06 07:12:28 PM PDT 24
Peak memory 200312 kb
Host smart-c4288a8c-6056-41e1-941f-c5c9035f07e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426835644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.426835644
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1586838914
Short name T450
Test name
Test status
Simulation time 23770638 ps
CPU time 0.59 seconds
Started Jul 06 07:11:48 PM PDT 24
Finished Jul 06 07:11:49 PM PDT 24
Peak memory 196872 kb
Host smart-5d44cce4-ba63-4858-99ad-fe70c50cf7c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586838914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1586838914
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.534615773
Short name T369
Test name
Test status
Simulation time 693462669 ps
CPU time 10.28 seconds
Started Jul 06 07:11:38 PM PDT 24
Finished Jul 06 07:11:49 PM PDT 24
Peak memory 200224 kb
Host smart-3f2a1c0e-0ee7-4181-bb19-0e65abf0e70a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=534615773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.534615773
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.4061799704
Short name T124
Test name
Test status
Simulation time 770966122 ps
CPU time 29.82 seconds
Started Jul 06 07:11:38 PM PDT 24
Finished Jul 06 07:12:08 PM PDT 24
Peak memory 200304 kb
Host smart-316fae35-af10-4bf3-9807-40ba8c08e065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061799704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.4061799704
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2017559149
Short name T137
Test name
Test status
Simulation time 18320255841 ps
CPU time 837.61 seconds
Started Jul 06 07:11:40 PM PDT 24
Finished Jul 06 07:25:38 PM PDT 24
Peak memory 656176 kb
Host smart-9417e810-b932-4890-9c69-b792dba5611c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2017559149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2017559149
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.773072847
Short name T133
Test name
Test status
Simulation time 8831671448 ps
CPU time 164.04 seconds
Started Jul 06 07:11:39 PM PDT 24
Finished Jul 06 07:14:24 PM PDT 24
Peak memory 200412 kb
Host smart-54d0f0dd-3830-4f26-98e8-04fedd078860
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773072847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.773072847
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2778390399
Short name T437
Test name
Test status
Simulation time 1645164942 ps
CPU time 95.6 seconds
Started Jul 06 07:11:39 PM PDT 24
Finished Jul 06 07:13:15 PM PDT 24
Peak memory 200300 kb
Host smart-c9f1728a-c341-4517-9684-9aed8a528993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778390399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2778390399
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2122461963
Short name T478
Test name
Test status
Simulation time 38498748 ps
CPU time 2.24 seconds
Started Jul 06 07:11:38 PM PDT 24
Finished Jul 06 07:11:41 PM PDT 24
Peak memory 200264 kb
Host smart-08aa3cc2-779b-4bb0-8d46-502597cf9996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122461963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2122461963
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.486109037
Short name T77
Test name
Test status
Simulation time 150892761245 ps
CPU time 2546.97 seconds
Started Jul 06 07:11:49 PM PDT 24
Finished Jul 06 07:54:17 PM PDT 24
Peak memory 787140 kb
Host smart-0951a3d5-5262-4866-b338-04dbff11fc19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486109037 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.486109037
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1875394915
Short name T346
Test name
Test status
Simulation time 9569038690 ps
CPU time 112.18 seconds
Started Jul 06 07:11:48 PM PDT 24
Finished Jul 06 07:13:41 PM PDT 24
Peak memory 200416 kb
Host smart-5924a0e0-6960-4aae-ad9b-4fb167f2a7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875394915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1875394915
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1456112486
Short name T216
Test name
Test status
Simulation time 13859590 ps
CPU time 0.62 seconds
Started Jul 06 07:11:51 PM PDT 24
Finished Jul 06 07:11:52 PM PDT 24
Peak memory 196196 kb
Host smart-da012dc2-d38a-4a4f-8ebc-fb6c8a4d19be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456112486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1456112486
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1224052297
Short name T275
Test name
Test status
Simulation time 143097609 ps
CPU time 4.21 seconds
Started Jul 06 07:11:47 PM PDT 24
Finished Jul 06 07:11:52 PM PDT 24
Peak memory 200228 kb
Host smart-15c20439-fced-4f64-bb5a-70d8dfa947d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1224052297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1224052297
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3398486460
Short name T123
Test name
Test status
Simulation time 3197291679 ps
CPU time 46.28 seconds
Started Jul 06 07:11:54 PM PDT 24
Finished Jul 06 07:12:41 PM PDT 24
Peak memory 208612 kb
Host smart-843fe4d5-cbde-47dc-b8ff-5782d5d559a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398486460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3398486460
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3744538592
Short name T470
Test name
Test status
Simulation time 5576836776 ps
CPU time 163.82 seconds
Started Jul 06 07:11:53 PM PDT 24
Finished Jul 06 07:14:37 PM PDT 24
Peak memory 356300 kb
Host smart-5423719c-28a3-4c04-a903-6620aefd1bec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3744538592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3744538592
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3260845065
Short name T144
Test name
Test status
Simulation time 15585921916 ps
CPU time 203.18 seconds
Started Jul 06 07:11:52 PM PDT 24
Finished Jul 06 07:15:16 PM PDT 24
Peak memory 200364 kb
Host smart-63d297ec-87fa-46cd-af72-0f5f1156638e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260845065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3260845065
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1476784058
Short name T241
Test name
Test status
Simulation time 51965064786 ps
CPU time 74.7 seconds
Started Jul 06 07:11:45 PM PDT 24
Finished Jul 06 07:13:01 PM PDT 24
Peak memory 200328 kb
Host smart-0be262ad-afbe-4b9d-9b45-199ad9298b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476784058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1476784058
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.4274804328
Short name T359
Test name
Test status
Simulation time 1154228953 ps
CPU time 9.58 seconds
Started Jul 06 07:11:48 PM PDT 24
Finished Jul 06 07:11:58 PM PDT 24
Peak memory 200328 kb
Host smart-a0c63073-f777-4cca-9524-85a8642c6581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274804328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.4274804328
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1880164624
Short name T76
Test name
Test status
Simulation time 76005325777 ps
CPU time 2022.02 seconds
Started Jul 06 07:11:52 PM PDT 24
Finished Jul 06 07:45:36 PM PDT 24
Peak memory 755980 kb
Host smart-11fda9b2-ae5e-4952-8c41-07094c424226
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880164624 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1880164624
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2453911440
Short name T261
Test name
Test status
Simulation time 2036279717 ps
CPU time 19.2 seconds
Started Jul 06 07:11:55 PM PDT 24
Finished Jul 06 07:12:15 PM PDT 24
Peak memory 200300 kb
Host smart-f15d533c-d6e7-4805-8d50-741996b87c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453911440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2453911440
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.3716792523
Short name T127
Test name
Test status
Simulation time 16309691 ps
CPU time 0.62 seconds
Started Jul 06 07:11:57 PM PDT 24
Finished Jul 06 07:11:58 PM PDT 24
Peak memory 196128 kb
Host smart-939e3862-13da-45bb-9c5e-97f4fcad477c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716792523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.3716792523
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.422113451
Short name T162
Test name
Test status
Simulation time 2978921261 ps
CPU time 13.49 seconds
Started Jul 06 07:11:53 PM PDT 24
Finished Jul 06 07:12:08 PM PDT 24
Peak memory 200368 kb
Host smart-6f1f1142-7515-46e3-885a-489873e84757
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=422113451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.422113451
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3497473041
Short name T479
Test name
Test status
Simulation time 1631124385 ps
CPU time 31.31 seconds
Started Jul 06 07:11:59 PM PDT 24
Finished Jul 06 07:12:32 PM PDT 24
Peak memory 200320 kb
Host smart-64e95635-48b7-4323-8aef-cd2a44d63de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497473041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3497473041
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1291716584
Short name T245
Test name
Test status
Simulation time 6327123268 ps
CPU time 1242.35 seconds
Started Jul 06 07:11:54 PM PDT 24
Finished Jul 06 07:32:37 PM PDT 24
Peak memory 686028 kb
Host smart-a96e48f5-2407-4c54-aa60-d8fe7dfc9608
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1291716584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1291716584
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.1182938113
Short name T365
Test name
Test status
Simulation time 1811302386 ps
CPU time 49.94 seconds
Started Jul 06 07:11:58 PM PDT 24
Finished Jul 06 07:12:49 PM PDT 24
Peak memory 200248 kb
Host smart-0c1a6935-93ea-4288-b42e-79e2e635a2b1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182938113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1182938113
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.993861673
Short name T47
Test name
Test status
Simulation time 3766452722 ps
CPU time 46.43 seconds
Started Jul 06 07:11:54 PM PDT 24
Finished Jul 06 07:12:41 PM PDT 24
Peak memory 200404 kb
Host smart-26990fa0-eb7a-4534-98dd-d5524f5337f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993861673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.993861673
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1884206974
Short name T407
Test name
Test status
Simulation time 199389351 ps
CPU time 9.27 seconds
Started Jul 06 07:11:53 PM PDT 24
Finished Jul 06 07:12:03 PM PDT 24
Peak memory 200304 kb
Host smart-00a9cfb2-aece-47ef-a3aa-e8c250022618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884206974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1884206974
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1489828164
Short name T229
Test name
Test status
Simulation time 15120797254 ps
CPU time 2044.52 seconds
Started Jul 06 07:11:57 PM PDT 24
Finished Jul 06 07:46:03 PM PDT 24
Peak memory 777948 kb
Host smart-f43c08aa-a022-422b-ba76-2b4491834826
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489828164 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1489828164
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.661267195
Short name T384
Test name
Test status
Simulation time 24254738510 ps
CPU time 76.07 seconds
Started Jul 06 07:11:57 PM PDT 24
Finished Jul 06 07:13:14 PM PDT 24
Peak memory 200388 kb
Host smart-b2e7f602-3c7f-4102-8f73-1c25d5811b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661267195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.661267195
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.378387016
Short name T254
Test name
Test status
Simulation time 26629364 ps
CPU time 0.59 seconds
Started Jul 06 07:10:58 PM PDT 24
Finished Jul 06 07:10:59 PM PDT 24
Peak memory 195160 kb
Host smart-2ecdd52a-b7b8-4cc4-9055-f3ebcbc76011
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378387016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.378387016
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.4094210697
Short name T461
Test name
Test status
Simulation time 2758714236 ps
CPU time 86.43 seconds
Started Jul 06 07:10:54 PM PDT 24
Finished Jul 06 07:12:22 PM PDT 24
Peak memory 200328 kb
Host smart-856f762a-f00a-4762-8f4e-3138ebc16aff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4094210697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.4094210697
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3235466265
Short name T490
Test name
Test status
Simulation time 23319426478 ps
CPU time 21.72 seconds
Started Jul 06 07:11:00 PM PDT 24
Finished Jul 06 07:11:23 PM PDT 24
Peak memory 216664 kb
Host smart-6d678404-c4d0-41d0-928d-2856a95a1537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235466265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3235466265
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3367895721
Short name T452
Test name
Test status
Simulation time 5315579260 ps
CPU time 941.55 seconds
Started Jul 06 07:10:55 PM PDT 24
Finished Jul 06 07:26:38 PM PDT 24
Peak memory 725408 kb
Host smart-950649d3-52d2-4112-9aa6-977634ae016b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3367895721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3367895721
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.180275032
Short name T282
Test name
Test status
Simulation time 70307732777 ps
CPU time 143.55 seconds
Started Jul 06 07:10:55 PM PDT 24
Finished Jul 06 07:13:20 PM PDT 24
Peak memory 200316 kb
Host smart-60d2fa96-065c-4cd1-8a33-78296844003e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180275032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.180275032
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.608208332
Short name T122
Test name
Test status
Simulation time 5993315764 ps
CPU time 109.73 seconds
Started Jul 06 07:10:54 PM PDT 24
Finished Jul 06 07:12:44 PM PDT 24
Peak memory 200344 kb
Host smart-7e1f8302-b3fb-42ea-b15e-9f4a7b579ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608208332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.608208332
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1815919879
Short name T41
Test name
Test status
Simulation time 389729174 ps
CPU time 0.91 seconds
Started Jul 06 07:10:57 PM PDT 24
Finished Jul 06 07:10:59 PM PDT 24
Peak memory 218272 kb
Host smart-fdb4b4c2-a998-49bf-9419-c091ff433684
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815919879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1815919879
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.1116731878
Short name T150
Test name
Test status
Simulation time 1672679242 ps
CPU time 5.57 seconds
Started Jul 06 07:10:54 PM PDT 24
Finished Jul 06 07:11:01 PM PDT 24
Peak memory 200292 kb
Host smart-808ad730-9369-47a9-8a13-03be9b195e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116731878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1116731878
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.70489464
Short name T420
Test name
Test status
Simulation time 19856671679 ps
CPU time 252.1 seconds
Started Jul 06 07:10:55 PM PDT 24
Finished Jul 06 07:15:08 PM PDT 24
Peak memory 216744 kb
Host smart-f4debfda-61ce-42c2-8d51-a31c6d06ca9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70489464 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.70489464
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.1316625436
Short name T234
Test name
Test status
Simulation time 6858787271 ps
CPU time 73.75 seconds
Started Jul 06 07:10:58 PM PDT 24
Finished Jul 06 07:12:12 PM PDT 24
Peak memory 200404 kb
Host smart-0679c495-026d-4be6-92d4-64390d4290b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1316625436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.1316625436
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.1617388484
Short name T242
Test name
Test status
Simulation time 6140731612 ps
CPU time 77.15 seconds
Started Jul 06 07:10:54 PM PDT 24
Finished Jul 06 07:12:13 PM PDT 24
Peak memory 200296 kb
Host smart-b2e1ebd6-04f3-45c5-9b4e-ca11d06b5c60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1617388484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.1617388484
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.1392607612
Short name T140
Test name
Test status
Simulation time 8352305231 ps
CPU time 138.37 seconds
Started Jul 06 07:10:55 PM PDT 24
Finished Jul 06 07:13:15 PM PDT 24
Peak memory 200388 kb
Host smart-fd6e00c0-20ed-4d1f-99e6-1981b9393b48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1392607612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.1392607612
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.3248180141
Short name T170
Test name
Test status
Simulation time 37853639300 ps
CPU time 633.69 seconds
Started Jul 06 07:10:54 PM PDT 24
Finished Jul 06 07:21:28 PM PDT 24
Peak memory 200372 kb
Host smart-3439015a-5ebe-4cbb-ba59-733c6b78bbd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3248180141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3248180141
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.254876392
Short name T227
Test name
Test status
Simulation time 40805888053 ps
CPU time 2170.53 seconds
Started Jul 06 07:10:57 PM PDT 24
Finished Jul 06 07:47:08 PM PDT 24
Peak memory 215944 kb
Host smart-421765f1-8bb1-433c-8c7e-a42276152877
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=254876392 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.254876392
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3101708225
Short name T307
Test name
Test status
Simulation time 1696728822 ps
CPU time 76.66 seconds
Started Jul 06 07:10:56 PM PDT 24
Finished Jul 06 07:12:13 PM PDT 24
Peak memory 200260 kb
Host smart-bc888816-b77c-4ca2-9687-4ecd0d1a4928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101708225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3101708225
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2065049175
Short name T102
Test name
Test status
Simulation time 119110458 ps
CPU time 7.74 seconds
Started Jul 06 07:11:56 PM PDT 24
Finished Jul 06 07:12:04 PM PDT 24
Peak memory 200320 kb
Host smart-5d84ca17-bdda-4f02-8b83-7013eb3de41c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2065049175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2065049175
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2946427866
Short name T50
Test name
Test status
Simulation time 1047948678 ps
CPU time 4 seconds
Started Jul 06 07:12:06 PM PDT 24
Finished Jul 06 07:12:11 PM PDT 24
Peak memory 200244 kb
Host smart-79c7e1e5-5f0d-4a0a-8c67-c820f637c127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946427866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2946427866
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.340659240
Short name T266
Test name
Test status
Simulation time 4665700820 ps
CPU time 940.88 seconds
Started Jul 06 07:11:57 PM PDT 24
Finished Jul 06 07:27:39 PM PDT 24
Peak memory 727804 kb
Host smart-fa213b9b-7ce5-427a-8a7d-f9e35ab0c67b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=340659240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.340659240
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3616313055
Short name T506
Test name
Test status
Simulation time 17481429058 ps
CPU time 221.54 seconds
Started Jul 06 07:12:12 PM PDT 24
Finished Jul 06 07:15:55 PM PDT 24
Peak memory 200344 kb
Host smart-71ba9541-26e6-40f6-833a-021169a86608
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616313055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3616313055
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1029309037
Short name T370
Test name
Test status
Simulation time 8950280439 ps
CPU time 124.45 seconds
Started Jul 06 07:12:06 PM PDT 24
Finished Jul 06 07:14:12 PM PDT 24
Peak memory 216640 kb
Host smart-e02da38c-9dc8-470e-8f38-4cd2452ac4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029309037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1029309037
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3910462257
Short name T459
Test name
Test status
Simulation time 171758581 ps
CPU time 3.53 seconds
Started Jul 06 07:11:57 PM PDT 24
Finished Jul 06 07:12:01 PM PDT 24
Peak memory 200300 kb
Host smart-1e455269-b534-472a-8f82-8281809795a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910462257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3910462257
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2877769385
Short name T415
Test name
Test status
Simulation time 43961991702 ps
CPU time 605.54 seconds
Started Jul 06 07:12:07 PM PDT 24
Finished Jul 06 07:22:13 PM PDT 24
Peak memory 216728 kb
Host smart-387db716-8715-4ce3-ac13-b349d45e04ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877769385 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2877769385
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1134189794
Short name T392
Test name
Test status
Simulation time 10065336042 ps
CPU time 124.85 seconds
Started Jul 06 07:12:12 PM PDT 24
Finished Jul 06 07:14:18 PM PDT 24
Peak memory 200200 kb
Host smart-1d8ac0ef-52b3-49ea-9397-35c2681a52b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134189794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1134189794
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.729089774
Short name T199
Test name
Test status
Simulation time 79737146 ps
CPU time 0.6 seconds
Started Jul 06 07:12:10 PM PDT 24
Finished Jul 06 07:12:12 PM PDT 24
Peak memory 195160 kb
Host smart-3f67b794-9cf5-423f-8778-fa46cf6906ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729089774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.729089774
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.2068368841
Short name T276
Test name
Test status
Simulation time 3059906392 ps
CPU time 45.77 seconds
Started Jul 06 07:12:06 PM PDT 24
Finished Jul 06 07:12:52 PM PDT 24
Peak memory 200324 kb
Host smart-807e3789-8618-4a85-82db-18dbc10c49cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068368841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2068368841
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.4151266418
Short name T509
Test name
Test status
Simulation time 22591327224 ps
CPU time 38.53 seconds
Started Jul 06 07:12:09 PM PDT 24
Finished Jul 06 07:12:49 PM PDT 24
Peak memory 200416 kb
Host smart-481be208-8337-457f-b78f-8cabc16fa141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151266418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.4151266418
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.524321241
Short name T240
Test name
Test status
Simulation time 5954383405 ps
CPU time 1250.43 seconds
Started Jul 06 07:12:09 PM PDT 24
Finished Jul 06 07:33:01 PM PDT 24
Peak memory 758656 kb
Host smart-48e4999f-c6da-473f-9c10-db70109186d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=524321241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.524321241
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1346428174
Short name T18
Test name
Test status
Simulation time 2683249299 ps
CPU time 17.38 seconds
Started Jul 06 07:12:09 PM PDT 24
Finished Jul 06 07:12:28 PM PDT 24
Peak memory 200260 kb
Host smart-cb87f45e-765b-42de-9541-12b168190f76
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346428174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1346428174
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.3973307227
Short name T173
Test name
Test status
Simulation time 14957213305 ps
CPU time 211.09 seconds
Started Jul 06 07:12:08 PM PDT 24
Finished Jul 06 07:15:40 PM PDT 24
Peak memory 216824 kb
Host smart-a8daeafa-60bc-4c1e-a770-751d944c16d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973307227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3973307227
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.4146660162
Short name T507
Test name
Test status
Simulation time 665905039 ps
CPU time 8.32 seconds
Started Jul 06 07:12:07 PM PDT 24
Finished Jul 06 07:12:17 PM PDT 24
Peak memory 200304 kb
Host smart-71bc9486-c3cf-4a9b-a7e2-c5df9f93e5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146660162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.4146660162
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.364701382
Short name T386
Test name
Test status
Simulation time 21832804276 ps
CPU time 1827.21 seconds
Started Jul 06 07:12:08 PM PDT 24
Finished Jul 06 07:42:37 PM PDT 24
Peak memory 702628 kb
Host smart-7530cc72-b080-47cb-9aea-a3639193793a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364701382 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.364701382
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1280955818
Short name T6
Test name
Test status
Simulation time 2551638558 ps
CPU time 122.04 seconds
Started Jul 06 07:12:11 PM PDT 24
Finished Jul 06 07:14:14 PM PDT 24
Peak memory 200400 kb
Host smart-b456c2ab-c7d9-40ef-8cce-b3de2991fda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280955818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1280955818
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2146343746
Short name T16
Test name
Test status
Simulation time 14372493 ps
CPU time 0.6 seconds
Started Jul 06 07:12:15 PM PDT 24
Finished Jul 06 07:12:18 PM PDT 24
Peak memory 195856 kb
Host smart-0aa01a21-f4b3-4e30-a049-e36afca2020d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146343746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2146343746
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2354275457
Short name T105
Test name
Test status
Simulation time 1092279228 ps
CPU time 57.98 seconds
Started Jul 06 07:12:12 PM PDT 24
Finished Jul 06 07:13:11 PM PDT 24
Peak memory 200340 kb
Host smart-62c09503-2acd-42ec-a68b-399332542567
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2354275457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2354275457
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1915200896
Short name T454
Test name
Test status
Simulation time 1061825802 ps
CPU time 19.85 seconds
Started Jul 06 07:12:15 PM PDT 24
Finished Jul 06 07:12:37 PM PDT 24
Peak memory 200320 kb
Host smart-e396cdad-65d3-4b85-8c78-b7f6f53f8f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915200896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1915200896
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.1979520449
Short name T247
Test name
Test status
Simulation time 15485038051 ps
CPU time 714.58 seconds
Started Jul 06 07:12:10 PM PDT 24
Finished Jul 06 07:24:06 PM PDT 24
Peak memory 688084 kb
Host smart-5ba8f13e-d3cd-46f3-bff9-13e2a33a91d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1979520449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.1979520449
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2603063106
Short name T411
Test name
Test status
Simulation time 35114792828 ps
CPU time 224.54 seconds
Started Jul 06 07:12:16 PM PDT 24
Finished Jul 06 07:16:04 PM PDT 24
Peak memory 200344 kb
Host smart-24858e9a-c7b1-4332-9c52-e24c9e990f38
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603063106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2603063106
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3856237242
Short name T302
Test name
Test status
Simulation time 37512765812 ps
CPU time 167.2 seconds
Started Jul 06 07:12:09 PM PDT 24
Finished Jul 06 07:14:58 PM PDT 24
Peak memory 216736 kb
Host smart-23b6b500-fd51-413c-8b2a-fd42afd6bac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856237242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3856237242
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.3778169804
Short name T178
Test name
Test status
Simulation time 144143043 ps
CPU time 6.39 seconds
Started Jul 06 07:12:09 PM PDT 24
Finished Jul 06 07:12:17 PM PDT 24
Peak memory 200292 kb
Host smart-74aa791d-4f59-46dc-8825-c4435d46abc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778169804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.3778169804
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1881637013
Short name T37
Test name
Test status
Simulation time 24876098202 ps
CPU time 275.28 seconds
Started Jul 06 07:12:16 PM PDT 24
Finished Jul 06 07:16:54 PM PDT 24
Peak memory 200416 kb
Host smart-033e5a5b-5f5e-4584-a2b7-8b08ca011904
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881637013 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1881637013
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2105783569
Short name T226
Test name
Test status
Simulation time 3328300907 ps
CPU time 38.83 seconds
Started Jul 06 07:12:15 PM PDT 24
Finished Jul 06 07:12:55 PM PDT 24
Peak memory 200360 kb
Host smart-2994ea04-a5c7-4bd0-88d7-52895e19b49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105783569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2105783569
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.788399874
Short name T525
Test name
Test status
Simulation time 11540727 ps
CPU time 0.57 seconds
Started Jul 06 07:12:21 PM PDT 24
Finished Jul 06 07:12:23 PM PDT 24
Peak memory 195768 kb
Host smart-2d834d30-b0b7-4998-bef5-7ccd8d0f605e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788399874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.788399874
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2032291314
Short name T373
Test name
Test status
Simulation time 1458224279 ps
CPU time 87.46 seconds
Started Jul 06 07:12:16 PM PDT 24
Finished Jul 06 07:13:46 PM PDT 24
Peak memory 200300 kb
Host smart-29e7bcb4-e6a2-4f1d-b826-90be91e297dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2032291314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2032291314
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1504059495
Short name T476
Test name
Test status
Simulation time 2123190334 ps
CPU time 29.25 seconds
Started Jul 06 07:12:20 PM PDT 24
Finished Jul 06 07:12:50 PM PDT 24
Peak memory 200332 kb
Host smart-fdfc54c7-a406-4225-99a9-6bb6f15bc349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504059495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1504059495
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.208296057
Short name T121
Test name
Test status
Simulation time 3693203961 ps
CPU time 727.02 seconds
Started Jul 06 07:12:16 PM PDT 24
Finished Jul 06 07:24:26 PM PDT 24
Peak memory 753956 kb
Host smart-3546e424-ef00-4a55-acc8-f8630df3a9ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=208296057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.208296057
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3826341628
Short name T520
Test name
Test status
Simulation time 5008734074 ps
CPU time 136.67 seconds
Started Jul 06 07:12:21 PM PDT 24
Finished Jul 06 07:14:38 PM PDT 24
Peak memory 200260 kb
Host smart-5f225440-9825-4791-ade0-cb9bb1738d4e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826341628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3826341628
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1577406727
Short name T357
Test name
Test status
Simulation time 147334347 ps
CPU time 0.97 seconds
Started Jul 06 07:12:18 PM PDT 24
Finished Jul 06 07:12:21 PM PDT 24
Peak memory 199336 kb
Host smart-6664c58d-0f02-49f7-a32f-02afb6db4c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577406727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1577406727
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.354719498
Short name T331
Test name
Test status
Simulation time 548472077 ps
CPU time 11.73 seconds
Started Jul 06 07:12:15 PM PDT 24
Finished Jul 06 07:12:29 PM PDT 24
Peak memory 200268 kb
Host smart-67229755-1894-41ef-a5ea-7396cd0984ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354719498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.354719498
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3387098754
Short name T496
Test name
Test status
Simulation time 140418506985 ps
CPU time 444.81 seconds
Started Jul 06 07:12:21 PM PDT 24
Finished Jul 06 07:19:47 PM PDT 24
Peak memory 200376 kb
Host smart-a6a4f4cb-d654-4589-8c2d-f3c294bf70d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387098754 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3387098754
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3890301653
Short name T299
Test name
Test status
Simulation time 2431152306 ps
CPU time 23.17 seconds
Started Jul 06 07:12:22 PM PDT 24
Finished Jul 06 07:12:46 PM PDT 24
Peak memory 200336 kb
Host smart-d950bca0-73dd-44b1-995d-3bd46a5c48b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890301653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3890301653
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.895048138
Short name T67
Test name
Test status
Simulation time 46696049 ps
CPU time 0.6 seconds
Started Jul 06 07:12:31 PM PDT 24
Finished Jul 06 07:12:32 PM PDT 24
Peak memory 196188 kb
Host smart-69e734ab-1bff-4ad9-a7c8-78b105f28ab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895048138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.895048138
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.859905921
Short name T191
Test name
Test status
Simulation time 2469484365 ps
CPU time 36.21 seconds
Started Jul 06 07:12:27 PM PDT 24
Finished Jul 06 07:13:04 PM PDT 24
Peak memory 200336 kb
Host smart-4bedaee2-4bc7-453e-b1d2-f4d923432c38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=859905921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.859905921
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1568579774
Short name T487
Test name
Test status
Simulation time 5907730250 ps
CPU time 46.75 seconds
Started Jul 06 07:12:26 PM PDT 24
Finished Jul 06 07:13:14 PM PDT 24
Peak memory 200360 kb
Host smart-5befdc02-2b52-43f6-a859-1aa4f92c07f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568579774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1568579774
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3990471185
Short name T148
Test name
Test status
Simulation time 12226941427 ps
CPU time 506.8 seconds
Started Jul 06 07:12:27 PM PDT 24
Finished Jul 06 07:20:55 PM PDT 24
Peak memory 633604 kb
Host smart-c7f81003-6a37-485e-86c6-7d0c35aa67d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3990471185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3990471185
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3198783688
Short name T449
Test name
Test status
Simulation time 1951322521 ps
CPU time 17.95 seconds
Started Jul 06 07:12:26 PM PDT 24
Finished Jul 06 07:12:46 PM PDT 24
Peak memory 200304 kb
Host smart-2dbf2882-a73e-4bec-bd58-b8bf5577193f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198783688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3198783688
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2959581240
Short name T337
Test name
Test status
Simulation time 179996133985 ps
CPU time 201.33 seconds
Started Jul 06 07:12:27 PM PDT 24
Finished Jul 06 07:15:50 PM PDT 24
Peak memory 200380 kb
Host smart-5b350856-e597-4f96-8e16-b5f08bbdc484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959581240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2959581240
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.905499317
Short name T379
Test name
Test status
Simulation time 57537876 ps
CPU time 1.34 seconds
Started Jul 06 07:12:26 PM PDT 24
Finished Jul 06 07:12:29 PM PDT 24
Peak memory 200324 kb
Host smart-806ca950-ebd2-49c7-916e-cc038e6bbd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905499317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.905499317
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.1008136536
Short name T64
Test name
Test status
Simulation time 231731145783 ps
CPU time 4578.76 seconds
Started Jul 06 07:12:26 PM PDT 24
Finished Jul 06 08:28:47 PM PDT 24
Peak memory 815208 kb
Host smart-bfd3fbff-58e5-4e20-ba82-890e323fbc86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008136536 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.1008136536
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1170863539
Short name T321
Test name
Test status
Simulation time 15521030688 ps
CPU time 94.67 seconds
Started Jul 06 07:12:28 PM PDT 24
Finished Jul 06 07:14:04 PM PDT 24
Peak memory 200404 kb
Host smart-3b3e8860-bc4e-4600-963c-f00da8cbac9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170863539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1170863539
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3809914806
Short name T298
Test name
Test status
Simulation time 13223458 ps
CPU time 0.62 seconds
Started Jul 06 07:12:38 PM PDT 24
Finished Jul 06 07:12:40 PM PDT 24
Peak memory 196868 kb
Host smart-a2423d44-3e12-4126-a833-236e3a134a19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809914806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3809914806
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1122749933
Short name T349
Test name
Test status
Simulation time 1504481869 ps
CPU time 88.91 seconds
Started Jul 06 07:12:33 PM PDT 24
Finished Jul 06 07:14:03 PM PDT 24
Peak memory 200332 kb
Host smart-4694f489-e221-4f26-ab2d-12c5b5376650
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1122749933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1122749933
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3411458828
Short name T165
Test name
Test status
Simulation time 2411704458 ps
CPU time 46.46 seconds
Started Jul 06 07:12:32 PM PDT 24
Finished Jul 06 07:13:19 PM PDT 24
Peak memory 200308 kb
Host smart-0868969b-1f21-41a2-a1a6-a4187dc16881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411458828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3411458828
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1683591979
Short name T483
Test name
Test status
Simulation time 1789405282 ps
CPU time 159.9 seconds
Started Jul 06 07:12:33 PM PDT 24
Finished Jul 06 07:15:14 PM PDT 24
Peak memory 578084 kb
Host smart-270725c2-45ef-4fc7-b6ed-5999f112adfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1683591979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1683591979
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.1366658398
Short name T448
Test name
Test status
Simulation time 57174273346 ps
CPU time 132.51 seconds
Started Jul 06 07:12:33 PM PDT 24
Finished Jul 06 07:14:46 PM PDT 24
Peak memory 200348 kb
Host smart-172bf303-b48a-4f59-b4e1-7ee409e3edbe
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366658398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1366658398
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.520106366
Short name T323
Test name
Test status
Simulation time 769920935 ps
CPU time 21.42 seconds
Started Jul 06 07:12:34 PM PDT 24
Finished Jul 06 07:12:57 PM PDT 24
Peak memory 200276 kb
Host smart-a8498abc-1bdb-49ff-8d49-baa0f017ef77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520106366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.520106366
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3957658610
Short name T482
Test name
Test status
Simulation time 89484580 ps
CPU time 3.36 seconds
Started Jul 06 07:12:32 PM PDT 24
Finished Jul 06 07:12:36 PM PDT 24
Peak memory 200268 kb
Host smart-ddddfed2-2b22-4f4e-9b63-25786fb7b216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957658610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3957658610
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.359449705
Short name T318
Test name
Test status
Simulation time 21689948478 ps
CPU time 2700.36 seconds
Started Jul 06 07:12:37 PM PDT 24
Finished Jul 06 07:57:39 PM PDT 24
Peak memory 775236 kb
Host smart-fa419687-dfb2-4204-a4a8-9ed323ed20c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359449705 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.359449705
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.4272545925
Short name T521
Test name
Test status
Simulation time 2644497989 ps
CPU time 50.38 seconds
Started Jul 06 07:12:37 PM PDT 24
Finished Jul 06 07:13:29 PM PDT 24
Peak memory 200388 kb
Host smart-8fce435a-49dc-44cd-a777-9f635806703b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272545925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.4272545925
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1245795524
Short name T52
Test name
Test status
Simulation time 21068586 ps
CPU time 0.6 seconds
Started Jul 06 07:12:43 PM PDT 24
Finished Jul 06 07:12:44 PM PDT 24
Peak memory 196204 kb
Host smart-081cac78-33b2-4773-9589-10c7095dd98f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245795524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1245795524
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3155511955
Short name T499
Test name
Test status
Simulation time 1234917219 ps
CPU time 69.51 seconds
Started Jul 06 07:12:38 PM PDT 24
Finished Jul 06 07:13:49 PM PDT 24
Peak memory 200312 kb
Host smart-44762686-2a09-4db6-84d5-6a3ff3d6abc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3155511955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3155511955
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.641546970
Short name T31
Test name
Test status
Simulation time 15603446434 ps
CPU time 49.72 seconds
Started Jul 06 07:12:37 PM PDT 24
Finished Jul 06 07:13:27 PM PDT 24
Peak memory 200336 kb
Host smart-9edda628-abce-4542-8ff6-a67b90cc900a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641546970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.641546970
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1172470967
Short name T333
Test name
Test status
Simulation time 19480719938 ps
CPU time 945.33 seconds
Started Jul 06 07:12:37 PM PDT 24
Finished Jul 06 07:28:24 PM PDT 24
Peak memory 678528 kb
Host smart-e8edbf55-175d-4f91-9ea1-6815dee06fb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1172470967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1172470967
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.1038362002
Short name T390
Test name
Test status
Simulation time 5677425050 ps
CPU time 76.76 seconds
Started Jul 06 07:12:38 PM PDT 24
Finished Jul 06 07:13:56 PM PDT 24
Peak memory 200356 kb
Host smart-c2f50286-b59b-4cc1-95fd-3042f3cda965
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038362002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1038362002
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1729638119
Short name T166
Test name
Test status
Simulation time 1881027574 ps
CPU time 26.86 seconds
Started Jul 06 07:12:37 PM PDT 24
Finished Jul 06 07:13:06 PM PDT 24
Peak memory 200316 kb
Host smart-954d024d-ff31-4ebd-92f5-c359c3622cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729638119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1729638119
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2400202329
Short name T489
Test name
Test status
Simulation time 902166731 ps
CPU time 4.08 seconds
Started Jul 06 07:12:38 PM PDT 24
Finished Jul 06 07:12:43 PM PDT 24
Peak memory 200304 kb
Host smart-e7c6de65-0374-4a2a-9101-a66f3dc8f4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400202329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2400202329
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.4063750324
Short name T21
Test name
Test status
Simulation time 34268248514 ps
CPU time 475.37 seconds
Started Jul 06 07:12:38 PM PDT 24
Finished Jul 06 07:20:34 PM PDT 24
Peak memory 200348 kb
Host smart-f6e9f9ae-ce87-48ff-b0dc-54f68a662df6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063750324 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.4063750324
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2358802611
Short name T347
Test name
Test status
Simulation time 5045013878 ps
CPU time 136.71 seconds
Started Jul 06 07:12:38 PM PDT 24
Finished Jul 06 07:14:56 PM PDT 24
Peak memory 200308 kb
Host smart-5db8dd26-851c-49f5-8e45-afc9ff1bc99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358802611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2358802611
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.4268545791
Short name T510
Test name
Test status
Simulation time 16561598 ps
CPU time 0.64 seconds
Started Jul 06 07:12:48 PM PDT 24
Finished Jul 06 07:12:49 PM PDT 24
Peak memory 196200 kb
Host smart-e63900bb-89e2-4fcc-8558-ec8f2df9fbd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268545791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.4268545791
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.439903295
Short name T447
Test name
Test status
Simulation time 2164895412 ps
CPU time 33.61 seconds
Started Jul 06 07:12:43 PM PDT 24
Finished Jul 06 07:13:17 PM PDT 24
Peak memory 200412 kb
Host smart-f8066713-7738-4e0e-8ed8-ce66daa68129
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=439903295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.439903295
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2845163167
Short name T368
Test name
Test status
Simulation time 6706834290 ps
CPU time 46.33 seconds
Started Jul 06 07:12:51 PM PDT 24
Finished Jul 06 07:13:38 PM PDT 24
Peak memory 200428 kb
Host smart-ae4b6aba-4903-429e-b2d3-4168623f4519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845163167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2845163167
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1654576479
Short name T429
Test name
Test status
Simulation time 18754285679 ps
CPU time 2184.51 seconds
Started Jul 06 07:12:45 PM PDT 24
Finished Jul 06 07:49:10 PM PDT 24
Peak memory 765488 kb
Host smart-194019e1-c6c9-47d3-bab2-6e69955b409f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1654576479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1654576479
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3581443773
Short name T25
Test name
Test status
Simulation time 10738598503 ps
CPU time 46.21 seconds
Started Jul 06 07:12:48 PM PDT 24
Finished Jul 06 07:13:35 PM PDT 24
Peak memory 200384 kb
Host smart-66c59d72-496c-4052-acae-7f5d807a1cec
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581443773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3581443773
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3171202283
Short name T237
Test name
Test status
Simulation time 1454491640 ps
CPU time 23.56 seconds
Started Jul 06 07:12:43 PM PDT 24
Finished Jul 06 07:13:07 PM PDT 24
Peak memory 200316 kb
Host smart-412ef31f-ed47-481f-a086-457deb13937f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171202283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3171202283
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3461711943
Short name T153
Test name
Test status
Simulation time 2270607706 ps
CPU time 11.38 seconds
Started Jul 06 07:12:42 PM PDT 24
Finished Jul 06 07:12:54 PM PDT 24
Peak memory 200364 kb
Host smart-280e6ddc-41bc-4740-9b69-8744cc03f6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461711943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3461711943
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.238490127
Short name T399
Test name
Test status
Simulation time 182412022166 ps
CPU time 1599.41 seconds
Started Jul 06 07:12:48 PM PDT 24
Finished Jul 06 07:39:29 PM PDT 24
Peak memory 718540 kb
Host smart-41a15fa3-acf5-4617-a34b-567e489e3b42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238490127 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.238490127
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2024130451
Short name T319
Test name
Test status
Simulation time 10934289480 ps
CPU time 97.42 seconds
Started Jul 06 07:12:49 PM PDT 24
Finished Jul 06 07:14:27 PM PDT 24
Peak memory 200428 kb
Host smart-30392ee4-97f7-4d79-aaa2-8f3d4086a7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024130451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2024130451
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2502635305
Short name T287
Test name
Test status
Simulation time 23539061 ps
CPU time 0.6 seconds
Started Jul 06 07:12:55 PM PDT 24
Finished Jul 06 07:12:57 PM PDT 24
Peak memory 195992 kb
Host smart-3a509095-d4b6-4e9c-b309-44bc45caa79d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502635305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2502635305
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2696498296
Short name T456
Test name
Test status
Simulation time 447437116 ps
CPU time 21.43 seconds
Started Jul 06 07:12:48 PM PDT 24
Finished Jul 06 07:13:11 PM PDT 24
Peak memory 200304 kb
Host smart-2a6692d6-5e93-4f8d-87d5-0b39e2ce3879
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2696498296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2696498296
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1464507247
Short name T288
Test name
Test status
Simulation time 2179999385 ps
CPU time 58.91 seconds
Started Jul 06 07:12:49 PM PDT 24
Finished Jul 06 07:13:49 PM PDT 24
Peak memory 200384 kb
Host smart-3f03a39d-8b8a-4642-937d-c3fe037b2904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464507247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1464507247
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3871060490
Short name T464
Test name
Test status
Simulation time 830804392 ps
CPU time 29.37 seconds
Started Jul 06 07:12:51 PM PDT 24
Finished Jul 06 07:13:21 PM PDT 24
Peak memory 253808 kb
Host smart-ee8e01a3-2416-4a4d-a13c-132921ba0fb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3871060490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3871060490
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1994172342
Short name T246
Test name
Test status
Simulation time 37600008888 ps
CPU time 149.11 seconds
Started Jul 06 07:12:57 PM PDT 24
Finished Jul 06 07:15:28 PM PDT 24
Peak memory 200388 kb
Host smart-f6107df0-5695-4e16-bcc5-e161c4037e76
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994172342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1994172342
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1973747614
Short name T528
Test name
Test status
Simulation time 19476941097 ps
CPU time 183.09 seconds
Started Jul 06 07:12:47 PM PDT 24
Finished Jul 06 07:15:51 PM PDT 24
Peak memory 200408 kb
Host smart-ce8d3765-28af-4f63-a641-92a723e90f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973747614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1973747614
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3242563807
Short name T228
Test name
Test status
Simulation time 806092031 ps
CPU time 9.02 seconds
Started Jul 06 07:12:48 PM PDT 24
Finished Jul 06 07:12:58 PM PDT 24
Peak memory 200320 kb
Host smart-6d342cda-f416-46ac-bac8-41d1d33157f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242563807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3242563807
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.1786085132
Short name T103
Test name
Test status
Simulation time 4479425515 ps
CPU time 91.05 seconds
Started Jul 06 07:12:56 PM PDT 24
Finished Jul 06 07:14:29 PM PDT 24
Peak memory 200280 kb
Host smart-c71748de-8e01-4e82-9d75-8a8e1f8fc3df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786085132 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.1786085132
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2835362820
Short name T329
Test name
Test status
Simulation time 3874295328 ps
CPU time 91.78 seconds
Started Jul 06 07:12:54 PM PDT 24
Finished Jul 06 07:14:27 PM PDT 24
Peak memory 200392 kb
Host smart-8a631616-938e-4e5b-97e6-4c1eb52f2cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835362820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2835362820
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3481898367
Short name T142
Test name
Test status
Simulation time 16336483 ps
CPU time 0.65 seconds
Started Jul 06 07:12:54 PM PDT 24
Finished Jul 06 07:12:55 PM PDT 24
Peak memory 196156 kb
Host smart-592c7a97-8f7c-4cd7-b037-4f9b4ad235d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481898367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3481898367
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1410429608
Short name T212
Test name
Test status
Simulation time 3227872972 ps
CPU time 69.29 seconds
Started Jul 06 07:12:55 PM PDT 24
Finished Jul 06 07:14:05 PM PDT 24
Peak memory 200388 kb
Host smart-51de8364-fb1d-4ac2-ab3c-a193dfd1e21b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1410429608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1410429608
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.920715626
Short name T473
Test name
Test status
Simulation time 1859358808 ps
CPU time 25.96 seconds
Started Jul 06 07:12:57 PM PDT 24
Finished Jul 06 07:13:26 PM PDT 24
Peak memory 200376 kb
Host smart-0c0c9ce1-30a2-41a9-9b33-eeed5455151a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920715626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.920715626
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.625881488
Short name T259
Test name
Test status
Simulation time 23073896353 ps
CPU time 1580.15 seconds
Started Jul 06 07:12:56 PM PDT 24
Finished Jul 06 07:39:19 PM PDT 24
Peak memory 782484 kb
Host smart-667b3133-5a54-45e3-ad73-233c1b40c49f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=625881488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.625881488
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.159145918
Short name T284
Test name
Test status
Simulation time 7300692750 ps
CPU time 99.68 seconds
Started Jul 06 07:12:55 PM PDT 24
Finished Jul 06 07:14:36 PM PDT 24
Peak memory 200384 kb
Host smart-8b25d21b-e890-42ec-a379-3645e568969a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159145918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.159145918
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_smoke.2670985246
Short name T24
Test name
Test status
Simulation time 81085317 ps
CPU time 1.75 seconds
Started Jul 06 07:12:55 PM PDT 24
Finished Jul 06 07:12:58 PM PDT 24
Peak memory 200344 kb
Host smart-c34b8947-848c-4d2d-b9ff-2ee0c9187ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670985246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2670985246
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3367479711
Short name T20
Test name
Test status
Simulation time 10381096009 ps
CPU time 553.6 seconds
Started Jul 06 07:12:56 PM PDT 24
Finished Jul 06 07:22:13 PM PDT 24
Peak memory 200356 kb
Host smart-054e3049-03a1-4e08-ac0b-446899683751
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367479711 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3367479711
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2610496927
Short name T207
Test name
Test status
Simulation time 2296904178 ps
CPU time 39.51 seconds
Started Jul 06 07:12:57 PM PDT 24
Finished Jul 06 07:13:39 PM PDT 24
Peak memory 200364 kb
Host smart-ea9c0a7d-d78e-4415-96df-e8adc94c8341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610496927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2610496927
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2489482984
Short name T498
Test name
Test status
Simulation time 32484080 ps
CPU time 0.57 seconds
Started Jul 06 07:11:04 PM PDT 24
Finished Jul 06 07:11:05 PM PDT 24
Peak memory 195196 kb
Host smart-135ee852-ae3b-4570-983b-5ec6efef3b83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489482984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2489482984
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.1003704981
Short name T265
Test name
Test status
Simulation time 172983630 ps
CPU time 10.51 seconds
Started Jul 06 07:10:58 PM PDT 24
Finished Jul 06 07:11:09 PM PDT 24
Peak memory 200296 kb
Host smart-cb615020-a900-4d3b-9a9c-097ff476e62d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1003704981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1003704981
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.366526484
Short name T175
Test name
Test status
Simulation time 35149830254 ps
CPU time 29.24 seconds
Started Jul 06 07:11:03 PM PDT 24
Finished Jul 06 07:11:33 PM PDT 24
Peak memory 200380 kb
Host smart-5f2ae7af-52de-4b36-9d55-179ae3e18a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366526484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.366526484
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.448280339
Short name T257
Test name
Test status
Simulation time 13960679964 ps
CPU time 1558.28 seconds
Started Jul 06 07:11:01 PM PDT 24
Finished Jul 06 07:37:00 PM PDT 24
Peak memory 737376 kb
Host smart-115c1a73-22a8-4370-a465-bef8a8253f04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=448280339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.448280339
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2876718463
Short name T358
Test name
Test status
Simulation time 7156502926 ps
CPU time 101.7 seconds
Started Jul 06 07:11:00 PM PDT 24
Finished Jul 06 07:12:42 PM PDT 24
Peak memory 200308 kb
Host smart-7e93a84a-9e78-4516-a1f5-4f5c9ae9f4fa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876718463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2876718463
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2254717213
Short name T152
Test name
Test status
Simulation time 21082912980 ps
CPU time 52.99 seconds
Started Jul 06 07:11:05 PM PDT 24
Finished Jul 06 07:11:59 PM PDT 24
Peak memory 200408 kb
Host smart-129d2637-4b9b-48d9-bdba-56c462669b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254717213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2254717213
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2252600153
Short name T43
Test name
Test status
Simulation time 183483496 ps
CPU time 0.97 seconds
Started Jul 06 07:11:05 PM PDT 24
Finished Jul 06 07:11:06 PM PDT 24
Peak memory 219388 kb
Host smart-8db46f9c-1e39-43f8-b9a5-35f0e0fb41e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252600153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2252600153
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.4217076492
Short name T215
Test name
Test status
Simulation time 1474280434 ps
CPU time 14.68 seconds
Started Jul 06 07:10:54 PM PDT 24
Finished Jul 06 07:11:10 PM PDT 24
Peak memory 200328 kb
Host smart-f88c7ab5-d608-44b0-a1ab-d8e5e0282f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217076492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.4217076492
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1333629072
Short name T66
Test name
Test status
Simulation time 206002645423 ps
CPU time 1324.25 seconds
Started Jul 06 07:11:02 PM PDT 24
Finished Jul 06 07:33:07 PM PDT 24
Peak memory 521544 kb
Host smart-647d3d66-6bdc-43aa-b360-5bea906f0eaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333629072 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1333629072
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.3774013106
Short name T58
Test name
Test status
Simulation time 39682117171 ps
CPU time 321.07 seconds
Started Jul 06 07:11:00 PM PDT 24
Finished Jul 06 07:16:22 PM PDT 24
Peak memory 208640 kb
Host smart-84e67888-b523-4f76-b136-5f171d04588e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3774013106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.3774013106
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.518391996
Short name T468
Test name
Test status
Simulation time 22952183560 ps
CPU time 75.59 seconds
Started Jul 06 07:11:02 PM PDT 24
Finished Jul 06 07:12:18 PM PDT 24
Peak memory 200364 kb
Host smart-ef77f649-b2c9-475f-87ee-a554d98aa3cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=518391996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.518391996
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.2221660143
Short name T508
Test name
Test status
Simulation time 9577299811 ps
CPU time 98.56 seconds
Started Jul 06 07:11:00 PM PDT 24
Finished Jul 06 07:12:40 PM PDT 24
Peak memory 200388 kb
Host smart-bcf78652-6e33-49b5-bf1a-e9e1fb79215a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2221660143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.2221660143
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.874239999
Short name T497
Test name
Test status
Simulation time 23015036475 ps
CPU time 133.63 seconds
Started Jul 06 07:10:59 PM PDT 24
Finished Jul 06 07:13:13 PM PDT 24
Peak memory 200348 kb
Host smart-78b7c2e3-c661-4532-9b54-53be7e8b257e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=874239999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.874239999
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.133521593
Short name T531
Test name
Test status
Simulation time 103382357426 ps
CPU time 661.43 seconds
Started Jul 06 07:11:04 PM PDT 24
Finished Jul 06 07:22:05 PM PDT 24
Peak memory 200384 kb
Host smart-85409849-86f9-4f2d-9337-9aa3e6778648
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=133521593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.133521593
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.515107971
Short name T444
Test name
Test status
Simulation time 928176260857 ps
CPU time 2847.42 seconds
Started Jul 06 07:11:01 PM PDT 24
Finished Jul 06 07:58:30 PM PDT 24
Peak memory 215856 kb
Host smart-9d348b4c-4a7b-47a3-886f-f2711e2a6aa7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=515107971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.515107971
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.1459552519
Short name T422
Test name
Test status
Simulation time 392374106362 ps
CPU time 2693.48 seconds
Started Jul 06 07:11:03 PM PDT 24
Finished Jul 06 07:55:57 PM PDT 24
Peak memory 215920 kb
Host smart-f58e5ccd-3ee9-4bab-b534-5a0a8bfa3085
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1459552519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.1459552519
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2077609242
Short name T248
Test name
Test status
Simulation time 2299280763 ps
CPU time 21.01 seconds
Started Jul 06 07:11:02 PM PDT 24
Finished Jul 06 07:11:24 PM PDT 24
Peak memory 200376 kb
Host smart-97eaf991-8107-4289-a56e-385d7f84a912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077609242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2077609242
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.321472854
Short name T375
Test name
Test status
Simulation time 19480244 ps
CPU time 0.61 seconds
Started Jul 06 07:12:59 PM PDT 24
Finished Jul 06 07:13:02 PM PDT 24
Peak memory 195184 kb
Host smart-62c219dd-e60a-40db-96bf-c244b82ed4b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321472854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.321472854
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1892426656
Short name T74
Test name
Test status
Simulation time 2198434426 ps
CPU time 36.18 seconds
Started Jul 06 07:12:54 PM PDT 24
Finished Jul 06 07:13:31 PM PDT 24
Peak memory 200384 kb
Host smart-de16655c-4a08-4a56-9fd2-79eda0a38048
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1892426656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1892426656
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3234285175
Short name T512
Test name
Test status
Simulation time 1708031210 ps
CPU time 22.37 seconds
Started Jul 06 07:12:59 PM PDT 24
Finished Jul 06 07:13:24 PM PDT 24
Peak memory 200328 kb
Host smart-55c5e253-820e-4e06-bad4-184e39aaf789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234285175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3234285175
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.3319206499
Short name T514
Test name
Test status
Simulation time 13542861882 ps
CPU time 720.9 seconds
Started Jul 06 07:12:55 PM PDT 24
Finished Jul 06 07:24:57 PM PDT 24
Peak memory 686128 kb
Host smart-d29b31b0-1c07-44d8-b4c4-15bcc0ababaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3319206499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.3319206499
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.2627030964
Short name T416
Test name
Test status
Simulation time 1114877616 ps
CPU time 31.1 seconds
Started Jul 06 07:13:01 PM PDT 24
Finished Jul 06 07:13:35 PM PDT 24
Peak memory 200308 kb
Host smart-1791b0b3-6909-44c9-bb58-d04782449337
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627030964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2627030964
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.694429676
Short name T157
Test name
Test status
Simulation time 19084815973 ps
CPU time 59.82 seconds
Started Jul 06 07:12:55 PM PDT 24
Finished Jul 06 07:13:57 PM PDT 24
Peak memory 200100 kb
Host smart-905ef633-ae26-4a2d-82a7-1ca225e8415f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694429676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.694429676
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3220211629
Short name T239
Test name
Test status
Simulation time 1572559353 ps
CPU time 14.21 seconds
Started Jul 06 07:12:56 PM PDT 24
Finished Jul 06 07:13:13 PM PDT 24
Peak memory 200328 kb
Host smart-a79ff386-c1a4-40bd-9adb-34101dcaa45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220211629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3220211629
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3293477782
Short name T376
Test name
Test status
Simulation time 8886055991 ps
CPU time 111.03 seconds
Started Jul 06 07:12:59 PM PDT 24
Finished Jul 06 07:14:53 PM PDT 24
Peak memory 200364 kb
Host smart-414b3ef3-fc75-4cb4-a11a-02ada5edfa14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293477782 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3293477782
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2977037088
Short name T232
Test name
Test status
Simulation time 909489208 ps
CPU time 17.62 seconds
Started Jul 06 07:12:59 PM PDT 24
Finished Jul 06 07:13:19 PM PDT 24
Peak memory 200348 kb
Host smart-b5d47a7d-cbd9-4668-810d-e8cd3e6717a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977037088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2977037088
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1979354202
Short name T395
Test name
Test status
Simulation time 43763650 ps
CPU time 0.59 seconds
Started Jul 06 07:13:05 PM PDT 24
Finished Jul 06 07:13:19 PM PDT 24
Peak memory 195780 kb
Host smart-02976807-65cf-4bc4-8517-7dca7b92a24e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979354202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1979354202
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1655432964
Short name T174
Test name
Test status
Simulation time 124951158 ps
CPU time 1.98 seconds
Started Jul 06 07:13:06 PM PDT 24
Finished Jul 06 07:13:26 PM PDT 24
Peak memory 200324 kb
Host smart-8baa6d73-5794-4088-9130-bd884d36a888
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1655432964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1655432964
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.892023146
Short name T230
Test name
Test status
Simulation time 4600532539 ps
CPU time 46.2 seconds
Started Jul 06 07:14:17 PM PDT 24
Finished Jul 06 07:16:29 PM PDT 24
Peak memory 200328 kb
Host smart-f8a67b7c-d77a-47a9-878e-b829103a311f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892023146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.892023146
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1826370975
Short name T325
Test name
Test status
Simulation time 6395811006 ps
CPU time 1355.99 seconds
Started Jul 06 07:13:03 PM PDT 24
Finished Jul 06 07:35:50 PM PDT 24
Peak memory 756904 kb
Host smart-d415e524-0925-49ce-89c0-d0b7962fd061
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1826370975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1826370975
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3201469713
Short name T53
Test name
Test status
Simulation time 729272585 ps
CPU time 39.44 seconds
Started Jul 06 07:13:06 PM PDT 24
Finished Jul 06 07:14:04 PM PDT 24
Peak memory 200312 kb
Host smart-8b357540-1e70-43f1-862e-8bd603ddfd3e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201469713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3201469713
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.712948403
Short name T1
Test name
Test status
Simulation time 30611774184 ps
CPU time 95.37 seconds
Started Jul 06 07:13:01 PM PDT 24
Finished Jul 06 07:14:41 PM PDT 24
Peak memory 200520 kb
Host smart-98e7b7ab-020e-4409-aff2-b835b7f29de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712948403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.712948403
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.4141777741
Short name T49
Test name
Test status
Simulation time 152284508 ps
CPU time 3.63 seconds
Started Jul 06 07:13:00 PM PDT 24
Finished Jul 06 07:13:07 PM PDT 24
Peak memory 200280 kb
Host smart-98f19d1f-4ecb-4735-b1c4-9513215f1266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141777741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.4141777741
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2395686447
Short name T125
Test name
Test status
Simulation time 240714258166 ps
CPU time 633.28 seconds
Started Jul 06 07:13:07 PM PDT 24
Finished Jul 06 07:24:04 PM PDT 24
Peak memory 216664 kb
Host smart-8cb8b9a8-f9a8-47d5-8e71-cd4ff738f322
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395686447 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2395686447
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1220661293
Short name T458
Test name
Test status
Simulation time 2470911118 ps
CPU time 64.65 seconds
Started Jul 06 07:13:07 PM PDT 24
Finished Jul 06 07:14:36 PM PDT 24
Peak memory 200284 kb
Host smart-55f5f070-e78a-4ecc-85ca-ba16f27ce4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220661293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1220661293
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3423731406
Short name T326
Test name
Test status
Simulation time 14400935 ps
CPU time 0.59 seconds
Started Jul 06 07:13:10 PM PDT 24
Finished Jul 06 07:13:39 PM PDT 24
Peak memory 195164 kb
Host smart-10df44eb-0cd5-4a32-8afa-3871d26384d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423731406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3423731406
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2167696553
Short name T209
Test name
Test status
Simulation time 1975545232 ps
CPU time 27.35 seconds
Started Jul 06 07:13:09 PM PDT 24
Finished Jul 06 07:14:03 PM PDT 24
Peak memory 200292 kb
Host smart-f695beb5-2082-4eff-8c10-ba9df0668253
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2167696553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2167696553
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1973037596
Short name T213
Test name
Test status
Simulation time 13482662262 ps
CPU time 59.47 seconds
Started Jul 06 07:13:09 PM PDT 24
Finished Jul 06 07:14:35 PM PDT 24
Peak memory 200432 kb
Host smart-433aa8f3-9034-4e2a-b34e-2ae28f3dcfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973037596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1973037596
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2602872957
Short name T253
Test name
Test status
Simulation time 2876051140 ps
CPU time 524.48 seconds
Started Jul 06 07:13:11 PM PDT 24
Finished Jul 06 07:22:23 PM PDT 24
Peak memory 721808 kb
Host smart-c7aba70a-8b1b-42e8-a056-807fd0338142
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2602872957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2602872957
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.977372355
Short name T238
Test name
Test status
Simulation time 2782597276 ps
CPU time 161.04 seconds
Started Jul 06 07:13:11 PM PDT 24
Finished Jul 06 07:16:20 PM PDT 24
Peak memory 200300 kb
Host smart-8bdc769a-ccb9-4036-91bc-6a4072ff769f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977372355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.977372355
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.654104146
Short name T271
Test name
Test status
Simulation time 30223617285 ps
CPU time 73.47 seconds
Started Jul 06 07:13:05 PM PDT 24
Finished Jul 06 07:14:35 PM PDT 24
Peak memory 216616 kb
Host smart-7f460dea-9904-4ca6-b353-4018faaa9dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654104146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.654104146
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.440288142
Short name T262
Test name
Test status
Simulation time 461991294 ps
CPU time 11.32 seconds
Started Jul 06 07:13:05 PM PDT 24
Finished Jul 06 07:13:30 PM PDT 24
Peak memory 200304 kb
Host smart-f536a136-b1ae-4224-b492-e390fbb386e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440288142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.440288142
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1504940563
Short name T440
Test name
Test status
Simulation time 15559671525 ps
CPU time 890.17 seconds
Started Jul 06 07:13:10 PM PDT 24
Finished Jul 06 07:28:29 PM PDT 24
Peak memory 696704 kb
Host smart-d8aa7809-41bf-4599-92b2-4b875618d2c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504940563 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1504940563
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.178261143
Short name T48
Test name
Test status
Simulation time 20746354589 ps
CPU time 102.2 seconds
Started Jul 06 07:13:09 PM PDT 24
Finished Jul 06 07:15:18 PM PDT 24
Peak memory 200432 kb
Host smart-bbf6fcb1-8821-4572-9058-e5228548371d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178261143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.178261143
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.3110438341
Short name T272
Test name
Test status
Simulation time 34552325 ps
CPU time 0.58 seconds
Started Jul 06 07:13:27 PM PDT 24
Finished Jul 06 07:13:50 PM PDT 24
Peak memory 195848 kb
Host smart-8e537a2b-0e23-4c7e-8412-2cab0784c015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110438341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3110438341
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.481420244
Short name T522
Test name
Test status
Simulation time 928276328 ps
CPU time 59.1 seconds
Started Jul 06 07:13:15 PM PDT 24
Finished Jul 06 07:14:42 PM PDT 24
Peak memory 200304 kb
Host smart-605ac83e-8660-4e3f-8e1a-eeff64372c3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=481420244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.481420244
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2064638095
Short name T151
Test name
Test status
Simulation time 3028988731 ps
CPU time 54.25 seconds
Started Jul 06 07:13:17 PM PDT 24
Finished Jul 06 07:14:38 PM PDT 24
Peak memory 200348 kb
Host smart-67180750-9108-4eab-808b-766c05b6c5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064638095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2064638095
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2799219316
Short name T518
Test name
Test status
Simulation time 22222229540 ps
CPU time 1032.19 seconds
Started Jul 06 07:13:15 PM PDT 24
Finished Jul 06 07:30:55 PM PDT 24
Peak memory 701772 kb
Host smart-5b9e0d0e-19d6-4d45-bf47-afc7b1279344
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2799219316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2799219316
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.661541262
Short name T269
Test name
Test status
Simulation time 2073617092 ps
CPU time 62.35 seconds
Started Jul 06 07:13:16 PM PDT 24
Finished Jul 06 07:14:45 PM PDT 24
Peak memory 200352 kb
Host smart-40da08aa-3705-4a51-9657-71fb5918d001
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661541262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.661541262
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3602348476
Short name T363
Test name
Test status
Simulation time 672873655 ps
CPU time 19.29 seconds
Started Jul 06 07:13:12 PM PDT 24
Finished Jul 06 07:13:59 PM PDT 24
Peak memory 200352 kb
Host smart-0998a982-b591-4c31-ba60-906f1f050243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602348476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3602348476
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1659352202
Short name T160
Test name
Test status
Simulation time 888527534 ps
CPU time 11.8 seconds
Started Jul 06 07:13:09 PM PDT 24
Finished Jul 06 07:13:46 PM PDT 24
Peak memory 200224 kb
Host smart-e4f7d368-68f6-445e-9a4f-7447af12d8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659352202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1659352202
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.1910022225
Short name T38
Test name
Test status
Simulation time 42195751442 ps
CPU time 529.54 seconds
Started Jul 06 07:13:14 PM PDT 24
Finished Jul 06 07:22:32 PM PDT 24
Peak memory 200540 kb
Host smart-e16f9380-e325-4448-96fd-4fcd4f2914e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910022225 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1910022225
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1890489614
Short name T260
Test name
Test status
Simulation time 59690777 ps
CPU time 3.41 seconds
Started Jul 06 07:13:16 PM PDT 24
Finished Jul 06 07:13:46 PM PDT 24
Peak memory 200248 kb
Host smart-53313946-c798-4435-8cdf-ef75e495406f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890489614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1890489614
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.744362892
Short name T430
Test name
Test status
Simulation time 22867961 ps
CPU time 0.58 seconds
Started Jul 06 07:13:21 PM PDT 24
Finished Jul 06 07:13:46 PM PDT 24
Peak memory 195756 kb
Host smart-f7fd82ed-9c08-4397-b1db-6ba6967e7d43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744362892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.744362892
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3830928872
Short name T322
Test name
Test status
Simulation time 1672114904 ps
CPU time 98.48 seconds
Started Jul 06 07:13:29 PM PDT 24
Finished Jul 06 07:15:30 PM PDT 24
Peak memory 200328 kb
Host smart-f2f76a00-7fec-4c3a-96fc-8c7aaea9ed39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3830928872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3830928872
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1972068734
Short name T277
Test name
Test status
Simulation time 6643917094 ps
CPU time 46.64 seconds
Started Jul 06 07:13:28 PM PDT 24
Finished Jul 06 07:14:39 PM PDT 24
Peak memory 200344 kb
Host smart-a31b339a-ebc3-496b-8547-ffab3107b66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972068734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1972068734
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.547547117
Short name T428
Test name
Test status
Simulation time 1959488510 ps
CPU time 346.66 seconds
Started Jul 06 07:13:21 PM PDT 24
Finished Jul 06 07:19:32 PM PDT 24
Peak memory 489088 kb
Host smart-87d324a0-8077-4daf-bb74-f8db3df651c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=547547117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.547547117
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3213858194
Short name T466
Test name
Test status
Simulation time 1421851384 ps
CPU time 74.57 seconds
Started Jul 06 07:13:20 PM PDT 24
Finished Jul 06 07:15:00 PM PDT 24
Peak memory 200244 kb
Host smart-c7a1f4bd-6e42-4363-b75c-6996a1118f46
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213858194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3213858194
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3343625961
Short name T398
Test name
Test status
Simulation time 35061914750 ps
CPU time 159.72 seconds
Started Jul 06 07:13:21 PM PDT 24
Finished Jul 06 07:16:25 PM PDT 24
Peak memory 200408 kb
Host smart-02f2fc17-987e-47a1-84fc-5cd85b0fa4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343625961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3343625961
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1193753981
Short name T218
Test name
Test status
Simulation time 2714235618 ps
CPU time 11.12 seconds
Started Jul 06 07:13:28 PM PDT 24
Finished Jul 06 07:14:03 PM PDT 24
Peak memory 200372 kb
Host smart-a493e331-5252-4811-8658-ef2a19115a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193753981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1193753981
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3351038050
Short name T263
Test name
Test status
Simulation time 46231370620 ps
CPU time 1873.08 seconds
Started Jul 06 07:13:27 PM PDT 24
Finished Jul 06 07:45:03 PM PDT 24
Peak memory 784312 kb
Host smart-fc697635-37fa-4d73-a5eb-9e4ba40a87d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351038050 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3351038050
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2103323954
Short name T332
Test name
Test status
Simulation time 651874251 ps
CPU time 29.88 seconds
Started Jul 06 07:13:21 PM PDT 24
Finished Jul 06 07:14:15 PM PDT 24
Peak memory 200308 kb
Host smart-a6a516c8-f662-4c1b-a94d-d22b3af894db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103323954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2103323954
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1991686449
Short name T328
Test name
Test status
Simulation time 20153218 ps
CPU time 0.61 seconds
Started Jul 06 07:13:28 PM PDT 24
Finished Jul 06 07:13:53 PM PDT 24
Peak memory 196232 kb
Host smart-9080f5ba-815b-46dc-8bd9-f2f83562fb10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991686449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1991686449
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.636026817
Short name T532
Test name
Test status
Simulation time 154455053 ps
CPU time 8.92 seconds
Started Jul 06 07:13:22 PM PDT 24
Finished Jul 06 07:13:55 PM PDT 24
Peak memory 200320 kb
Host smart-58561255-f874-4521-b882-48ff9f245b88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=636026817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.636026817
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2729497158
Short name T138
Test name
Test status
Simulation time 6972074755 ps
CPU time 61.91 seconds
Started Jul 06 07:13:28 PM PDT 24
Finished Jul 06 07:14:54 PM PDT 24
Peak memory 200392 kb
Host smart-9c446534-f003-416a-8070-90739c8d93c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729497158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2729497158
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1728069040
Short name T163
Test name
Test status
Simulation time 1490063203 ps
CPU time 278.69 seconds
Started Jul 06 07:13:21 PM PDT 24
Finished Jul 06 07:18:24 PM PDT 24
Peak memory 595984 kb
Host smart-ca03d632-5ea3-4a9a-82d3-91f3091ebacc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1728069040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1728069040
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.2891235225
Short name T39
Test name
Test status
Simulation time 23588388443 ps
CPU time 104.39 seconds
Started Jul 06 07:13:27 PM PDT 24
Finished Jul 06 07:15:34 PM PDT 24
Peak memory 200264 kb
Host smart-d98d4977-a0b3-447d-aa5f-9815e16f01ba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891235225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2891235225
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.2164475161
Short name T132
Test name
Test status
Simulation time 29561104680 ps
CPU time 195.75 seconds
Started Jul 06 07:13:21 PM PDT 24
Finished Jul 06 07:17:01 PM PDT 24
Peak memory 200672 kb
Host smart-6a49b1c0-aac9-43bd-878b-1919aa1f4245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164475161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2164475161
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3133656011
Short name T204
Test name
Test status
Simulation time 2424505067 ps
CPU time 7.93 seconds
Started Jul 06 07:13:20 PM PDT 24
Finished Jul 06 07:13:53 PM PDT 24
Peak memory 200432 kb
Host smart-dec053a7-101e-4370-ae4b-85da45f31246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133656011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3133656011
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1397422109
Short name T13
Test name
Test status
Simulation time 22256241143 ps
CPU time 3375.61 seconds
Started Jul 06 07:13:29 PM PDT 24
Finished Jul 06 08:10:08 PM PDT 24
Peak memory 738140 kb
Host smart-4e058151-2f8e-42e1-9f41-866d847a78ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397422109 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1397422109
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.762481179
Short name T339
Test name
Test status
Simulation time 101882491234 ps
CPU time 129.27 seconds
Started Jul 06 07:13:29 PM PDT 24
Finished Jul 06 07:16:01 PM PDT 24
Peak memory 200384 kb
Host smart-9430b544-ae8c-4512-a44c-7ab55b69d4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762481179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.762481179
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3697352586
Short name T451
Test name
Test status
Simulation time 28517818 ps
CPU time 0.65 seconds
Started Jul 06 07:13:31 PM PDT 24
Finished Jul 06 07:13:55 PM PDT 24
Peak memory 196188 kb
Host smart-03aaf5a6-c611-4497-b789-d10c1645a9e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697352586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3697352586
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1403028942
Short name T71
Test name
Test status
Simulation time 2334500530 ps
CPU time 66.81 seconds
Started Jul 06 07:13:29 PM PDT 24
Finished Jul 06 07:14:59 PM PDT 24
Peak memory 200376 kb
Host smart-4eb7dc57-ca48-4e15-8a7d-bbcda453d2e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1403028942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1403028942
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2936276468
Short name T315
Test name
Test status
Simulation time 10341598519 ps
CPU time 68.07 seconds
Started Jul 06 07:13:28 PM PDT 24
Finished Jul 06 07:15:00 PM PDT 24
Peak memory 200392 kb
Host smart-3de9db5f-c2e3-4472-b019-1506b7642703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936276468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2936276468
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2834658628
Short name T243
Test name
Test status
Simulation time 13620437 ps
CPU time 0.86 seconds
Started Jul 06 07:13:28 PM PDT 24
Finished Jul 06 07:13:52 PM PDT 24
Peak memory 208400 kb
Host smart-f6d0bd95-1e81-4573-ab0b-b94d4fae5ea5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2834658628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2834658628
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2722409202
Short name T292
Test name
Test status
Simulation time 21357492789 ps
CPU time 97.7 seconds
Started Jul 06 07:13:28 PM PDT 24
Finished Jul 06 07:15:29 PM PDT 24
Peak memory 200388 kb
Host smart-ead25983-ca1c-4470-a813-29e8ae902937
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722409202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2722409202
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.1743941568
Short name T208
Test name
Test status
Simulation time 4294210383 ps
CPU time 76.2 seconds
Started Jul 06 07:13:29 PM PDT 24
Finished Jul 06 07:15:08 PM PDT 24
Peak memory 200364 kb
Host smart-0e358e79-a97d-4af3-b7c0-1329579adef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743941568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.1743941568
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1558458872
Short name T455
Test name
Test status
Simulation time 481035474 ps
CPU time 5.36 seconds
Started Jul 06 07:13:29 PM PDT 24
Finished Jul 06 07:13:57 PM PDT 24
Peak memory 200312 kb
Host smart-51753022-e650-49ec-ae51-bfb914ae8575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558458872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1558458872
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.1914022911
Short name T104
Test name
Test status
Simulation time 306863658855 ps
CPU time 287.72 seconds
Started Jul 06 07:13:30 PM PDT 24
Finished Jul 06 07:18:40 PM PDT 24
Peak memory 200308 kb
Host smart-89629208-2c9a-4ffa-bade-365d593b3a51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914022911 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.1914022911
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2813455398
Short name T23
Test name
Test status
Simulation time 4805370181 ps
CPU time 68.87 seconds
Started Jul 06 07:13:29 PM PDT 24
Finished Jul 06 07:15:01 PM PDT 24
Peak memory 200368 kb
Host smart-28e58a6a-f6e2-4c06-b38e-0900f61ba85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813455398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2813455398
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2681835501
Short name T70
Test name
Test status
Simulation time 38767419 ps
CPU time 0.62 seconds
Started Jul 06 07:13:31 PM PDT 24
Finished Jul 06 07:13:55 PM PDT 24
Peak memory 195856 kb
Host smart-b8163e75-a9bc-4f22-85d0-5974f111e5a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681835501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2681835501
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3179788370
Short name T418
Test name
Test status
Simulation time 1573439296 ps
CPU time 94.14 seconds
Started Jul 06 07:13:28 PM PDT 24
Finished Jul 06 07:15:26 PM PDT 24
Peak memory 200300 kb
Host smart-7f36353b-78d6-48a1-905c-97563f71a0aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3179788370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3179788370
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.4228043155
Short name T255
Test name
Test status
Simulation time 15436199702 ps
CPU time 89.31 seconds
Started Jul 06 07:13:29 PM PDT 24
Finished Jul 06 07:15:22 PM PDT 24
Peak memory 216528 kb
Host smart-baec7a78-51cc-4b0e-89f6-a40a798f4772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228043155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.4228043155
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2944334708
Short name T504
Test name
Test status
Simulation time 6069763123 ps
CPU time 1294.69 seconds
Started Jul 06 07:13:28 PM PDT 24
Finished Jul 06 07:35:27 PM PDT 24
Peak memory 745600 kb
Host smart-d1a0f89d-d1d5-4d5f-8b5a-e8fdf9787bd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2944334708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2944334708
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1290773908
Short name T372
Test name
Test status
Simulation time 19550352088 ps
CPU time 152.7 seconds
Started Jul 06 07:13:31 PM PDT 24
Finished Jul 06 07:16:25 PM PDT 24
Peak memory 200408 kb
Host smart-7335d8c2-9d5e-4d6c-8704-e9148a026f0b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290773908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1290773908
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3598612766
Short name T433
Test name
Test status
Simulation time 2815693246 ps
CPU time 179.65 seconds
Started Jul 06 07:13:28 PM PDT 24
Finished Jul 06 07:16:52 PM PDT 24
Peak memory 200372 kb
Host smart-21ec8e7b-7c7e-4e89-932d-75c51bf55f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598612766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3598612766
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.4289526811
Short name T378
Test name
Test status
Simulation time 504331000 ps
CPU time 6.39 seconds
Started Jul 06 07:13:31 PM PDT 24
Finished Jul 06 07:13:59 PM PDT 24
Peak memory 200292 kb
Host smart-6d1cdf1b-877f-40f6-95b3-d54317e61f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289526811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.4289526811
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.4180120686
Short name T457
Test name
Test status
Simulation time 36937700340 ps
CPU time 3085.67 seconds
Started Jul 06 07:13:31 PM PDT 24
Finished Jul 06 08:05:21 PM PDT 24
Peak memory 787352 kb
Host smart-16a18e2c-9f1c-4a6f-827f-5d71ef946764
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180120686 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.4180120686
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2790093545
Short name T360
Test name
Test status
Simulation time 6792454592 ps
CPU time 67.75 seconds
Started Jul 06 07:13:31 PM PDT 24
Finished Jul 06 07:15:02 PM PDT 24
Peak memory 200324 kb
Host smart-6cce048b-eeaa-43a6-9488-1251e795d001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790093545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2790093545
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.284096122
Short name T501
Test name
Test status
Simulation time 41820323 ps
CPU time 0.67 seconds
Started Jul 06 07:13:37 PM PDT 24
Finished Jul 06 07:14:03 PM PDT 24
Peak memory 196204 kb
Host smart-645cf946-61c6-44cf-8ad4-a3610781e129
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284096122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.284096122
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.168634384
Short name T128
Test name
Test status
Simulation time 837155141 ps
CPU time 23.88 seconds
Started Jul 06 07:13:32 PM PDT 24
Finished Jul 06 07:14:19 PM PDT 24
Peak memory 200312 kb
Host smart-b91ec1f5-54ac-462d-8824-728f9b30f7a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=168634384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.168634384
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3640800000
Short name T290
Test name
Test status
Simulation time 18865536707 ps
CPU time 38.91 seconds
Started Jul 06 07:13:32 PM PDT 24
Finished Jul 06 07:14:34 PM PDT 24
Peak memory 200424 kb
Host smart-8f487229-2490-495b-9da2-a0cff2d185cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640800000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3640800000
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3189869613
Short name T436
Test name
Test status
Simulation time 20826351627 ps
CPU time 977.33 seconds
Started Jul 06 07:13:32 PM PDT 24
Finished Jul 06 07:30:13 PM PDT 24
Peak memory 717652 kb
Host smart-4dad252c-c76d-4770-8aa9-036cf4bba74b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3189869613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3189869613
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.199881678
Short name T176
Test name
Test status
Simulation time 15716696386 ps
CPU time 239.43 seconds
Started Jul 06 07:13:31 PM PDT 24
Finished Jul 06 07:17:54 PM PDT 24
Peak memory 200400 kb
Host smart-617a6ba0-2109-4b37-8091-f0581650adb7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199881678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.199881678
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3426055718
Short name T194
Test name
Test status
Simulation time 6142923307 ps
CPU time 91.72 seconds
Started Jul 06 07:13:32 PM PDT 24
Finished Jul 06 07:15:26 PM PDT 24
Peak memory 200408 kb
Host smart-1be80949-3ec6-4f2a-b9af-430de4374600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426055718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3426055718
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2864444677
Short name T19
Test name
Test status
Simulation time 33663223 ps
CPU time 0.9 seconds
Started Jul 06 07:13:32 PM PDT 24
Finished Jul 06 07:13:56 PM PDT 24
Peak memory 198844 kb
Host smart-eaa697b7-8de4-4efc-b4a1-ddb33c7f2732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864444677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2864444677
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.88415661
Short name T27
Test name
Test status
Simulation time 138189873203 ps
CPU time 1603.98 seconds
Started Jul 06 07:13:39 PM PDT 24
Finished Jul 06 07:40:50 PM PDT 24
Peak memory 731860 kb
Host smart-8ca051d0-d49c-4956-991b-253659aa7625
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88415661 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.88415661
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.2082789739
Short name T161
Test name
Test status
Simulation time 4332355002 ps
CPU time 16.66 seconds
Started Jul 06 07:13:37 PM PDT 24
Finished Jul 06 07:14:19 PM PDT 24
Peak memory 200384 kb
Host smart-ff8b44e5-298b-42b9-a4b5-34f7ac664763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082789739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.2082789739
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.347610006
Short name T264
Test name
Test status
Simulation time 20975647 ps
CPU time 0.63 seconds
Started Jul 06 07:13:43 PM PDT 24
Finished Jul 06 07:14:22 PM PDT 24
Peak memory 195108 kb
Host smart-501460a6-4960-4322-9144-c53770ff888c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347610006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.347610006
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.255756548
Short name T211
Test name
Test status
Simulation time 385326928 ps
CPU time 22.15 seconds
Started Jul 06 07:13:38 PM PDT 24
Finished Jul 06 07:14:28 PM PDT 24
Peak memory 200308 kb
Host smart-086e16dd-57a8-4bbf-8934-0b650c95ffdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=255756548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.255756548
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.116557526
Short name T167
Test name
Test status
Simulation time 7557762205 ps
CPU time 27.39 seconds
Started Jul 06 07:13:39 PM PDT 24
Finished Jul 06 07:14:33 PM PDT 24
Peak memory 200404 kb
Host smart-e8a4b99e-27fe-4433-83cc-f38d5a3955f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116557526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.116557526
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2208725043
Short name T385
Test name
Test status
Simulation time 21404931706 ps
CPU time 1041.32 seconds
Started Jul 06 07:13:38 PM PDT 24
Finished Jul 06 07:31:24 PM PDT 24
Peak memory 747740 kb
Host smart-33263103-909d-4b5b-8713-fcb496707534
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2208725043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2208725043
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3084650718
Short name T393
Test name
Test status
Simulation time 6682628805 ps
CPU time 188.54 seconds
Started Jul 06 07:13:37 PM PDT 24
Finished Jul 06 07:17:11 PM PDT 24
Peak memory 200384 kb
Host smart-b5fed49b-07b1-4173-91ec-32cee6d29570
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084650718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3084650718
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.856923578
Short name T186
Test name
Test status
Simulation time 29601968739 ps
CPU time 195.25 seconds
Started Jul 06 07:13:37 PM PDT 24
Finished Jul 06 07:17:17 PM PDT 24
Peak memory 200324 kb
Host smart-50a0596d-7e76-45fa-be9c-1cd9004db2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856923578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.856923578
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3545400532
Short name T118
Test name
Test status
Simulation time 128533197 ps
CPU time 1.66 seconds
Started Jul 06 07:13:39 PM PDT 24
Finished Jul 06 07:14:07 PM PDT 24
Peak memory 200328 kb
Host smart-19205244-c9b8-4c21-87c6-52d218c9a1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545400532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3545400532
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2012573907
Short name T295
Test name
Test status
Simulation time 85417707164 ps
CPU time 587.39 seconds
Started Jul 06 07:13:42 PM PDT 24
Finished Jul 06 07:24:08 PM PDT 24
Peak memory 686524 kb
Host smart-efbbd5fd-d1c7-454f-8ed0-7fd2bb362393
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012573907 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2012573907
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.2082412503
Short name T236
Test name
Test status
Simulation time 29560014985 ps
CPU time 77.58 seconds
Started Jul 06 07:13:37 PM PDT 24
Finished Jul 06 07:15:20 PM PDT 24
Peak memory 200372 kb
Host smart-c87bb2a9-d866-4a35-b86a-b1c21cf41e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082412503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.2082412503
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2889625493
Short name T362
Test name
Test status
Simulation time 14956182 ps
CPU time 0.6 seconds
Started Jul 06 07:11:10 PM PDT 24
Finished Jul 06 07:11:11 PM PDT 24
Peak memory 196200 kb
Host smart-a2e8a560-55b3-4443-87bd-01d036fe34cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889625493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2889625493
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1420663115
Short name T293
Test name
Test status
Simulation time 3620556954 ps
CPU time 104.93 seconds
Started Jul 06 07:11:04 PM PDT 24
Finished Jul 06 07:12:49 PM PDT 24
Peak memory 200424 kb
Host smart-611d0944-5f6d-4117-839f-93c9ca9d5158
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1420663115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1420663115
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.1509214020
Short name T352
Test name
Test status
Simulation time 1173160215 ps
CPU time 64.24 seconds
Started Jul 06 07:11:00 PM PDT 24
Finished Jul 06 07:12:06 PM PDT 24
Peak memory 200364 kb
Host smart-bbfc6538-c1bd-4bb1-a54e-068971d2e01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509214020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.1509214020
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2413253497
Short name T68
Test name
Test status
Simulation time 4686262396 ps
CPU time 904.93 seconds
Started Jul 06 07:11:03 PM PDT 24
Finished Jul 06 07:26:08 PM PDT 24
Peak memory 740292 kb
Host smart-aecc78b9-8e17-4f7b-bc66-f4f1d24d7303
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2413253497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2413253497
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2106234566
Short name T206
Test name
Test status
Simulation time 534840736 ps
CPU time 30.81 seconds
Started Jul 06 07:11:00 PM PDT 24
Finished Jul 06 07:11:32 PM PDT 24
Peak memory 200300 kb
Host smart-1ebf8634-700e-4181-9961-5ecedf821937
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106234566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2106234566
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2317639393
Short name T33
Test name
Test status
Simulation time 2079056759 ps
CPU time 120.91 seconds
Started Jul 06 07:11:00 PM PDT 24
Finished Jul 06 07:13:01 PM PDT 24
Peak memory 200340 kb
Host smart-f9cd5513-8dfa-41a5-a907-d64909b12583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317639393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2317639393
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3931894097
Short name T45
Test name
Test status
Simulation time 59341466 ps
CPU time 0.93 seconds
Started Jul 06 07:11:07 PM PDT 24
Finished Jul 06 07:11:09 PM PDT 24
Peak memory 218484 kb
Host smart-ae14ed69-fabf-4485-8111-2a6344f71049
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931894097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3931894097
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.17123117
Short name T190
Test name
Test status
Simulation time 993311372 ps
CPU time 16.41 seconds
Started Jul 06 07:11:00 PM PDT 24
Finished Jul 06 07:11:18 PM PDT 24
Peak memory 200364 kb
Host smart-0801a259-5ef0-477d-bf1a-788e1f778fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17123117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.17123117
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.3065119594
Short name T14
Test name
Test status
Simulation time 247152441010 ps
CPU time 1710.11 seconds
Started Jul 06 07:11:09 PM PDT 24
Finished Jul 06 07:39:40 PM PDT 24
Peak memory 728900 kb
Host smart-f20b5d84-42bf-44a7-8309-0e5bc8a63f50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3065119594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.3065119594
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.1710076156
Short name T179
Test name
Test status
Simulation time 1108076531 ps
CPU time 39.31 seconds
Started Jul 06 07:11:06 PM PDT 24
Finished Jul 06 07:11:46 PM PDT 24
Peak memory 200348 kb
Host smart-2f71111f-68b1-41e6-9653-725b294da463
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1710076156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.1710076156
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.4111134167
Short name T529
Test name
Test status
Simulation time 40696485927 ps
CPU time 69.75 seconds
Started Jul 06 07:11:13 PM PDT 24
Finished Jul 06 07:12:25 PM PDT 24
Peak memory 200392 kb
Host smart-9358ba84-4f0a-41f3-94e3-6b9febc79da9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4111134167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.4111134167
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.1965750251
Short name T434
Test name
Test status
Simulation time 4984550241 ps
CPU time 83.21 seconds
Started Jul 06 07:11:07 PM PDT 24
Finished Jul 06 07:12:31 PM PDT 24
Peak memory 200388 kb
Host smart-b9dc0c11-fbb7-440b-84ed-35409d77e58e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1965750251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.1965750251
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.3204270073
Short name T401
Test name
Test status
Simulation time 40554749975 ps
CPU time 613.26 seconds
Started Jul 06 07:11:08 PM PDT 24
Finished Jul 06 07:21:22 PM PDT 24
Peak memory 200388 kb
Host smart-fde1ea3f-27ca-4086-ba44-55f8a93b281d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3204270073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.3204270073
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.585683265
Short name T427
Test name
Test status
Simulation time 154650078145 ps
CPU time 2538.14 seconds
Started Jul 06 07:11:10 PM PDT 24
Finished Jul 06 07:53:30 PM PDT 24
Peak memory 215952 kb
Host smart-319a2178-260e-42fa-b37e-03388eb793b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=585683265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.585683265
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.1345702440
Short name T120
Test name
Test status
Simulation time 167617496414 ps
CPU time 2556.3 seconds
Started Jul 06 07:11:07 PM PDT 24
Finished Jul 06 07:53:46 PM PDT 24
Peak memory 215960 kb
Host smart-a5de3e45-dcc3-4a1c-8485-83bc70d58546
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1345702440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.1345702440
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.762882041
Short name T462
Test name
Test status
Simulation time 11559369362 ps
CPU time 107.91 seconds
Started Jul 06 07:11:02 PM PDT 24
Finished Jul 06 07:12:51 PM PDT 24
Peak memory 200380 kb
Host smart-e26b3b26-a364-46da-a89b-62682c2d3c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762882041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.762882041
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1476539910
Short name T219
Test name
Test status
Simulation time 56668888 ps
CPU time 0.58 seconds
Started Jul 06 07:13:46 PM PDT 24
Finished Jul 06 07:14:31 PM PDT 24
Peak memory 195828 kb
Host smart-6df98905-6fdf-43e6-bb81-df547633f7f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476539910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1476539910
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.29749016
Short name T196
Test name
Test status
Simulation time 1286258968 ps
CPU time 79.84 seconds
Started Jul 06 07:13:42 PM PDT 24
Finished Jul 06 07:15:35 PM PDT 24
Peak memory 200264 kb
Host smart-f98ec7c7-4623-480d-b98c-4a7e442136a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=29749016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.29749016
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.421481882
Short name T443
Test name
Test status
Simulation time 29548913096 ps
CPU time 56.92 seconds
Started Jul 06 07:13:42 PM PDT 24
Finished Jul 06 07:15:12 PM PDT 24
Peak memory 200424 kb
Host smart-d4cccf0e-a538-450d-b3d7-6b6608566dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421481882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.421481882
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.123827475
Short name T201
Test name
Test status
Simulation time 11168183165 ps
CPU time 1426.97 seconds
Started Jul 06 07:13:44 PM PDT 24
Finished Jul 06 07:38:08 PM PDT 24
Peak memory 758620 kb
Host smart-6ad5704b-e396-440b-a81d-c6dd19c4975f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=123827475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.123827475
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2194110308
Short name T356
Test name
Test status
Simulation time 5860528840 ps
CPU time 84.2 seconds
Started Jul 06 07:13:43 PM PDT 24
Finished Jul 06 07:15:45 PM PDT 24
Peak memory 200320 kb
Host smart-11e7c513-6ab6-4caa-93e2-dd131d3ad5df
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194110308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2194110308
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2661876206
Short name T301
Test name
Test status
Simulation time 34099477733 ps
CPU time 156.52 seconds
Started Jul 06 07:13:42 PM PDT 24
Finished Jul 06 07:16:52 PM PDT 24
Peak memory 200412 kb
Host smart-4dc3c2b5-d93b-4805-9282-6e4594784fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661876206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2661876206
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.8703549
Short name T320
Test name
Test status
Simulation time 1077943437 ps
CPU time 13.34 seconds
Started Jul 06 07:13:42 PM PDT 24
Finished Jul 06 07:14:34 PM PDT 24
Peak memory 200336 kb
Host smart-b512dde5-880b-44fd-9527-3d2d45569081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8703549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.8703549
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.483552900
Short name T431
Test name
Test status
Simulation time 9185305955 ps
CPU time 77.62 seconds
Started Jul 06 07:13:44 PM PDT 24
Finished Jul 06 07:15:39 PM PDT 24
Peak memory 200356 kb
Host smart-92ebe605-b5c3-46dc-8bc5-6a3f487f0eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483552900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.483552900
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2286134098
Short name T280
Test name
Test status
Simulation time 13728627 ps
CPU time 0.63 seconds
Started Jul 06 07:13:58 PM PDT 24
Finished Jul 06 07:15:07 PM PDT 24
Peak memory 196900 kb
Host smart-a0e1752f-4136-42cc-92a1-4a84ef5b85b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286134098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2286134098
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1480953630
Short name T530
Test name
Test status
Simulation time 6087426049 ps
CPU time 31.31 seconds
Started Jul 06 07:13:53 PM PDT 24
Finished Jul 06 07:15:22 PM PDT 24
Peak memory 200368 kb
Host smart-fb72b82f-16fc-407f-b75b-6c8397257687
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1480953630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1480953630
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.213908602
Short name T3
Test name
Test status
Simulation time 16001219502 ps
CPU time 47.47 seconds
Started Jul 06 07:13:52 PM PDT 24
Finished Jul 06 07:15:38 PM PDT 24
Peak memory 200392 kb
Host smart-a96b5c58-a0b5-4d61-b9f9-eedb33bf12d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213908602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.213908602
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2286671246
Short name T26
Test name
Test status
Simulation time 4599918477 ps
CPU time 857.63 seconds
Started Jul 06 07:13:53 PM PDT 24
Finished Jul 06 07:29:08 PM PDT 24
Peak memory 698132 kb
Host smart-a9ef59f0-a7d3-4278-a809-286c350dda54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2286671246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2286671246
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.3132122100
Short name T494
Test name
Test status
Simulation time 6173576864 ps
CPU time 95.5 seconds
Started Jul 06 07:13:55 PM PDT 24
Finished Jul 06 07:16:30 PM PDT 24
Peak memory 200372 kb
Host smart-1fd63c9b-aae7-446b-a250-d076db13c687
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132122100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.3132122100
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.654011868
Short name T289
Test name
Test status
Simulation time 445771533 ps
CPU time 8.36 seconds
Started Jul 06 07:13:50 PM PDT 24
Finished Jul 06 07:14:53 PM PDT 24
Peak memory 200312 kb
Host smart-b702d43e-5673-4427-87fb-1e06b3be8806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654011868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.654011868
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2222313183
Short name T256
Test name
Test status
Simulation time 379596475 ps
CPU time 8.59 seconds
Started Jul 06 07:13:49 PM PDT 24
Finished Jul 06 07:14:53 PM PDT 24
Peak memory 200320 kb
Host smart-ec905065-100e-4f5e-908e-c4d82ca059e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222313183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2222313183
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1961366371
Short name T334
Test name
Test status
Simulation time 102725090509 ps
CPU time 1374.93 seconds
Started Jul 06 07:13:53 PM PDT 24
Finished Jul 06 07:37:45 PM PDT 24
Peak memory 625760 kb
Host smart-6ce0ba8a-50fb-4ac8-bcbf-d0f39bc733ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961366371 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1961366371
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1740836384
Short name T249
Test name
Test status
Simulation time 1984151199 ps
CPU time 85.27 seconds
Started Jul 06 07:13:53 PM PDT 24
Finished Jul 06 07:16:16 PM PDT 24
Peak memory 200300 kb
Host smart-99186da9-34c6-483f-956a-3129314e8a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740836384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1740836384
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3021606536
Short name T164
Test name
Test status
Simulation time 42539981 ps
CPU time 0.56 seconds
Started Jul 06 07:13:59 PM PDT 24
Finished Jul 06 07:15:07 PM PDT 24
Peak memory 195840 kb
Host smart-066f7a43-e861-417a-9751-61b3168fdecf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021606536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3021606536
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3844673344
Short name T22
Test name
Test status
Simulation time 11194726490 ps
CPU time 43.56 seconds
Started Jul 06 07:13:58 PM PDT 24
Finished Jul 06 07:15:50 PM PDT 24
Peak memory 200404 kb
Host smart-d67e949d-e16c-47c2-a296-eb575990192f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3844673344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3844673344
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.4244076949
Short name T467
Test name
Test status
Simulation time 3779417819 ps
CPU time 11.63 seconds
Started Jul 06 07:13:59 PM PDT 24
Finished Jul 06 07:15:26 PM PDT 24
Peak memory 200368 kb
Host smart-a3e83830-77f6-4b1d-82c1-d8861a881c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244076949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.4244076949
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.554653418
Short name T61
Test name
Test status
Simulation time 7793021002 ps
CPU time 415.56 seconds
Started Jul 06 07:13:57 PM PDT 24
Finished Jul 06 07:22:02 PM PDT 24
Peak memory 632788 kb
Host smart-e101b42a-d89e-4093-becc-f8c99c2029d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=554653418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.554653418
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.716755226
Short name T474
Test name
Test status
Simulation time 5749034373 ps
CPU time 81.06 seconds
Started Jul 06 07:13:58 PM PDT 24
Finished Jul 06 07:16:27 PM PDT 24
Peak memory 200300 kb
Host smart-829d8488-d39e-40d3-b5f2-40cb2003b8d9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716755226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.716755226
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.4215043330
Short name T147
Test name
Test status
Simulation time 5928695961 ps
CPU time 45.87 seconds
Started Jul 06 07:13:59 PM PDT 24
Finished Jul 06 07:15:52 PM PDT 24
Peak memory 200408 kb
Host smart-f58ca7de-9337-4973-b55e-5b1e3fef0836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215043330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.4215043330
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3838778504
Short name T28
Test name
Test status
Simulation time 209395664 ps
CPU time 3.74 seconds
Started Jul 06 07:13:59 PM PDT 24
Finished Jul 06 07:15:18 PM PDT 24
Peak memory 200224 kb
Host smart-9da6e3ae-9d18-4a39-bc8b-c48527a91aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838778504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3838778504
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.1854380144
Short name T348
Test name
Test status
Simulation time 162263210354 ps
CPU time 1290.55 seconds
Started Jul 06 07:13:58 PM PDT 24
Finished Jul 06 07:36:37 PM PDT 24
Peak memory 689176 kb
Host smart-6d89e720-8c50-4223-b9ce-1700ef35813f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854380144 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1854380144
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3077902744
Short name T361
Test name
Test status
Simulation time 6002487999 ps
CPU time 107.07 seconds
Started Jul 06 07:13:58 PM PDT 24
Finished Jul 06 07:16:53 PM PDT 24
Peak memory 200368 kb
Host smart-7decc024-f8b5-4b77-a3d6-a7c91f92da45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077902744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3077902744
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2765210039
Short name T220
Test name
Test status
Simulation time 35900630 ps
CPU time 0.58 seconds
Started Jul 06 07:14:09 PM PDT 24
Finished Jul 06 07:15:38 PM PDT 24
Peak memory 195164 kb
Host smart-6b763fae-66ea-422b-b97d-ec19638531ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765210039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2765210039
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1818522936
Short name T139
Test name
Test status
Simulation time 7376328104 ps
CPU time 70.3 seconds
Started Jul 06 07:14:00 PM PDT 24
Finished Jul 06 07:16:25 PM PDT 24
Peak memory 200344 kb
Host smart-232af745-5a63-46a2-b097-fde6f7a9e258
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1818522936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1818522936
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1668017717
Short name T221
Test name
Test status
Simulation time 26543557947 ps
CPU time 82.7 seconds
Started Jul 06 07:14:02 PM PDT 24
Finished Jul 06 07:16:49 PM PDT 24
Peak memory 208568 kb
Host smart-789d236e-ef87-4802-a2a0-8a4447b133da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668017717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1668017717
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.4166365387
Short name T364
Test name
Test status
Simulation time 11855996665 ps
CPU time 1028.82 seconds
Started Jul 06 07:14:05 PM PDT 24
Finished Jul 06 07:32:46 PM PDT 24
Peak memory 740892 kb
Host smart-e2eeb928-17b6-49c9-a9e5-527a1e195a21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4166365387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.4166365387
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3610939067
Short name T273
Test name
Test status
Simulation time 9447250523 ps
CPU time 127.86 seconds
Started Jul 06 07:14:04 PM PDT 24
Finished Jul 06 07:17:45 PM PDT 24
Peak memory 200332 kb
Host smart-e59887a9-f6b2-4e70-b841-9d20992cd65a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610939067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3610939067
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2236221301
Short name T172
Test name
Test status
Simulation time 17135254689 ps
CPU time 162.63 seconds
Started Jul 06 07:13:58 PM PDT 24
Finished Jul 06 07:17:49 PM PDT 24
Peak memory 216580 kb
Host smart-d20b9a89-f30e-44b6-80d1-df48b173efb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236221301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2236221301
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1503459284
Short name T438
Test name
Test status
Simulation time 1110591321 ps
CPU time 2.23 seconds
Started Jul 06 07:13:59 PM PDT 24
Finished Jul 06 07:15:08 PM PDT 24
Peak memory 200216 kb
Host smart-a17ec82d-2b28-4624-b99b-e30bbb4c711d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503459284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1503459284
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.503354125
Short name T279
Test name
Test status
Simulation time 50585315794 ps
CPU time 663.21 seconds
Started Jul 06 07:14:04 PM PDT 24
Finished Jul 06 07:26:30 PM PDT 24
Peak memory 693372 kb
Host smart-bf055860-b6e1-44aa-842e-0257366b58c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503354125 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.503354125
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2767493652
Short name T330
Test name
Test status
Simulation time 36439388716 ps
CPU time 118.73 seconds
Started Jul 06 07:14:04 PM PDT 24
Finished Jul 06 07:17:36 PM PDT 24
Peak memory 200388 kb
Host smart-62aa59f1-0620-4a24-9b87-83465d9ed672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767493652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2767493652
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2626426393
Short name T159
Test name
Test status
Simulation time 13235510 ps
CPU time 0.59 seconds
Started Jul 06 07:14:16 PM PDT 24
Finished Jul 06 07:15:44 PM PDT 24
Peak memory 195144 kb
Host smart-2b2889a0-0b38-416e-94ea-d1e6bd0126e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626426393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2626426393
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.397753549
Short name T421
Test name
Test status
Simulation time 3983434403 ps
CPU time 53.17 seconds
Started Jul 06 07:14:10 PM PDT 24
Finished Jul 06 07:16:36 PM PDT 24
Peak memory 200332 kb
Host smart-0319439f-07a0-4d35-8f9a-eb9763bc61f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=397753549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.397753549
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2807785779
Short name T136
Test name
Test status
Simulation time 4990566583 ps
CPU time 69.45 seconds
Started Jul 06 07:14:10 PM PDT 24
Finished Jul 06 07:16:53 PM PDT 24
Peak memory 200332 kb
Host smart-993ab8ae-b0ae-4795-ac56-e8016a9c2a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807785779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2807785779
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1652942568
Short name T10
Test name
Test status
Simulation time 16392597772 ps
CPU time 634.27 seconds
Started Jul 06 07:14:12 PM PDT 24
Finished Jul 06 07:26:12 PM PDT 24
Peak memory 685872 kb
Host smart-d6dd22b5-05b2-4876-82f6-859ba89b9bbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1652942568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1652942568
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1343649891
Short name T336
Test name
Test status
Simulation time 3032158237 ps
CPU time 160.7 seconds
Started Jul 06 07:14:12 PM PDT 24
Finished Jul 06 07:18:18 PM PDT 24
Peak memory 200416 kb
Host smart-5fcc95ff-8982-4875-9c69-132bd6f9757d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343649891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1343649891
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.455854272
Short name T158
Test name
Test status
Simulation time 5511119754 ps
CPU time 67.83 seconds
Started Jul 06 07:14:12 PM PDT 24
Finished Jul 06 07:16:45 PM PDT 24
Peak memory 216816 kb
Host smart-ed434c5c-a5c1-431e-b0e5-a38fa38b48f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455854272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.455854272
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.535336925
Short name T513
Test name
Test status
Simulation time 2181757208 ps
CPU time 7.16 seconds
Started Jul 06 07:14:10 PM PDT 24
Finished Jul 06 07:15:50 PM PDT 24
Peak memory 200388 kb
Host smart-26517e41-3c1b-439c-9c21-d98acc6c0c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535336925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.535336925
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2445626753
Short name T192
Test name
Test status
Simulation time 389082235818 ps
CPU time 905.02 seconds
Started Jul 06 07:14:15 PM PDT 24
Finished Jul 06 07:30:48 PM PDT 24
Peak memory 641248 kb
Host smart-58307b6f-9dae-4ad3-a770-ae2216c31914
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445626753 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2445626753
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.762138557
Short name T154
Test name
Test status
Simulation time 8552563830 ps
CPU time 108.3 seconds
Started Jul 06 07:14:08 PM PDT 24
Finished Jul 06 07:17:31 PM PDT 24
Peak memory 200384 kb
Host smart-c1998cfb-0020-4f0d-8a51-bd03a4a86d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762138557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.762138557
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1244189335
Short name T397
Test name
Test status
Simulation time 51067848 ps
CPU time 0.62 seconds
Started Jul 06 07:14:20 PM PDT 24
Finished Jul 06 07:15:44 PM PDT 24
Peak memory 196196 kb
Host smart-b5c09106-99b4-49fe-82c3-1d2391096ae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244189335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1244189335
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3767488234
Short name T523
Test name
Test status
Simulation time 982771642 ps
CPU time 53.35 seconds
Started Jul 06 07:14:16 PM PDT 24
Finished Jul 06 07:16:37 PM PDT 24
Peak memory 200336 kb
Host smart-332d3ec8-b77b-4b9c-8c8b-fc07dea8819d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3767488234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3767488234
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.426798031
Short name T351
Test name
Test status
Simulation time 41961108344 ps
CPU time 41.44 seconds
Started Jul 06 07:14:19 PM PDT 24
Finished Jul 06 07:16:25 PM PDT 24
Peak memory 200420 kb
Host smart-f389f6bc-24bb-4754-aab0-3c02a9064b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426798031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.426798031
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3543642088
Short name T389
Test name
Test status
Simulation time 2215682047 ps
CPU time 401.31 seconds
Started Jul 06 07:14:16 PM PDT 24
Finished Jul 06 07:22:25 PM PDT 24
Peak memory 600168 kb
Host smart-7b757553-3be3-4d61-883c-2cd0cfb2e271
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3543642088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3543642088
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.590298694
Short name T350
Test name
Test status
Simulation time 2778850540 ps
CPU time 78.22 seconds
Started Jul 06 07:14:20 PM PDT 24
Finished Jul 06 07:17:01 PM PDT 24
Peak memory 200392 kb
Host smart-a30cedec-ee57-40f5-b0a9-c45e69591d7b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590298694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.590298694
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.4130985258
Short name T377
Test name
Test status
Simulation time 557682017 ps
CPU time 17.38 seconds
Started Jul 06 07:14:15 PM PDT 24
Finished Jul 06 07:16:01 PM PDT 24
Peak memory 200256 kb
Host smart-4f583315-b0c4-4f8d-8ddd-faf016fe1480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130985258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.4130985258
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.970626301
Short name T252
Test name
Test status
Simulation time 31100357 ps
CPU time 0.73 seconds
Started Jul 06 07:14:14 PM PDT 24
Finished Jul 06 07:15:39 PM PDT 24
Peak memory 198352 kb
Host smart-c39de5c0-3b22-40f6-b953-98bdc241bf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970626301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.970626301
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2928467754
Short name T182
Test name
Test status
Simulation time 13433315327 ps
CPU time 93.96 seconds
Started Jul 06 07:14:20 PM PDT 24
Finished Jul 06 07:17:17 PM PDT 24
Peak memory 216540 kb
Host smart-739c3dbc-0d4c-492d-ac50-70931e1be2f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928467754 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2928467754
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.1981985951
Short name T270
Test name
Test status
Simulation time 1224551800 ps
CPU time 70.49 seconds
Started Jul 06 07:14:19 PM PDT 24
Finished Jul 06 07:16:54 PM PDT 24
Peak memory 200332 kb
Host smart-8a357ca7-f421-4e89-914d-f51494fb1e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981985951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.1981985951
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.1890020188
Short name T129
Test name
Test status
Simulation time 44490986 ps
CPU time 0.57 seconds
Started Jul 06 07:14:32 PM PDT 24
Finished Jul 06 07:15:57 PM PDT 24
Peak memory 195832 kb
Host smart-3662f2e9-49c3-48a5-b3b9-faf41a40eb40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890020188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1890020188
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1382107220
Short name T485
Test name
Test status
Simulation time 651700539 ps
CPU time 10.11 seconds
Started Jul 06 07:14:26 PM PDT 24
Finished Jul 06 07:15:58 PM PDT 24
Peak memory 200308 kb
Host smart-413035ab-2501-4cae-81f6-bf1175ebd57b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1382107220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1382107220
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1069769669
Short name T274
Test name
Test status
Simulation time 6197115216 ps
CPU time 55.46 seconds
Started Jul 06 07:14:31 PM PDT 24
Finished Jul 06 07:16:49 PM PDT 24
Peak memory 200380 kb
Host smart-3cfef64f-bf70-4dcc-a079-c840c3779611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069769669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1069769669
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2876347427
Short name T189
Test name
Test status
Simulation time 4545772939 ps
CPU time 801.21 seconds
Started Jul 06 07:14:26 PM PDT 24
Finished Jul 06 07:29:09 PM PDT 24
Peak memory 740692 kb
Host smart-dde0d5b2-2f51-4e3e-8ed8-7a64f267a886
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2876347427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2876347427
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.449213219
Short name T188
Test name
Test status
Simulation time 100013779680 ps
CPU time 202.1 seconds
Started Jul 06 07:14:31 PM PDT 24
Finished Jul 06 07:19:18 PM PDT 24
Peak memory 200320 kb
Host smart-b86883b7-f316-4a1b-93af-9b2b4b552ea4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449213219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.449213219
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.4019094827
Short name T145
Test name
Test status
Simulation time 920912726 ps
CPU time 26.52 seconds
Started Jul 06 07:14:27 PM PDT 24
Finished Jul 06 07:16:15 PM PDT 24
Peak memory 200328 kb
Host smart-9a7d3c75-849e-4077-8d89-5a2f9db1cf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019094827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.4019094827
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3227719979
Short name T463
Test name
Test status
Simulation time 535127381 ps
CPU time 11.59 seconds
Started Jul 06 07:14:19 PM PDT 24
Finished Jul 06 07:15:55 PM PDT 24
Peak memory 200212 kb
Host smart-a6a0340e-38c1-4065-8f54-9391d02f5d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227719979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3227719979
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.461040204
Short name T419
Test name
Test status
Simulation time 101493101549 ps
CPU time 474.39 seconds
Started Jul 06 07:14:29 PM PDT 24
Finished Jul 06 07:23:51 PM PDT 24
Peak memory 608700 kb
Host smart-6d4c075a-58af-4412-aa78-5373f0c494e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461040204 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.461040204
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1996621611
Short name T354
Test name
Test status
Simulation time 31894833277 ps
CPU time 54.12 seconds
Started Jul 06 07:14:31 PM PDT 24
Finished Jul 06 07:16:51 PM PDT 24
Peak memory 200364 kb
Host smart-9c4524a6-cf9c-48ca-a40e-db0c87a46ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996621611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1996621611
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1402322055
Short name T17
Test name
Test status
Simulation time 13539852 ps
CPU time 0.6 seconds
Started Jul 06 07:14:39 PM PDT 24
Finished Jul 06 07:15:57 PM PDT 24
Peak memory 196196 kb
Host smart-d69094ee-9bbe-4651-a293-7e243ff7ae08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402322055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1402322055
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.489982312
Short name T405
Test name
Test status
Simulation time 319905421 ps
CPU time 8.11 seconds
Started Jul 06 07:14:34 PM PDT 24
Finished Jul 06 07:16:10 PM PDT 24
Peak memory 200292 kb
Host smart-1cd89134-2380-48c8-bf1f-10c9fbc85dfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=489982312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.489982312
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3684002517
Short name T310
Test name
Test status
Simulation time 1056144728 ps
CPU time 19.99 seconds
Started Jul 06 07:14:31 PM PDT 24
Finished Jul 06 07:16:18 PM PDT 24
Peak memory 200368 kb
Host smart-f7767e34-3cce-499c-aaff-4734c7faf633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684002517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3684002517
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1041892661
Short name T313
Test name
Test status
Simulation time 3526938344 ps
CPU time 307.27 seconds
Started Jul 06 07:14:34 PM PDT 24
Finished Jul 06 07:21:07 PM PDT 24
Peak memory 621264 kb
Host smart-c6464c89-aedb-4a86-a4df-3316de0d22fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1041892661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1041892661
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1452113212
Short name T409
Test name
Test status
Simulation time 12137843151 ps
CPU time 151.08 seconds
Started Jul 06 07:14:33 PM PDT 24
Finished Jul 06 07:18:25 PM PDT 24
Peak memory 200396 kb
Host smart-5ac0bf5d-af10-470b-980b-de614c38bace
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452113212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1452113212
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.4041017688
Short name T424
Test name
Test status
Simulation time 25500330442 ps
CPU time 169.07 seconds
Started Jul 06 07:14:30 PM PDT 24
Finished Jul 06 07:18:51 PM PDT 24
Peak memory 216620 kb
Host smart-97920a12-617d-40f9-88bd-fd92eaaadc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041017688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.4041017688
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.4104355690
Short name T29
Test name
Test status
Simulation time 229083136 ps
CPU time 6.03 seconds
Started Jul 06 07:14:31 PM PDT 24
Finished Jul 06 07:16:02 PM PDT 24
Peak memory 200304 kb
Host smart-3853ab5c-41e3-4b09-a005-e412b272b3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104355690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.4104355690
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.2542578550
Short name T394
Test name
Test status
Simulation time 35394531214 ps
CPU time 2541.59 seconds
Started Jul 06 07:14:30 PM PDT 24
Finished Jul 06 07:58:24 PM PDT 24
Peak memory 786588 kb
Host smart-f8553ddf-9234-476a-9fd2-deccd819e16c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542578550 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2542578550
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.704094232
Short name T251
Test name
Test status
Simulation time 13057476312 ps
CPU time 121.81 seconds
Started Jul 06 07:14:32 PM PDT 24
Finished Jul 06 07:17:58 PM PDT 24
Peak memory 200388 kb
Host smart-591a2c4e-f1ef-4225-90cd-8064bc8ec3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704094232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.704094232
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1057533246
Short name T40
Test name
Test status
Simulation time 75077034 ps
CPU time 0.57 seconds
Started Jul 06 07:14:36 PM PDT 24
Finished Jul 06 07:15:57 PM PDT 24
Peak memory 195836 kb
Host smart-84be0cd4-d6e3-4da5-984b-bf8e458078f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057533246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1057533246
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2995767078
Short name T475
Test name
Test status
Simulation time 1213291819 ps
CPU time 32.31 seconds
Started Jul 06 07:14:38 PM PDT 24
Finished Jul 06 07:16:28 PM PDT 24
Peak memory 200356 kb
Host smart-015e6371-49f5-4b34-8f73-9cbf04345831
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2995767078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2995767078
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3196557717
Short name T205
Test name
Test status
Simulation time 975802183 ps
CPU time 56.36 seconds
Started Jul 06 07:14:37 PM PDT 24
Finished Jul 06 07:16:53 PM PDT 24
Peak memory 200300 kb
Host smart-b1707bec-ff08-423e-b40e-30665a2d292b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196557717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3196557717
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.928267087
Short name T505
Test name
Test status
Simulation time 6819200704 ps
CPU time 1388.01 seconds
Started Jul 06 07:14:36 PM PDT 24
Finished Jul 06 07:39:04 PM PDT 24
Peak memory 702196 kb
Host smart-00bc33da-902d-4092-91bd-a007ec5e6e1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=928267087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.928267087
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3370500009
Short name T134
Test name
Test status
Simulation time 32130992568 ps
CPU time 134.36 seconds
Started Jul 06 07:14:35 PM PDT 24
Finished Jul 06 07:18:17 PM PDT 24
Peak memory 200264 kb
Host smart-35d45336-eed3-4f55-8d8c-fb8769bb0fbf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370500009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3370500009
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2833461702
Short name T340
Test name
Test status
Simulation time 11067114685 ps
CPU time 89.66 seconds
Started Jul 06 07:14:36 PM PDT 24
Finished Jul 06 07:17:26 PM PDT 24
Peak memory 200652 kb
Host smart-40d2d571-2808-4c3c-8a78-eb4cbafa2de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833461702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2833461702
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3012717040
Short name T297
Test name
Test status
Simulation time 243705639 ps
CPU time 3.44 seconds
Started Jul 06 07:14:37 PM PDT 24
Finished Jul 06 07:16:00 PM PDT 24
Peak memory 200372 kb
Host smart-c8415a52-b9e6-42bf-a91e-3ddcc6d4f409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012717040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3012717040
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3695339060
Short name T65
Test name
Test status
Simulation time 1043656511523 ps
CPU time 2211.77 seconds
Started Jul 06 07:14:38 PM PDT 24
Finished Jul 06 07:52:49 PM PDT 24
Peak memory 731212 kb
Host smart-ed242a7a-6cdb-4770-8673-24d234991cfa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695339060 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3695339060
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2400453617
Short name T445
Test name
Test status
Simulation time 6992394860 ps
CPU time 93.48 seconds
Started Jul 06 07:14:36 PM PDT 24
Finished Jul 06 07:17:29 PM PDT 24
Peak memory 200388 kb
Host smart-b7831a92-6218-413d-8870-b412322b3391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400453617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2400453617
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1872036508
Short name T131
Test name
Test status
Simulation time 15026181 ps
CPU time 0.59 seconds
Started Jul 06 07:14:54 PM PDT 24
Finished Jul 06 07:16:08 PM PDT 24
Peak memory 196872 kb
Host smart-9ec36a25-0c40-4b3f-8493-2cccf0abd733
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872036508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1872036508
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2725854977
Short name T34
Test name
Test status
Simulation time 2231414734 ps
CPU time 61.96 seconds
Started Jul 06 07:14:44 PM PDT 24
Finished Jul 06 07:17:04 PM PDT 24
Peak memory 200400 kb
Host smart-129bc38e-db9e-411e-bf5b-ea5366249cf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2725854977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2725854977
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.3027124989
Short name T294
Test name
Test status
Simulation time 10527860747 ps
CPU time 34.59 seconds
Started Jul 06 07:14:47 PM PDT 24
Finished Jul 06 07:16:36 PM PDT 24
Peak memory 200380 kb
Host smart-8ccc5ed3-3b45-45f7-8801-d2959e08bb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027124989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.3027124989
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1994117574
Short name T367
Test name
Test status
Simulation time 938131786 ps
CPU time 196.27 seconds
Started Jul 06 07:14:58 PM PDT 24
Finished Jul 06 07:19:22 PM PDT 24
Peak memory 474192 kb
Host smart-5e8c4489-e04d-4adc-b54f-3055415d3f88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1994117574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1994117574
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.709322503
Short name T231
Test name
Test status
Simulation time 5940678037 ps
CPU time 175.36 seconds
Started Jul 06 07:14:42 PM PDT 24
Finished Jul 06 07:18:58 PM PDT 24
Peak memory 200324 kb
Host smart-ac5eeb11-65bb-4ac2-b4f6-fba0edf74793
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709322503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.709322503
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.14510486
Short name T327
Test name
Test status
Simulation time 30781410199 ps
CPU time 170.04 seconds
Started Jul 06 07:14:42 PM PDT 24
Finished Jul 06 07:18:50 PM PDT 24
Peak memory 200588 kb
Host smart-2ad185c4-aeb5-4a80-95f5-19556f146bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14510486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.14510486
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1437123160
Short name T435
Test name
Test status
Simulation time 618406784 ps
CPU time 13.49 seconds
Started Jul 06 07:15:00 PM PDT 24
Finished Jul 06 07:16:19 PM PDT 24
Peak memory 200364 kb
Host smart-07a5f38e-6a7d-476e-9233-7a42ed75a970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437123160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1437123160
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1643135935
Short name T488
Test name
Test status
Simulation time 59008514128 ps
CPU time 1763.52 seconds
Started Jul 06 07:14:42 PM PDT 24
Finished Jul 06 07:45:24 PM PDT 24
Peak memory 790072 kb
Host smart-0e43a3b1-87a8-49d6-9cfa-ba657aa6976c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643135935 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1643135935
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3703486024
Short name T472
Test name
Test status
Simulation time 5201511233 ps
CPU time 18.92 seconds
Started Jul 06 07:14:44 PM PDT 24
Finished Jul 06 07:16:21 PM PDT 24
Peak memory 200344 kb
Host smart-9140467b-9495-4990-a9f2-1c35f8e6c31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703486024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3703486024
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2036086398
Short name T381
Test name
Test status
Simulation time 32841262 ps
CPU time 0.59 seconds
Started Jul 06 07:11:14 PM PDT 24
Finished Jul 06 07:11:16 PM PDT 24
Peak memory 195844 kb
Host smart-b6fc88b4-468a-46e6-837b-1936ab967777
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036086398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2036086398
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.4213775275
Short name T233
Test name
Test status
Simulation time 844894853 ps
CPU time 53.07 seconds
Started Jul 06 07:11:09 PM PDT 24
Finished Jul 06 07:12:03 PM PDT 24
Peak memory 200348 kb
Host smart-4d54d7ec-9b14-4d26-a0de-036fc1bbafeb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4213775275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.4213775275
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1031180633
Short name T526
Test name
Test status
Simulation time 1071329859 ps
CPU time 63.57 seconds
Started Jul 06 07:11:07 PM PDT 24
Finished Jul 06 07:12:12 PM PDT 24
Peak memory 200384 kb
Host smart-bf8539b4-7ce2-4174-acd8-0f61fe0b228e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031180633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1031180633
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2872255078
Short name T517
Test name
Test status
Simulation time 16147425192 ps
CPU time 913.65 seconds
Started Jul 06 07:11:07 PM PDT 24
Finished Jul 06 07:26:22 PM PDT 24
Peak memory 672060 kb
Host smart-b5fca87b-4a33-4ccd-98ac-c98ba4524e55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2872255078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2872255078
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.2469491707
Short name T400
Test name
Test status
Simulation time 22631664174 ps
CPU time 64.15 seconds
Started Jul 06 07:11:09 PM PDT 24
Finished Jul 06 07:12:14 PM PDT 24
Peak memory 200304 kb
Host smart-df2a8965-b8d5-4507-9964-9a1f03a35390
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469491707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.2469491707
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1561342434
Short name T391
Test name
Test status
Simulation time 173929004577 ps
CPU time 148.04 seconds
Started Jul 06 07:11:06 PM PDT 24
Finished Jul 06 07:13:35 PM PDT 24
Peak memory 200404 kb
Host smart-e81b99c3-1084-49e3-9ca8-0f4d2560b87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561342434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1561342434
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3143054850
Short name T500
Test name
Test status
Simulation time 1121924361 ps
CPU time 10.14 seconds
Started Jul 06 07:11:11 PM PDT 24
Finished Jul 06 07:11:22 PM PDT 24
Peak memory 200304 kb
Host smart-f15fb885-7b2c-43fd-91e2-1451370df581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143054850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3143054850
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1459696551
Short name T119
Test name
Test status
Simulation time 69954584818 ps
CPU time 306.26 seconds
Started Jul 06 07:11:07 PM PDT 24
Finished Jul 06 07:16:15 PM PDT 24
Peak memory 216680 kb
Host smart-1c9da372-255e-4485-85c9-82d20d239d5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459696551 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1459696551
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3599585603
Short name T59
Test name
Test status
Simulation time 56728153660 ps
CPU time 1491.82 seconds
Started Jul 06 07:11:13 PM PDT 24
Finished Jul 06 07:36:07 PM PDT 24
Peak memory 437792 kb
Host smart-3509ffe0-ff48-4ba6-ac77-3bc226be03b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3599585603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3599585603
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3459019783
Short name T286
Test name
Test status
Simulation time 3622042814 ps
CPU time 72.32 seconds
Started Jul 06 07:11:07 PM PDT 24
Finished Jul 06 07:12:21 PM PDT 24
Peak memory 200364 kb
Host smart-b3f82fb8-6e5a-48db-9929-281dfe956bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459019783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3459019783
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.633090818
Short name T306
Test name
Test status
Simulation time 56772494 ps
CPU time 0.61 seconds
Started Jul 06 07:11:11 PM PDT 24
Finished Jul 06 07:11:12 PM PDT 24
Peak memory 196852 kb
Host smart-f76c62ee-fbe8-4598-8722-eb7f2d74e526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633090818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.633090818
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.4036067956
Short name T285
Test name
Test status
Simulation time 774105118 ps
CPU time 33.74 seconds
Started Jul 06 07:11:07 PM PDT 24
Finished Jul 06 07:11:42 PM PDT 24
Peak memory 200260 kb
Host smart-9aa44959-d356-4cfe-a078-d4f72dc94b92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4036067956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.4036067956
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1091367665
Short name T244
Test name
Test status
Simulation time 9912520963 ps
CPU time 45.6 seconds
Started Jul 06 07:11:09 PM PDT 24
Finished Jul 06 07:11:56 PM PDT 24
Peak memory 200376 kb
Host smart-bfda8a68-bcdc-4c03-b41d-585de8d2390b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091367665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1091367665
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.672037494
Short name T345
Test name
Test status
Simulation time 8276645724 ps
CPU time 782.69 seconds
Started Jul 06 07:11:06 PM PDT 24
Finished Jul 06 07:24:10 PM PDT 24
Peak memory 683536 kb
Host smart-a5d66eec-408c-43fe-b797-3483b336fcb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=672037494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.672037494
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3945784887
Short name T149
Test name
Test status
Simulation time 11950117296 ps
CPU time 161.8 seconds
Started Jul 06 07:11:10 PM PDT 24
Finished Jul 06 07:13:52 PM PDT 24
Peak memory 200392 kb
Host smart-79edec04-0db9-4262-ae40-7b22f3723974
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945784887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3945784887
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3717325763
Short name T469
Test name
Test status
Simulation time 7977423690 ps
CPU time 128.9 seconds
Started Jul 06 07:11:06 PM PDT 24
Finished Jul 06 07:13:15 PM PDT 24
Peak memory 216688 kb
Host smart-3b215e73-b1c0-4f35-9368-240d3dbe611c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717325763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3717325763
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3775162717
Short name T511
Test name
Test status
Simulation time 380521301 ps
CPU time 9.11 seconds
Started Jul 06 07:11:05 PM PDT 24
Finished Jul 06 07:11:15 PM PDT 24
Peak memory 200328 kb
Host smart-3d84a932-7272-432e-842b-b7772eb76118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775162717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3775162717
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.4285419636
Short name T503
Test name
Test status
Simulation time 28749823480 ps
CPU time 255.6 seconds
Started Jul 06 07:11:07 PM PDT 24
Finished Jul 06 07:15:24 PM PDT 24
Peak memory 200376 kb
Host smart-3e657ab7-8830-4b72-a104-7fdf632e9a38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285419636 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.4285419636
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.4164052357
Short name T126
Test name
Test status
Simulation time 499480873 ps
CPU time 12.65 seconds
Started Jul 06 07:11:09 PM PDT 24
Finished Jul 06 07:11:22 PM PDT 24
Peak memory 200320 kb
Host smart-2cb1a12d-7be4-4c73-b671-199df0efaa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164052357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.4164052357
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2230953129
Short name T181
Test name
Test status
Simulation time 24100184 ps
CPU time 0.6 seconds
Started Jul 06 07:11:12 PM PDT 24
Finished Jul 06 07:11:14 PM PDT 24
Peak memory 196164 kb
Host smart-daf95191-5edd-48cc-bd39-6a76f0198712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230953129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2230953129
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3562566923
Short name T200
Test name
Test status
Simulation time 275757998 ps
CPU time 14.85 seconds
Started Jul 06 07:11:09 PM PDT 24
Finished Jul 06 07:11:25 PM PDT 24
Peak memory 200252 kb
Host smart-3f5f5990-de11-44e9-9356-7e3c05eb485e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3562566923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3562566923
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2248848658
Short name T193
Test name
Test status
Simulation time 1506880930 ps
CPU time 87.66 seconds
Started Jul 06 07:11:07 PM PDT 24
Finished Jul 06 07:12:37 PM PDT 24
Peak memory 200360 kb
Host smart-df639920-a2fb-4b82-9509-361669954031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248848658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2248848658
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.650048627
Short name T72
Test name
Test status
Simulation time 30006521036 ps
CPU time 1384.3 seconds
Started Jul 06 07:11:13 PM PDT 24
Finished Jul 06 07:34:19 PM PDT 24
Peak memory 766584 kb
Host smart-6c74d1c8-90e0-4283-a454-c4cdbcd12a1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=650048627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.650048627
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1444858648
Short name T432
Test name
Test status
Simulation time 6117132380 ps
CPU time 114.32 seconds
Started Jul 06 07:11:07 PM PDT 24
Finished Jul 06 07:13:03 PM PDT 24
Peak memory 200332 kb
Host smart-74f64829-dd73-4a1a-9473-4a5d394063bb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444858648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1444858648
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2385318991
Short name T343
Test name
Test status
Simulation time 12043605254 ps
CPU time 161.28 seconds
Started Jul 06 07:11:09 PM PDT 24
Finished Jul 06 07:13:51 PM PDT 24
Peak memory 200368 kb
Host smart-ca867dc3-f756-4eae-803f-268da4f9d456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385318991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2385318991
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3002663679
Short name T202
Test name
Test status
Simulation time 72235320 ps
CPU time 2.95 seconds
Started Jul 06 07:11:11 PM PDT 24
Finished Jul 06 07:11:15 PM PDT 24
Peak memory 200304 kb
Host smart-b9941d5b-1d1f-4b3b-93f2-ec7f4a7b9ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002663679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3002663679
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.3528080279
Short name T35
Test name
Test status
Simulation time 130085784252 ps
CPU time 1788.5 seconds
Started Jul 06 07:11:12 PM PDT 24
Finished Jul 06 07:41:02 PM PDT 24
Peak memory 652288 kb
Host smart-f78738ba-37ac-446a-8fb2-1286aad5d820
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3528080279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.3528080279
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.985807256
Short name T183
Test name
Test status
Simulation time 4753534117 ps
CPU time 94.89 seconds
Started Jul 06 07:11:11 PM PDT 24
Finished Jul 06 07:12:46 PM PDT 24
Peak memory 200348 kb
Host smart-557d71b1-4855-4792-8104-3ed032b77fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985807256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.985807256
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1864648624
Short name T342
Test name
Test status
Simulation time 15684321 ps
CPU time 0.62 seconds
Started Jul 06 07:11:15 PM PDT 24
Finished Jul 06 07:11:17 PM PDT 24
Peak memory 196220 kb
Host smart-df0c8a08-626c-41f6-a423-05dd9cdcf9e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864648624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1864648624
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2785448463
Short name T406
Test name
Test status
Simulation time 15164924175 ps
CPU time 59.48 seconds
Started Jul 06 07:11:14 PM PDT 24
Finished Jul 06 07:12:15 PM PDT 24
Peak memory 200324 kb
Host smart-75271393-5fcc-4a04-9023-a07255d48993
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2785448463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2785448463
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1578898400
Short name T484
Test name
Test status
Simulation time 4283744262 ps
CPU time 56.89 seconds
Started Jul 06 07:11:12 PM PDT 24
Finished Jul 06 07:12:10 PM PDT 24
Peak memory 200356 kb
Host smart-e6d6eca1-b12f-4e41-af50-f606f73c8944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578898400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1578898400
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2899641033
Short name T187
Test name
Test status
Simulation time 4187737614 ps
CPU time 763.96 seconds
Started Jul 06 07:11:15 PM PDT 24
Finished Jul 06 07:24:00 PM PDT 24
Peak memory 670780 kb
Host smart-551fb2ca-79bf-40a1-a30f-047d63a69f63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2899641033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2899641033
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1164386503
Short name T366
Test name
Test status
Simulation time 4999907329 ps
CPU time 69.69 seconds
Started Jul 06 07:11:13 PM PDT 24
Finished Jul 06 07:12:24 PM PDT 24
Peak memory 200408 kb
Host smart-0628b37c-de9b-434a-9397-1718d9b64575
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164386503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1164386503
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.2849433277
Short name T353
Test name
Test status
Simulation time 2063720999 ps
CPU time 37.05 seconds
Started Jul 06 07:11:12 PM PDT 24
Finished Jul 06 07:11:50 PM PDT 24
Peak memory 200320 kb
Host smart-130c26b0-3fba-4663-afb2-0c48b81474ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849433277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2849433277
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.4057704769
Short name T141
Test name
Test status
Simulation time 717660726 ps
CPU time 3.29 seconds
Started Jul 06 07:11:13 PM PDT 24
Finished Jul 06 07:11:18 PM PDT 24
Peak memory 200300 kb
Host smart-ed7a5713-794d-4daa-a650-7b67a3314044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057704769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.4057704769
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3995159877
Short name T146
Test name
Test status
Simulation time 19203164891 ps
CPU time 1135.45 seconds
Started Jul 06 07:11:11 PM PDT 24
Finished Jul 06 07:30:07 PM PDT 24
Peak memory 703644 kb
Host smart-4f9b99ca-3482-46b0-a46f-cde086403186
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995159877 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3995159877
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.351657000
Short name T15
Test name
Test status
Simulation time 87596940454 ps
CPU time 1799.54 seconds
Started Jul 06 07:11:12 PM PDT 24
Finished Jul 06 07:41:14 PM PDT 24
Peak memory 697260 kb
Host smart-8403b7f7-5917-42e1-b4e0-83092cd44c35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=351657000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.351657000
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.3444637583
Short name T396
Test name
Test status
Simulation time 2703271686 ps
CPU time 125.48 seconds
Started Jul 06 07:11:14 PM PDT 24
Finished Jul 06 07:13:21 PM PDT 24
Peak memory 200324 kb
Host smart-1e0afe92-3ec6-4996-86fc-72eeb1ae31d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444637583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3444637583
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3479742537
Short name T168
Test name
Test status
Simulation time 12476302 ps
CPU time 0.61 seconds
Started Jul 06 07:11:12 PM PDT 24
Finished Jul 06 07:11:14 PM PDT 24
Peak memory 196224 kb
Host smart-0402be9d-a270-4df5-98a3-a4a7d2152b2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479742537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3479742537
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1701529811
Short name T465
Test name
Test status
Simulation time 2999650176 ps
CPU time 94.57 seconds
Started Jul 06 07:11:15 PM PDT 24
Finished Jul 06 07:12:51 PM PDT 24
Peak memory 200376 kb
Host smart-d572afb3-607b-40c3-a647-fd488e6b918d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1701529811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1701529811
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.1871300295
Short name T374
Test name
Test status
Simulation time 1390854081 ps
CPU time 72.4 seconds
Started Jul 06 07:11:13 PM PDT 24
Finished Jul 06 07:12:27 PM PDT 24
Peak memory 200260 kb
Host smart-df0f19ac-57e7-4712-b475-43f8451ded9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871300295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1871300295
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3993958061
Short name T524
Test name
Test status
Simulation time 5236422675 ps
CPU time 553.88 seconds
Started Jul 06 07:11:14 PM PDT 24
Finished Jul 06 07:20:30 PM PDT 24
Peak memory 730428 kb
Host smart-415e7d5b-954c-4728-9c59-b02c0121f058
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3993958061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3993958061
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2536685887
Short name T324
Test name
Test status
Simulation time 12324367894 ps
CPU time 220.08 seconds
Started Jul 06 07:11:14 PM PDT 24
Finished Jul 06 07:14:56 PM PDT 24
Peak memory 200340 kb
Host smart-bea36668-106a-477d-9d9d-67652eed2ffb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536685887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2536685887
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.69567588
Short name T278
Test name
Test status
Simulation time 1096206680 ps
CPU time 64.21 seconds
Started Jul 06 07:11:12 PM PDT 24
Finished Jul 06 07:12:18 PM PDT 24
Peak memory 200328 kb
Host smart-0aeec03d-9303-499f-abc6-451fea70d7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69567588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.69567588
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3922902485
Short name T185
Test name
Test status
Simulation time 349266005 ps
CPU time 4.52 seconds
Started Jul 06 07:11:12 PM PDT 24
Finished Jul 06 07:11:18 PM PDT 24
Peak memory 200320 kb
Host smart-c6b797a9-eaa7-4d69-82eb-ceb334c1bd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922902485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3922902485
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1283402945
Short name T317
Test name
Test status
Simulation time 93056687815 ps
CPU time 3740.78 seconds
Started Jul 06 07:11:13 PM PDT 24
Finished Jul 06 08:13:36 PM PDT 24
Peak memory 833872 kb
Host smart-195e7145-89e3-46fb-ba43-53d503d524c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283402945 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1283402945
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2526956217
Short name T225
Test name
Test status
Simulation time 14457651675 ps
CPU time 135.89 seconds
Started Jul 06 07:11:11 PM PDT 24
Finished Jul 06 07:13:28 PM PDT 24
Peak memory 200428 kb
Host smart-9afcc94d-8fae-4f4c-8a99-e9414c194027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526956217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2526956217
Directory /workspace/9.hmac_wipe_secret/latest
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