Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	19954220	1			T1	12044		T2	223717		T3	9157
all_values[1]	19954220	1			T1	12044		T2	223717		T3	9157
all_values[2]	19954220	1			T1	12044		T2	223717		T3	9157

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

256167

1

T1

1990

T2

6074

T4

94

auto[1]

59606493

1

T1

34142

T2

665077

T3

27471

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51019122

1

T1

25959

T2

551485

T3

23029

auto[1]

8843538

1

T1

10173

T2

119666

T3

4442

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	64173	1			T1	995		T2	673		T6	40
all_values[0]	auto[0]	auto[1]	331	1			T2	3		T6	2		T7	5
all_values[0]	auto[1]	auto[0]	19868109	1			T1	11049		T2	222882		T3	9145
all_values[0]	auto[1]	auto[1]	21607	1			T2	159		T3	12		T4	17
all_values[1]	auto[0]	auto[0]	103426	1			T1	995		T2	2152		T15	2
all_values[1]	auto[0]	auto[1]	196	1			T2	2		T7	6		T8	8
all_values[1]	auto[1]	auto[0]	19850210	1			T1	11049		T2	221559		T3	9157
all_values[1]	auto[1]	auto[1]	388	1			T2	4		T6	2		T7	5
all_values[2]	auto[0]	auto[0]	45708	1			T2	870		T4	94		T6	30
all_values[2]	auto[0]	auto[1]	42333	1			T2	2374		T6	18		T7	2
all_values[2]	auto[1]	auto[0]	11087496	1			T1	1871		T2	103349		T3	4727
all_values[2]	auto[1]	auto[1]	8778683	1			T1	10173		T2	117124		T3	4430