Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

147655

1

T1

14

T2

2050

T3

10

auto[1]

136576

1

T1

10

T2

898

T3

6

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	108761	1			T2	1308		T3	6		T4	1
len_1026_2046	6348	1			T2	28		T4	2		T5	5
len_514_1022	4452	1			T2	23		T5	2		T14	2
len_2_510	3674	1			T2	11		T4	9		T5	3
len_2056	170	1			T2	2		T15	2		T6	5
len_2048	357	1			T2	1		T6	12		T7	8
len_2040	188	1			T2	1		T15	3		T6	3
len_1032	254	1			T2	2		T4	3		T6	3
len_1024	1825	1			T2	5		T5	2		T15	2
len_1016	196	1			T2	3		T4	2		T6	6
len_520	235	1			T2	1		T4	3		T6	4
len_512	410	1			T2	7		T4	1		T15	5
len_504	308	1			T2	1		T4	2		T15	2
len_8	1360	1			T2	13		T6	30		T68	13
len_0	13578	1			T1	12		T2	68		T3	2

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

136

1

T4

1

T7

5

T28

4

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	57192	1			T2	951		T3	4		T4	1
auto[0]	len_1026_2046	3471	1			T2	18		T5	3		T6	53
auto[0]	len_514_1022	3009	1			T2	15		T5	2		T14	2
auto[0]	len_2_510	2655	1			T2	8		T4	3		T5	3
auto[0]	len_2056	83	1			T2	2		T6	2		T25	3
auto[0]	len_2048	206	1			T6	5		T7	4		T25	1
auto[0]	len_2040	105	1			T15	2		T6	1		T7	3
auto[0]	len_1032	114	1			T4	2		T7	4		T8	10
auto[0]	len_1024	296	1			T2	3		T5	2		T15	1
auto[0]	len_1016	106	1			T2	2		T4	2		T6	2
auto[0]	len_520	147	1			T2	1		T6	3		T7	19
auto[0]	len_512	262	1			T2	3		T4	1		T15	2
auto[0]	len_504	195	1			T2	1		T4	1		T15	2
auto[0]	len_8	97	1			T2	1		T128	1		T129	1
auto[0]	len_0	5890	1			T1	7		T2	20		T3	1
auto[1]	len_2050_plus	51569	1			T2	357		T3	2		T5	8
auto[1]	len_1026_2046	2877	1			T2	10		T4	2		T5	2
auto[1]	len_514_1022	1443	1			T2	8		T6	24		T7	31
auto[1]	len_2_510	1019	1			T2	3		T4	6		T6	25
auto[1]	len_2056	87	1			T15	2		T6	3		T7	1
auto[1]	len_2048	151	1			T2	1		T6	7		T7	4
auto[1]	len_2040	83	1			T2	1		T15	1		T6	2
auto[1]	len_1032	140	1			T2	2		T4	1		T6	3
auto[1]	len_1024	1529	1			T2	2		T15	1		T6	2
auto[1]	len_1016	90	1			T2	1		T6	4		T25	3
auto[1]	len_520	88	1			T4	3		T6	1		T7	1
auto[1]	len_512	148	1			T2	4		T15	3		T6	7
auto[1]	len_504	113	1			T4	1		T7	3		T8	7
auto[1]	len_8	1263	1			T2	12		T6	30		T68	13
auto[1]	len_0	7688	1			T1	5		T2	48		T3	1

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

86

1

T4

1

T7

2

T28

4

auto[1]

len_upper

50

1

T7

3

T34

1

T36

2