Group : hmac_env_pkg::hmac_env_cov::save_and_restore_cg
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Group : hmac_env_pkg::hmac_env_cov::save_and_restore_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv



Summary for Group hmac_env_pkg::hmac_env_cov::save_and_restore_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 9 0 9 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::save_and_restore_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_size_cp 3 0 3 100.00 100 1 1 0
save_and_restore_cp 3 0 3 100.00 100 1 1 0


Crosses for Group hmac_env_pkg::hmac_env_cov::save_and_restore_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
sar_type_x_digest_size 9 0 9 100.00 100 1 1 0


Summary for Variable digest_size_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for digest_size_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sha2_512 185 1 T39 1 T40 1 T28 2
sha2_384 219 1 T5 2 T6 1 T7 6
sha2_256 199 1 T4 1 T7 6 T66 1



Summary for Variable save_and_restore_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for save_and_restore_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
stop_and_continue 194 1 T7 4 T25 1 T22 1
different_context 210 1 T4 1 T5 1 T7 5
same_context 199 1 T5 1 T6 1 T7 3



Summary for Cross sar_type_x_digest_size

Samples crossed: save_and_restore_cp digest_size_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 9 0 9 100.00


Automatically Generated Cross Bins for sar_type_x_digest_size

Bins
save_and_restore_cpdigest_size_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
stop_and_continue sha2_512 64 1 T28 1 T130 1 T131 1
stop_and_continue sha2_384 78 1 T7 1 T25 1 T36 1
stop_and_continue sha2_256 52 1 T7 3 T22 1 T23 1
different_context sha2_512 67 1 T40 1 T28 1 T34 1
different_context sha2_384 76 1 T5 1 T7 4 T28 2
different_context sha2_256 67 1 T4 1 T7 1 T66 1
same_context sha2_512 54 1 T39 1 T23 2 T18 2
same_context sha2_384 65 1 T5 1 T6 1 T7 1
same_context sha2_256 80 1 T7 2 T8 1 T28 1

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