Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5099305 1 T1 871 T2 57368 T3 1381
auto[1] 3339595 1 T1 732 T2 38510 T3 3245


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3383313 1 T1 1581 T2 46728 T3 3081
auto[1] 5055587 1 T1 22 T2 49150 T3 1545


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3534501 1 T1 231 T2 20837 T3 1701
auto[1] 4904399 1 T1 1372 T2 75041 T3 2925


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5127349 1 T1 1579 T2 46327 T3 2192
auto[1] 3311551 1 T1 24 T2 49551 T3 2434


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 7527644 1 T1 1603 T2 94963 T3 4573
fifo_depth[1] 138588 1 T2 597 T3 40 T4 6
fifo_depth[2] 112987 1 T2 236 T3 10 T4 3
fifo_depth[3] 95373 1 T2 33 T3 3 T4 3
fifo_depth[4] 89107 1 T2 36 T4 1 T5 192
fifo_depth[5] 73027 1 T2 6 T4 1 T5 180
fifo_depth[6] 58839 1 T2 5 T5 158 T13 42
fifo_depth[7] 39281 1 T2 1 T5 94 T13 22


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 911256 1 T2 915 T3 53 T4 14
auto[1] 7527644 1 T1 1603 T2 94963 T3 4573


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8426481 1 T1 1603 T2 95878 T3 4626
auto[1] 12419 1 T22 1 T8 283 T23 4


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 34948 1 T2 34 T3 19 T4 1
auto[0] auto[0] auto[0] auto[0] auto[1] 41274 1 T2 65 T3 9 T4 1
auto[0] auto[0] auto[0] auto[1] auto[0] 40353 1 T2 32 T14 11 T6 48
auto[0] auto[0] auto[0] auto[1] auto[1] 40734 1 T2 24 T14 42 T6 10
auto[0] auto[0] auto[1] auto[0] auto[0] 151311 1 T2 3 T5 69 T6 39
auto[0] auto[0] auto[1] auto[0] auto[1] 49570 1 T2 49 T5 291 T13 61
auto[0] auto[0] auto[1] auto[1] auto[0] 47954 1 T2 96 T3 11 T5 253
auto[0] auto[0] auto[1] auto[1] auto[1] 43588 1 T2 32 T14 51 T6 21
auto[0] auto[1] auto[0] auto[0] auto[0] 62843 1 T2 15 T4 7 T5 187
auto[0] auto[1] auto[0] auto[0] auto[1] 58764 1 T2 154 T5 12 T13 190
auto[0] auto[1] auto[0] auto[1] auto[0] 65704 1 T2 42 T14 30 T6 39
auto[0] auto[1] auto[0] auto[1] auto[1] 56121 1 T2 11 T5 197 T14 48
auto[0] auto[1] auto[1] auto[0] auto[0] 58594 1 T2 21 T3 2 T4 2
auto[0] auto[1] auto[1] auto[0] auto[1] 55036 1 T2 161 T3 12 T4 3
auto[0] auto[1] auto[1] auto[1] auto[0] 51717 1 T2 93 T5 123 T13 153
auto[0] auto[1] auto[1] auto[1] auto[1] 52745 1 T2 83 T6 71 T7 143
auto[1] auto[0] auto[0] auto[0] auto[0] 186969 1 T1 4 T2 1557 T3 514
auto[1] auto[0] auto[0] auto[0] auto[1] 188495 1 T2 3740 T3 431 T4 46
auto[1] auto[0] auto[0] auto[1] auto[0] 196574 1 T1 205 T2 3492 T4 13
auto[1] auto[0] auto[0] auto[1] auto[1] 188362 1 T1 1 T2 1431 T3 475
auto[1] auto[0] auto[1] auto[0] auto[0] 1741774 1 T2 478 T4 13 T5 626
auto[1] auto[0] auto[1] auto[0] auto[1] 187247 1 T1 20 T2 3098 T3 15
auto[1] auto[0] auto[1] auto[1] auto[0] 204697 1 T2 4361 T3 227 T4 13
auto[1] auto[0] auto[1] auto[1] auto[1] 190651 1 T1 1 T2 2345 T4 53
auto[1] auto[1] auto[0] auto[0] auto[0] 544026 1 T1 846 T2 10207 T4 77
auto[1] auto[1] auto[0] auto[0] auto[1] 542944 1 T2 14014 T4 58 T5 425
auto[1] auto[1] auto[0] auto[1] auto[0] 591445 1 T1 524 T2 9616 T3 967
auto[1] auto[1] auto[0] auto[1] auto[1] 543757 1 T1 1 T2 2294 T3 666
auto[1] auto[1] auto[1] auto[0] auto[0] 631433 1 T2 11090 T3 23 T4 56
auto[1] auto[1] auto[1] auto[0] auto[1] 564077 1 T1 1 T2 12682 T3 356
auto[1] auto[1] auto[1] auto[1] auto[0] 517007 1 T2 5190 T3 429 T4 1
auto[1] auto[1] auto[1] auto[1] auto[1] 508186 1 T2 9368 T3 470 T4 11


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 220963 1 T1 4 T2 1591 T3 533
auto[0] auto[0] auto[0] auto[0] auto[1] 228998 1 T2 3805 T3 440 T4 47
auto[0] auto[0] auto[0] auto[1] auto[0] 236015 1 T1 205 T2 3524 T4 13
auto[0] auto[0] auto[0] auto[1] auto[1] 228584 1 T1 1 T2 1455 T3 475
auto[0] auto[0] auto[1] auto[0] auto[0] 1892059 1 T2 481 T4 13 T5 695
auto[0] auto[0] auto[1] auto[0] auto[1] 235680 1 T1 20 T2 3147 T3 15
auto[0] auto[0] auto[1] auto[1] auto[0] 251467 1 T2 4457 T3 238 T4 13
auto[0] auto[0] auto[1] auto[1] auto[1] 233066 1 T1 1 T2 2377 T4 53
auto[0] auto[1] auto[0] auto[0] auto[0] 605531 1 T1 846 T2 10222 T4 84
auto[0] auto[1] auto[0] auto[0] auto[1] 600933 1 T2 14168 T4 58 T5 437
auto[0] auto[1] auto[0] auto[1] auto[0] 656241 1 T1 524 T2 9658 T3 967
auto[0] auto[1] auto[0] auto[1] auto[1] 599570 1 T1 1 T2 2305 T3 666
auto[0] auto[1] auto[1] auto[0] auto[0] 689443 1 T2 11111 T3 25 T4 58
auto[0] auto[1] auto[1] auto[0] auto[1] 618843 1 T1 1 T2 12843 T3 368
auto[0] auto[1] auto[1] auto[1] auto[0] 568639 1 T2 5283 T3 429 T4 1
auto[0] auto[1] auto[1] auto[1] auto[1] 560449 1 T2 9451 T3 470 T4 11
auto[1] auto[0] auto[0] auto[0] auto[0] 954 1 T22 1 T55 4 T20 86
auto[1] auto[0] auto[0] auto[0] auto[1] 771 1 T8 27 T23 1 T115 2
auto[1] auto[0] auto[0] auto[1] auto[0] 912 1 T8 1 T23 1 T20 40
auto[1] auto[0] auto[0] auto[1] auto[1] 512 1 T8 45 T23 1 T115 5
auto[1] auto[0] auto[1] auto[0] auto[0] 1026 1 T8 7 T23 1 T55 7
auto[1] auto[0] auto[1] auto[0] auto[1] 1137 1 T8 46 T55 82 T58 1
auto[1] auto[0] auto[1] auto[1] auto[0] 1184 1 T8 33 T115 101 T55 164
auto[1] auto[0] auto[1] auto[1] auto[1] 1173 1 T8 21 T20 14 T19 5
auto[1] auto[1] auto[0] auto[0] auto[0] 1338 1 T55 15 T20 25 T132 1
auto[1] auto[1] auto[0] auto[0] auto[1] 775 1 T115 4 T20 4 T133 2
auto[1] auto[1] auto[0] auto[1] auto[0] 908 1 T8 21 T132 96 T134 1
auto[1] auto[1] auto[0] auto[1] auto[1] 308 1 T8 13 T20 120 T19 11
auto[1] auto[1] auto[1] auto[0] auto[0] 584 1 T8 60 T55 2 T20 77
auto[1] auto[1] auto[1] auto[0] auto[1] 270 1 T8 9 T55 4 T19 9
auto[1] auto[1] auto[1] auto[1] auto[0] 85 1 T115 12 T55 22 T20 31
auto[1] auto[1] auto[1] auto[1] auto[1] 482 1 T115 3 T58 112 T133 11


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 186969 1 T1 4 T2 1557 T3 514
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 188495 1 T2 3740 T3 431 T4 46
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 196574 1 T1 205 T2 3492 T4 13
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 188362 1 T1 1 T2 1431 T3 475
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1741774 1 T2 478 T4 13 T5 626
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 187247 1 T1 20 T2 3098 T3 15
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 204697 1 T2 4361 T3 227 T4 13
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 190651 1 T1 1 T2 2345 T4 53
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 544026 1 T1 846 T2 10207 T4 77
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 542944 1 T2 14014 T4 58 T5 425
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 591445 1 T1 524 T2 9616 T3 967
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 543757 1 T1 1 T2 2294 T3 666
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 631433 1 T2 11090 T3 23 T4 56
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 564077 1 T1 1 T2 12682 T3 356
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 517007 1 T2 5190 T3 429 T4 1
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 508186 1 T2 9368 T3 470 T4 11
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 3947 1 T2 20 T3 17 T5 32
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 4516 1 T2 39 T3 7 T4 1
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 4123 1 T2 9 T14 4 T6 8
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 4395 1 T2 18 T14 25 T6 7
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 42341 1 T5 13 T6 21 T7 21
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 5070 1 T2 36 T5 46 T13 18
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 4778 1 T2 28 T3 7 T5 36
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 4711 1 T2 26 T14 32 T6 12
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 8377 1 T2 3 T4 3 T5 42
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 7375 1 T2 117 T5 1 T13 38
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 8705 1 T2 33 T14 19 T6 20
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 7699 1 T2 7 T5 31 T14 29
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 9011 1 T2 18 T5 19 T6 62
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 7847 1 T2 108 T3 9 T4 2
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 7597 1 T2 71 T5 22 T13 22
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 8096 1 T2 64 T6 51 T7 101
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 3443 1 T2 5 T3 2 T4 1
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 3763 1 T2 20 T3 2 T5 7
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 4174 1 T2 16 T14 5 T6 12
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 3847 1 T2 4 T14 13 T7 30
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 26992 1 T2 2 T5 10 T6 8
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 4423 1 T2 8 T5 43 T13 11
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 4171 1 T2 47 T3 3 T5 41
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 3940 1 T2 5 T14 16 T6 5
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 7624 1 T2 9 T4 1 T5 39
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 6605 1 T2 34 T5 1 T13 31
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 7947 1 T2 7 T14 8 T6 13
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 7020 1 T2 3 T5 29 T14 13
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 7582 1 T2 2 T3 1 T4 1
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 7264 1 T2 38 T3 2 T14 1
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 6970 1 T2 19 T5 15 T13 19
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 7222 1 T2 17 T6 14 T7 25
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 2572 1 T2 4 T5 28 T6 2
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 3035 1 T5 5 T14 1 T6 1
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 3167 1 T2 4 T14 2 T6 9
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 3231 1 T2 1 T14 4 T7 9
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 19303 1 T5 6 T6 2 T25 1
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 3767 1 T2 2 T5 46 T13 11
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 3510 1 T2 1 T3 1 T5 38
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 3385 1 T2 1 T14 3 T6 2
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 7063 1 T2 1 T4 2 T5 34
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 6205 1 T2 3 T5 2 T13 30
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 7314 1 T2 1 T14 3 T6 4
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 6409 1 T2 1 T5 31 T14 5
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 6853 1 T2 1 T3 1 T4 1
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 6657 1 T2 9 T3 1 T14 2
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 6449 1 T2 2 T5 26 T13 27
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 6453 1 T2 2 T6 2 T7 9
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2667 1 T2 2 T5 31 T7 1
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 3344 1 T2 2 T5 8 T7 5
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 3355 1 T2 2 T6 5 T7 2
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 3270 1 T2 1 T6 3 T7 13
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 14337 1 T2 1 T5 9 T6 4
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 3665 1 T2 1 T5 34 T13 5
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 3481 1 T2 20 T5 37 T6 9
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 3028 1 T6 1 T7 12 T44 1
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 6860 1 T2 2 T5 20 T6 7
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 6195 1 T5 2 T13 35 T7 29
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 7145 1 T2 1 T6 1 T7 5
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 6210 1 T5 22 T14 1 T7 1
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 6487 1 T5 10 T6 4 T68 81
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 6382 1 T2 3 T4 1 T14 1
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 6371 1 T2 1 T5 19 T13 21
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 6310 1 T6 2 T7 2 T40 96
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 2052 1 T2 1 T5 25 T22 8
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 2523 1 T2 1 T5 4 T14 1
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 2385 1 T2 1 T6 5 T8 44
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 2519 1 T7 1 T25 2 T69 7
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 10728 1 T5 8 T6 4 T25 1
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 2966 1 T2 2 T5 32 T13 4
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 2614 1 T5 31 T69 16 T8 57
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 2485 1 T6 1 T7 1 T66 1
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 5808 1 T4 1 T5 17 T6 1
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 5507 1 T5 1 T13 27 T7 17
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 6137 1 T6 1 T7 5 T68 75
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 5373 1 T5 36 T68 88 T8 88
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 5517 1 T5 12 T25 2 T68 70
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 5650 1 T2 1 T7 1 T25 2
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 5444 1 T5 14 T13 27 T6 4
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 5319 1 T6 1 T7 2 T40 82
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1755 1 T2 1 T5 19 T22 72
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 2129 1 T2 3 T5 8 T7 1
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 2453 1 T6 6 T8 34 T36 4
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 2207 1 T7 1 T25 2 T69 4
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 7343 1 T5 8 T25 2 T8 165
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 2351 1 T5 29 T13 5 T6 4
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 2122 1 T5 31 T69 10 T8 38
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1857 1 T7 2 T8 126 T114 7
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 4827 1 T5 17 T6 1 T40 2
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 4514 1 T5 1 T13 18 T7 7
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 4878 1 T68 70 T39 1 T40 37
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 4486 1 T5 24 T68 69 T8 43
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 4344 1 T5 6 T25 3 T68 69
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 4688 1 T2 1 T6 1 T7 1
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 4564 1 T5 15 T13 19 T6 3
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 4321 1 T6 1 T7 2 T40 69
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 1009 1 T5 5 T25 1 T22 9
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 1350 1 T5 3 T7 2 T8 28
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 1470 1 T6 2 T8 13 T23 40
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 1461 1 T25 1 T69 6 T8 79
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 4590 1 T5 5 T8 75 T135 6
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 1656 1 T5 23 T13 6 T69 1
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 1475 1 T5 23 T69 8 T8 13
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 1225 1 T8 112 T114 5 T78 6
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 3202 1 T5 10 T8 49 T9 2
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 3300 1 T5 1 T13 5 T7 2
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 3391 1 T68 64 T40 26 T8 56
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 3003 1 T5 11 T68 63 T8 34
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 3051 1 T5 7 T6 1 T25 1
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 3244 1 T2 1 T7 1 T25 2
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 2999 1 T5 6 T13 11 T6 1
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 2855 1 T7 2 T40 43 T8 73

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