Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	19954220	1			T1	12044		T2	223717		T3	9157
all_pins[1]	19954220	1			T1	12044		T2	223717		T3	9157
all_pins[2]	19954220	1			T1	12044		T2	223717		T3	9157

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	51060983	1			T1	25959		T2	553859		T3	23029
values[0x1]	8801677	1			T1	10173		T2	117292		T3	4442
transitions[0x0=>0x1]	8801525	1			T1	10173		T2	117292		T3	4442
transitions[0x1=>0x0]	8801535	1			T1	10173		T2	117292		T3	4442

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	19931652	1			T1	12044		T2	223553		T3	9145
all_pins[0]	values[0x1]	22568	1			T2	164		T3	12		T4	17
all_pins[0]	transitions[0x0=>0x1]	22508	1			T2	164		T3	12		T4	17
all_pins[0]	transitions[0x1=>0x0]	8778633	1			T1	10173		T2	117124		T3	4430
all_pins[1]	values[0x0]	19953794	1			T1	12044		T2	223713		T3	9157
all_pins[1]	values[0x1]	426	1			T2	4		T6	2		T7	5
all_pins[1]	transitions[0x0=>0x1]	384	1			T2	4		T6	2		T7	3
all_pins[1]	transitions[0x1=>0x0]	22526	1			T2	164		T3	12		T4	17
all_pins[2]	values[0x0]	11175537	1			T1	1871		T2	106593		T3	4727
all_pins[2]	values[0x1]	8778683	1			T1	10173		T2	117124		T3	4430
all_pins[2]	transitions[0x0=>0x1]	8778633	1			T1	10173		T2	117124		T3	4430
all_pins[2]	transitions[0x1=>0x0]	376	1			T2	4		T6	1		T7	5