Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	18	0	18	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	18	0	18	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	1019	1			T2	11		T6	7		T7	22
all_values[1]	1019	1			T2	11		T6	7		T7	22
all_values[2]	1019	1			T2	11		T6	7		T7	22

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1497

1

T2

17

T6

13

T7

21

auto[1]

1560

1

T2

16

T6

8

T7

45

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1172

1

T2

15

T6

7

T7

28

auto[1]

1885

1

T2

18

T6

14

T7

38

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1774

1

T2

21

T6

10

T7

39

auto[1]

1283

1

T2

12

T6

11

T7

27

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	18	0	18	100.00
Automatically Generated Cross Bins	18	0	18	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

192

1

T2

1

T6

1

T7

2

all_values[0]

auto[0]

auto[0]

auto[1]

93

1

T2

1

T7

1

T8

1

all_values[0]

auto[0]

auto[1]

auto[0]

213

1

T2

6

T6

1

T7

7

all_values[0]

auto[0]

auto[1]

auto[1]

93

1

T6

1

T7

2

T8

2

all_values[0]

auto[1]

auto[0]

auto[1]

187

1

T2

1

T6

4

T7

1

all_values[0]

auto[1]

auto[1]

auto[1]

241

1

T2

2

T7

9

T8

9

all_values[1]

auto[0]

auto[0]

auto[0]

176

1

T2

2

T6

4

T8

3

all_values[1]

auto[0]

auto[0]

auto[1]

110

1

T2

1

T7

3

T8

6

all_values[1]

auto[0]

auto[1]

auto[0]

174

1

T7

4

T28

3

T9

2

all_values[1]

auto[0]

auto[1]

auto[1]

135

1

T2

2

T6

1

T7

4

all_values[1]

auto[1]

auto[0]

auto[1]

198

1

T2

3

T7

3

T8

5

all_values[1]

auto[1]

auto[1]

auto[1]

226

1

T2

3

T6

2

T7

8

all_values[2]

auto[0]

auto[0]

auto[0]

225

1

T2

5

T6

1

T7

7

all_values[2]

auto[0]

auto[0]

auto[1]

86

1

T2

2

T6

1

T8

3

all_values[2]

auto[0]

auto[1]

auto[0]

192

1

T2

1

T7

8

T8

8

all_values[2]

auto[0]

auto[1]

auto[1]

85

1

T7

1

T8

2

T9

1

all_values[2]

auto[1]

auto[0]

auto[1]

230

1

T2

1

T6

2

T7

4

all_values[2]

auto[1]

auto[1]

auto[1]

201

1

T2

2

T6

3

T7

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal