Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4671	1			T1	2		T2	68		T3	4
sha2_none	4832	1			T1	3		T2	55		T3	1
sha2_512	8204	1			T1	1		T2	71		T3	4
sha2_384	7930	1			T1	1		T2	56		T3	3
sha2_256	7006	1			T1	1		T2	66		T3	2

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20232

1

T1

4

T2

159

T3

6

auto[1]

12852

1

T1

4

T2

162

T3

10

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12656

1

T1

6

T2

157

T3

10

auto[1]

20428

1

T1

2

T2

164

T3

6

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

17399

1

T1

3

T2

189

T3

9

disabled

15685

1

T1

5

T2

132

T3

7

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5268	1			T1	2		T2	65		T3	2
key_none	8151	1			T1	1		T2	43		T3	2
key_1024	4810	1			T2	40		T3	4		T4	4
key_512	4124	1			T2	53		T3	1		T4	4
key_384	3838	1			T1	1		T2	33		T3	3
key_256	3424	1			T1	3		T2	40		T3	2
key_128	3378	1			T1	1		T2	43		T3	2

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20312

1

T1

5

T2

167

T3

8

auto[1]

12772

1

T1

3

T2

154

T3

8

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

32905

1

T1

8

T2

318

T3

16

disabled

179

1

T2

3

T6

2

T44

2

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1788

1

T1

2

T2

20

T4

5

enabled

auto[0]

auto[0]

auto[1]

1790

1

T2

26

T4

2

T5

3

enabled

auto[0]

auto[1]

auto[0]

1842

1

T1

1

T2

28

T3

3

enabled

auto[0]

auto[1]

auto[1]

1856

1

T2

17

T3

2

T4

3

enabled

auto[1]

auto[0]

auto[0]

4505

1

T2

29

T3

1

T4

4

enabled

auto[1]

auto[0]

auto[1]

1876

1

T2

24

T3

1

T4

4

enabled

auto[1]

auto[1]

auto[0]

1947

1

T2

25

T3

1

T4

1

enabled

auto[1]

auto[1]

auto[1]

1795

1

T2

20

T3

1

T4

1

disabled

auto[0]

auto[0]

auto[0]

1316

1

T1

1

T2

12

T3

2

disabled

auto[0]

auto[0]

auto[1]

1383

1

T2

19

T3

1

T4

2

disabled

auto[0]

auto[1]

auto[0]

1352

1

T1

1

T2

23

T4

2

disabled

auto[0]

auto[1]

auto[1]

1329

1

T1

1

T2

12

T3

2

disabled

auto[1]

auto[0]

auto[0]

6178

1

T2

12

T4

2

T5

3

disabled

auto[1]

auto[0]

auto[1]

1396

1

T1

1

T2

17

T3

1

disabled

auto[1]

auto[1]

auto[0]

1384

1

T2

18

T3

1

T4

1

disabled

auto[1]

auto[1]

auto[1]

1347

1

T1

1

T2

19

T4

3

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

17325

1

T1

3

T2

188

T3

9

enabled

disabled

74

1

T2

1

T6

1

T8

1

disabled

disabled

105

1

T2

2

T6

1

T44

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15580

1

T1

5

T2

130

T3

7

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1200	1			T2	16		T4	2		T13	1
key_invalid	sha2_none	1024	1			T1	2		T2	10		T5	3
key_invalid	sha2_512	1008	1			T2	17		T4	1		T5	2
key_invalid	sha2_384	917	1			T2	8		T5	1		T14	2
key_invalid	sha2_256	997	1			T2	12		T3	1		T4	2
key_none	sha2_invalid	588	1			T2	7		T3	1		T4	1
key_none	sha2_none	620	1			T2	10		T4	1		T5	1
key_none	sha2_512	2622	1			T1	1		T2	9		T4	2
key_none	sha2_384	2614	1			T2	8		T3	1		T4	1
key_none	sha2_256	1656	1			T2	9		T4	2		T5	3
key_1024	sha2_invalid	611	1			T2	10		T3	1		T4	1
key_1024	sha2_none	602	1			T2	6		T4	1		T5	1
key_1024	sha2_512	1855	1			T2	9		T5	2		T14	1
key_1024	sha2_384	982	1			T2	7		T3	1		T4	2
key_512	sha2_invalid	562	1			T2	11		T3	1		T6	6
key_512	sha2_none	643	1			T2	10		T5	1		T13	1
key_512	sha2_512	656	1			T2	8		T4	1		T5	1
key_512	sha2_384	1292	1			T2	12		T4	1		T5	2
key_512	sha2_256	916	1			T2	11		T4	2		T5	3
key_384	sha2_invalid	552	1			T2	4		T4	1		T5	1
key_384	sha2_none	660	1			T2	7		T3	1		T4	2
key_384	sha2_512	689	1			T2	9		T3	2		T5	1
key_384	sha2_384	723	1			T1	1		T2	7		T4	1
key_384	sha2_256	1166	1			T2	4		T4	2		T13	1
key_256	sha2_invalid	573	1			T1	1		T2	9		T3	1
key_256	sha2_none	628	1			T1	1		T2	5		T4	2
key_256	sha2_512	648	1			T2	4		T3	1		T4	1
key_256	sha2_384	692	1			T2	10		T5	2		T14	1
key_256	sha2_256	827	1			T1	1		T2	12		T5	2
key_128	sha2_invalid	561	1			T1	1		T2	9		T4	1
key_128	sha2_none	638	1			T2	7		T4	2		T5	1
key_128	sha2_512	710	1			T2	15		T3	1		T4	3
key_128	sha2_384	690	1			T2	2		T3	1		T14	1
key_128	sha2_256	727	1			T2	10		T13	1		T14	1

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

706

1

T2

8

T3

1

T5

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1200	1			T2	16		T4	2		T13	1
key_invalid	sha2_none	1024	1			T1	2		T2	10		T5	3
key_invalid	sha2_512	1008	1			T2	17		T4	1		T5	2
key_invalid	sha2_384	917	1			T2	8		T5	1		T14	2
key_invalid	sha2_256	997	1			T2	12		T3	1		T4	2
key_none	sha2_invalid	588	1			T2	7		T3	1		T4	1
key_none	sha2_none	620	1			T2	10		T4	1		T5	1
key_none	sha2_512	2622	1			T1	1		T2	9		T4	2
key_none	sha2_384	2614	1			T2	8		T3	1		T4	1
key_none	sha2_256	1656	1			T2	9		T4	2		T5	3
key_1024	sha2_invalid	611	1			T2	10		T3	1		T4	1
key_1024	sha2_none	602	1			T2	6		T4	1		T5	1
key_1024	sha2_512	1855	1			T2	9		T5	2		T14	1
key_1024	sha2_384	982	1			T2	7		T3	1		T4	2
key_1024	sha2_256	706	1			T2	8		T3	1		T5	1
key_512	sha2_invalid	562	1			T2	11		T3	1		T6	6
key_512	sha2_none	643	1			T2	10		T5	1		T13	1
key_512	sha2_512	656	1			T2	8		T4	1		T5	1
key_512	sha2_384	1292	1			T2	12		T4	1		T5	2
key_512	sha2_256	916	1			T2	11		T4	2		T5	3
key_384	sha2_invalid	552	1			T2	4		T4	1		T5	1
key_384	sha2_none	660	1			T2	7		T3	1		T4	2
key_384	sha2_512	689	1			T2	9		T3	2		T5	1
key_384	sha2_384	723	1			T1	1		T2	7		T4	1
key_384	sha2_256	1166	1			T2	4		T4	2		T13	1
key_256	sha2_invalid	573	1			T1	1		T2	9		T3	1
key_256	sha2_none	628	1			T1	1		T2	5		T4	2
key_256	sha2_512	648	1			T2	4		T3	1		T4	1
key_256	sha2_384	692	1			T2	10		T5	2		T14	1
key_256	sha2_256	827	1			T1	1		T2	12		T5	2
key_128	sha2_invalid	561	1			T1	1		T2	9		T4	1
key_128	sha2_none	638	1			T2	7		T4	2		T5	1
key_128	sha2_512	710	1			T2	15		T3	1		T4	3
key_128	sha2_384	690	1			T2	2		T3	1		T14	1
key_128	sha2_256	727	1			T2	10		T13	1		T14	1