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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.46 95.40 97.22 100.00 100.00 98.27 98.48 99.85


Total test records in report: 660
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T99 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2119614351 Jul 09 05:30:33 PM PDT 24 Jul 09 05:30:44 PM PDT 24 934018862 ps
T107 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3851676347 Jul 09 05:30:52 PM PDT 24 Jul 09 05:30:59 PM PDT 24 176504501 ps
T536 /workspace/coverage/cover_reg_top/17.hmac_intr_test.657689686 Jul 09 05:30:47 PM PDT 24 Jul 09 05:30:49 PM PDT 24 31431437 ps
T537 /workspace/coverage/cover_reg_top/9.hmac_intr_test.3276224725 Jul 09 05:30:44 PM PDT 24 Jul 09 05:30:46 PM PDT 24 11804709 ps
T538 /workspace/coverage/cover_reg_top/19.hmac_intr_test.661659489 Jul 09 05:30:50 PM PDT 24 Jul 09 05:30:55 PM PDT 24 26807538 ps
T91 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1047912118 Jul 09 05:30:50 PM PDT 24 Jul 09 05:30:54 PM PDT 24 264405521 ps
T539 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1126432860 Jul 09 05:30:25 PM PDT 24 Jul 09 05:30:30 PM PDT 24 562268815 ps
T108 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1224417024 Jul 09 05:30:52 PM PDT 24 Jul 09 05:30:57 PM PDT 24 68340396 ps
T540 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2440885494 Jul 09 05:30:50 PM PDT 24 Jul 09 05:30:55 PM PDT 24 30637372 ps
T60 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1706642343 Jul 09 05:30:47 PM PDT 24 Jul 09 05:30:53 PM PDT 24 469234517 ps
T541 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3899185455 Jul 09 05:30:45 PM PDT 24 Jul 09 05:30:49 PM PDT 24 2095630946 ps
T542 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2011763074 Jul 09 05:30:50 PM PDT 24 Jul 09 05:30:58 PM PDT 24 82527222 ps
T543 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1904309617 Jul 09 05:30:46 PM PDT 24 Jul 09 05:30:48 PM PDT 24 18610523 ps
T109 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2679887791 Jul 09 05:30:52 PM PDT 24 Jul 09 05:30:58 PM PDT 24 1002918315 ps
T110 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3483298951 Jul 09 05:30:50 PM PDT 24 Jul 09 05:30:54 PM PDT 24 87173118 ps
T544 /workspace/coverage/cover_reg_top/23.hmac_intr_test.3972169613 Jul 09 05:30:52 PM PDT 24 Jul 09 05:30:56 PM PDT 24 44104260 ps
T61 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3362004360 Jul 09 05:30:44 PM PDT 24 Jul 09 05:30:49 PM PDT 24 552097970 ps
T545 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.413907175 Jul 09 05:30:49 PM PDT 24 Jul 09 05:30:54 PM PDT 24 63645975 ps
T62 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3131064214 Jul 09 05:30:46 PM PDT 24 Jul 09 05:30:52 PM PDT 24 295771315 ps
T546 /workspace/coverage/cover_reg_top/45.hmac_intr_test.902244196 Jul 09 05:30:52 PM PDT 24 Jul 09 05:30:57 PM PDT 24 15216831 ps
T547 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1705804693 Jul 09 05:30:45 PM PDT 24 Jul 09 05:30:49 PM PDT 24 47454002 ps
T548 /workspace/coverage/cover_reg_top/39.hmac_intr_test.851209850 Jul 09 05:30:49 PM PDT 24 Jul 09 05:30:52 PM PDT 24 13747950 ps
T549 /workspace/coverage/cover_reg_top/46.hmac_intr_test.3283197719 Jul 09 05:30:50 PM PDT 24 Jul 09 05:30:55 PM PDT 24 33292726 ps
T550 /workspace/coverage/cover_reg_top/10.hmac_intr_test.476635808 Jul 09 05:30:48 PM PDT 24 Jul 09 05:30:51 PM PDT 24 43458887 ps
T551 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1243804668 Jul 09 05:30:25 PM PDT 24 Jul 09 05:30:30 PM PDT 24 172839632 ps
T92 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.884410693 Jul 09 05:30:34 PM PDT 24 Jul 09 05:30:40 PM PDT 24 478048032 ps
T552 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2983592062 Jul 09 05:30:52 PM PDT 24 Jul 09 05:30:58 PM PDT 24 28013077 ps
T553 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1218048543 Jul 09 05:30:43 PM PDT 24 Jul 09 05:34:05 PM PDT 24 20450498950 ps
T554 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1229139631 Jul 09 05:30:23 PM PDT 24 Jul 09 05:30:25 PM PDT 24 52501817 ps
T555 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1740391837 Jul 09 05:30:44 PM PDT 24 Jul 09 05:30:47 PM PDT 24 148717563 ps
T556 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2013960098 Jul 09 05:30:45 PM PDT 24 Jul 09 05:30:48 PM PDT 24 305454255 ps
T93 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1849701081 Jul 09 05:30:19 PM PDT 24 Jul 09 05:30:27 PM PDT 24 618519587 ps
T557 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2380070988 Jul 09 05:30:51 PM PDT 24 Jul 09 05:30:56 PM PDT 24 52035312 ps
T558 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2309423848 Jul 09 05:30:46 PM PDT 24 Jul 09 05:30:49 PM PDT 24 99324189 ps
T559 /workspace/coverage/cover_reg_top/12.hmac_intr_test.1415361749 Jul 09 05:30:50 PM PDT 24 Jul 09 05:30:54 PM PDT 24 33920015 ps
T560 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1111338857 Jul 09 05:30:20 PM PDT 24 Jul 09 05:30:21 PM PDT 24 73045406 ps
T94 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2998737430 Jul 09 05:30:25 PM PDT 24 Jul 09 05:30:31 PM PDT 24 113842064 ps
T561 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3326132115 Jul 09 05:30:51 PM PDT 24 Jul 09 05:30:56 PM PDT 24 19855238 ps
T562 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3057204870 Jul 09 05:30:48 PM PDT 24 Jul 09 05:30:52 PM PDT 24 331768126 ps
T111 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.131404703 Jul 09 05:30:23 PM PDT 24 Jul 09 05:30:26 PM PDT 24 116214890 ps
T563 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1185861564 Jul 09 05:30:53 PM PDT 24 Jul 09 05:30:57 PM PDT 24 44127573 ps
T564 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1941279226 Jul 09 05:30:50 PM PDT 24 Jul 09 05:30:54 PM PDT 24 11047564 ps
T565 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.363486811 Jul 09 05:30:28 PM PDT 24 Jul 09 05:30:44 PM PDT 24 2117700727 ps
T95 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2193116240 Jul 09 05:30:43 PM PDT 24 Jul 09 05:30:45 PM PDT 24 24333728 ps
T566 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3267442698 Jul 09 05:30:48 PM PDT 24 Jul 09 05:30:52 PM PDT 24 103779038 ps
T96 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2645490753 Jul 09 05:30:50 PM PDT 24 Jul 09 05:30:54 PM PDT 24 44436457 ps
T567 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2364414760 Jul 09 05:30:52 PM PDT 24 Jul 09 05:30:57 PM PDT 24 41084553 ps
T112 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3327118880 Jul 09 05:30:46 PM PDT 24 Jul 09 05:30:48 PM PDT 24 58611196 ps
T113 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3966022662 Jul 09 05:30:48 PM PDT 24 Jul 09 05:30:53 PM PDT 24 116887385 ps
T568 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3271646925 Jul 09 05:30:25 PM PDT 24 Jul 09 05:30:27 PM PDT 24 17715935 ps
T569 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1029601407 Jul 09 05:30:47 PM PDT 24 Jul 09 05:30:52 PM PDT 24 581007594 ps
T570 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2255373438 Jul 09 05:30:23 PM PDT 24 Jul 09 05:30:25 PM PDT 24 87419190 ps
T118 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3170881548 Jul 09 05:30:49 PM PDT 24 Jul 09 05:30:54 PM PDT 24 279379327 ps
T97 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2697699479 Jul 09 05:30:48 PM PDT 24 Jul 09 05:30:52 PM PDT 24 40677811 ps
T571 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1397419053 Jul 09 05:30:28 PM PDT 24 Jul 09 05:30:31 PM PDT 24 488491441 ps
T572 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.786373687 Jul 09 05:30:49 PM PDT 24 Jul 09 05:30:53 PM PDT 24 43109265 ps
T573 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2090325773 Jul 09 05:30:49 PM PDT 24 Jul 09 05:30:53 PM PDT 24 32297147 ps
T119 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1843457401 Jul 09 05:30:21 PM PDT 24 Jul 09 05:30:26 PM PDT 24 1144521425 ps
T574 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2514514898 Jul 09 05:30:47 PM PDT 24 Jul 09 05:30:49 PM PDT 24 50689289 ps
T120 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2122482214 Jul 09 05:30:49 PM PDT 24 Jul 09 05:30:53 PM PDT 24 59568636 ps
T121 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2803134415 Jul 09 05:30:42 PM PDT 24 Jul 09 05:30:46 PM PDT 24 148746627 ps
T575 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1367960655 Jul 09 05:30:48 PM PDT 24 Jul 09 05:30:52 PM PDT 24 25256141 ps
T98 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.502615122 Jul 09 05:30:47 PM PDT 24 Jul 09 05:30:50 PM PDT 24 13898144 ps
T122 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.646110886 Jul 09 05:30:43 PM PDT 24 Jul 09 05:30:48 PM PDT 24 231520225 ps
T63 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.951404730 Jul 09 05:30:34 PM PDT 24 Jul 09 05:30:38 PM PDT 24 161513746 ps
T126 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1073402497 Jul 09 05:30:50 PM PDT 24 Jul 09 05:30:56 PM PDT 24 88357917 ps
T576 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.176809707 Jul 09 05:30:24 PM PDT 24 Jul 09 05:30:27 PM PDT 24 96738305 ps
T577 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.38678927 Jul 09 05:30:44 PM PDT 24 Jul 09 05:30:49 PM PDT 24 1061300208 ps
T578 /workspace/coverage/cover_reg_top/22.hmac_intr_test.428780462 Jul 09 05:30:51 PM PDT 24 Jul 09 05:30:56 PM PDT 24 14644614 ps
T579 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.820376408 Jul 09 05:30:34 PM PDT 24 Jul 09 05:30:37 PM PDT 24 50645787 ps
T580 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3954710122 Jul 09 05:30:46 PM PDT 24 Jul 09 05:30:49 PM PDT 24 43977410 ps
T581 /workspace/coverage/cover_reg_top/30.hmac_intr_test.28732666 Jul 09 05:30:49 PM PDT 24 Jul 09 05:30:53 PM PDT 24 34527713 ps
T582 /workspace/coverage/cover_reg_top/47.hmac_intr_test.1379903735 Jul 09 05:30:50 PM PDT 24 Jul 09 05:30:55 PM PDT 24 34594940 ps
T583 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.977240488 Jul 09 05:30:47 PM PDT 24 Jul 09 05:30:50 PM PDT 24 61992834 ps
T124 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.907555290 Jul 09 05:30:23 PM PDT 24 Jul 09 05:30:27 PM PDT 24 680928605 ps
T584 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2265645205 Jul 09 05:30:50 PM PDT 24 Jul 09 05:30:54 PM PDT 24 207275905 ps
T101 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3232396051 Jul 09 05:30:49 PM PDT 24 Jul 09 05:30:53 PM PDT 24 34233036 ps
T585 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1116840059 Jul 09 05:30:29 PM PDT 24 Jul 09 05:30:41 PM PDT 24 737641369 ps
T586 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.49822127 Jul 09 05:30:27 PM PDT 24 Jul 09 05:30:29 PM PDT 24 92768471 ps
T587 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3773259237 Jul 09 05:30:49 PM PDT 24 Jul 09 05:30:52 PM PDT 24 15870802 ps
T100 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.4116927798 Jul 09 05:30:25 PM PDT 24 Jul 09 05:30:31 PM PDT 24 109035732 ps
T588 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2728686751 Jul 09 05:30:49 PM PDT 24 Jul 09 05:30:54 PM PDT 24 98758712 ps
T589 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3841328918 Jul 09 05:30:23 PM PDT 24 Jul 09 05:30:24 PM PDT 24 19581549 ps
T102 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.534991792 Jul 09 05:30:25 PM PDT 24 Jul 09 05:30:27 PM PDT 24 43872260 ps
T590 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.314341350 Jul 09 05:30:24 PM PDT 24 Jul 09 05:30:27 PM PDT 24 192708607 ps
T591 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.784384880 Jul 09 05:30:46 PM PDT 24 Jul 09 05:43:01 PM PDT 24 73710296287 ps
T592 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.4154161117 Jul 09 05:30:29 PM PDT 24 Jul 09 05:46:41 PM PDT 24 105911688489 ps
T593 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.708891626 Jul 09 05:30:36 PM PDT 24 Jul 09 05:30:40 PM PDT 24 534174160 ps
T594 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3567901276 Jul 09 05:30:33 PM PDT 24 Jul 09 05:30:36 PM PDT 24 146766238 ps
T595 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2290823367 Jul 09 05:30:27 PM PDT 24 Jul 09 05:30:28 PM PDT 24 52022075 ps
T596 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3251821910 Jul 09 05:30:51 PM PDT 24 Jul 09 05:30:57 PM PDT 24 104183619 ps
T597 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3376740855 Jul 09 05:30:25 PM PDT 24 Jul 09 05:30:27 PM PDT 24 287988491 ps
T598 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2287435200 Jul 09 05:30:54 PM PDT 24 Jul 09 05:30:58 PM PDT 24 93926303 ps
T599 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1261131103 Jul 09 05:30:55 PM PDT 24 Jul 09 05:30:59 PM PDT 24 32369476 ps
T600 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3554467933 Jul 09 05:30:46 PM PDT 24 Jul 09 05:30:49 PM PDT 24 51578185 ps
T601 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4116294699 Jul 09 05:30:52 PM PDT 24 Jul 09 05:30:57 PM PDT 24 307854986 ps
T602 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3989974551 Jul 09 05:30:47 PM PDT 24 Jul 09 05:30:50 PM PDT 24 13185025 ps
T603 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1344987829 Jul 09 05:30:51 PM PDT 24 Jul 09 05:30:56 PM PDT 24 181496933 ps
T604 /workspace/coverage/cover_reg_top/8.hmac_intr_test.1394312584 Jul 09 05:30:49 PM PDT 24 Jul 09 05:30:53 PM PDT 24 48178108 ps
T605 /workspace/coverage/cover_reg_top/48.hmac_intr_test.3339843528 Jul 09 05:30:51 PM PDT 24 Jul 09 05:30:55 PM PDT 24 14082255 ps
T606 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.235289474 Jul 09 05:30:37 PM PDT 24 Jul 09 05:30:38 PM PDT 24 29070598 ps
T607 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1093227526 Jul 09 05:30:25 PM PDT 24 Jul 09 05:30:32 PM PDT 24 111170597 ps
T608 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3445271033 Jul 09 05:30:56 PM PDT 24 Jul 09 05:31:00 PM PDT 24 81282167 ps
T609 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.4239765702 Jul 09 05:30:23 PM PDT 24 Jul 09 05:30:27 PM PDT 24 160834275 ps
T610 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1273009179 Jul 09 05:30:23 PM PDT 24 Jul 09 05:30:27 PM PDT 24 58318348 ps
T611 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3447260326 Jul 09 05:30:48 PM PDT 24 Jul 09 05:30:51 PM PDT 24 43132834 ps
T612 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1840387053 Jul 09 05:30:51 PM PDT 24 Jul 09 05:30:56 PM PDT 24 23963781 ps
T613 /workspace/coverage/cover_reg_top/5.hmac_intr_test.947355824 Jul 09 05:30:38 PM PDT 24 Jul 09 05:30:39 PM PDT 24 29213300 ps
T125 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3539936851 Jul 09 05:30:34 PM PDT 24 Jul 09 05:30:39 PM PDT 24 133527650 ps
T614 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.888153210 Jul 09 05:30:45 PM PDT 24 Jul 09 05:30:46 PM PDT 24 143939434 ps
T615 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1375455907 Jul 09 05:30:49 PM PDT 24 Jul 09 05:30:53 PM PDT 24 24706330 ps
T616 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4289312050 Jul 09 05:30:49 PM PDT 24 Jul 09 05:47:12 PM PDT 24 278096774886 ps
T617 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.816317771 Jul 09 05:30:26 PM PDT 24 Jul 09 05:30:29 PM PDT 24 155026477 ps
T618 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3744467919 Jul 09 05:30:53 PM PDT 24 Jul 09 05:30:59 PM PDT 24 253513864 ps
T619 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3730796844 Jul 09 05:30:35 PM PDT 24 Jul 09 05:30:37 PM PDT 24 123454004 ps
T620 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3176239624 Jul 09 05:30:32 PM PDT 24 Jul 09 05:30:34 PM PDT 24 130279827 ps
T621 /workspace/coverage/cover_reg_top/31.hmac_intr_test.2302916585 Jul 09 05:30:52 PM PDT 24 Jul 09 05:30:57 PM PDT 24 56629257 ps
T622 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1974091548 Jul 09 05:30:48 PM PDT 24 Jul 09 05:30:52 PM PDT 24 40333796 ps
T623 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2516042994 Jul 09 05:30:52 PM PDT 24 Jul 09 05:30:56 PM PDT 24 13379883 ps
T103 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3469598374 Jul 09 05:30:49 PM PDT 24 Jul 09 05:30:53 PM PDT 24 37690159 ps
T624 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.4057189833 Jul 09 05:30:46 PM PDT 24 Jul 09 05:30:49 PM PDT 24 18476351 ps
T625 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2813929793 Jul 09 05:30:46 PM PDT 24 Jul 09 05:30:49 PM PDT 24 99842512 ps
T626 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2841661846 Jul 09 05:30:50 PM PDT 24 Jul 09 05:30:58 PM PDT 24 232707891 ps
T123 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2947685956 Jul 09 05:30:21 PM PDT 24 Jul 09 05:30:24 PM PDT 24 439231442 ps
T104 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3145769531 Jul 09 05:30:27 PM PDT 24 Jul 09 05:30:29 PM PDT 24 33738848 ps
T627 /workspace/coverage/cover_reg_top/7.hmac_intr_test.3338530977 Jul 09 05:30:48 PM PDT 24 Jul 09 05:30:51 PM PDT 24 63589944 ps
T628 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2996171898 Jul 09 05:30:53 PM PDT 24 Jul 09 05:30:57 PM PDT 24 65302672 ps
T629 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1891686710 Jul 09 05:30:49 PM PDT 24 Jul 09 05:30:54 PM PDT 24 167977362 ps
T630 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.471391263 Jul 09 05:30:44 PM PDT 24 Jul 09 05:30:46 PM PDT 24 108522960 ps
T631 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.815883146 Jul 09 05:30:26 PM PDT 24 Jul 09 05:30:28 PM PDT 24 54535203 ps
T632 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3012972088 Jul 09 05:31:45 PM PDT 24 Jul 09 05:31:47 PM PDT 24 61401485 ps
T633 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1563448237 Jul 09 05:30:45 PM PDT 24 Jul 09 05:30:49 PM PDT 24 551882171 ps
T634 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.395262346 Jul 09 05:30:48 PM PDT 24 Jul 09 05:30:52 PM PDT 24 198817089 ps
T635 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1467767629 Jul 09 05:30:47 PM PDT 24 Jul 09 05:30:50 PM PDT 24 60995375 ps
T636 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3196392530 Jul 09 05:30:32 PM PDT 24 Jul 09 05:30:33 PM PDT 24 105807975 ps
T637 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2232773423 Jul 09 05:30:48 PM PDT 24 Jul 09 05:47:29 PM PDT 24 73305727551 ps
T638 /workspace/coverage/cover_reg_top/4.hmac_intr_test.786233866 Jul 09 05:30:31 PM PDT 24 Jul 09 05:30:32 PM PDT 24 11856553 ps
T639 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2454609754 Jul 09 05:30:50 PM PDT 24 Jul 09 05:30:54 PM PDT 24 57911681 ps
T640 /workspace/coverage/cover_reg_top/38.hmac_intr_test.1028601377 Jul 09 05:30:55 PM PDT 24 Jul 09 05:30:58 PM PDT 24 14590657 ps
T641 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.335747766 Jul 09 05:30:45 PM PDT 24 Jul 09 05:30:48 PM PDT 24 364319685 ps
T642 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.588970720 Jul 09 05:30:23 PM PDT 24 Jul 09 05:30:27 PM PDT 24 608769495 ps
T643 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3356397477 Jul 09 05:30:39 PM PDT 24 Jul 09 05:30:41 PM PDT 24 17540661 ps
T644 /workspace/coverage/cover_reg_top/37.hmac_intr_test.57685317 Jul 09 05:30:51 PM PDT 24 Jul 09 05:30:55 PM PDT 24 13840733 ps
T645 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.253231137 Jul 09 05:30:49 PM PDT 24 Jul 09 05:30:55 PM PDT 24 72143341 ps
T646 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1193181340 Jul 09 05:30:45 PM PDT 24 Jul 09 05:30:49 PM PDT 24 113298091 ps
T647 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2112467048 Jul 09 05:30:32 PM PDT 24 Jul 09 05:30:35 PM PDT 24 239444723 ps
T648 /workspace/coverage/cover_reg_top/49.hmac_intr_test.3139943742 Jul 09 05:30:49 PM PDT 24 Jul 09 05:30:53 PM PDT 24 14367262 ps
T649 /workspace/coverage/cover_reg_top/28.hmac_intr_test.1971118059 Jul 09 05:30:48 PM PDT 24 Jul 09 05:30:52 PM PDT 24 135665123 ps
T650 /workspace/coverage/cover_reg_top/2.hmac_intr_test.1647868315 Jul 09 05:30:22 PM PDT 24 Jul 09 05:30:24 PM PDT 24 52291502 ps
T651 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2467745900 Jul 09 05:30:34 PM PDT 24 Jul 09 05:32:54 PM PDT 24 18471495165 ps
T652 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.442036290 Jul 09 05:30:52 PM PDT 24 Jul 09 05:38:52 PM PDT 24 50965320573 ps
T653 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3283587955 Jul 09 05:30:53 PM PDT 24 Jul 09 05:30:57 PM PDT 24 13212307 ps
T654 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2806486909 Jul 09 05:30:51 PM PDT 24 Jul 09 05:30:55 PM PDT 24 42040722 ps
T655 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1699158890 Jul 09 05:30:52 PM PDT 24 Jul 09 05:30:56 PM PDT 24 13526113 ps
T656 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.586572494 Jul 09 05:30:49 PM PDT 24 Jul 09 05:30:56 PM PDT 24 470739588 ps
T657 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1853748162 Jul 09 05:30:29 PM PDT 24 Jul 09 05:30:33 PM PDT 24 678934609 ps
T658 /workspace/coverage/cover_reg_top/40.hmac_intr_test.499208012 Jul 09 05:30:51 PM PDT 24 Jul 09 05:30:55 PM PDT 24 13540934 ps
T659 /workspace/coverage/cover_reg_top/15.hmac_intr_test.147268357 Jul 09 05:30:52 PM PDT 24 Jul 09 05:30:56 PM PDT 24 49566540 ps
T660 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1315983584 Jul 09 05:30:51 PM PDT 24 Jul 09 05:30:57 PM PDT 24 23172325 ps
T127 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3018224192 Jul 09 05:30:47 PM PDT 24 Jul 09 05:30:51 PM PDT 24 208334505 ps

Test location /workspace/coverage/default/6.hmac_smoke.781909892
Short name T4
Test name
Test status
Simulation time 2614004641 ps
CPU time 10.15 seconds
Started Jul 09 07:03:01 PM PDT 24
Finished Jul 09 07:03:15 PM PDT 24
Peak memory 200420 kb
Host smart-74199ae1-35a4-4179-84ca-48d74caff1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781909892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.781909892
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.3855474571
Short name T8
Test name
Test status
Simulation time 484872723867 ps
CPU time 4711.01 seconds
Started Jul 09 07:03:02 PM PDT 24
Finished Jul 09 08:21:38 PM PDT 24
Peak memory 795236 kb
Host smart-0939554e-25f2-4adf-9c79-bc2124d22375
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3855474571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.3855474571
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3850551594
Short name T7
Test name
Test status
Simulation time 281632973842 ps
CPU time 1371.37 seconds
Started Jul 09 07:02:48 PM PDT 24
Finished Jul 09 07:25:40 PM PDT 24
Peak memory 626664 kb
Host smart-3a2863b1-0aaa-4f1d-a548-012753a055d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3850551594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3850551594
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.55815003
Short name T42
Test name
Test status
Simulation time 247381270705 ps
CPU time 7776.23 seconds
Started Jul 09 07:03:01 PM PDT 24
Finished Jul 09 09:12:42 PM PDT 24
Peak memory 859884 kb
Host smart-d6665cdc-c830-413f-9b35-f41015421f83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=55815003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.55815003
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1706642343
Short name T60
Test name
Test status
Simulation time 469234517 ps
CPU time 4.03 seconds
Started Jul 09 05:30:47 PM PDT 24
Finished Jul 09 05:30:53 PM PDT 24
Peak memory 200292 kb
Host smart-8ed3af87-f18e-42c2-8453-521ae7fd8f07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706642343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1706642343
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.2813253229
Short name T19
Test name
Test status
Simulation time 123262613069 ps
CPU time 3672.18 seconds
Started Jul 09 07:02:47 PM PDT 24
Finished Jul 09 08:04:01 PM PDT 24
Peak memory 779360 kb
Host smart-d0d464a9-b7f5-499c-b8d3-546cc6161848
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2813253229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.2813253229
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2137993865
Short name T154
Test name
Test status
Simulation time 15047074 ps
CPU time 0.6 seconds
Started Jul 09 07:03:07 PM PDT 24
Finished Jul 09 07:03:12 PM PDT 24
Peak memory 196864 kb
Host smart-4e22f016-29dd-4f67-9264-cc5363d56ff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137993865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2137993865
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1476300054
Short name T49
Test name
Test status
Simulation time 147699126 ps
CPU time 0.83 seconds
Started Jul 09 07:02:42 PM PDT 24
Finished Jul 09 07:02:44 PM PDT 24
Peak memory 218272 kb
Host smart-24f148b8-206f-4d80-9b5e-c628c93211be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476300054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1476300054
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/16.hmac_stress_all.4269630145
Short name T28
Test name
Test status
Simulation time 418299246093 ps
CPU time 3144.83 seconds
Started Jul 09 07:03:20 PM PDT 24
Finished Jul 09 07:55:47 PM PDT 24
Peak memory 803628 kb
Host smart-f4aaa52c-ecab-46e4-98e7-0a8ab79d744c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269630145 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.4269630145
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2193116240
Short name T95
Test name
Test status
Simulation time 24333728 ps
CPU time 0.77 seconds
Started Jul 09 05:30:43 PM PDT 24
Finished Jul 09 05:30:45 PM PDT 24
Peak memory 197928 kb
Host smart-971e92ad-9f6b-4d43-b721-c3f1747772c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193116240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2193116240
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.1843457401
Short name T119
Test name
Test status
Simulation time 1144521425 ps
CPU time 4.46 seconds
Started Jul 09 05:30:21 PM PDT 24
Finished Jul 09 05:30:26 PM PDT 24
Peak memory 200364 kb
Host smart-cbd29745-96b2-4e2d-9d40-95985ac998a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843457401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.1843457401
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1361258645
Short name T79
Test name
Test status
Simulation time 60234161874 ps
CPU time 2228.78 seconds
Started Jul 09 07:03:09 PM PDT 24
Finished Jul 09 07:40:22 PM PDT 24
Peak memory 784296 kb
Host smart-8df57863-c919-445a-8456-5ee47e9abe4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361258645 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1361258645
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.951404730
Short name T63
Test name
Test status
Simulation time 161513746 ps
CPU time 3.19 seconds
Started Jul 09 05:30:34 PM PDT 24
Finished Jul 09 05:30:38 PM PDT 24
Peak memory 200288 kb
Host smart-e9009d97-52fe-4283-8e1a-835ffcff1e98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951404730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.951404730
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1073402497
Short name T126
Test name
Test status
Simulation time 88357917 ps
CPU time 1.89 seconds
Started Jul 09 05:30:50 PM PDT 24
Finished Jul 09 05:30:56 PM PDT 24
Peak memory 200260 kb
Host smart-05b321fa-503a-434e-b105-0f869edbd6eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073402497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1073402497
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3927501431
Short name T39
Test name
Test status
Simulation time 2808520648 ps
CPU time 26.37 seconds
Started Jul 09 07:02:40 PM PDT 24
Finished Jul 09 07:03:07 PM PDT 24
Peak memory 200392 kb
Host smart-f48dd7c6-cfe6-4861-8456-98060733a308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927501431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3927501431
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1849701081
Short name T93
Test name
Test status
Simulation time 618519587 ps
CPU time 7.93 seconds
Started Jul 09 05:30:19 PM PDT 24
Finished Jul 09 05:30:27 PM PDT 24
Peak memory 200272 kb
Host smart-d7cb86ee-e04c-4ff9-a38c-6ed3dadc0cd1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849701081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1849701081
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1116840059
Short name T585
Test name
Test status
Simulation time 737641369 ps
CPU time 11.12 seconds
Started Jul 09 05:30:29 PM PDT 24
Finished Jul 09 05:30:41 PM PDT 24
Peak memory 200368 kb
Host smart-e41d5760-95b5-4652-af20-71da55263c67
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116840059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1116840059
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2255373438
Short name T570
Test name
Test status
Simulation time 87419190 ps
CPU time 0.96 seconds
Started Jul 09 05:30:23 PM PDT 24
Finished Jul 09 05:30:25 PM PDT 24
Peak memory 199944 kb
Host smart-13381769-0199-4014-acca-e90d6196abe8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255373438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2255373438
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.4239765702
Short name T609
Test name
Test status
Simulation time 160834275 ps
CPU time 2.37 seconds
Started Jul 09 05:30:23 PM PDT 24
Finished Jul 09 05:30:27 PM PDT 24
Peak memory 200288 kb
Host smart-70d8e5d0-33a2-4e82-8759-f54006bb01ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239765702 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.4239765702
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.944891974
Short name T106
Test name
Test status
Simulation time 16677635 ps
CPU time 0.92 seconds
Started Jul 09 05:30:22 PM PDT 24
Finished Jul 09 05:30:24 PM PDT 24
Peak memory 200100 kb
Host smart-c6367981-8e57-4fcc-89df-95c88f1b3fa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944891974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.944891974
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1229139631
Short name T554
Test name
Test status
Simulation time 52501817 ps
CPU time 0.63 seconds
Started Jul 09 05:30:23 PM PDT 24
Finished Jul 09 05:30:25 PM PDT 24
Peak memory 195284 kb
Host smart-8246dda7-c35d-4023-85cd-2e63faa268ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229139631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1229139631
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2066325737
Short name T105
Test name
Test status
Simulation time 124570553 ps
CPU time 1.6 seconds
Started Jul 09 05:30:34 PM PDT 24
Finished Jul 09 05:30:36 PM PDT 24
Peak memory 200284 kb
Host smart-6882a00a-f1ff-45c1-84a8-e067afdf9a12
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066325737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2066325737
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1273009179
Short name T610
Test name
Test status
Simulation time 58318348 ps
CPU time 2.84 seconds
Started Jul 09 05:30:23 PM PDT 24
Finished Jul 09 05:30:27 PM PDT 24
Peak memory 200372 kb
Host smart-6926ca27-a4f1-4b0d-aa02-273afa6887dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273009179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1273009179
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.907555290
Short name T124
Test name
Test status
Simulation time 680928605 ps
CPU time 3.2 seconds
Started Jul 09 05:30:23 PM PDT 24
Finished Jul 09 05:30:27 PM PDT 24
Peak memory 200316 kb
Host smart-958233cb-2192-4c42-9a6a-4e78570d8a76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907555290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.907555290
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.4116927798
Short name T100
Test name
Test status
Simulation time 109035732 ps
CPU time 5.45 seconds
Started Jul 09 05:30:25 PM PDT 24
Finished Jul 09 05:30:31 PM PDT 24
Peak memory 200196 kb
Host smart-b36b3f20-49be-4aca-b568-36262e947c24
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116927798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.4116927798
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1093227526
Short name T607
Test name
Test status
Simulation time 111170597 ps
CPU time 5.38 seconds
Started Jul 09 05:30:25 PM PDT 24
Finished Jul 09 05:30:32 PM PDT 24
Peak memory 199260 kb
Host smart-1d8010c0-1669-40c6-a6ed-7816f39ad4cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093227526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1093227526
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1111338857
Short name T560
Test name
Test status
Simulation time 73045406 ps
CPU time 0.71 seconds
Started Jul 09 05:30:20 PM PDT 24
Finished Jul 09 05:30:21 PM PDT 24
Peak memory 198480 kb
Host smart-5b1d7a58-d2b0-4a1a-be13-7c6b45e64eda
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111338857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1111338857
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2112467048
Short name T647
Test name
Test status
Simulation time 239444723 ps
CPU time 2.59 seconds
Started Jul 09 05:30:32 PM PDT 24
Finished Jul 09 05:30:35 PM PDT 24
Peak memory 200316 kb
Host smart-9caae098-d42c-4f90-9f7d-1fb8bccdc97e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112467048 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2112467048
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3841328918
Short name T589
Test name
Test status
Simulation time 19581549 ps
CPU time 0.89 seconds
Started Jul 09 05:30:23 PM PDT 24
Finished Jul 09 05:30:24 PM PDT 24
Peak memory 199912 kb
Host smart-49c06f45-37b5-42b7-b075-c93d2829156f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841328918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3841328918
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.221638839
Short name T534
Test name
Test status
Simulation time 11910465 ps
CPU time 0.58 seconds
Started Jul 09 05:30:21 PM PDT 24
Finished Jul 09 05:30:22 PM PDT 24
Peak memory 195176 kb
Host smart-b98ec514-841a-4edf-ab71-d8f38a0ceb69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221638839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.221638839
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.176809707
Short name T576
Test name
Test status
Simulation time 96738305 ps
CPU time 1.84 seconds
Started Jul 09 05:30:24 PM PDT 24
Finished Jul 09 05:30:27 PM PDT 24
Peak memory 200276 kb
Host smart-4b7ebdcc-eb6f-49e1-8992-322064b8b82a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176809707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.176809707
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.588970720
Short name T642
Test name
Test status
Simulation time 608769495 ps
CPU time 2.68 seconds
Started Jul 09 05:30:23 PM PDT 24
Finished Jul 09 05:30:27 PM PDT 24
Peak memory 200284 kb
Host smart-51d2f70f-f37f-45af-9909-cc965a20d338
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588970720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.588970720
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2947685956
Short name T123
Test name
Test status
Simulation time 439231442 ps
CPU time 2.04 seconds
Started Jul 09 05:30:21 PM PDT 24
Finished Jul 09 05:30:24 PM PDT 24
Peak memory 200312 kb
Host smart-d64771d9-a8e1-4933-bc58-587d087b6d92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947685956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2947685956
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3954710122
Short name T580
Test name
Test status
Simulation time 43977410 ps
CPU time 1.11 seconds
Started Jul 09 05:30:46 PM PDT 24
Finished Jul 09 05:30:49 PM PDT 24
Peak memory 200184 kb
Host smart-60ac2bb6-3d9e-42fb-979c-b6e7f8df905d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954710122 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3954710122
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.476635808
Short name T550
Test name
Test status
Simulation time 43458887 ps
CPU time 0.63 seconds
Started Jul 09 05:30:48 PM PDT 24
Finished Jul 09 05:30:51 PM PDT 24
Peak memory 195164 kb
Host smart-157205f4-b218-44ca-a011-b35976686af1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476635808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.476635808
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1224417024
Short name T108
Test name
Test status
Simulation time 68340396 ps
CPU time 1.14 seconds
Started Jul 09 05:30:52 PM PDT 24
Finished Jul 09 05:30:57 PM PDT 24
Peak memory 200176 kb
Host smart-e4b01446-9d8b-4b63-b0b5-f7794eb3d1ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224417024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1224417024
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2013960098
Short name T556
Test name
Test status
Simulation time 305454255 ps
CPU time 2.09 seconds
Started Jul 09 05:30:45 PM PDT 24
Finished Jul 09 05:30:48 PM PDT 24
Peak memory 200272 kb
Host smart-0779ede2-bcd1-40ff-96e3-3c47e5e6d9d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013960098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2013960098
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2122482214
Short name T120
Test name
Test status
Simulation time 59568636 ps
CPU time 1.72 seconds
Started Jul 09 05:30:49 PM PDT 24
Finished Jul 09 05:30:53 PM PDT 24
Peak memory 200276 kb
Host smart-39e9c8b1-ddd3-4fbf-bf89-0393c830bb2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122482214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2122482214
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2983592062
Short name T552
Test name
Test status
Simulation time 28013077 ps
CPU time 1.65 seconds
Started Jul 09 05:30:52 PM PDT 24
Finished Jul 09 05:30:58 PM PDT 24
Peak memory 200276 kb
Host smart-cad37c9a-7143-410d-8aea-7a32a8a209e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983592062 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.2983592062
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2514514898
Short name T574
Test name
Test status
Simulation time 50689289 ps
CPU time 0.69 seconds
Started Jul 09 05:30:47 PM PDT 24
Finished Jul 09 05:30:49 PM PDT 24
Peak memory 198116 kb
Host smart-7a94f48c-aee0-41ef-9bd2-ffc24709249d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514514898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2514514898
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2454609754
Short name T639
Test name
Test status
Simulation time 57911681 ps
CPU time 0.63 seconds
Started Jul 09 05:30:50 PM PDT 24
Finished Jul 09 05:30:54 PM PDT 24
Peak memory 195172 kb
Host smart-02acdd75-eb04-4c14-ac36-4c7569c5a49f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454609754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2454609754
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.888153210
Short name T614
Test name
Test status
Simulation time 143939434 ps
CPU time 1.17 seconds
Started Jul 09 05:30:45 PM PDT 24
Finished Jul 09 05:30:46 PM PDT 24
Peak memory 200220 kb
Host smart-92ffa59d-3169-45d8-9b52-3562492fa473
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888153210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.888153210
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1740391837
Short name T555
Test name
Test status
Simulation time 148717563 ps
CPU time 1.85 seconds
Started Jul 09 05:30:44 PM PDT 24
Finished Jul 09 05:30:47 PM PDT 24
Peak memory 200192 kb
Host smart-31b66833-972e-43b6-9de6-ae5d9dad6929
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740391837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1740391837
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2803134415
Short name T121
Test name
Test status
Simulation time 148746627 ps
CPU time 3.23 seconds
Started Jul 09 05:30:42 PM PDT 24
Finished Jul 09 05:30:46 PM PDT 24
Peak memory 200272 kb
Host smart-9bd35cb9-4aba-45e2-8942-98c55c8bf18a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803134415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2803134415
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2232773423
Short name T637
Test name
Test status
Simulation time 73305727551 ps
CPU time 999.68 seconds
Started Jul 09 05:30:48 PM PDT 24
Finished Jul 09 05:47:29 PM PDT 24
Peak memory 216676 kb
Host smart-f5ff79cd-cf1e-42a8-8ea0-821d30cebdd2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232773423 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2232773423
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2697699479
Short name T97
Test name
Test status
Simulation time 40677811 ps
CPU time 0.79 seconds
Started Jul 09 05:30:48 PM PDT 24
Finished Jul 09 05:30:52 PM PDT 24
Peak memory 199000 kb
Host smart-a02a2bc5-fedc-4e12-8cb4-e4326f6b22b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697699479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2697699479
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.1415361749
Short name T559
Test name
Test status
Simulation time 33920015 ps
CPU time 0.65 seconds
Started Jul 09 05:30:50 PM PDT 24
Finished Jul 09 05:30:54 PM PDT 24
Peak memory 195376 kb
Host smart-cd6ab69c-df33-4f81-9011-20c64d22c581
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415361749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.1415361749
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3445271033
Short name T608
Test name
Test status
Simulation time 81282167 ps
CPU time 1.73 seconds
Started Jul 09 05:30:56 PM PDT 24
Finished Jul 09 05:31:00 PM PDT 24
Peak memory 200152 kb
Host smart-a1f8efa7-d4c7-4fbb-9d20-00ed872156f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445271033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3445271033
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1375455907
Short name T615
Test name
Test status
Simulation time 24706330 ps
CPU time 1.34 seconds
Started Jul 09 05:30:49 PM PDT 24
Finished Jul 09 05:30:53 PM PDT 24
Peak memory 200280 kb
Host smart-e97de738-9dc0-4872-808d-6e00d0458907
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375455907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1375455907
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3018224192
Short name T127
Test name
Test status
Simulation time 208334505 ps
CPU time 3.18 seconds
Started Jul 09 05:30:47 PM PDT 24
Finished Jul 09 05:30:51 PM PDT 24
Peak memory 200216 kb
Host smart-a29141db-1658-4f1c-a6c3-4755b3a0d778
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018224192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3018224192
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.1315983584
Short name T660
Test name
Test status
Simulation time 23172325 ps
CPU time 1.26 seconds
Started Jul 09 05:30:51 PM PDT 24
Finished Jul 09 05:30:57 PM PDT 24
Peak memory 200348 kb
Host smart-a0f97c2d-25d1-470d-a068-1b0c405b0200
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315983584 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.1315983584
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3483298951
Short name T110
Test name
Test status
Simulation time 87173118 ps
CPU time 0.84 seconds
Started Jul 09 05:30:50 PM PDT 24
Finished Jul 09 05:30:54 PM PDT 24
Peak memory 199652 kb
Host smart-12b15134-ccf6-4129-bf30-751bd3835b8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483298951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3483298951
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2380070988
Short name T557
Test name
Test status
Simulation time 52035312 ps
CPU time 0.63 seconds
Started Jul 09 05:30:51 PM PDT 24
Finished Jul 09 05:30:56 PM PDT 24
Peak memory 195148 kb
Host smart-e450b3aa-a9d6-46de-986f-777fa70683a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380070988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2380070988
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.3851676347
Short name T107
Test name
Test status
Simulation time 176504501 ps
CPU time 2.21 seconds
Started Jul 09 05:30:52 PM PDT 24
Finished Jul 09 05:30:59 PM PDT 24
Peak memory 200264 kb
Host smart-55e1fed0-d00a-40e7-9180-84619d00429f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851676347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.3851676347
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3899185455
Short name T541
Test name
Test status
Simulation time 2095630946 ps
CPU time 2.74 seconds
Started Jul 09 05:30:45 PM PDT 24
Finished Jul 09 05:30:49 PM PDT 24
Peak memory 200164 kb
Host smart-179efbfa-1799-47c4-bdaa-89032e09bb20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899185455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3899185455
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1193181340
Short name T646
Test name
Test status
Simulation time 113298091 ps
CPU time 2.54 seconds
Started Jul 09 05:30:45 PM PDT 24
Finished Jul 09 05:30:49 PM PDT 24
Peak memory 200296 kb
Host smart-81f7c5cb-97d9-4496-9673-00b14c71badd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193181340 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1193181340
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2645490753
Short name T96
Test name
Test status
Simulation time 44436457 ps
CPU time 0.85 seconds
Started Jul 09 05:30:50 PM PDT 24
Finished Jul 09 05:30:54 PM PDT 24
Peak memory 199704 kb
Host smart-9afe2299-8692-4e3d-ac68-5f97f86bb06f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645490753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2645490753
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1904309617
Short name T543
Test name
Test status
Simulation time 18610523 ps
CPU time 0.61 seconds
Started Jul 09 05:30:46 PM PDT 24
Finished Jul 09 05:30:48 PM PDT 24
Peak memory 195208 kb
Host smart-55565571-dbf9-47aa-92c4-6d951d1877a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904309617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1904309617
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3966022662
Short name T113
Test name
Test status
Simulation time 116887385 ps
CPU time 2.35 seconds
Started Jul 09 05:30:48 PM PDT 24
Finished Jul 09 05:30:53 PM PDT 24
Peak memory 200248 kb
Host smart-206ac510-5388-4b51-b48d-bc5fc882af88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966022662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3966022662
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2011763074
Short name T542
Test name
Test status
Simulation time 82527222 ps
CPU time 3.89 seconds
Started Jul 09 05:30:50 PM PDT 24
Finished Jul 09 05:30:58 PM PDT 24
Peak memory 200304 kb
Host smart-a668ab11-bab0-49e7-a048-381be2ff6cb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011763074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2011763074
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3170881548
Short name T118
Test name
Test status
Simulation time 279379327 ps
CPU time 1.8 seconds
Started Jul 09 05:30:49 PM PDT 24
Finished Jul 09 05:30:54 PM PDT 24
Peak memory 200176 kb
Host smart-ca3b0d7e-9633-4dda-8861-cb7cf05de37c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170881548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3170881548
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2093301020
Short name T535
Test name
Test status
Simulation time 65285239 ps
CPU time 3.28 seconds
Started Jul 09 05:30:49 PM PDT 24
Finished Jul 09 05:30:55 PM PDT 24
Peak memory 216756 kb
Host smart-60edaad4-bfc4-4a88-ac84-6df5bdfff3d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093301020 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2093301020
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3469598374
Short name T103
Test name
Test status
Simulation time 37690159 ps
CPU time 0.72 seconds
Started Jul 09 05:30:49 PM PDT 24
Finished Jul 09 05:30:53 PM PDT 24
Peak memory 198232 kb
Host smart-ede28117-9e51-4dc2-85bb-0f1081cdd98e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469598374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3469598374
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.147268357
Short name T659
Test name
Test status
Simulation time 49566540 ps
CPU time 0.6 seconds
Started Jul 09 05:30:52 PM PDT 24
Finished Jul 09 05:30:56 PM PDT 24
Peak memory 195140 kb
Host smart-a0a19588-3e47-4246-8528-a7a33d758d6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147268357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.147268357
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.335747766
Short name T641
Test name
Test status
Simulation time 364319685 ps
CPU time 1.73 seconds
Started Jul 09 05:30:45 PM PDT 24
Finished Jul 09 05:30:48 PM PDT 24
Peak memory 200212 kb
Host smart-bcc24b99-d222-4f27-8a65-39f79da0a52d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335747766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.335747766
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.413907175
Short name T545
Test name
Test status
Simulation time 63645975 ps
CPU time 1.63 seconds
Started Jul 09 05:30:49 PM PDT 24
Finished Jul 09 05:30:54 PM PDT 24
Peak memory 200260 kb
Host smart-83935fd2-24f2-4487-8a5c-628de1ada6a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413907175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.413907175
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3744467919
Short name T618
Test name
Test status
Simulation time 253513864 ps
CPU time 1.72 seconds
Started Jul 09 05:30:53 PM PDT 24
Finished Jul 09 05:30:59 PM PDT 24
Peak memory 200292 kb
Host smart-6a487ad8-5823-4f46-88b4-3e89b377ea25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744467919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3744467919
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2309423848
Short name T558
Test name
Test status
Simulation time 99324189 ps
CPU time 1.72 seconds
Started Jul 09 05:30:46 PM PDT 24
Finished Jul 09 05:30:49 PM PDT 24
Peak memory 200244 kb
Host smart-269cf610-3d43-4525-a0df-d336a125b9ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309423848 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2309423848
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3232396051
Short name T101
Test name
Test status
Simulation time 34233036 ps
CPU time 0.96 seconds
Started Jul 09 05:30:49 PM PDT 24
Finished Jul 09 05:30:53 PM PDT 24
Peak memory 200028 kb
Host smart-b289e685-9801-40e3-96b4-1fe97b0660b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232396051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3232396051
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2516042994
Short name T623
Test name
Test status
Simulation time 13379883 ps
CPU time 0.61 seconds
Started Jul 09 05:30:52 PM PDT 24
Finished Jul 09 05:30:56 PM PDT 24
Peak memory 195196 kb
Host smart-0d70eae1-6c0c-4e50-a570-b1c5e01f397a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516042994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2516042994
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3327118880
Short name T112
Test name
Test status
Simulation time 58611196 ps
CPU time 1.27 seconds
Started Jul 09 05:30:46 PM PDT 24
Finished Jul 09 05:30:48 PM PDT 24
Peak memory 200008 kb
Host smart-7c30b391-91c6-48fc-b7d6-2f2049cee5f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327118880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3327118880
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.395262346
Short name T634
Test name
Test status
Simulation time 198817089 ps
CPU time 1.4 seconds
Started Jul 09 05:30:48 PM PDT 24
Finished Jul 09 05:30:52 PM PDT 24
Peak memory 200180 kb
Host smart-4ba78aa5-05b8-48b6-9d97-f3d6a54ae819
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395262346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.395262346
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.586572494
Short name T656
Test name
Test status
Simulation time 470739588 ps
CPU time 3.99 seconds
Started Jul 09 05:30:49 PM PDT 24
Finished Jul 09 05:30:56 PM PDT 24
Peak memory 200316 kb
Host smart-91a132b5-b5b4-4c41-b625-56b011d31772
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586572494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.586572494
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1891686710
Short name T629
Test name
Test status
Simulation time 167977362 ps
CPU time 1.3 seconds
Started Jul 09 05:30:49 PM PDT 24
Finished Jul 09 05:30:54 PM PDT 24
Peak memory 200284 kb
Host smart-ad25833c-d3cb-4a78-ba1d-b60b760d8a30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891686710 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1891686710
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1047912118
Short name T91
Test name
Test status
Simulation time 264405521 ps
CPU time 0.89 seconds
Started Jul 09 05:30:50 PM PDT 24
Finished Jul 09 05:30:54 PM PDT 24
Peak memory 200100 kb
Host smart-2315ec3e-685c-4ec8-aa54-ebb0af97744f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047912118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1047912118
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.657689686
Short name T536
Test name
Test status
Simulation time 31431437 ps
CPU time 0.57 seconds
Started Jul 09 05:30:47 PM PDT 24
Finished Jul 09 05:30:49 PM PDT 24
Peak memory 195156 kb
Host smart-5df3f0f5-09a0-414f-a838-1e0d827c03e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657689686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.657689686
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1029601407
Short name T569
Test name
Test status
Simulation time 581007594 ps
CPU time 2.3 seconds
Started Jul 09 05:30:47 PM PDT 24
Finished Jul 09 05:30:52 PM PDT 24
Peak memory 200284 kb
Host smart-4f081da2-34f6-4144-b211-dbb3919c624f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029601407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1029601407
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.253231137
Short name T645
Test name
Test status
Simulation time 72143341 ps
CPU time 3.65 seconds
Started Jul 09 05:30:49 PM PDT 24
Finished Jul 09 05:30:55 PM PDT 24
Peak memory 200308 kb
Host smart-27dfa5f6-c952-4b60-97ba-5f1c48e9f0bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253231137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.253231137
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.3131064214
Short name T62
Test name
Test status
Simulation time 295771315 ps
CPU time 4.37 seconds
Started Jul 09 05:30:46 PM PDT 24
Finished Jul 09 05:30:52 PM PDT 24
Peak memory 200288 kb
Host smart-58632a93-d02f-48f4-98b6-c493a7e41d46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131064214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.3131064214
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.786373687
Short name T572
Test name
Test status
Simulation time 43109265 ps
CPU time 1.18 seconds
Started Jul 09 05:30:49 PM PDT 24
Finished Jul 09 05:30:53 PM PDT 24
Peak memory 200188 kb
Host smart-07d1342c-d3f6-48e0-be6b-2a89c04051eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786373687 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.786373687
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1367960655
Short name T575
Test name
Test status
Simulation time 25256141 ps
CPU time 0.85 seconds
Started Jul 09 05:30:48 PM PDT 24
Finished Jul 09 05:30:52 PM PDT 24
Peak memory 199696 kb
Host smart-ebf21a57-1eaf-4357-add3-9efb9e64689c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367960655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1367960655
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3773259237
Short name T587
Test name
Test status
Simulation time 15870802 ps
CPU time 0.62 seconds
Started Jul 09 05:30:49 PM PDT 24
Finished Jul 09 05:30:52 PM PDT 24
Peak memory 195264 kb
Host smart-ec111278-519a-4770-9cb7-3e6025a95783
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773259237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3773259237
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.2679887791
Short name T109
Test name
Test status
Simulation time 1002918315 ps
CPU time 2.4 seconds
Started Jul 09 05:30:52 PM PDT 24
Finished Jul 09 05:30:58 PM PDT 24
Peak memory 200304 kb
Host smart-0f4b2db8-ea2b-40e1-8217-139ebaa1c66a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679887791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.2679887791
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.4116294699
Short name T601
Test name
Test status
Simulation time 307854986 ps
CPU time 1.77 seconds
Started Jul 09 05:30:52 PM PDT 24
Finished Jul 09 05:30:57 PM PDT 24
Peak memory 199916 kb
Host smart-0a587038-765d-4057-a54d-29f0e1a034f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116294699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.4116294699
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3251821910
Short name T596
Test name
Test status
Simulation time 104183619 ps
CPU time 1.78 seconds
Started Jul 09 05:30:51 PM PDT 24
Finished Jul 09 05:30:57 PM PDT 24
Peak memory 200320 kb
Host smart-a89f9fb5-bff5-4e99-b9f6-ae28fe7ad7a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251821910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3251821910
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.442036290
Short name T652
Test name
Test status
Simulation time 50965320573 ps
CPU time 476.26 seconds
Started Jul 09 05:30:52 PM PDT 24
Finished Jul 09 05:38:52 PM PDT 24
Peak memory 215952 kb
Host smart-16aa8f9f-3e83-4ffe-b709-b34309fdd044
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442036290 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.442036290
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2806486909
Short name T654
Test name
Test status
Simulation time 42040722 ps
CPU time 0.79 seconds
Started Jul 09 05:30:51 PM PDT 24
Finished Jul 09 05:30:55 PM PDT 24
Peak memory 199864 kb
Host smart-2d7237f6-6737-44b9-a7da-96e0a116d2b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806486909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2806486909
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.661659489
Short name T538
Test name
Test status
Simulation time 26807538 ps
CPU time 0.64 seconds
Started Jul 09 05:30:50 PM PDT 24
Finished Jul 09 05:30:55 PM PDT 24
Peak memory 195280 kb
Host smart-54a5f905-a2a5-4cd9-a2b3-897394e174ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661659489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.661659489
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.977240488
Short name T583
Test name
Test status
Simulation time 61992834 ps
CPU time 1.23 seconds
Started Jul 09 05:30:47 PM PDT 24
Finished Jul 09 05:30:50 PM PDT 24
Peak memory 200256 kb
Host smart-5e655277-f171-4e45-9a2e-7b8d90681858
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977240488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.977240488
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3057204870
Short name T562
Test name
Test status
Simulation time 331768126 ps
CPU time 2.01 seconds
Started Jul 09 05:30:48 PM PDT 24
Finished Jul 09 05:30:52 PM PDT 24
Peak memory 200172 kb
Host smart-563ef3b5-db87-458c-b146-75ad287e77af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057204870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3057204870
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1243804668
Short name T551
Test name
Test status
Simulation time 172839632 ps
CPU time 3.29 seconds
Started Jul 09 05:30:25 PM PDT 24
Finished Jul 09 05:30:30 PM PDT 24
Peak memory 200284 kb
Host smart-ceb0c3ba-238a-4a04-807a-5113ee1c7380
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243804668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1243804668
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.363486811
Short name T565
Test name
Test status
Simulation time 2117700727 ps
CPU time 15.57 seconds
Started Jul 09 05:30:28 PM PDT 24
Finished Jul 09 05:30:44 PM PDT 24
Peak memory 200336 kb
Host smart-2dbfb28b-06d4-4545-b7ff-f9b1fdcc6d1c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363486811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.363486811
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.815883146
Short name T631
Test name
Test status
Simulation time 54535203 ps
CPU time 0.73 seconds
Started Jul 09 05:30:26 PM PDT 24
Finished Jul 09 05:30:28 PM PDT 24
Peak memory 198180 kb
Host smart-60cabe93-cc97-46b6-acdd-fae5dfd903a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815883146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.815883146
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.4154161117
Short name T592
Test name
Test status
Simulation time 105911688489 ps
CPU time 971.62 seconds
Started Jul 09 05:30:29 PM PDT 24
Finished Jul 09 05:46:41 PM PDT 24
Peak memory 230208 kb
Host smart-461f79f6-60a5-426b-8a28-bd2f6a34d300
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154161117 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.4154161117
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.3145769531
Short name T104
Test name
Test status
Simulation time 33738848 ps
CPU time 0.95 seconds
Started Jul 09 05:30:27 PM PDT 24
Finished Jul 09 05:30:29 PM PDT 24
Peak memory 199860 kb
Host smart-725be7a6-0c8f-4488-a5ba-2c80f95a4c4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145769531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.3145769531
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.1647868315
Short name T650
Test name
Test status
Simulation time 52291502 ps
CPU time 0.71 seconds
Started Jul 09 05:30:22 PM PDT 24
Finished Jul 09 05:30:24 PM PDT 24
Peak memory 195204 kb
Host smart-ae753b73-0b12-4c0c-bb19-9d37f7e47713
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647868315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1647868315
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3376740855
Short name T597
Test name
Test status
Simulation time 287988491 ps
CPU time 1.75 seconds
Started Jul 09 05:30:25 PM PDT 24
Finished Jul 09 05:30:27 PM PDT 24
Peak memory 200192 kb
Host smart-13476612-fb8b-403a-aaa7-f4e4ce727e4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376740855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3376740855
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1126432860
Short name T539
Test name
Test status
Simulation time 562268815 ps
CPU time 2.75 seconds
Started Jul 09 05:30:25 PM PDT 24
Finished Jul 09 05:30:30 PM PDT 24
Peak memory 200220 kb
Host smart-fa847835-c3da-4838-a478-caf9391574c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126432860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1126432860
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1467767629
Short name T635
Test name
Test status
Simulation time 60995375 ps
CPU time 0.6 seconds
Started Jul 09 05:30:47 PM PDT 24
Finished Jul 09 05:30:50 PM PDT 24
Peak memory 195108 kb
Host smart-a706f5d0-b4d2-43ad-9dc7-c2e694cd37ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467767629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1467767629
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2440885494
Short name T540
Test name
Test status
Simulation time 30637372 ps
CPU time 0.62 seconds
Started Jul 09 05:30:50 PM PDT 24
Finished Jul 09 05:30:55 PM PDT 24
Peak memory 195260 kb
Host smart-4d552ad5-52b1-47df-a5e8-ea58da8e0cce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440885494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2440885494
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.428780462
Short name T578
Test name
Test status
Simulation time 14644614 ps
CPU time 0.62 seconds
Started Jul 09 05:30:51 PM PDT 24
Finished Jul 09 05:30:56 PM PDT 24
Peak memory 195196 kb
Host smart-860ed382-8691-475f-9b8f-d908e389b2f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428780462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.428780462
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3972169613
Short name T544
Test name
Test status
Simulation time 44104260 ps
CPU time 0.59 seconds
Started Jul 09 05:30:52 PM PDT 24
Finished Jul 09 05:30:56 PM PDT 24
Peak memory 194812 kb
Host smart-230100bc-61ae-42dd-be2f-fa6b36c5cf29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972169613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3972169613
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1974091548
Short name T622
Test name
Test status
Simulation time 40333796 ps
CPU time 0.59 seconds
Started Jul 09 05:30:48 PM PDT 24
Finished Jul 09 05:30:52 PM PDT 24
Peak memory 195180 kb
Host smart-bd9ff507-d4c3-459d-835e-5f76af62688e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974091548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1974091548
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3989974551
Short name T602
Test name
Test status
Simulation time 13185025 ps
CPU time 0.58 seconds
Started Jul 09 05:30:47 PM PDT 24
Finished Jul 09 05:30:50 PM PDT 24
Peak memory 195200 kb
Host smart-b1d2f9de-f2c5-4103-91af-1f81b9493878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989974551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3989974551
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1185861564
Short name T563
Test name
Test status
Simulation time 44127573 ps
CPU time 0.57 seconds
Started Jul 09 05:30:53 PM PDT 24
Finished Jul 09 05:30:57 PM PDT 24
Peak memory 195204 kb
Host smart-9307283a-4374-4145-adc8-5f008fcd18c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185861564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1185861564
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2364414760
Short name T567
Test name
Test status
Simulation time 41084553 ps
CPU time 0.57 seconds
Started Jul 09 05:30:52 PM PDT 24
Finished Jul 09 05:30:57 PM PDT 24
Peak memory 195172 kb
Host smart-cb3b6599-8621-4c0f-8e70-2cf83068dfb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364414760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2364414760
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1971118059
Short name T649
Test name
Test status
Simulation time 135665123 ps
CPU time 0.58 seconds
Started Jul 09 05:30:48 PM PDT 24
Finished Jul 09 05:30:52 PM PDT 24
Peak memory 195208 kb
Host smart-90190b31-b21f-4c44-b9c3-7d75597f5e09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971118059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1971118059
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1941279226
Short name T564
Test name
Test status
Simulation time 11047564 ps
CPU time 0.61 seconds
Started Jul 09 05:30:50 PM PDT 24
Finished Jul 09 05:30:54 PM PDT 24
Peak memory 195088 kb
Host smart-c1ffab66-4b27-4fe3-b110-2f313534d79f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941279226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1941279226
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.884410693
Short name T92
Test name
Test status
Simulation time 478048032 ps
CPU time 5.59 seconds
Started Jul 09 05:30:34 PM PDT 24
Finished Jul 09 05:30:40 PM PDT 24
Peak memory 200332 kb
Host smart-256d8cda-c3ec-45fe-a8af-cd21f4f42403
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884410693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.884410693
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2998737430
Short name T94
Test name
Test status
Simulation time 113842064 ps
CPU time 5.26 seconds
Started Jul 09 05:30:25 PM PDT 24
Finished Jul 09 05:30:31 PM PDT 24
Peak memory 200304 kb
Host smart-6c493bee-fc72-4c45-bf37-a6ba14d78a66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998737430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2998737430
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.534991792
Short name T102
Test name
Test status
Simulation time 43872260 ps
CPU time 1.02 seconds
Started Jul 09 05:30:25 PM PDT 24
Finished Jul 09 05:30:27 PM PDT 24
Peak memory 200156 kb
Host smart-2a200f67-f637-40f5-b428-dc3474dc6fb4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534991792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.534991792
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2467745900
Short name T651
Test name
Test status
Simulation time 18471495165 ps
CPU time 139.12 seconds
Started Jul 09 05:30:34 PM PDT 24
Finished Jul 09 05:32:54 PM PDT 24
Peak memory 216192 kb
Host smart-289d35a6-0dbc-4d70-8c21-fa414f211fe0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467745900 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2467745900
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2290823367
Short name T595
Test name
Test status
Simulation time 52022075 ps
CPU time 0.7 seconds
Started Jul 09 05:30:27 PM PDT 24
Finished Jul 09 05:30:28 PM PDT 24
Peak memory 198528 kb
Host smart-93c79bcb-cff3-460e-a825-4336ecbb9dae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290823367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2290823367
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3271646925
Short name T568
Test name
Test status
Simulation time 17715935 ps
CPU time 0.64 seconds
Started Jul 09 05:30:25 PM PDT 24
Finished Jul 09 05:30:27 PM PDT 24
Peak memory 195200 kb
Host smart-34991b9d-ec62-481f-83b7-97857f4ea87e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271646925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3271646925
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.131404703
Short name T111
Test name
Test status
Simulation time 116214890 ps
CPU time 1.51 seconds
Started Jul 09 05:30:23 PM PDT 24
Finished Jul 09 05:30:26 PM PDT 24
Peak memory 200132 kb
Host smart-5f91468e-07cd-4cb0-bd5f-d07fe1cbc041
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131404703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.131404703
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.816317771
Short name T617
Test name
Test status
Simulation time 155026477 ps
CPU time 1.8 seconds
Started Jul 09 05:30:26 PM PDT 24
Finished Jul 09 05:30:29 PM PDT 24
Peak memory 200336 kb
Host smart-c3619205-fade-4ebf-bb3f-a0c4c0d39311
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816317771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.816317771
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.314341350
Short name T590
Test name
Test status
Simulation time 192708607 ps
CPU time 1.81 seconds
Started Jul 09 05:30:24 PM PDT 24
Finished Jul 09 05:30:27 PM PDT 24
Peak memory 200268 kb
Host smart-826021ab-df9b-4b50-b92c-11103ce4457e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314341350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.314341350
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.28732666
Short name T581
Test name
Test status
Simulation time 34527713 ps
CPU time 0.58 seconds
Started Jul 09 05:30:49 PM PDT 24
Finished Jul 09 05:30:53 PM PDT 24
Peak memory 195180 kb
Host smart-d5638efa-9828-4267-92dd-f4ca9c504e90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28732666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.28732666
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2302916585
Short name T621
Test name
Test status
Simulation time 56629257 ps
CPU time 0.63 seconds
Started Jul 09 05:30:52 PM PDT 24
Finished Jul 09 05:30:57 PM PDT 24
Peak memory 195376 kb
Host smart-48fa293f-0270-499a-920b-474b194e811d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302916585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2302916585
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1699158890
Short name T655
Test name
Test status
Simulation time 13526113 ps
CPU time 0.69 seconds
Started Jul 09 05:30:52 PM PDT 24
Finished Jul 09 05:30:56 PM PDT 24
Peak memory 195192 kb
Host smart-0904fd09-55bf-4af4-866b-a6246dcbe93c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699158890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1699158890
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.114730709
Short name T533
Test name
Test status
Simulation time 20370612 ps
CPU time 0.63 seconds
Started Jul 09 05:30:58 PM PDT 24
Finished Jul 09 05:31:00 PM PDT 24
Peak memory 195272 kb
Host smart-cd6135ee-3407-41af-a481-765a2d3c5e6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114730709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.114730709
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1344987829
Short name T603
Test name
Test status
Simulation time 181496933 ps
CPU time 0.63 seconds
Started Jul 09 05:30:51 PM PDT 24
Finished Jul 09 05:30:56 PM PDT 24
Peak memory 195256 kb
Host smart-ceeb838b-5832-4581-a5c4-5604ed5ed635
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344987829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1344987829
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3447260326
Short name T611
Test name
Test status
Simulation time 43132834 ps
CPU time 0.65 seconds
Started Jul 09 05:30:48 PM PDT 24
Finished Jul 09 05:30:51 PM PDT 24
Peak memory 195132 kb
Host smart-0de2f7f4-537f-45aa-b136-c5d93590736c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447260326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3447260326
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2996171898
Short name T628
Test name
Test status
Simulation time 65302672 ps
CPU time 0.62 seconds
Started Jul 09 05:30:53 PM PDT 24
Finished Jul 09 05:30:57 PM PDT 24
Peak memory 195364 kb
Host smart-cea99afa-656d-42db-bc14-52a853c0f5e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996171898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2996171898
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.57685317
Short name T644
Test name
Test status
Simulation time 13840733 ps
CPU time 0.61 seconds
Started Jul 09 05:30:51 PM PDT 24
Finished Jul 09 05:30:55 PM PDT 24
Peak memory 195312 kb
Host smart-9f7a0a84-fb1b-43b5-8bfe-70138c587100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57685317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.57685317
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.1028601377
Short name T640
Test name
Test status
Simulation time 14590657 ps
CPU time 0.58 seconds
Started Jul 09 05:30:55 PM PDT 24
Finished Jul 09 05:30:58 PM PDT 24
Peak memory 195304 kb
Host smart-97f345c7-ac98-4da4-93cc-e6144d01b607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028601377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.1028601377
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.851209850
Short name T548
Test name
Test status
Simulation time 13747950 ps
CPU time 0.6 seconds
Started Jul 09 05:30:49 PM PDT 24
Finished Jul 09 05:30:52 PM PDT 24
Peak memory 195180 kb
Host smart-a3bf6e61-3182-48a0-af08-3c18f65c31d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851209850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.851209850
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1853748162
Short name T657
Test name
Test status
Simulation time 678934609 ps
CPU time 3.5 seconds
Started Jul 09 05:30:29 PM PDT 24
Finished Jul 09 05:30:33 PM PDT 24
Peak memory 200248 kb
Host smart-7caf362d-1611-4fe3-9f5b-e499f8147f9d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853748162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1853748162
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2119614351
Short name T99
Test name
Test status
Simulation time 934018862 ps
CPU time 9.73 seconds
Started Jul 09 05:30:33 PM PDT 24
Finished Jul 09 05:30:44 PM PDT 24
Peak memory 200308 kb
Host smart-8efdd973-6e06-4349-a0de-3864acacb6a7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119614351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2119614351
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.49822127
Short name T586
Test name
Test status
Simulation time 92768471 ps
CPU time 0.71 seconds
Started Jul 09 05:30:27 PM PDT 24
Finished Jul 09 05:30:29 PM PDT 24
Peak memory 198208 kb
Host smart-dd03e252-ab1e-4405-8d47-5b38b0b8c3e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49822127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.49822127
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.784384880
Short name T591
Test name
Test status
Simulation time 73710296287 ps
CPU time 733.44 seconds
Started Jul 09 05:30:46 PM PDT 24
Finished Jul 09 05:43:01 PM PDT 24
Peak memory 216808 kb
Host smart-f1696076-f76a-4da9-96dd-c2ca016de8a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784384880 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.784384880
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3356397477
Short name T643
Test name
Test status
Simulation time 17540661 ps
CPU time 0.93 seconds
Started Jul 09 05:30:39 PM PDT 24
Finished Jul 09 05:30:41 PM PDT 24
Peak memory 199592 kb
Host smart-bcb8ff07-2cae-47ca-abb6-2d8927b299c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356397477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3356397477
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.786233866
Short name T638
Test name
Test status
Simulation time 11856553 ps
CPU time 0.59 seconds
Started Jul 09 05:30:31 PM PDT 24
Finished Jul 09 05:30:32 PM PDT 24
Peak memory 195236 kb
Host smart-9a838997-6a1a-41d8-898f-c6c17b6085e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786233866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.786233866
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1397419053
Short name T571
Test name
Test status
Simulation time 488491441 ps
CPU time 2.11 seconds
Started Jul 09 05:30:28 PM PDT 24
Finished Jul 09 05:30:31 PM PDT 24
Peak memory 200256 kb
Host smart-84a0f517-0ede-4f03-92ae-a145550b6956
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397419053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1397419053
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.820376408
Short name T579
Test name
Test status
Simulation time 50645787 ps
CPU time 2.64 seconds
Started Jul 09 05:30:34 PM PDT 24
Finished Jul 09 05:30:37 PM PDT 24
Peak memory 200292 kb
Host smart-96e5738b-7c14-4189-8d33-b6e6687d8152
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820376408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.820376408
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.499208012
Short name T658
Test name
Test status
Simulation time 13540934 ps
CPU time 0.57 seconds
Started Jul 09 05:30:51 PM PDT 24
Finished Jul 09 05:30:55 PM PDT 24
Peak memory 195136 kb
Host smart-02fca6f8-bbf9-4749-8637-ac395b1ffdf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499208012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.499208012
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1840387053
Short name T612
Test name
Test status
Simulation time 23963781 ps
CPU time 0.6 seconds
Started Jul 09 05:30:51 PM PDT 24
Finished Jul 09 05:30:56 PM PDT 24
Peak memory 195228 kb
Host smart-52b8ff90-365f-495e-9606-d48f07ced995
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840387053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1840387053
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3326132115
Short name T561
Test name
Test status
Simulation time 19855238 ps
CPU time 0.63 seconds
Started Jul 09 05:30:51 PM PDT 24
Finished Jul 09 05:30:56 PM PDT 24
Peak memory 195128 kb
Host smart-793531b6-0ad7-46c4-87c0-5cbb03a1dec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326132115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3326132115
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2090325773
Short name T573
Test name
Test status
Simulation time 32297147 ps
CPU time 0.57 seconds
Started Jul 09 05:30:49 PM PDT 24
Finished Jul 09 05:30:53 PM PDT 24
Peak memory 195184 kb
Host smart-c0f3313c-1e67-4ea5-8695-f8a26c4e1c3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090325773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2090325773
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3283587955
Short name T653
Test name
Test status
Simulation time 13212307 ps
CPU time 0.63 seconds
Started Jul 09 05:30:53 PM PDT 24
Finished Jul 09 05:30:57 PM PDT 24
Peak memory 195272 kb
Host smart-1f052dce-b75d-499a-be13-221c9ed5ed74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283587955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3283587955
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.902244196
Short name T546
Test name
Test status
Simulation time 15216831 ps
CPU time 0.62 seconds
Started Jul 09 05:30:52 PM PDT 24
Finished Jul 09 05:30:57 PM PDT 24
Peak memory 195284 kb
Host smart-2a99d480-659d-47d5-9945-e4dc73d792cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902244196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.902244196
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.3283197719
Short name T549
Test name
Test status
Simulation time 33292726 ps
CPU time 0.62 seconds
Started Jul 09 05:30:50 PM PDT 24
Finished Jul 09 05:30:55 PM PDT 24
Peak memory 195204 kb
Host smart-b93e220c-0e10-4d4e-ba35-86e3a280686f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283197719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.3283197719
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1379903735
Short name T582
Test name
Test status
Simulation time 34594940 ps
CPU time 0.62 seconds
Started Jul 09 05:30:50 PM PDT 24
Finished Jul 09 05:30:55 PM PDT 24
Peak memory 195124 kb
Host smart-980e9c96-fb48-46d6-a0b2-c429bcb30b09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379903735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1379903735
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.3339843528
Short name T605
Test name
Test status
Simulation time 14082255 ps
CPU time 0.57 seconds
Started Jul 09 05:30:51 PM PDT 24
Finished Jul 09 05:30:55 PM PDT 24
Peak memory 195176 kb
Host smart-d363205c-0982-4488-9051-1c925466a9c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339843528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.3339843528
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3139943742
Short name T648
Test name
Test status
Simulation time 14367262 ps
CPU time 0.58 seconds
Started Jul 09 05:30:49 PM PDT 24
Finished Jul 09 05:30:53 PM PDT 24
Peak memory 195172 kb
Host smart-f04f6b82-447e-4615-9b1a-8be714663965
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139943742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3139943742
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4289312050
Short name T616
Test name
Test status
Simulation time 278096774886 ps
CPU time 979.93 seconds
Started Jul 09 05:30:49 PM PDT 24
Finished Jul 09 05:47:12 PM PDT 24
Peak memory 216696 kb
Host smart-0cec75e0-7fce-4ed1-b449-d260a8d98ec2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289312050 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.4289312050
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.502615122
Short name T98
Test name
Test status
Simulation time 13898144 ps
CPU time 0.69 seconds
Started Jul 09 05:30:47 PM PDT 24
Finished Jul 09 05:30:50 PM PDT 24
Peak memory 198168 kb
Host smart-7dca4724-8665-411d-90a6-260a6ebe0b26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502615122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.502615122
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.947355824
Short name T613
Test name
Test status
Simulation time 29213300 ps
CPU time 0.58 seconds
Started Jul 09 05:30:38 PM PDT 24
Finished Jul 09 05:30:39 PM PDT 24
Peak memory 195192 kb
Host smart-a998cae2-f575-4b61-85fd-4b8d2e2d57e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947355824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.947355824
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3567901276
Short name T594
Test name
Test status
Simulation time 146766238 ps
CPU time 2.45 seconds
Started Jul 09 05:30:33 PM PDT 24
Finished Jul 09 05:30:36 PM PDT 24
Peak memory 200188 kb
Host smart-7e64fea4-0419-432c-a38f-2381171aa68e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567901276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3567901276
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1261131103
Short name T599
Test name
Test status
Simulation time 32369476 ps
CPU time 1.49 seconds
Started Jul 09 05:30:55 PM PDT 24
Finished Jul 09 05:30:59 PM PDT 24
Peak memory 200304 kb
Host smart-9dcbc8ea-4c7b-4e00-860e-9e774f87b123
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261131103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1261131103
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3539936851
Short name T125
Test name
Test status
Simulation time 133527650 ps
CPU time 3.98 seconds
Started Jul 09 05:30:34 PM PDT 24
Finished Jul 09 05:30:39 PM PDT 24
Peak memory 200312 kb
Host smart-cec63714-8832-407a-bcdb-1fe28abfb100
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539936851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3539936851
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1705804693
Short name T547
Test name
Test status
Simulation time 47454002 ps
CPU time 2.81 seconds
Started Jul 09 05:30:45 PM PDT 24
Finished Jul 09 05:30:49 PM PDT 24
Peak memory 200436 kb
Host smart-acacd88b-4863-461c-baa0-7ee90c2a5b58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705804693 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1705804693
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.235289474
Short name T606
Test name
Test status
Simulation time 29070598 ps
CPU time 0.95 seconds
Started Jul 09 05:30:37 PM PDT 24
Finished Jul 09 05:30:38 PM PDT 24
Peak memory 200104 kb
Host smart-ae38596b-55a2-40de-befe-024acce9c49f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235289474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.235289474
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3196392530
Short name T636
Test name
Test status
Simulation time 105807975 ps
CPU time 0.59 seconds
Started Jul 09 05:30:32 PM PDT 24
Finished Jul 09 05:30:33 PM PDT 24
Peak memory 195196 kb
Host smart-c721398b-7abb-4255-8821-bf3494618624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196392530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3196392530
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3176239624
Short name T620
Test name
Test status
Simulation time 130279827 ps
CPU time 1.62 seconds
Started Jul 09 05:30:32 PM PDT 24
Finished Jul 09 05:30:34 PM PDT 24
Peak memory 200208 kb
Host smart-fd899602-564e-4e38-916b-9d783495c488
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176239624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3176239624
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.708891626
Short name T593
Test name
Test status
Simulation time 534174160 ps
CPU time 3.27 seconds
Started Jul 09 05:30:36 PM PDT 24
Finished Jul 09 05:30:40 PM PDT 24
Peak memory 200364 kb
Host smart-f4a31cbe-4020-4e0e-a35b-a61fb029ec99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708891626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.708891626
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2841661846
Short name T626
Test name
Test status
Simulation time 232707891 ps
CPU time 4.13 seconds
Started Jul 09 05:30:50 PM PDT 24
Finished Jul 09 05:30:58 PM PDT 24
Peak memory 200316 kb
Host smart-c550b8c5-10a5-420b-9efa-2ba19c974a10
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841661846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2841661846
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1218048543
Short name T553
Test name
Test status
Simulation time 20450498950 ps
CPU time 201.44 seconds
Started Jul 09 05:30:43 PM PDT 24
Finished Jul 09 05:34:05 PM PDT 24
Peak memory 215968 kb
Host smart-7372ffe9-4017-44b2-80b4-3dae318ce956
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218048543 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1218048543
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.4057189833
Short name T624
Test name
Test status
Simulation time 18476351 ps
CPU time 0.92 seconds
Started Jul 09 05:30:46 PM PDT 24
Finished Jul 09 05:30:49 PM PDT 24
Peak memory 199924 kb
Host smart-12fd390e-c192-45a1-ab1c-c6c2922b08c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057189833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.4057189833
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3338530977
Short name T627
Test name
Test status
Simulation time 63589944 ps
CPU time 0.59 seconds
Started Jul 09 05:30:48 PM PDT 24
Finished Jul 09 05:30:51 PM PDT 24
Peak memory 195204 kb
Host smart-ee521a79-c660-4add-96f5-d666eb7917d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338530977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3338530977
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2728686751
Short name T588
Test name
Test status
Simulation time 98758712 ps
CPU time 1.75 seconds
Started Jul 09 05:30:49 PM PDT 24
Finished Jul 09 05:30:54 PM PDT 24
Peak memory 200288 kb
Host smart-1fde7947-f2e8-4f02-8e5d-1b3259844f96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728686751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2728686751
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3267442698
Short name T566
Test name
Test status
Simulation time 103779038 ps
CPU time 1.36 seconds
Started Jul 09 05:30:48 PM PDT 24
Finished Jul 09 05:30:52 PM PDT 24
Peak memory 200168 kb
Host smart-5d24bfb4-6cd2-493e-a4fd-8ffe93c0f382
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267442698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3267442698
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3554467933
Short name T600
Test name
Test status
Simulation time 51578185 ps
CPU time 1.74 seconds
Started Jul 09 05:30:46 PM PDT 24
Finished Jul 09 05:30:49 PM PDT 24
Peak memory 200312 kb
Host smart-3ae479ac-e773-4445-9426-0da755ac3a7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554467933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3554467933
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3012972088
Short name T632
Test name
Test status
Simulation time 61401485 ps
CPU time 1.67 seconds
Started Jul 09 05:31:45 PM PDT 24
Finished Jul 09 05:31:47 PM PDT 24
Peak memory 200176 kb
Host smart-dbcf9b22-6e4d-4370-b03d-22bbedd963d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012972088 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3012972088
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.471391263
Short name T630
Test name
Test status
Simulation time 108522960 ps
CPU time 0.88 seconds
Started Jul 09 05:30:44 PM PDT 24
Finished Jul 09 05:30:46 PM PDT 24
Peak memory 200160 kb
Host smart-53336597-f879-44c5-8e87-d2d0dfca620b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471391263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.471391263
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.1394312584
Short name T604
Test name
Test status
Simulation time 48178108 ps
CPU time 0.59 seconds
Started Jul 09 05:30:49 PM PDT 24
Finished Jul 09 05:30:53 PM PDT 24
Peak memory 195156 kb
Host smart-6b832d84-7c24-47dc-bfae-e5b4cf760cdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394312584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1394312584
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3730796844
Short name T619
Test name
Test status
Simulation time 123454004 ps
CPU time 1.68 seconds
Started Jul 09 05:30:35 PM PDT 24
Finished Jul 09 05:30:37 PM PDT 24
Peak memory 200072 kb
Host smart-32180061-9564-4b21-9bb6-5356352c574f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730796844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3730796844
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1563448237
Short name T633
Test name
Test status
Simulation time 551882171 ps
CPU time 2.5 seconds
Started Jul 09 05:30:45 PM PDT 24
Finished Jul 09 05:30:49 PM PDT 24
Peak memory 200300 kb
Host smart-861b44c7-d99d-4f36-ac21-4c4463e7a7a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563448237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1563448237
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.646110886
Short name T122
Test name
Test status
Simulation time 231520225 ps
CPU time 4.39 seconds
Started Jul 09 05:30:43 PM PDT 24
Finished Jul 09 05:30:48 PM PDT 24
Peak memory 200316 kb
Host smart-f60a21fa-b9ad-411c-801f-d4488a9695d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646110886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.646110886
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2813929793
Short name T625
Test name
Test status
Simulation time 99842512 ps
CPU time 1.7 seconds
Started Jul 09 05:30:46 PM PDT 24
Finished Jul 09 05:30:49 PM PDT 24
Peak memory 200220 kb
Host smart-7bf11b9a-7563-44a2-b92a-d845420f4e41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813929793 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2813929793
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2287435200
Short name T598
Test name
Test status
Simulation time 93926303 ps
CPU time 0.79 seconds
Started Jul 09 05:30:54 PM PDT 24
Finished Jul 09 05:30:58 PM PDT 24
Peak memory 199564 kb
Host smart-c5646206-c636-4d04-a5e7-98a364b0e022
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287435200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2287435200
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3276224725
Short name T537
Test name
Test status
Simulation time 11804709 ps
CPU time 0.57 seconds
Started Jul 09 05:30:44 PM PDT 24
Finished Jul 09 05:30:46 PM PDT 24
Peak memory 195196 kb
Host smart-375e3079-75f0-42bd-a61e-b768560d62f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276224725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3276224725
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2265645205
Short name T584
Test name
Test status
Simulation time 207275905 ps
CPU time 1.21 seconds
Started Jul 09 05:30:50 PM PDT 24
Finished Jul 09 05:30:54 PM PDT 24
Peak memory 198624 kb
Host smart-c08f1420-78ed-40a4-8409-90ce659936e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265645205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2265645205
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.38678927
Short name T577
Test name
Test status
Simulation time 1061300208 ps
CPU time 4.1 seconds
Started Jul 09 05:30:44 PM PDT 24
Finished Jul 09 05:30:49 PM PDT 24
Peak memory 200268 kb
Host smart-052fb766-b8a4-49db-94f6-0007b48258f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38678927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.38678927
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3362004360
Short name T61
Test name
Test status
Simulation time 552097970 ps
CPU time 3.95 seconds
Started Jul 09 05:30:44 PM PDT 24
Finished Jul 09 05:30:49 PM PDT 24
Peak memory 200316 kb
Host smart-1a004ed1-4c05-49e7-83f5-22c784f65cb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362004360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3362004360
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3779998377
Short name T428
Test name
Test status
Simulation time 31300685 ps
CPU time 0.58 seconds
Started Jul 09 07:02:52 PM PDT 24
Finished Jul 09 07:02:55 PM PDT 24
Peak memory 195840 kb
Host smart-38e99bb3-7070-47b0-b04e-fc94c48c5e8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779998377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3779998377
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.137691906
Short name T38
Test name
Test status
Simulation time 4698574577 ps
CPU time 58.86 seconds
Started Jul 09 07:02:45 PM PDT 24
Finished Jul 09 07:03:45 PM PDT 24
Peak memory 216856 kb
Host smart-456e8368-4223-4fbe-a2a3-c95f7e2cd161
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=137691906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.137691906
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1754844909
Short name T201
Test name
Test status
Simulation time 2423113199 ps
CPU time 575.5 seconds
Started Jul 09 07:02:44 PM PDT 24
Finished Jul 09 07:12:21 PM PDT 24
Peak memory 683672 kb
Host smart-358a4875-ef44-46ae-a572-6e8d70813094
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1754844909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1754844909
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.969573926
Short name T348
Test name
Test status
Simulation time 4024185151 ps
CPU time 106.56 seconds
Started Jul 09 07:02:39 PM PDT 24
Finished Jul 09 07:04:26 PM PDT 24
Peak memory 200584 kb
Host smart-b94c9172-41e1-4fe2-a14a-a0d3a28f968a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969573926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.969573926
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.3022281677
Short name T289
Test name
Test status
Simulation time 61276815627 ps
CPU time 139.87 seconds
Started Jul 09 07:02:40 PM PDT 24
Finished Jul 09 07:05:01 PM PDT 24
Peak memory 200420 kb
Host smart-ec23ca97-b975-4dae-bae4-23afa1dbfa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022281677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.3022281677
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.3679935748
Short name T323
Test name
Test status
Simulation time 44539659 ps
CPU time 0.9 seconds
Started Jul 09 07:02:46 PM PDT 24
Finished Jul 09 07:02:47 PM PDT 24
Peak memory 198896 kb
Host smart-fd4559cc-9343-43c4-a66f-3ada050b5fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679935748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3679935748
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.201190198
Short name T452
Test name
Test status
Simulation time 32096765805 ps
CPU time 542.77 seconds
Started Jul 09 07:02:47 PM PDT 24
Finished Jul 09 07:11:51 PM PDT 24
Peak memory 465088 kb
Host smart-d371ed8d-cfd6-434f-bd14-81f4be59d570
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201190198 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.201190198
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.3508343694
Short name T9
Test name
Test status
Simulation time 9163477599 ps
CPU time 136.14 seconds
Started Jul 09 07:02:38 PM PDT 24
Finished Jul 09 07:04:55 PM PDT 24
Peak memory 216536 kb
Host smart-bdb4d683-c6bc-430e-9d4b-fdc722bdb002
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3508343694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.3508343694
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.3976591667
Short name T360
Test name
Test status
Simulation time 13095584837 ps
CPU time 76.7 seconds
Started Jul 09 07:02:41 PM PDT 24
Finished Jul 09 07:03:58 PM PDT 24
Peak memory 200348 kb
Host smart-cf859790-1a51-46a2-8727-e883e003b8b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3976591667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.3976591667
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.126201033
Short name T478
Test name
Test status
Simulation time 4922037430 ps
CPU time 96.1 seconds
Started Jul 09 07:02:40 PM PDT 24
Finished Jul 09 07:04:17 PM PDT 24
Peak memory 200380 kb
Host smart-c2585de3-63f4-4efb-b7ed-450f0af4c860
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=126201033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.126201033
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.249629223
Short name T517
Test name
Test status
Simulation time 2284887541 ps
CPU time 77.24 seconds
Started Jul 09 07:02:39 PM PDT 24
Finished Jul 09 07:03:57 PM PDT 24
Peak memory 200244 kb
Host smart-426cd697-ec59-4b52-9cac-fc386e6c76cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=249629223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.249629223
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3787822800
Short name T364
Test name
Test status
Simulation time 83765870539 ps
CPU time 606.68 seconds
Started Jul 09 07:02:41 PM PDT 24
Finished Jul 09 07:12:49 PM PDT 24
Peak memory 200368 kb
Host smart-bf291f34-fa28-4c7f-b34e-49fb1f7fe942
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3787822800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3787822800
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.1402880703
Short name T480
Test name
Test status
Simulation time 273319280148 ps
CPU time 2406.47 seconds
Started Jul 09 07:02:51 PM PDT 24
Finished Jul 09 07:42:59 PM PDT 24
Peak memory 216404 kb
Host smart-8d8cc208-465b-4163-b445-6a00f00319bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1402880703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.1402880703
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.3345841126
Short name T235
Test name
Test status
Simulation time 1138123344425 ps
CPU time 2336.43 seconds
Started Jul 09 07:02:41 PM PDT 24
Finished Jul 09 07:41:39 PM PDT 24
Peak memory 216232 kb
Host smart-67e8bd5d-3164-4ae5-8d18-9d189a665863
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3345841126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.3345841126
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.4186488618
Short name T476
Test name
Test status
Simulation time 2226263186 ps
CPU time 101.38 seconds
Started Jul 09 07:02:41 PM PDT 24
Finished Jul 09 07:04:23 PM PDT 24
Peak memory 200408 kb
Host smart-3dfdd79f-1346-4169-877c-d25af8bcbd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186488618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.4186488618
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.794474638
Short name T457
Test name
Test status
Simulation time 48570836 ps
CPU time 0.59 seconds
Started Jul 09 07:02:51 PM PDT 24
Finished Jul 09 07:02:53 PM PDT 24
Peak memory 195192 kb
Host smart-edb6fb17-d570-44d4-a931-1122e468883a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794474638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.794474638
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.372532897
Short name T206
Test name
Test status
Simulation time 3742847582 ps
CPU time 88.98 seconds
Started Jul 09 07:02:40 PM PDT 24
Finished Jul 09 07:04:10 PM PDT 24
Peak memory 216648 kb
Host smart-63330b42-82f9-40e0-a599-31ccc4ba8733
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=372532897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.372532897
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2644624065
Short name T163
Test name
Test status
Simulation time 3137076048 ps
CPU time 40.38 seconds
Started Jul 09 07:02:42 PM PDT 24
Finished Jul 09 07:03:23 PM PDT 24
Peak memory 200340 kb
Host smart-ba098023-c7a8-40b5-aac4-842f04b75007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644624065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2644624065
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.155981739
Short name T312
Test name
Test status
Simulation time 807917763 ps
CPU time 156.82 seconds
Started Jul 09 07:02:41 PM PDT 24
Finished Jul 09 07:05:19 PM PDT 24
Peak memory 622224 kb
Host smart-56819620-5be6-42b8-9ab1-89c7a10b7db5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=155981739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.155981739
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.2365192795
Short name T477
Test name
Test status
Simulation time 8074926505 ps
CPU time 70.51 seconds
Started Jul 09 07:02:54 PM PDT 24
Finished Jul 09 07:04:06 PM PDT 24
Peak memory 200428 kb
Host smart-afaaac04-cb89-485e-9015-0dba85117539
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365192795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.2365192795
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.671781043
Short name T259
Test name
Test status
Simulation time 59858602 ps
CPU time 3.67 seconds
Started Jul 09 07:02:41 PM PDT 24
Finished Jul 09 07:02:45 PM PDT 24
Peak memory 200256 kb
Host smart-5e154484-7099-4f75-a8c9-95781ba50504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671781043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.671781043
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.2327416419
Short name T48
Test name
Test status
Simulation time 80318123 ps
CPU time 0.88 seconds
Started Jul 09 07:02:49 PM PDT 24
Finished Jul 09 07:02:51 PM PDT 24
Peak memory 218448 kb
Host smart-f3a743ed-f349-46d7-9ebd-9d30a52fc3d9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327416419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.2327416419
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.550997959
Short name T249
Test name
Test status
Simulation time 3402499683 ps
CPU time 13.45 seconds
Started Jul 09 07:02:43 PM PDT 24
Finished Jul 09 07:02:57 PM PDT 24
Peak memory 200436 kb
Host smart-5a9f8a86-9561-41f6-9e75-b5be35f566c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550997959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.550997959
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3935000710
Short name T498
Test name
Test status
Simulation time 81738502409 ps
CPU time 796.84 seconds
Started Jul 09 07:02:48 PM PDT 24
Finished Jul 09 07:16:06 PM PDT 24
Peak memory 497912 kb
Host smart-7296a659-1075-481a-af65-b1451a6b185f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935000710 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3935000710
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.1424623865
Short name T376
Test name
Test status
Simulation time 1601707019 ps
CPU time 62.67 seconds
Started Jul 09 07:02:50 PM PDT 24
Finished Jul 09 07:03:54 PM PDT 24
Peak memory 200252 kb
Host smart-62946ade-8e58-4b48-8b8d-429d0d811a08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1424623865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.1424623865
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.1134306224
Short name T382
Test name
Test status
Simulation time 4786723894 ps
CPU time 101.03 seconds
Started Jul 09 07:02:54 PM PDT 24
Finished Jul 09 07:04:37 PM PDT 24
Peak memory 200364 kb
Host smart-ff84fbd2-c6f5-4052-bc73-e4460eabb716
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1134306224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.1134306224
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.1588894305
Short name T232
Test name
Test status
Simulation time 24167397174 ps
CPU time 146.88 seconds
Started Jul 09 07:02:49 PM PDT 24
Finished Jul 09 07:05:17 PM PDT 24
Peak memory 200396 kb
Host smart-1b4acb10-cd0f-4697-b9c0-79ce6ed772bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1588894305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.1588894305
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.3982999709
Short name T215
Test name
Test status
Simulation time 490927286769 ps
CPU time 633.87 seconds
Started Jul 09 07:02:45 PM PDT 24
Finished Jul 09 07:13:19 PM PDT 24
Peak memory 200412 kb
Host smart-56562c92-e179-4185-bee8-af2faa72dfef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3982999709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.3982999709
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.2568999666
Short name T128
Test name
Test status
Simulation time 221630992413 ps
CPU time 2166.85 seconds
Started Jul 09 07:02:52 PM PDT 24
Finished Jul 09 07:39:01 PM PDT 24
Peak memory 215920 kb
Host smart-e7eb4470-a1e1-4722-befe-81dcce3a473e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2568999666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.2568999666
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.2591193928
Short name T409
Test name
Test status
Simulation time 425484251974 ps
CPU time 2159.49 seconds
Started Jul 09 07:02:52 PM PDT 24
Finished Jul 09 07:38:53 PM PDT 24
Peak memory 216612 kb
Host smart-6e451e86-55d8-47ce-8000-1f601f3f57e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2591193928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.2591193928
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1341161027
Short name T334
Test name
Test status
Simulation time 4067770167 ps
CPU time 53.52 seconds
Started Jul 09 07:02:47 PM PDT 24
Finished Jul 09 07:03:42 PM PDT 24
Peak memory 200360 kb
Host smart-4bf3c626-547c-40f9-8eec-7c1ef76df5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341161027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1341161027
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3229940094
Short name T282
Test name
Test status
Simulation time 17093382 ps
CPU time 0.59 seconds
Started Jul 09 07:03:08 PM PDT 24
Finished Jul 09 07:03:12 PM PDT 24
Peak memory 196216 kb
Host smart-bdc792b0-e4ce-4510-b978-5bcc197ce996
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229940094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3229940094
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.943131058
Short name T243
Test name
Test status
Simulation time 8046535686 ps
CPU time 90.97 seconds
Started Jul 09 07:03:13 PM PDT 24
Finished Jul 09 07:04:46 PM PDT 24
Peak memory 208572 kb
Host smart-1781b0b3-ac3a-413c-bf20-fa149a0ed617
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=943131058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.943131058
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.277613768
Short name T273
Test name
Test status
Simulation time 9785899520 ps
CPU time 58.97 seconds
Started Jul 09 07:03:02 PM PDT 24
Finished Jul 09 07:04:05 PM PDT 24
Peak memory 200380 kb
Host smart-53be9f2d-33a1-4df6-9ed7-a4b736c4910f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277613768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.277613768
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1679840490
Short name T277
Test name
Test status
Simulation time 5142698280 ps
CPU time 807.92 seconds
Started Jul 09 07:03:02 PM PDT 24
Finished Jul 09 07:16:35 PM PDT 24
Peak memory 692136 kb
Host smart-15f68f2b-9ef2-4f07-939e-3ccc6f0d4cfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679840490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1679840490
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.4175725191
Short name T502
Test name
Test status
Simulation time 5402213899 ps
CPU time 151.31 seconds
Started Jul 09 07:03:12 PM PDT 24
Finished Jul 09 07:05:46 PM PDT 24
Peak memory 200376 kb
Host smart-756b9f31-83fa-48ae-bba2-95eb33fb5d78
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175725191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.4175725191
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1043084259
Short name T67
Test name
Test status
Simulation time 325751260 ps
CPU time 4.71 seconds
Started Jul 09 07:03:02 PM PDT 24
Finished Jul 09 07:03:11 PM PDT 24
Peak memory 200260 kb
Host smart-0e01238a-737a-448f-bad6-93556ea94299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043084259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1043084259
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3361584660
Short name T15
Test name
Test status
Simulation time 551782991 ps
CPU time 6.86 seconds
Started Jul 09 07:03:03 PM PDT 24
Finished Jul 09 07:03:14 PM PDT 24
Peak memory 200316 kb
Host smart-81d21415-2ab9-4fc3-b6ee-7c02981f8063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361584660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3361584660
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.112636754
Short name T401
Test name
Test status
Simulation time 26443417023 ps
CPU time 197.42 seconds
Started Jul 09 07:03:03 PM PDT 24
Finished Jul 09 07:06:25 PM PDT 24
Peak memory 200372 kb
Host smart-26d35373-a402-4cec-9c6f-fb94e5a417f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112636754 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.112636754
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.449305061
Short name T310
Test name
Test status
Simulation time 1657141679 ps
CPU time 80.22 seconds
Started Jul 09 07:03:02 PM PDT 24
Finished Jul 09 07:04:27 PM PDT 24
Peak memory 200300 kb
Host smart-edfc9540-d2f8-4e89-ad41-9d573f908fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449305061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.449305061
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3899029722
Short name T469
Test name
Test status
Simulation time 16410761 ps
CPU time 0.59 seconds
Started Jul 09 07:03:18 PM PDT 24
Finished Jul 09 07:03:21 PM PDT 24
Peak memory 196208 kb
Host smart-24662b78-e722-41e7-bb70-49147472b383
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899029722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3899029722
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.283323880
Short name T11
Test name
Test status
Simulation time 323143441 ps
CPU time 18.36 seconds
Started Jul 09 07:03:01 PM PDT 24
Finished Jul 09 07:03:22 PM PDT 24
Peak memory 200336 kb
Host smart-407f55e0-0f04-415d-88de-653fd95d4086
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=283323880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.283323880
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3635789787
Short name T281
Test name
Test status
Simulation time 9899488396 ps
CPU time 31.77 seconds
Started Jul 09 07:03:14 PM PDT 24
Finished Jul 09 07:03:48 PM PDT 24
Peak memory 200264 kb
Host smart-2b35e98f-7b29-4565-8f68-92df4aa450de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635789787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3635789787
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.566811359
Short name T68
Test name
Test status
Simulation time 3908800559 ps
CPU time 853.5 seconds
Started Jul 09 07:03:13 PM PDT 24
Finished Jul 09 07:17:28 PM PDT 24
Peak memory 694516 kb
Host smart-f838c9f8-e997-49b0-bd48-d1de61c6046d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=566811359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.566811359
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.4026729567
Short name T292
Test name
Test status
Simulation time 1817839007 ps
CPU time 26.02 seconds
Started Jul 09 07:03:01 PM PDT 24
Finished Jul 09 07:03:32 PM PDT 24
Peak memory 200344 kb
Host smart-bfa39810-5088-406c-9b64-874314dade01
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026729567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.4026729567
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3455967598
Short name T229
Test name
Test status
Simulation time 4809915220 ps
CPU time 89.57 seconds
Started Jul 09 07:03:06 PM PDT 24
Finished Jul 09 07:04:41 PM PDT 24
Peak memory 200352 kb
Host smart-1b5f2855-2465-4cf5-9a49-9b8dabe661b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455967598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3455967598
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2499537831
Short name T175
Test name
Test status
Simulation time 1804019599 ps
CPU time 11.23 seconds
Started Jul 09 07:03:04 PM PDT 24
Finished Jul 09 07:03:20 PM PDT 24
Peak memory 200308 kb
Host smart-536b1495-de4a-460a-bfb6-a9bf73ce7aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499537831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2499537831
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.254238233
Short name T3
Test name
Test status
Simulation time 16048390261 ps
CPU time 50.01 seconds
Started Jul 09 07:03:03 PM PDT 24
Finished Jul 09 07:03:58 PM PDT 24
Peak memory 200384 kb
Host smart-fd92cdbb-5a98-4223-8e90-c622fe499f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254238233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.254238233
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2798867113
Short name T426
Test name
Test status
Simulation time 33854806 ps
CPU time 0.61 seconds
Started Jul 09 07:03:04 PM PDT 24
Finished Jul 09 07:03:10 PM PDT 24
Peak memory 195852 kb
Host smart-547bc5ca-5674-43a7-8934-b992606cdb76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798867113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2798867113
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3519386359
Short name T340
Test name
Test status
Simulation time 788556223 ps
CPU time 42.73 seconds
Started Jul 09 07:03:07 PM PDT 24
Finished Jul 09 07:03:54 PM PDT 24
Peak memory 200360 kb
Host smart-3dd6a208-59ce-4adf-9010-03e7de7d9d12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3519386359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3519386359
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.798129876
Short name T164
Test name
Test status
Simulation time 4004850812 ps
CPU time 17.55 seconds
Started Jul 09 07:03:02 PM PDT 24
Finished Jul 09 07:03:25 PM PDT 24
Peak memory 200468 kb
Host smart-681aa0db-64a4-4029-b729-44aa2e151212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798129876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.798129876
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.629992546
Short name T226
Test name
Test status
Simulation time 23979183284 ps
CPU time 1022.66 seconds
Started Jul 09 07:03:03 PM PDT 24
Finished Jul 09 07:20:11 PM PDT 24
Peak memory 685852 kb
Host smart-614165af-61a4-46d8-b7a2-f62ed7772af8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=629992546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.629992546
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1629043906
Short name T194
Test name
Test status
Simulation time 7568760794 ps
CPU time 30.4 seconds
Started Jul 09 07:03:03 PM PDT 24
Finished Jul 09 07:03:39 PM PDT 24
Peak memory 200192 kb
Host smart-f9a2bf7b-ece1-4d2a-bc8e-5a89f60ad94b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629043906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1629043906
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1152861145
Short name T472
Test name
Test status
Simulation time 86129271070 ps
CPU time 142.86 seconds
Started Jul 09 07:03:04 PM PDT 24
Finished Jul 09 07:05:33 PM PDT 24
Peak memory 200368 kb
Host smart-2589f5f4-a978-4274-8bc3-df45ebba0bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152861145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1152861145
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2010268621
Short name T216
Test name
Test status
Simulation time 1128252108 ps
CPU time 10.93 seconds
Started Jul 09 07:03:04 PM PDT 24
Finished Jul 09 07:03:21 PM PDT 24
Peak memory 200200 kb
Host smart-3d6659f4-67fd-466f-9590-ae7baf94ebb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010268621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2010268621
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2898464832
Short name T73
Test name
Test status
Simulation time 37107291213 ps
CPU time 638.17 seconds
Started Jul 09 07:03:09 PM PDT 24
Finished Jul 09 07:13:51 PM PDT 24
Peak memory 443804 kb
Host smart-3750ba94-1771-45e0-b5e0-ea92ded95edd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898464832 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2898464832
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1180715802
Short name T77
Test name
Test status
Simulation time 1881971731 ps
CPU time 24.49 seconds
Started Jul 09 07:03:08 PM PDT 24
Finished Jul 09 07:03:37 PM PDT 24
Peak memory 200348 kb
Host smart-f89c1c5a-02e3-4748-8b62-0b169244f205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180715802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1180715802
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3477834653
Short name T183
Test name
Test status
Simulation time 1284845608 ps
CPU time 71.81 seconds
Started Jul 09 07:03:24 PM PDT 24
Finished Jul 09 07:04:38 PM PDT 24
Peak memory 200300 kb
Host smart-033d974c-c011-44c0-9525-24a18b7898cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3477834653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3477834653
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.781626230
Short name T317
Test name
Test status
Simulation time 5231680336 ps
CPU time 36.01 seconds
Started Jul 09 07:03:07 PM PDT 24
Finished Jul 09 07:03:47 PM PDT 24
Peak memory 200440 kb
Host smart-a3a95fbc-7346-4993-85ff-b548cebd188d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781626230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.781626230
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3453639221
Short name T234
Test name
Test status
Simulation time 5033275051 ps
CPU time 1101.7 seconds
Started Jul 09 07:03:08 PM PDT 24
Finished Jul 09 07:21:34 PM PDT 24
Peak memory 771892 kb
Host smart-5aa40ecc-7043-4941-bf8c-a633f82f7d40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3453639221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3453639221
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1760217684
Short name T520
Test name
Test status
Simulation time 45199156911 ps
CPU time 180.05 seconds
Started Jul 09 07:03:18 PM PDT 24
Finished Jul 09 07:06:20 PM PDT 24
Peak memory 200348 kb
Host smart-302a53ff-787b-48b2-8abe-c41f4facabb5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760217684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1760217684
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.3212007139
Short name T245
Test name
Test status
Simulation time 44671291752 ps
CPU time 108.78 seconds
Started Jul 09 07:03:03 PM PDT 24
Finished Jul 09 07:04:57 PM PDT 24
Peak memory 200396 kb
Host smart-2fdb5efa-1e57-41ed-92c0-86ba4294952d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212007139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3212007139
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1128246538
Short name T130
Test name
Test status
Simulation time 2111139913 ps
CPU time 13.7 seconds
Started Jul 09 07:03:05 PM PDT 24
Finished Jul 09 07:03:23 PM PDT 24
Peak memory 200260 kb
Host smart-cf2b158b-5800-4e19-b028-3482222905e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128246538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1128246538
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2102629181
Short name T71
Test name
Test status
Simulation time 97875939681 ps
CPU time 357.61 seconds
Started Jul 09 07:03:05 PM PDT 24
Finished Jul 09 07:09:08 PM PDT 24
Peak memory 208544 kb
Host smart-5c0d4a83-058d-4bc8-83c7-263fe9ae0bc8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102629181 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2102629181
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.805555529
Short name T13
Test name
Test status
Simulation time 3186927625 ps
CPU time 36.3 seconds
Started Jul 09 07:03:05 PM PDT 24
Finished Jul 09 07:03:47 PM PDT 24
Peak memory 200372 kb
Host smart-1a4a308c-0ae2-45fc-aec7-763d9a1f32ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805555529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.805555529
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1584806583
Short name T504
Test name
Test status
Simulation time 15547452 ps
CPU time 0.59 seconds
Started Jul 09 07:03:26 PM PDT 24
Finished Jul 09 07:03:28 PM PDT 24
Peak memory 196212 kb
Host smart-a9512906-4f29-43d1-8283-ad74c2e1b43c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584806583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1584806583
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3292582094
Short name T361
Test name
Test status
Simulation time 894463340 ps
CPU time 25.22 seconds
Started Jul 09 07:03:01 PM PDT 24
Finished Jul 09 07:03:30 PM PDT 24
Peak memory 200292 kb
Host smart-3eab8d27-b4be-4d2f-867a-4ae4491e6f25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3292582094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3292582094
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.1022474398
Short name T333
Test name
Test status
Simulation time 952749308 ps
CPU time 51.22 seconds
Started Jul 09 07:03:17 PM PDT 24
Finished Jul 09 07:04:10 PM PDT 24
Peak memory 200280 kb
Host smart-9218efb7-8ae5-4d6a-aa36-04405ffbb30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022474398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.1022474398
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.777060333
Short name T307
Test name
Test status
Simulation time 17613901343 ps
CPU time 770.83 seconds
Started Jul 09 07:03:04 PM PDT 24
Finished Jul 09 07:16:01 PM PDT 24
Peak memory 666596 kb
Host smart-e985c454-bd51-4138-80fc-29fae1dba2d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=777060333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.777060333
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1111364730
Short name T188
Test name
Test status
Simulation time 1256459010 ps
CPU time 66.07 seconds
Started Jul 09 07:03:06 PM PDT 24
Finished Jul 09 07:04:17 PM PDT 24
Peak memory 200240 kb
Host smart-36737995-2ac4-45a2-91c9-dee9f2b293b9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111364730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1111364730
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2361885421
Short name T286
Test name
Test status
Simulation time 1180788923 ps
CPU time 30.18 seconds
Started Jul 09 07:03:18 PM PDT 24
Finished Jul 09 07:03:50 PM PDT 24
Peak memory 200308 kb
Host smart-94203113-cbfb-4ac4-952c-205cb8e31368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361885421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2361885421
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1334674357
Short name T386
Test name
Test status
Simulation time 926732903 ps
CPU time 3.33 seconds
Started Jul 09 07:03:23 PM PDT 24
Finished Jul 09 07:03:28 PM PDT 24
Peak memory 200308 kb
Host smart-a90667c6-952b-43ec-8ef2-80a91b9251d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334674357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1334674357
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2600114979
Short name T431
Test name
Test status
Simulation time 47552409436 ps
CPU time 1086.95 seconds
Started Jul 09 07:03:23 PM PDT 24
Finished Jul 09 07:21:32 PM PDT 24
Peak memory 759112 kb
Host smart-5b972938-a613-459e-a20b-07246507487d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600114979 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2600114979
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.4232172091
Short name T410
Test name
Test status
Simulation time 1217667165 ps
CPU time 23.29 seconds
Started Jul 09 07:03:22 PM PDT 24
Finished Jul 09 07:03:47 PM PDT 24
Peak memory 200344 kb
Host smart-4c9742c7-b272-405a-9186-22c2819096d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232172091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.4232172091
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.4109805703
Short name T143
Test name
Test status
Simulation time 39243409 ps
CPU time 0.58 seconds
Started Jul 09 07:03:07 PM PDT 24
Finished Jul 09 07:03:12 PM PDT 24
Peak memory 196216 kb
Host smart-647125fd-0201-4fac-beed-68fadc0e4456
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109805703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.4109805703
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1117152905
Short name T288
Test name
Test status
Simulation time 2866785881 ps
CPU time 37.82 seconds
Started Jul 09 07:03:13 PM PDT 24
Finished Jul 09 07:03:53 PM PDT 24
Peak memory 200352 kb
Host smart-e5059475-7864-45ba-8c15-60a2ccb8b597
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1117152905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1117152905
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.915405446
Short name T239
Test name
Test status
Simulation time 5570144104 ps
CPU time 35.54 seconds
Started Jul 09 07:03:17 PM PDT 24
Finished Jul 09 07:03:55 PM PDT 24
Peak memory 216768 kb
Host smart-f37c88d4-25cd-4c21-ad38-24258048ebfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915405446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.915405446
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.4113351437
Short name T299
Test name
Test status
Simulation time 1193493694 ps
CPU time 212.53 seconds
Started Jul 09 07:03:18 PM PDT 24
Finished Jul 09 07:06:53 PM PDT 24
Peak memory 629316 kb
Host smart-0fbece96-8eac-45cc-be09-aa746897dd2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4113351437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.4113351437
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.674339982
Short name T342
Test name
Test status
Simulation time 4629700777 ps
CPU time 56.99 seconds
Started Jul 09 07:03:15 PM PDT 24
Finished Jul 09 07:04:14 PM PDT 24
Peak memory 200300 kb
Host smart-21acd5cb-5da0-467c-8c5e-3304780ed142
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674339982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.674339982
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2475996964
Short name T432
Test name
Test status
Simulation time 3075087790 ps
CPU time 130.69 seconds
Started Jul 09 07:03:17 PM PDT 24
Finished Jul 09 07:05:29 PM PDT 24
Peak memory 200412 kb
Host smart-febcb1ba-8011-4a80-99f1-e4baed81307e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475996964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2475996964
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.643266773
Short name T417
Test name
Test status
Simulation time 683281002 ps
CPU time 11.59 seconds
Started Jul 09 07:03:23 PM PDT 24
Finished Jul 09 07:03:36 PM PDT 24
Peak memory 200276 kb
Host smart-0966ef36-ecae-4e29-a160-f3e5ce253025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643266773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.643266773
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1782360734
Short name T506
Test name
Test status
Simulation time 19583148734 ps
CPU time 3261.25 seconds
Started Jul 09 07:03:23 PM PDT 24
Finished Jul 09 07:57:46 PM PDT 24
Peak memory 824572 kb
Host smart-ff2fad8f-6334-4d98-9d09-a977f49c0b2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782360734 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1782360734
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3776846616
Short name T276
Test name
Test status
Simulation time 6063958699 ps
CPU time 9.71 seconds
Started Jul 09 07:03:18 PM PDT 24
Finished Jul 09 07:03:29 PM PDT 24
Peak memory 200392 kb
Host smart-a94f93e2-716f-4e79-bb4d-20cd8c0148fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776846616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3776846616
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3115360030
Short name T341
Test name
Test status
Simulation time 14944988 ps
CPU time 0.6 seconds
Started Jul 09 07:03:12 PM PDT 24
Finished Jul 09 07:03:15 PM PDT 24
Peak memory 196784 kb
Host smart-2e04273f-d33f-4529-9bc3-b851a9b32f51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115360030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3115360030
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1321592666
Short name T465
Test name
Test status
Simulation time 1594553849 ps
CPU time 9.3 seconds
Started Jul 09 07:03:16 PM PDT 24
Finished Jul 09 07:03:27 PM PDT 24
Peak memory 200188 kb
Host smart-11b4c1b2-b7f6-4495-8d72-49493f1fb78d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1321592666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1321592666
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3648849858
Short name T180
Test name
Test status
Simulation time 10905651613 ps
CPU time 35.58 seconds
Started Jul 09 07:03:10 PM PDT 24
Finished Jul 09 07:03:49 PM PDT 24
Peak memory 200320 kb
Host smart-014d5b8e-c5b6-4a47-856c-bbd35e445696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648849858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3648849858
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2107342921
Short name T316
Test name
Test status
Simulation time 13697096911 ps
CPU time 353.74 seconds
Started Jul 09 07:03:09 PM PDT 24
Finished Jul 09 07:09:06 PM PDT 24
Peak memory 693848 kb
Host smart-55fc8e35-dab2-4ce9-b1ec-fa52306ac451
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2107342921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2107342921
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.3796322161
Short name T220
Test name
Test status
Simulation time 12202983450 ps
CPU time 173.54 seconds
Started Jul 09 07:03:10 PM PDT 24
Finished Jul 09 07:06:07 PM PDT 24
Peak memory 200380 kb
Host smart-0725eb35-246a-4c73-9788-31a3a0c952dc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796322161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3796322161
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2834005484
Short name T378
Test name
Test status
Simulation time 28988152732 ps
CPU time 137.55 seconds
Started Jul 09 07:03:07 PM PDT 24
Finished Jul 09 07:05:29 PM PDT 24
Peak memory 200376 kb
Host smart-7a898a2b-0ccc-456c-8905-f147e824f4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834005484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2834005484
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2882962873
Short name T387
Test name
Test status
Simulation time 806866305 ps
CPU time 13.31 seconds
Started Jul 09 07:03:20 PM PDT 24
Finished Jul 09 07:03:35 PM PDT 24
Peak memory 200188 kb
Host smart-433cf1eb-2785-49c7-b7dc-6f673d230731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882962873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2882962873
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.454880019
Short name T265
Test name
Test status
Simulation time 29317947445 ps
CPU time 88.67 seconds
Started Jul 09 07:03:19 PM PDT 24
Finished Jul 09 07:04:50 PM PDT 24
Peak memory 200400 kb
Host smart-b9e69c73-bcfe-474e-88d5-42e59a08dffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454880019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.454880019
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1207623852
Short name T347
Test name
Test status
Simulation time 13646549 ps
CPU time 0.61 seconds
Started Jul 09 07:03:20 PM PDT 24
Finished Jul 09 07:03:22 PM PDT 24
Peak memory 196864 kb
Host smart-3e81ea03-0f2a-4b4b-8a8f-59b8c1fae4c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207623852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1207623852
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3395963662
Short name T525
Test name
Test status
Simulation time 898234375 ps
CPU time 12.88 seconds
Started Jul 09 07:03:10 PM PDT 24
Finished Jul 09 07:03:26 PM PDT 24
Peak memory 200360 kb
Host smart-8058e816-a5d0-4291-835f-407cb3bf4efd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3395963662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3395963662
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3583049568
Short name T260
Test name
Test status
Simulation time 1266731975 ps
CPU time 7.96 seconds
Started Jul 09 07:03:25 PM PDT 24
Finished Jul 09 07:03:35 PM PDT 24
Peak memory 200312 kb
Host smart-9130d45c-ac8d-4e2c-bba3-6421973d6a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583049568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3583049568
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2867826947
Short name T193
Test name
Test status
Simulation time 8576014500 ps
CPU time 370.32 seconds
Started Jul 09 07:03:08 PM PDT 24
Finished Jul 09 07:09:23 PM PDT 24
Peak memory 653224 kb
Host smart-5508d68f-1a20-4818-b0f8-9e1749d8b201
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2867826947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2867826947
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1687263387
Short name T29
Test name
Test status
Simulation time 3725338313 ps
CPU time 52.49 seconds
Started Jul 09 07:03:10 PM PDT 24
Finished Jul 09 07:04:06 PM PDT 24
Peak memory 200316 kb
Host smart-b0703929-ce93-4c83-b4b0-5740ecefb7ae
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687263387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1687263387
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2650014226
Short name T507
Test name
Test status
Simulation time 23476800774 ps
CPU time 168.34 seconds
Started Jul 09 07:03:19 PM PDT 24
Finished Jul 09 07:06:09 PM PDT 24
Peak memory 200544 kb
Host smart-c2a4b221-07c7-4970-a957-74029c11424f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650014226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2650014226
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.673961623
Short name T171
Test name
Test status
Simulation time 1351764703 ps
CPU time 4.91 seconds
Started Jul 09 07:03:21 PM PDT 24
Finished Jul 09 07:03:28 PM PDT 24
Peak memory 200316 kb
Host smart-60222a6c-60d5-41d4-921b-ebf141885cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673961623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.673961623
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.777816198
Short name T532
Test name
Test status
Simulation time 16211473838 ps
CPU time 330.07 seconds
Started Jul 09 07:03:21 PM PDT 24
Finished Jul 09 07:08:53 PM PDT 24
Peak memory 370432 kb
Host smart-b1d60e5f-9d3d-4df0-bd88-4dc40b995da5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777816198 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.777816198
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.994586585
Short name T151
Test name
Test status
Simulation time 16093466541 ps
CPU time 53.1 seconds
Started Jul 09 07:03:18 PM PDT 24
Finished Jul 09 07:04:13 PM PDT 24
Peak memory 200392 kb
Host smart-9a0b504e-3039-43bc-8851-f262c602e0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994586585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.994586585
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1322831497
Short name T162
Test name
Test status
Simulation time 34746492 ps
CPU time 0.61 seconds
Started Jul 09 07:03:08 PM PDT 24
Finished Jul 09 07:03:13 PM PDT 24
Peak memory 196396 kb
Host smart-6fc92a00-0048-4731-af54-cfaa40ae3a28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322831497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1322831497
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.3795076447
Short name T18
Test name
Test status
Simulation time 2677721971 ps
CPU time 38.59 seconds
Started Jul 09 07:03:15 PM PDT 24
Finished Jul 09 07:03:56 PM PDT 24
Peak memory 208520 kb
Host smart-99a3c54d-64e3-408f-b596-27f4a7767f1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3795076447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3795076447
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.414034963
Short name T427
Test name
Test status
Simulation time 9870451219 ps
CPU time 58.6 seconds
Started Jul 09 07:03:18 PM PDT 24
Finished Jul 09 07:04:18 PM PDT 24
Peak memory 208528 kb
Host smart-487af4b1-f88d-4a90-8725-2799c73aafe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414034963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.414034963
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2181204700
Short name T405
Test name
Test status
Simulation time 19698386051 ps
CPU time 1082.41 seconds
Started Jul 09 07:03:07 PM PDT 24
Finished Jul 09 07:21:14 PM PDT 24
Peak memory 763848 kb
Host smart-d06f4495-c7c5-4b2a-9756-3ea78c4d16dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2181204700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2181204700
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.362978131
Short name T186
Test name
Test status
Simulation time 2086572931 ps
CPU time 118.28 seconds
Started Jul 09 07:03:13 PM PDT 24
Finished Jul 09 07:05:13 PM PDT 24
Peak memory 200284 kb
Host smart-c0853ee0-cb64-471a-a32b-cba5675e7dfd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362978131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.362978131
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2988251277
Short name T370
Test name
Test status
Simulation time 8299011814 ps
CPU time 155.66 seconds
Started Jul 09 07:03:24 PM PDT 24
Finished Jul 09 07:06:02 PM PDT 24
Peak memory 208588 kb
Host smart-c4c670f1-bcf5-4b91-be89-97b5938295fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988251277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2988251277
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3430134777
Short name T462
Test name
Test status
Simulation time 818398254 ps
CPU time 2.15 seconds
Started Jul 09 07:03:25 PM PDT 24
Finished Jul 09 07:03:29 PM PDT 24
Peak memory 200328 kb
Host smart-b8986877-9d2e-4c8a-9d98-76e7165e4d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430134777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3430134777
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1773905860
Short name T511
Test name
Test status
Simulation time 285069352102 ps
CPU time 2159.65 seconds
Started Jul 09 07:03:11 PM PDT 24
Finished Jul 09 07:39:14 PM PDT 24
Peak memory 768024 kb
Host smart-cbcc9243-a41c-4d9a-8177-2e12b1455de1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773905860 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1773905860
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3022923863
Short name T443
Test name
Test status
Simulation time 25687795205 ps
CPU time 111.48 seconds
Started Jul 09 07:03:24 PM PDT 24
Finished Jul 09 07:05:18 PM PDT 24
Peak memory 200424 kb
Host smart-f0160efd-8588-49a4-b0e0-637c20ee94d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022923863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3022923863
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.4158663029
Short name T419
Test name
Test status
Simulation time 16227460 ps
CPU time 0.61 seconds
Started Jul 09 07:03:18 PM PDT 24
Finished Jul 09 07:03:20 PM PDT 24
Peak memory 196820 kb
Host smart-cb1ce85f-371b-455c-a6c5-e1ba8ea029f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158663029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.4158663029
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.4045827365
Short name T205
Test name
Test status
Simulation time 5812207416 ps
CPU time 83.37 seconds
Started Jul 09 07:03:09 PM PDT 24
Finished Jul 09 07:04:36 PM PDT 24
Peak memory 200384 kb
Host smart-805ec666-0332-4414-8f9d-4f8b91ac28ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4045827365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.4045827365
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.4040997091
Short name T468
Test name
Test status
Simulation time 3125172738 ps
CPU time 14.06 seconds
Started Jul 09 07:03:25 PM PDT 24
Finished Jul 09 07:03:41 PM PDT 24
Peak memory 200432 kb
Host smart-962556ab-d991-40df-b5b7-75ddcc6ab5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040997091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.4040997091
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3598391469
Short name T338
Test name
Test status
Simulation time 14060563496 ps
CPU time 1265.31 seconds
Started Jul 09 07:03:13 PM PDT 24
Finished Jul 09 07:24:21 PM PDT 24
Peak memory 758924 kb
Host smart-cd44136a-7696-40c1-af6c-e3db656a62d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3598391469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3598391469
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.1581214286
Short name T473
Test name
Test status
Simulation time 11099059333 ps
CPU time 123.84 seconds
Started Jul 09 07:03:08 PM PDT 24
Finished Jul 09 07:05:16 PM PDT 24
Peak memory 200328 kb
Host smart-b8a0f8a8-2ded-4551-a87f-30cbc61a21e0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581214286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1581214286
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1319524749
Short name T82
Test name
Test status
Simulation time 10185681398 ps
CPU time 138.43 seconds
Started Jul 09 07:03:10 PM PDT 24
Finished Jul 09 07:05:32 PM PDT 24
Peak memory 200504 kb
Host smart-68d1cc6b-d6af-47bc-a79d-d8a26ed72686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319524749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1319524749
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3508894478
Short name T168
Test name
Test status
Simulation time 1124511849 ps
CPU time 10.38 seconds
Started Jul 09 07:03:07 PM PDT 24
Finished Jul 09 07:03:22 PM PDT 24
Peak memory 200392 kb
Host smart-1c89d10e-e35f-4ed9-b098-8ec3df1ec40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508894478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3508894478
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3878894371
Short name T115
Test name
Test status
Simulation time 51812567262 ps
CPU time 1587.99 seconds
Started Jul 09 07:03:19 PM PDT 24
Finished Jul 09 07:29:49 PM PDT 24
Peak memory 686996 kb
Host smart-18c20a9d-7c38-48a1-a559-3f97bee3c7bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878894371 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3878894371
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3175711248
Short name T185
Test name
Test status
Simulation time 248159101 ps
CPU time 12.37 seconds
Started Jul 09 07:03:12 PM PDT 24
Finished Jul 09 07:03:27 PM PDT 24
Peak memory 200264 kb
Host smart-6ffa200a-c8f3-4527-9435-0bf2d1256cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175711248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3175711248
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1046628665
Short name T297
Test name
Test status
Simulation time 24656545 ps
CPU time 0.63 seconds
Started Jul 09 07:02:47 PM PDT 24
Finished Jul 09 07:02:49 PM PDT 24
Peak memory 196184 kb
Host smart-cf854ab3-5be9-444c-8f54-dc496c28dc10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046628665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1046628665
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1474259760
Short name T451
Test name
Test status
Simulation time 572951445 ps
CPU time 16.95 seconds
Started Jul 09 07:02:47 PM PDT 24
Finished Jul 09 07:03:05 PM PDT 24
Peak memory 200296 kb
Host smart-a00ce64b-92d5-43ce-b918-07851b73fd42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1474259760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1474259760
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2793582152
Short name T43
Test name
Test status
Simulation time 556203418 ps
CPU time 7.09 seconds
Started Jul 09 07:02:47 PM PDT 24
Finished Jul 09 07:02:55 PM PDT 24
Peak memory 200324 kb
Host smart-350947c7-d31c-445c-8c54-e82276d9aacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793582152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2793582152
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3459340604
Short name T354
Test name
Test status
Simulation time 15613266461 ps
CPU time 1379.4 seconds
Started Jul 09 07:02:50 PM PDT 24
Finished Jul 09 07:25:50 PM PDT 24
Peak memory 765696 kb
Host smart-77286074-76cf-4f34-a282-29967546bbb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3459340604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3459340604
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3914902946
Short name T149
Test name
Test status
Simulation time 14632711716 ps
CPU time 27.24 seconds
Started Jul 09 07:02:49 PM PDT 24
Finished Jul 09 07:03:17 PM PDT 24
Peak memory 200392 kb
Host smart-364ce42e-72a6-4d8b-ba46-beea63a49059
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914902946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3914902946
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.532683140
Short name T463
Test name
Test status
Simulation time 126458965024 ps
CPU time 215.87 seconds
Started Jul 09 07:02:50 PM PDT 24
Finished Jul 09 07:06:27 PM PDT 24
Peak memory 208652 kb
Host smart-20666808-ad90-445e-8f15-b5d70c85bc03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532683140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.532683140
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.721074305
Short name T51
Test name
Test status
Simulation time 184082674 ps
CPU time 1.05 seconds
Started Jul 09 07:02:52 PM PDT 24
Finished Jul 09 07:02:55 PM PDT 24
Peak memory 218288 kb
Host smart-dd98d24a-7cfe-403d-945c-a43c3b92f008
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721074305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.721074305
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3435775845
Short name T339
Test name
Test status
Simulation time 5138072840 ps
CPU time 15.01 seconds
Started Jul 09 07:02:54 PM PDT 24
Finished Jul 09 07:03:11 PM PDT 24
Peak memory 200376 kb
Host smart-79031b22-f5fd-4995-8ea5-79d82012c9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435775845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3435775845
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3732329870
Short name T24
Test name
Test status
Simulation time 67269519947 ps
CPU time 927.8 seconds
Started Jul 09 07:02:48 PM PDT 24
Finished Jul 09 07:18:16 PM PDT 24
Peak memory 504852 kb
Host smart-a34550e3-ebf0-481d-aaa4-3faa08f41c58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732329870 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3732329870
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.3850224541
Short name T359
Test name
Test status
Simulation time 14318660374 ps
CPU time 78.57 seconds
Started Jul 09 07:02:48 PM PDT 24
Finished Jul 09 07:04:08 PM PDT 24
Peak memory 200360 kb
Host smart-cf1152ff-c79d-466e-a666-8bc8293e728c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3850224541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3850224541
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.3771240811
Short name T148
Test name
Test status
Simulation time 1782200621 ps
CPU time 59.31 seconds
Started Jul 09 07:02:45 PM PDT 24
Finished Jul 09 07:03:45 PM PDT 24
Peak memory 200312 kb
Host smart-a4010aac-fc81-461c-a4c0-42f3a2cee412
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3771240811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.3771240811
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.3269755223
Short name T142
Test name
Test status
Simulation time 44214121092 ps
CPU time 132.3 seconds
Started Jul 09 07:02:51 PM PDT 24
Finished Jul 09 07:05:05 PM PDT 24
Peak memory 200316 kb
Host smart-ec61929a-6718-4a49-be6b-1f4d53d75b67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3269755223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.3269755223
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.1665668121
Short name T250
Test name
Test status
Simulation time 39253456320 ps
CPU time 535.16 seconds
Started Jul 09 07:02:44 PM PDT 24
Finished Jul 09 07:11:40 PM PDT 24
Peak memory 200376 kb
Host smart-3ef52b5e-e81e-4eb1-b850-7ca70f6024ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1665668121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.1665668121
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.2009818476
Short name T129
Test name
Test status
Simulation time 911240687953 ps
CPU time 2860.68 seconds
Started Jul 09 07:02:51 PM PDT 24
Finished Jul 09 07:50:33 PM PDT 24
Peak memory 216556 kb
Host smart-ee9df671-95bc-4935-b370-39a6d3cc67c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2009818476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.2009818476
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.386150345
Short name T512
Test name
Test status
Simulation time 144615233349 ps
CPU time 2112.72 seconds
Started Jul 09 07:02:51 PM PDT 24
Finished Jul 09 07:38:06 PM PDT 24
Peak memory 216352 kb
Host smart-50a7bcdd-d945-4a71-92ab-07f0e703f558
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=386150345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.386150345
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.2658469920
Short name T515
Test name
Test status
Simulation time 1836020588 ps
CPU time 20.99 seconds
Started Jul 09 07:02:52 PM PDT 24
Finished Jul 09 07:03:15 PM PDT 24
Peak memory 200256 kb
Host smart-5ab2b4c3-12f8-49bf-a8d0-bd636b5e56e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658469920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.2658469920
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.4223151859
Short name T258
Test name
Test status
Simulation time 15177718 ps
CPU time 0.61 seconds
Started Jul 09 07:03:15 PM PDT 24
Finished Jul 09 07:03:17 PM PDT 24
Peak memory 196240 kb
Host smart-f9422431-3f01-4c67-949d-e4f8cc9e8826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223151859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.4223151859
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1106849947
Short name T165
Test name
Test status
Simulation time 2474365339 ps
CPU time 72.5 seconds
Started Jul 09 07:03:24 PM PDT 24
Finished Jul 09 07:04:38 PM PDT 24
Peak memory 200332 kb
Host smart-44c18a0b-9777-41f2-a407-a69e22e6f51d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1106849947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1106849947
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3072772605
Short name T305
Test name
Test status
Simulation time 447686998 ps
CPU time 8.72 seconds
Started Jul 09 07:03:23 PM PDT 24
Finished Jul 09 07:03:34 PM PDT 24
Peak memory 200356 kb
Host smart-77f8814a-e076-42fa-bbf2-c2b1ac2a4a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072772605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3072772605
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3248950030
Short name T380
Test name
Test status
Simulation time 4643322466 ps
CPU time 963.65 seconds
Started Jul 09 07:03:13 PM PDT 24
Finished Jul 09 07:19:19 PM PDT 24
Peak memory 723332 kb
Host smart-f1df5b65-274b-4c06-8c72-1f4b3b23b4c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3248950030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3248950030
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3085615323
Short name T314
Test name
Test status
Simulation time 2000034560 ps
CPU time 102.66 seconds
Started Jul 09 07:03:19 PM PDT 24
Finished Jul 09 07:05:04 PM PDT 24
Peak memory 200288 kb
Host smart-23d2ab63-0928-44a4-8236-64af7618dff9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085615323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3085615323
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.3254999802
Short name T497
Test name
Test status
Simulation time 150236556 ps
CPU time 8.59 seconds
Started Jul 09 07:03:25 PM PDT 24
Finished Jul 09 07:03:35 PM PDT 24
Peak memory 200384 kb
Host smart-48fdf2bf-539a-45d7-b6b1-c2f26f2effcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254999802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.3254999802
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1707267045
Short name T177
Test name
Test status
Simulation time 418622629 ps
CPU time 10.12 seconds
Started Jul 09 07:03:18 PM PDT 24
Finished Jul 09 07:03:30 PM PDT 24
Peak memory 200244 kb
Host smart-43fdaa65-4e33-4ee0-829d-7326d7896772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707267045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1707267045
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2268091521
Short name T70
Test name
Test status
Simulation time 283002418208 ps
CPU time 893.87 seconds
Started Jul 09 07:03:16 PM PDT 24
Finished Jul 09 07:18:11 PM PDT 24
Peak memory 200408 kb
Host smart-a491f2e3-2865-45be-b142-8dd2acefabbe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268091521 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2268091521
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3048842971
Short name T367
Test name
Test status
Simulation time 7896009167 ps
CPU time 8.87 seconds
Started Jul 09 07:03:23 PM PDT 24
Finished Jul 09 07:03:33 PM PDT 24
Peak memory 200348 kb
Host smart-6da8316a-a030-48bb-824e-09c7210c0683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048842971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3048842971
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.407189375
Short name T45
Test name
Test status
Simulation time 47901975 ps
CPU time 0.63 seconds
Started Jul 09 07:03:23 PM PDT 24
Finished Jul 09 07:03:25 PM PDT 24
Peak memory 196160 kb
Host smart-1ad8f9c2-2f1f-444d-b420-ac2be977cabc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407189375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.407189375
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3713789571
Short name T356
Test name
Test status
Simulation time 3300284574 ps
CPU time 65.43 seconds
Started Jul 09 07:03:23 PM PDT 24
Finished Jul 09 07:04:30 PM PDT 24
Peak memory 200384 kb
Host smart-9cb2d431-a686-4e6b-8d19-4c6b5cf26f62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3713789571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3713789571
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1075036336
Short name T308
Test name
Test status
Simulation time 3088678445 ps
CPU time 41.85 seconds
Started Jul 09 07:03:16 PM PDT 24
Finished Jul 09 07:04:00 PM PDT 24
Peak memory 200452 kb
Host smart-edf18272-2a03-42ea-8768-a3879ba48973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075036336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1075036336
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2734681542
Short name T225
Test name
Test status
Simulation time 1345245558 ps
CPU time 312.08 seconds
Started Jul 09 07:03:18 PM PDT 24
Finished Jul 09 07:08:33 PM PDT 24
Peak memory 683668 kb
Host smart-524bad5f-3eaf-4bc9-875a-adbe0c9fe62f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2734681542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2734681542
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1875934757
Short name T475
Test name
Test status
Simulation time 1719235286 ps
CPU time 51.74 seconds
Started Jul 09 07:03:15 PM PDT 24
Finished Jul 09 07:04:08 PM PDT 24
Peak memory 200296 kb
Host smart-6591fcd9-654d-4f63-93c2-c61b1053ab1e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875934757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1875934757
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2309236264
Short name T404
Test name
Test status
Simulation time 44594956367 ps
CPU time 203.41 seconds
Started Jul 09 07:03:25 PM PDT 24
Finished Jul 09 07:06:50 PM PDT 24
Peak memory 216828 kb
Host smart-6f03c459-ed69-473b-b1d2-45de1786c824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309236264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2309236264
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3785413268
Short name T242
Test name
Test status
Simulation time 16831533 ps
CPU time 0.67 seconds
Started Jul 09 07:03:14 PM PDT 24
Finished Jul 09 07:03:16 PM PDT 24
Peak memory 196856 kb
Host smart-d5c0a213-3636-487f-ab2d-79687275cd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785413268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3785413268
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1113777275
Short name T470
Test name
Test status
Simulation time 9637066575 ps
CPU time 1477.49 seconds
Started Jul 09 07:03:14 PM PDT 24
Finished Jul 09 07:27:53 PM PDT 24
Peak memory 661996 kb
Host smart-1e6e54c8-871e-4e44-8a56-0faf5b42ba5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113777275 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1113777275
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.656937951
Short name T59
Test name
Test status
Simulation time 806338089 ps
CPU time 5.26 seconds
Started Jul 09 07:03:22 PM PDT 24
Finished Jul 09 07:03:29 PM PDT 24
Peak memory 200240 kb
Host smart-cd749b18-19f2-407b-bde6-e73485566c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656937951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.656937951
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2085678762
Short name T516
Test name
Test status
Simulation time 11629751 ps
CPU time 0.58 seconds
Started Jul 09 07:03:16 PM PDT 24
Finished Jul 09 07:03:18 PM PDT 24
Peak memory 195952 kb
Host smart-862fbe76-c4fe-4ff1-b380-245097eefe93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085678762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2085678762
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.4185243448
Short name T54
Test name
Test status
Simulation time 991005968 ps
CPU time 56.38 seconds
Started Jul 09 07:03:24 PM PDT 24
Finished Jul 09 07:04:22 PM PDT 24
Peak memory 200356 kb
Host smart-bf1bec69-65a3-49bd-99e9-98e37537a45a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4185243448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.4185243448
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.3796873124
Short name T303
Test name
Test status
Simulation time 746253292 ps
CPU time 7.6 seconds
Started Jul 09 07:03:22 PM PDT 24
Finished Jul 09 07:03:31 PM PDT 24
Peak memory 200272 kb
Host smart-f35021e1-b4d2-405a-99da-23c821981410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796873124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3796873124
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3475483765
Short name T264
Test name
Test status
Simulation time 12813490581 ps
CPU time 1060 seconds
Started Jul 09 07:03:16 PM PDT 24
Finished Jul 09 07:20:58 PM PDT 24
Peak memory 666356 kb
Host smart-a6316b19-0ef9-47e1-9c63-ec09c0cfb7b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3475483765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3475483765
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.959496801
Short name T301
Test name
Test status
Simulation time 2273735935 ps
CPU time 33.96 seconds
Started Jul 09 07:03:16 PM PDT 24
Finished Jul 09 07:03:52 PM PDT 24
Peak memory 200344 kb
Host smart-261c6900-d604-4c1d-969c-b0a93c8b2365
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959496801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.959496801
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.442839074
Short name T85
Test name
Test status
Simulation time 40989907409 ps
CPU time 192.37 seconds
Started Jul 09 07:03:23 PM PDT 24
Finished Jul 09 07:06:37 PM PDT 24
Peak memory 208664 kb
Host smart-17eecb92-0b39-45f9-ae7b-8662c73b881d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442839074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.442839074
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1403489309
Short name T400
Test name
Test status
Simulation time 856647547 ps
CPU time 3.12 seconds
Started Jul 09 07:03:13 PM PDT 24
Finished Jul 09 07:03:18 PM PDT 24
Peak memory 200300 kb
Host smart-26ae2213-de35-4830-a05d-e428c1f83800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403489309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1403489309
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2991054412
Short name T268
Test name
Test status
Simulation time 34578479006 ps
CPU time 812.8 seconds
Started Jul 09 07:03:15 PM PDT 24
Finished Jul 09 07:16:50 PM PDT 24
Peak memory 620720 kb
Host smart-1c9928fc-42f5-49c4-b758-e97ee3892d2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991054412 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2991054412
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1743227643
Short name T280
Test name
Test status
Simulation time 988347346 ps
CPU time 47.4 seconds
Started Jul 09 07:03:24 PM PDT 24
Finished Jul 09 07:04:13 PM PDT 24
Peak memory 200280 kb
Host smart-810e567c-7d22-4818-ac5c-eb43417a4cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743227643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1743227643
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1120392405
Short name T84
Test name
Test status
Simulation time 14083580 ps
CPU time 0.6 seconds
Started Jul 09 07:03:22 PM PDT 24
Finished Jul 09 07:03:24 PM PDT 24
Peak memory 195864 kb
Host smart-5b09ee7b-644e-4e24-b407-899d99fc6860
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120392405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1120392405
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3994910805
Short name T37
Test name
Test status
Simulation time 4003174192 ps
CPU time 57.06 seconds
Started Jul 09 07:03:18 PM PDT 24
Finished Jul 09 07:04:17 PM PDT 24
Peak memory 200376 kb
Host smart-54c8dcd3-1fb9-4d8b-b107-64a066fe3b7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3994910805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3994910805
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.815053906
Short name T270
Test name
Test status
Simulation time 3779763711 ps
CPU time 48.34 seconds
Started Jul 09 07:03:22 PM PDT 24
Finished Jul 09 07:04:11 PM PDT 24
Peak memory 200376 kb
Host smart-9c3ec02d-ada7-45ac-999c-49d2c2a69816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815053906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.815053906
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.3667875202
Short name T519
Test name
Test status
Simulation time 9171582603 ps
CPU time 2162.99 seconds
Started Jul 09 07:03:23 PM PDT 24
Finished Jul 09 07:39:28 PM PDT 24
Peak memory 739420 kb
Host smart-2b1566b0-8a96-4eab-905e-645bedab05b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3667875202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.3667875202
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3255161490
Short name T1
Test name
Test status
Simulation time 1043940558 ps
CPU time 61.58 seconds
Started Jul 09 07:03:25 PM PDT 24
Finished Jul 09 07:04:28 PM PDT 24
Peak memory 200264 kb
Host smart-10655efa-3722-4932-8926-c0de59c42324
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255161490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3255161490
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2376657934
Short name T300
Test name
Test status
Simulation time 15259534430 ps
CPU time 207.66 seconds
Started Jul 09 07:03:18 PM PDT 24
Finished Jul 09 07:06:48 PM PDT 24
Peak memory 208572 kb
Host smart-ecd90515-2ded-44a8-8488-1b1b007ae1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376657934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2376657934
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.3523095457
Short name T204
Test name
Test status
Simulation time 1550359335 ps
CPU time 10.55 seconds
Started Jul 09 07:03:24 PM PDT 24
Finished Jul 09 07:03:36 PM PDT 24
Peak memory 200272 kb
Host smart-739c7c31-a53d-4d31-9ab6-dfa6f197ef79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523095457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.3523095457
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1638330645
Short name T6
Test name
Test status
Simulation time 154720408272 ps
CPU time 2324.51 seconds
Started Jul 09 07:03:21 PM PDT 24
Finished Jul 09 07:42:07 PM PDT 24
Peak memory 769104 kb
Host smart-c38d9ebd-de14-4cd1-98e7-e72ed20bd225
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638330645 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1638330645
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1402245301
Short name T509
Test name
Test status
Simulation time 16216533151 ps
CPU time 54.18 seconds
Started Jul 09 07:03:23 PM PDT 24
Finished Jul 09 07:04:19 PM PDT 24
Peak memory 200392 kb
Host smart-4befeb25-bc00-4f0c-a0b1-02b47d8d1fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402245301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1402245301
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2773954013
Short name T219
Test name
Test status
Simulation time 21674033 ps
CPU time 0.57 seconds
Started Jul 09 07:03:14 PM PDT 24
Finished Jul 09 07:03:16 PM PDT 24
Peak memory 196880 kb
Host smart-3cf3b0ef-9acc-4757-81f6-868e657afcde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773954013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2773954013
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3141788764
Short name T345
Test name
Test status
Simulation time 18442517215 ps
CPU time 100.48 seconds
Started Jul 09 07:03:18 PM PDT 24
Finished Jul 09 07:05:01 PM PDT 24
Peak memory 208552 kb
Host smart-5626f713-1c1b-4d3c-8314-256404caccb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3141788764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3141788764
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.676519361
Short name T474
Test name
Test status
Simulation time 381247307 ps
CPU time 21.42 seconds
Started Jul 09 07:03:16 PM PDT 24
Finished Jul 09 07:03:39 PM PDT 24
Peak memory 200316 kb
Host smart-0ee1ab7b-30d5-4294-943a-cc2dcc2eafd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676519361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.676519361
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3829719274
Short name T88
Test name
Test status
Simulation time 4705869350 ps
CPU time 1091.05 seconds
Started Jul 09 07:03:23 PM PDT 24
Finished Jul 09 07:21:35 PM PDT 24
Peak memory 749588 kb
Host smart-8d369f77-6e30-4877-9234-af12a49ba73a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3829719274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3829719274
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3726936506
Short name T491
Test name
Test status
Simulation time 9574296645 ps
CPU time 81.65 seconds
Started Jul 09 07:03:21 PM PDT 24
Finished Jul 09 07:04:44 PM PDT 24
Peak memory 200420 kb
Host smart-0a033f9f-f625-49fa-ae9b-68ea9bcbd9e1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726936506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3726936506
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1704571887
Short name T240
Test name
Test status
Simulation time 760653684 ps
CPU time 20.16 seconds
Started Jul 09 07:03:23 PM PDT 24
Finished Jul 09 07:03:44 PM PDT 24
Peak memory 200352 kb
Host smart-c99e2100-2ff3-478c-8774-974625c915d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704571887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1704571887
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2422816378
Short name T437
Test name
Test status
Simulation time 556248245 ps
CPU time 7.06 seconds
Started Jul 09 07:03:17 PM PDT 24
Finished Jul 09 07:03:26 PM PDT 24
Peak memory 200336 kb
Host smart-a5cce6e6-4fab-4381-a91e-15da7af9be9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422816378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2422816378
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3676563315
Short name T267
Test name
Test status
Simulation time 13118319989 ps
CPU time 1162.98 seconds
Started Jul 09 07:03:21 PM PDT 24
Finished Jul 09 07:22:45 PM PDT 24
Peak memory 692616 kb
Host smart-2ff47ee5-d038-474a-91e5-7a25481bd044
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676563315 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3676563315
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1649773225
Short name T416
Test name
Test status
Simulation time 20918318818 ps
CPU time 97.91 seconds
Started Jul 09 07:03:15 PM PDT 24
Finished Jul 09 07:04:54 PM PDT 24
Peak memory 200388 kb
Host smart-450c90f6-aa03-4a1a-9350-3954bb77f3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649773225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1649773225
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3625761183
Short name T155
Test name
Test status
Simulation time 11872359 ps
CPU time 0.57 seconds
Started Jul 09 07:03:33 PM PDT 24
Finished Jul 09 07:03:36 PM PDT 24
Peak memory 195204 kb
Host smart-27d86f76-bff1-4e04-8053-fb4d0ae2dbd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625761183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3625761183
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.352955528
Short name T408
Test name
Test status
Simulation time 1627272050 ps
CPU time 22.58 seconds
Started Jul 09 07:03:25 PM PDT 24
Finished Jul 09 07:03:49 PM PDT 24
Peak memory 200360 kb
Host smart-ef81676a-4981-4683-9148-1de762f329c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=352955528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.352955528
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1447985367
Short name T251
Test name
Test status
Simulation time 2989157086 ps
CPU time 52.91 seconds
Started Jul 09 07:03:27 PM PDT 24
Finished Jul 09 07:04:21 PM PDT 24
Peak memory 200396 kb
Host smart-517c67c6-6531-4176-af4b-86bd7dcb247a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447985367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1447985367
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1755979222
Short name T136
Test name
Test status
Simulation time 7873837499 ps
CPU time 388.76 seconds
Started Jul 09 07:03:30 PM PDT 24
Finished Jul 09 07:10:00 PM PDT 24
Peak memory 657060 kb
Host smart-a5e16b21-a94d-4626-9cc7-cb6e8bad76a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1755979222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1755979222
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2899949569
Short name T236
Test name
Test status
Simulation time 19796163525 ps
CPU time 190.18 seconds
Started Jul 09 07:03:17 PM PDT 24
Finished Jul 09 07:06:29 PM PDT 24
Peak memory 200376 kb
Host smart-68971d63-1343-4ee9-8a52-48cca18caecc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899949569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2899949569
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.325965975
Short name T481
Test name
Test status
Simulation time 1957573865 ps
CPU time 26.68 seconds
Started Jul 09 07:03:32 PM PDT 24
Finished Jul 09 07:04:01 PM PDT 24
Peak memory 200336 kb
Host smart-eb112e5c-1b99-4430-9582-1ad7c781b26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325965975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.325965975
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1529877991
Short name T262
Test name
Test status
Simulation time 2415326665 ps
CPU time 8.21 seconds
Started Jul 09 07:03:34 PM PDT 24
Finished Jul 09 07:03:44 PM PDT 24
Peak memory 200376 kb
Host smart-65d65320-c72b-4e69-a41c-369cb7e03cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529877991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1529877991
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2809236540
Short name T530
Test name
Test status
Simulation time 31975140579 ps
CPU time 240.22 seconds
Started Jul 09 07:03:20 PM PDT 24
Finished Jul 09 07:07:22 PM PDT 24
Peak memory 216740 kb
Host smart-88f9544f-d366-4340-a647-64c83874edfa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809236540 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2809236540
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3896805079
Short name T32
Test name
Test status
Simulation time 34477876966 ps
CPU time 122.82 seconds
Started Jul 09 07:03:33 PM PDT 24
Finished Jul 09 07:05:38 PM PDT 24
Peak memory 200384 kb
Host smart-4b803b6d-e5af-46d3-b99e-9736d93bdf1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896805079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3896805079
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3203105550
Short name T16
Test name
Test status
Simulation time 12086483 ps
CPU time 0.6 seconds
Started Jul 09 07:03:31 PM PDT 24
Finished Jul 09 07:03:33 PM PDT 24
Peak memory 195164 kb
Host smart-526eaa90-adce-4341-adb0-74ec6e0747fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203105550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3203105550
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3459545235
Short name T90
Test name
Test status
Simulation time 260748761 ps
CPU time 15.31 seconds
Started Jul 09 07:03:29 PM PDT 24
Finished Jul 09 07:03:46 PM PDT 24
Peak memory 200308 kb
Host smart-8ad9e4ab-29cf-465e-ad36-3db38b3dd9a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3459545235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3459545235
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.683886676
Short name T414
Test name
Test status
Simulation time 62053035857 ps
CPU time 65.83 seconds
Started Jul 09 07:03:32 PM PDT 24
Finished Jul 09 07:04:40 PM PDT 24
Peak memory 208600 kb
Host smart-bc8cd551-5eb1-469a-9112-906941040440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683886676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.683886676
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1028112943
Short name T490
Test name
Test status
Simulation time 8823969490 ps
CPU time 870.2 seconds
Started Jul 09 07:03:23 PM PDT 24
Finished Jul 09 07:17:56 PM PDT 24
Peak memory 661432 kb
Host smart-6785680f-76a4-4ecd-8d40-e57dc02db2a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1028112943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1028112943
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3134175860
Short name T372
Test name
Test status
Simulation time 2104277757 ps
CPU time 35.95 seconds
Started Jul 09 07:03:35 PM PDT 24
Finished Jul 09 07:04:14 PM PDT 24
Peak memory 200252 kb
Host smart-0985cc6e-8d27-4546-bb1f-46d39d486003
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134175860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3134175860
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2169503946
Short name T241
Test name
Test status
Simulation time 33928038015 ps
CPU time 113.71 seconds
Started Jul 09 07:03:27 PM PDT 24
Finished Jul 09 07:05:22 PM PDT 24
Peak memory 200308 kb
Host smart-19378b81-190d-454a-bb1b-9cc844d1f884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169503946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2169503946
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2273394597
Short name T255
Test name
Test status
Simulation time 266184248 ps
CPU time 4.06 seconds
Started Jul 09 07:03:23 PM PDT 24
Finished Jul 09 07:03:28 PM PDT 24
Peak memory 200328 kb
Host smart-da666ef7-d08b-463b-9912-8099172cda02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273394597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2273394597
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.2603473131
Short name T55
Test name
Test status
Simulation time 95105396547 ps
CPU time 2435.74 seconds
Started Jul 09 07:03:29 PM PDT 24
Finished Jul 09 07:44:07 PM PDT 24
Peak memory 762084 kb
Host smart-de81e412-a3d6-466e-a3cc-18da3fca5d9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603473131 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.2603473131
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1909420543
Short name T138
Test name
Test status
Simulation time 47257231610 ps
CPU time 88.8 seconds
Started Jul 09 07:03:32 PM PDT 24
Finished Jul 09 07:05:03 PM PDT 24
Peak memory 200404 kb
Host smart-7fc8627f-f39f-4713-89f9-e8ebfd966aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909420543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1909420543
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.2576376784
Short name T501
Test name
Test status
Simulation time 59417602 ps
CPU time 0.61 seconds
Started Jul 09 07:03:34 PM PDT 24
Finished Jul 09 07:03:37 PM PDT 24
Peak memory 195176 kb
Host smart-a27fd66e-ae18-48ce-8deb-537e617f2d94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576376784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.2576376784
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2736429320
Short name T449
Test name
Test status
Simulation time 49797222 ps
CPU time 2.91 seconds
Started Jul 09 07:03:31 PM PDT 24
Finished Jul 09 07:03:36 PM PDT 24
Peak memory 200288 kb
Host smart-91c35323-bfa2-4b8f-a7f7-30c3fe2514fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2736429320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2736429320
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.1240170373
Short name T296
Test name
Test status
Simulation time 624817501 ps
CPU time 14.11 seconds
Started Jul 09 07:03:30 PM PDT 24
Finished Jul 09 07:03:46 PM PDT 24
Peak memory 200320 kb
Host smart-42a9f089-e329-43ca-abf9-cd1ef2ee75ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240170373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.1240170373
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2789962899
Short name T363
Test name
Test status
Simulation time 17162582162 ps
CPU time 779.93 seconds
Started Jul 09 07:03:28 PM PDT 24
Finished Jul 09 07:16:30 PM PDT 24
Peak memory 727760 kb
Host smart-0ef75b72-b3e3-4943-a273-db8be7970c43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2789962899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2789962899
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3646688517
Short name T369
Test name
Test status
Simulation time 4065337224 ps
CPU time 68.43 seconds
Started Jul 09 07:03:19 PM PDT 24
Finished Jul 09 07:04:29 PM PDT 24
Peak memory 200288 kb
Host smart-40f45b20-ab51-4f4a-9192-a049e2e5ba00
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646688517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3646688517
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.903068475
Short name T284
Test name
Test status
Simulation time 11384844259 ps
CPU time 153.47 seconds
Started Jul 09 07:03:32 PM PDT 24
Finished Jul 09 07:06:08 PM PDT 24
Peak memory 200404 kb
Host smart-52d658c5-6eac-4e27-a562-49a7ed1ca95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903068475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.903068475
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2130365681
Short name T365
Test name
Test status
Simulation time 2104110210 ps
CPU time 7.29 seconds
Started Jul 09 07:03:29 PM PDT 24
Finished Jul 09 07:03:38 PM PDT 24
Peak memory 200272 kb
Host smart-d9cfd62e-bade-41c5-ac42-9186c6be7762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130365681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2130365681
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.53415225
Short name T228
Test name
Test status
Simulation time 21339043180 ps
CPU time 2413.69 seconds
Started Jul 09 07:03:30 PM PDT 24
Finished Jul 09 07:43:46 PM PDT 24
Peak memory 746840 kb
Host smart-acf92820-3022-40f0-82f2-81b28d7c49f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53415225 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.53415225
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1960107307
Short name T161
Test name
Test status
Simulation time 4678907053 ps
CPU time 21.41 seconds
Started Jul 09 07:03:28 PM PDT 24
Finished Jul 09 07:03:51 PM PDT 24
Peak memory 200360 kb
Host smart-ad029096-b43a-44da-b822-a08dc9cc1891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960107307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1960107307
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1342413212
Short name T471
Test name
Test status
Simulation time 37248147 ps
CPU time 0.61 seconds
Started Jul 09 07:03:33 PM PDT 24
Finished Jul 09 07:03:37 PM PDT 24
Peak memory 196188 kb
Host smart-23041a57-b53f-4f54-a73d-5c25e56b668b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342413212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1342413212
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.3331154602
Short name T524
Test name
Test status
Simulation time 3344858747 ps
CPU time 45.89 seconds
Started Jul 09 07:03:25 PM PDT 24
Finished Jul 09 07:04:13 PM PDT 24
Peak memory 200320 kb
Host smart-d235bd50-6d54-4c87-bb6a-6b67c25948f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3331154602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.3331154602
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.693602473
Short name T53
Test name
Test status
Simulation time 9536414232 ps
CPU time 34.34 seconds
Started Jul 09 07:03:29 PM PDT 24
Finished Jul 09 07:04:05 PM PDT 24
Peak memory 200400 kb
Host smart-b201ef8f-d777-4916-a5c5-c2a2ad8c7d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693602473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.693602473
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1861136800
Short name T210
Test name
Test status
Simulation time 8203141642 ps
CPU time 323.74 seconds
Started Jul 09 07:03:30 PM PDT 24
Finished Jul 09 07:08:55 PM PDT 24
Peak memory 613752 kb
Host smart-8c6a8a41-ab0c-4197-a347-7885ff33d6c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1861136800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1861136800
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.2563391401
Short name T44
Test name
Test status
Simulation time 30887968858 ps
CPU time 136.21 seconds
Started Jul 09 07:03:29 PM PDT 24
Finished Jul 09 07:05:47 PM PDT 24
Peak memory 200372 kb
Host smart-b3d380e4-f24d-4127-8837-093d4bdece43
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563391401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2563391401
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2035490881
Short name T207
Test name
Test status
Simulation time 7527642896 ps
CPU time 110.07 seconds
Started Jul 09 07:03:24 PM PDT 24
Finished Jul 09 07:05:16 PM PDT 24
Peak memory 200428 kb
Host smart-b827ec6a-1c2b-4c3c-bb1f-a9d5875d84c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035490881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2035490881
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3610298618
Short name T275
Test name
Test status
Simulation time 274771809 ps
CPU time 4.68 seconds
Started Jul 09 07:03:35 PM PDT 24
Finished Jul 09 07:03:42 PM PDT 24
Peak memory 200280 kb
Host smart-8e02ea66-cce3-4a0c-83be-b9df2375d899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610298618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3610298618
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.2997498549
Short name T454
Test name
Test status
Simulation time 75927127305 ps
CPU time 1868.35 seconds
Started Jul 09 07:03:36 PM PDT 24
Finished Jul 09 07:34:47 PM PDT 24
Peak memory 725784 kb
Host smart-b63fb92e-3ac9-4ae8-841b-41db8c958113
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997498549 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.2997498549
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3436541599
Short name T244
Test name
Test status
Simulation time 3873507218 ps
CPU time 20.51 seconds
Started Jul 09 07:03:30 PM PDT 24
Finished Jul 09 07:03:52 PM PDT 24
Peak memory 200588 kb
Host smart-e9f67735-1826-442b-b6e4-3e5390a492b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436541599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3436541599
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1632270134
Short name T139
Test name
Test status
Simulation time 13066530 ps
CPU time 0.58 seconds
Started Jul 09 07:03:28 PM PDT 24
Finished Jul 09 07:03:30 PM PDT 24
Peak memory 195328 kb
Host smart-9186ae10-4ee4-42f8-b07e-7d97760c0708
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632270134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1632270134
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.89801195
Short name T446
Test name
Test status
Simulation time 3460531749 ps
CPU time 58.26 seconds
Started Jul 09 07:03:27 PM PDT 24
Finished Jul 09 07:04:26 PM PDT 24
Peak memory 200312 kb
Host smart-c6a67864-06cb-409f-b535-868bf3dd966f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=89801195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.89801195
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.58085352
Short name T134
Test name
Test status
Simulation time 4787974368 ps
CPU time 61.67 seconds
Started Jul 09 07:03:30 PM PDT 24
Finished Jul 09 07:04:34 PM PDT 24
Peak memory 200408 kb
Host smart-8afb4b43-a59d-4c23-a142-88ba21f17c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58085352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.58085352
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.1087832449
Short name T467
Test name
Test status
Simulation time 10264688228 ps
CPU time 915.22 seconds
Started Jul 09 07:03:27 PM PDT 24
Finished Jul 09 07:18:44 PM PDT 24
Peak memory 760788 kb
Host smart-ac468277-72c0-40ee-bf3b-254bb9bc80cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1087832449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.1087832449
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.535175010
Short name T309
Test name
Test status
Simulation time 3381012677 ps
CPU time 190.06 seconds
Started Jul 09 07:03:32 PM PDT 24
Finished Jul 09 07:06:44 PM PDT 24
Peak memory 200192 kb
Host smart-92153e59-e39b-4d06-bc9d-221ec4d4df5e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535175010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.535175010
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2819973084
Short name T147
Test name
Test status
Simulation time 3749099650 ps
CPU time 109.93 seconds
Started Jul 09 07:03:30 PM PDT 24
Finished Jul 09 07:05:22 PM PDT 24
Peak memory 200268 kb
Host smart-82fcc3e2-7c0e-45da-813f-04e941664181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819973084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2819973084
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.3805257286
Short name T294
Test name
Test status
Simulation time 1321855521 ps
CPU time 13.3 seconds
Started Jul 09 07:03:28 PM PDT 24
Finished Jul 09 07:03:42 PM PDT 24
Peak memory 200336 kb
Host smart-cc2fbc71-0fb2-4843-b50e-b1c3aeebbef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805257286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3805257286
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2214232822
Short name T349
Test name
Test status
Simulation time 38395486512 ps
CPU time 2160.81 seconds
Started Jul 09 07:03:32 PM PDT 24
Finished Jul 09 07:39:35 PM PDT 24
Peak memory 776048 kb
Host smart-288b05de-1c30-462d-9d9c-4312153756d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214232822 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2214232822
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1199334341
Short name T430
Test name
Test status
Simulation time 5107357659 ps
CPU time 86.98 seconds
Started Jul 09 07:03:30 PM PDT 24
Finished Jul 09 07:04:58 PM PDT 24
Peak memory 200304 kb
Host smart-3377f630-409d-49eb-8898-89c8fcb3c8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199334341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1199334341
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2166623971
Short name T246
Test name
Test status
Simulation time 43466185 ps
CPU time 0.59 seconds
Started Jul 09 07:02:51 PM PDT 24
Finished Jul 09 07:02:53 PM PDT 24
Peak memory 196216 kb
Host smart-126645ff-57fe-4226-b76c-9f0ec5f42189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166623971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2166623971
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.788130902
Short name T510
Test name
Test status
Simulation time 1822118161 ps
CPU time 106.57 seconds
Started Jul 09 07:02:56 PM PDT 24
Finished Jul 09 07:04:44 PM PDT 24
Peak memory 200296 kb
Host smart-a0ddda7c-3729-413d-a47a-50985c76c73c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=788130902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.788130902
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.928801262
Short name T394
Test name
Test status
Simulation time 3011977669 ps
CPU time 57.08 seconds
Started Jul 09 07:02:52 PM PDT 24
Finished Jul 09 07:03:50 PM PDT 24
Peak memory 200448 kb
Host smart-c05b0d43-e5f9-42c6-9c27-3d2b7e50a91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928801262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.928801262
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3852281109
Short name T197
Test name
Test status
Simulation time 2551630046 ps
CPU time 475.89 seconds
Started Jul 09 07:02:58 PM PDT 24
Finished Jul 09 07:10:57 PM PDT 24
Peak memory 643424 kb
Host smart-6b88cf75-b80a-43f2-8715-9236d09d745b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3852281109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3852281109
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1503464954
Short name T89
Test name
Test status
Simulation time 7129191927 ps
CPU time 125.27 seconds
Started Jul 09 07:02:51 PM PDT 24
Finished Jul 09 07:04:57 PM PDT 24
Peak memory 200364 kb
Host smart-845aac4d-f918-428e-9497-8231650307e8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503464954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1503464954
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3785750609
Short name T458
Test name
Test status
Simulation time 38503371992 ps
CPU time 137.11 seconds
Started Jul 09 07:02:54 PM PDT 24
Finished Jul 09 07:05:13 PM PDT 24
Peak memory 200400 kb
Host smart-544c69b6-bae7-474d-9064-b7b848125612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785750609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3785750609
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2264266240
Short name T47
Test name
Test status
Simulation time 60879695 ps
CPU time 0.86 seconds
Started Jul 09 07:02:57 PM PDT 24
Finished Jul 09 07:03:00 PM PDT 24
Peak memory 218404 kb
Host smart-92e496a1-0b6f-4ada-aa7e-ec96d36c2278
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264266240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2264266240
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1972602532
Short name T399
Test name
Test status
Simulation time 574855171 ps
CPU time 7.19 seconds
Started Jul 09 07:02:57 PM PDT 24
Finished Jul 09 07:03:06 PM PDT 24
Peak memory 200316 kb
Host smart-515c8c0d-d4f7-4ac2-a7e6-6b182b9c4820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972602532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1972602532
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.2980947670
Short name T422
Test name
Test status
Simulation time 102919865707 ps
CPU time 2001.66 seconds
Started Jul 09 07:02:53 PM PDT 24
Finished Jul 09 07:36:17 PM PDT 24
Peak memory 727948 kb
Host smart-d914d38e-4784-4f76-98be-b2b250c22689
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980947670 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.2980947670
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.4001567521
Short name T12
Test name
Test status
Simulation time 95654181684 ps
CPU time 2038.88 seconds
Started Jul 09 07:02:53 PM PDT 24
Finished Jul 09 07:36:54 PM PDT 24
Peak memory 669880 kb
Host smart-c251fe30-5dd7-4ad2-9970-48ea3ea6718f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4001567521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.4001567521
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.2166818910
Short name T402
Test name
Test status
Simulation time 4786976650 ps
CPU time 86.93 seconds
Started Jul 09 07:02:53 PM PDT 24
Finished Jul 09 07:04:21 PM PDT 24
Peak memory 200404 kb
Host smart-fa69efcc-2502-408b-b74d-2ce2421fcb17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2166818910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.2166818910
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.466621724
Short name T31
Test name
Test status
Simulation time 6243893065 ps
CPU time 98.42 seconds
Started Jul 09 07:02:51 PM PDT 24
Finished Jul 09 07:04:30 PM PDT 24
Peak memory 200336 kb
Host smart-013ae448-5c38-4504-881d-7769b73e470d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=466621724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.466621724
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.804585272
Short name T196
Test name
Test status
Simulation time 9844150571 ps
CPU time 132.21 seconds
Started Jul 09 07:02:59 PM PDT 24
Finished Jul 09 07:05:14 PM PDT 24
Peak memory 200288 kb
Host smart-d570d0fa-b5d7-44f0-8d4a-36a3fd47a949
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=804585272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.804585272
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.571152325
Short name T379
Test name
Test status
Simulation time 35863058887 ps
CPU time 635.41 seconds
Started Jul 09 07:02:54 PM PDT 24
Finished Jul 09 07:13:31 PM PDT 24
Peak memory 200196 kb
Host smart-b093d45a-57d9-4a02-95b1-a2e1719e523f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=571152325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.571152325
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.2272945983
Short name T150
Test name
Test status
Simulation time 135142182631 ps
CPU time 2422.02 seconds
Started Jul 09 07:02:48 PM PDT 24
Finished Jul 09 07:43:12 PM PDT 24
Peak memory 215892 kb
Host smart-5a952d67-d2d8-48f7-abbd-6fa9b8d4ddf4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2272945983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.2272945983
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.824290355
Short name T415
Test name
Test status
Simulation time 441194899417 ps
CPU time 2625.01 seconds
Started Jul 09 07:02:51 PM PDT 24
Finished Jul 09 07:46:37 PM PDT 24
Peak memory 215944 kb
Host smart-78a13486-7750-45aa-9397-bbc67eb7ce22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=824290355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.824290355
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2442575305
Short name T221
Test name
Test status
Simulation time 1234991541 ps
CPU time 33.34 seconds
Started Jul 09 07:02:51 PM PDT 24
Finished Jul 09 07:03:26 PM PDT 24
Peak memory 200304 kb
Host smart-1a538658-485f-4c63-878a-5416cba223a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442575305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2442575305
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1568640739
Short name T212
Test name
Test status
Simulation time 15219632 ps
CPU time 0.63 seconds
Started Jul 09 07:03:33 PM PDT 24
Finished Jul 09 07:03:36 PM PDT 24
Peak memory 196188 kb
Host smart-d08d300e-d0ea-4665-845d-0708dfabdc68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568640739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1568640739
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1020481368
Short name T83
Test name
Test status
Simulation time 881689294 ps
CPU time 50.28 seconds
Started Jul 09 07:03:34 PM PDT 24
Finished Jul 09 07:04:27 PM PDT 24
Peak memory 200352 kb
Host smart-0fe9ff46-b433-4a1b-950b-007d26c20e92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1020481368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1020481368
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.2942791832
Short name T266
Test name
Test status
Simulation time 1050824264 ps
CPU time 15.95 seconds
Started Jul 09 07:03:33 PM PDT 24
Finished Jul 09 07:03:52 PM PDT 24
Peak memory 200376 kb
Host smart-304cf186-0a70-4d4f-92d4-ba25aff001f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942791832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.2942791832
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.983514931
Short name T287
Test name
Test status
Simulation time 8406759992 ps
CPU time 367.9 seconds
Started Jul 09 07:03:28 PM PDT 24
Finished Jul 09 07:09:38 PM PDT 24
Peak memory 491912 kb
Host smart-758767e4-ca38-46d8-8464-7d58b763a5fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=983514931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.983514931
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.2320821572
Short name T513
Test name
Test status
Simulation time 7357695068 ps
CPU time 35.56 seconds
Started Jul 09 07:03:33 PM PDT 24
Finished Jul 09 07:04:11 PM PDT 24
Peak memory 200380 kb
Host smart-f0a45ad6-c052-4e3e-8ce8-357db262bd8b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320821572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2320821572
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.936662141
Short name T357
Test name
Test status
Simulation time 47100428924 ps
CPU time 98.94 seconds
Started Jul 09 07:03:33 PM PDT 24
Finished Jul 09 07:05:14 PM PDT 24
Peak memory 200412 kb
Host smart-b34f5426-f5b6-451f-89d8-1e60cff52350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936662141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.936662141
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2430173636
Short name T156
Test name
Test status
Simulation time 2767724019 ps
CPU time 12.08 seconds
Started Jul 09 07:03:32 PM PDT 24
Finished Jul 09 07:03:46 PM PDT 24
Peak memory 200388 kb
Host smart-68b25fb6-995c-44ba-8b97-55469c1310f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430173636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2430173636
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.140022927
Short name T337
Test name
Test status
Simulation time 72942492873 ps
CPU time 859.32 seconds
Started Jul 09 07:03:35 PM PDT 24
Finished Jul 09 07:17:57 PM PDT 24
Peak memory 495656 kb
Host smart-705c532c-4990-4423-87dc-61ef48e1091c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140022927 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.140022927
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2331754899
Short name T14
Test name
Test status
Simulation time 6344585309 ps
CPU time 110.16 seconds
Started Jul 09 07:03:31 PM PDT 24
Finished Jul 09 07:05:24 PM PDT 24
Peak memory 200432 kb
Host smart-21d16b7e-3ace-42e0-b722-365016ef638a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331754899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2331754899
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.784368276
Short name T445
Test name
Test status
Simulation time 37751827 ps
CPU time 0.6 seconds
Started Jul 09 07:03:36 PM PDT 24
Finished Jul 09 07:03:39 PM PDT 24
Peak memory 196208 kb
Host smart-6a83abb1-3dfe-4d11-9e71-47dfde3b5c13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784368276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.784368276
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.4098363910
Short name T403
Test name
Test status
Simulation time 993782211 ps
CPU time 29.88 seconds
Started Jul 09 07:03:32 PM PDT 24
Finished Jul 09 07:04:05 PM PDT 24
Peak memory 200328 kb
Host smart-892f3123-8e0f-495b-8d35-0d628e2e069f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4098363910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.4098363910
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2251388470
Short name T36
Test name
Test status
Simulation time 2278599021 ps
CPU time 42.44 seconds
Started Jul 09 07:03:31 PM PDT 24
Finished Jul 09 07:04:16 PM PDT 24
Peak memory 200396 kb
Host smart-55589ac5-3731-4190-acdc-2480967c9b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251388470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2251388470
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3359206319
Short name T291
Test name
Test status
Simulation time 9162032339 ps
CPU time 820.73 seconds
Started Jul 09 07:03:33 PM PDT 24
Finished Jul 09 07:17:17 PM PDT 24
Peak memory 526136 kb
Host smart-2d93b114-4da2-4433-9642-4fafb333bb25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3359206319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3359206319
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.888692610
Short name T514
Test name
Test status
Simulation time 8530096931 ps
CPU time 103.34 seconds
Started Jul 09 07:03:35 PM PDT 24
Finished Jul 09 07:05:21 PM PDT 24
Peak memory 200360 kb
Host smart-1f0436f2-28bb-4b84-af24-87d8f07fa174
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888692610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.888692610
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.4097339149
Short name T487
Test name
Test status
Simulation time 40266355784 ps
CPU time 113.55 seconds
Started Jul 09 07:03:33 PM PDT 24
Finished Jul 09 07:05:29 PM PDT 24
Peak memory 200452 kb
Host smart-869d3c64-6e4a-4869-be64-01a18ed85a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097339149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.4097339149
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3943658790
Short name T418
Test name
Test status
Simulation time 2329249058 ps
CPU time 11.06 seconds
Started Jul 09 07:03:34 PM PDT 24
Finished Jul 09 07:03:48 PM PDT 24
Peak memory 200348 kb
Host smart-0205c928-42a3-4995-bc97-3c66c5e0252e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943658790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3943658790
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.2537144204
Short name T484
Test name
Test status
Simulation time 51057015715 ps
CPU time 276.52 seconds
Started Jul 09 07:03:34 PM PDT 24
Finished Jul 09 07:08:13 PM PDT 24
Peak memory 368460 kb
Host smart-f5f652e3-099f-4a89-8432-16bb2b238fa2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537144204 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.2537144204
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1772306448
Short name T441
Test name
Test status
Simulation time 3435275431 ps
CPU time 91.75 seconds
Started Jul 09 07:03:33 PM PDT 24
Finished Jul 09 07:05:07 PM PDT 24
Peak memory 200400 kb
Host smart-38ac6348-e4c2-4b09-80e0-3b9a004320bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772306448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1772306448
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.403933752
Short name T392
Test name
Test status
Simulation time 34978275 ps
CPU time 0.61 seconds
Started Jul 09 07:03:36 PM PDT 24
Finished Jul 09 07:03:39 PM PDT 24
Peak memory 196852 kb
Host smart-e3240909-da63-428b-a916-ca435ef4147d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403933752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.403933752
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.593196294
Short name T482
Test name
Test status
Simulation time 2138699249 ps
CPU time 11.77 seconds
Started Jul 09 07:03:33 PM PDT 24
Finished Jul 09 07:03:48 PM PDT 24
Peak memory 200320 kb
Host smart-4b8f8112-e210-4e99-84d4-4a41646e1861
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=593196294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.593196294
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1195885235
Short name T494
Test name
Test status
Simulation time 1492886933 ps
CPU time 27.36 seconds
Started Jul 09 07:03:35 PM PDT 24
Finished Jul 09 07:04:05 PM PDT 24
Peak memory 200388 kb
Host smart-e1089ff0-7db7-48b8-b567-2ef772750189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195885235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1195885235
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3109173290
Short name T328
Test name
Test status
Simulation time 26598083735 ps
CPU time 1696.49 seconds
Started Jul 09 07:03:36 PM PDT 24
Finished Jul 09 07:31:55 PM PDT 24
Peak memory 741188 kb
Host smart-93166691-cbac-4764-95a7-cc65587f6a03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3109173290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3109173290
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.667163561
Short name T344
Test name
Test status
Simulation time 2224411938 ps
CPU time 30.06 seconds
Started Jul 09 07:03:36 PM PDT 24
Finished Jul 09 07:04:08 PM PDT 24
Peak memory 200300 kb
Host smart-12818c93-fb44-4a4b-a348-93b2c0441b7d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667163561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.667163561
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2365307206
Short name T531
Test name
Test status
Simulation time 4323166506 ps
CPU time 123.33 seconds
Started Jul 09 07:03:35 PM PDT 24
Finished Jul 09 07:05:41 PM PDT 24
Peak memory 216672 kb
Host smart-baf1093e-9702-4d52-96f5-304d433ee545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365307206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2365307206
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.4163140362
Short name T35
Test name
Test status
Simulation time 1500283283 ps
CPU time 5.16 seconds
Started Jul 09 07:03:32 PM PDT 24
Finished Jul 09 07:03:39 PM PDT 24
Peak memory 200368 kb
Host smart-35287fe7-5862-4f8d-906e-adc2de9df4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163140362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.4163140362
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.3285199346
Short name T529
Test name
Test status
Simulation time 15007329135 ps
CPU time 154.83 seconds
Started Jul 09 07:03:33 PM PDT 24
Finished Jul 09 07:06:11 PM PDT 24
Peak memory 200428 kb
Host smart-37d7413c-6223-4b2e-849c-d7ca703e2be4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285199346 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3285199346
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.3124307820
Short name T438
Test name
Test status
Simulation time 12298722842 ps
CPU time 26.15 seconds
Started Jul 09 07:03:33 PM PDT 24
Finished Jul 09 07:04:02 PM PDT 24
Peak memory 200396 kb
Host smart-c448ada2-84b6-46b1-a597-2cd810ad275f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124307820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.3124307820
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.687601892
Short name T434
Test name
Test status
Simulation time 203928168 ps
CPU time 0.61 seconds
Started Jul 09 07:03:44 PM PDT 24
Finished Jul 09 07:03:46 PM PDT 24
Peak memory 196908 kb
Host smart-40bcacc2-9489-4ed4-b689-348cc30aae9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687601892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.687601892
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.2754917998
Short name T170
Test name
Test status
Simulation time 5186650435 ps
CPU time 67.58 seconds
Started Jul 09 07:03:42 PM PDT 24
Finished Jul 09 07:04:51 PM PDT 24
Peak memory 200412 kb
Host smart-edbd803c-77e1-4490-bd2a-0dc9bf145426
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2754917998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2754917998
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2616326677
Short name T413
Test name
Test status
Simulation time 2803996752 ps
CPU time 52.93 seconds
Started Jul 09 07:03:36 PM PDT 24
Finished Jul 09 07:04:31 PM PDT 24
Peak memory 200508 kb
Host smart-56fc80c1-d168-43c6-84a3-180f3428653a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616326677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2616326677
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2272171024
Short name T406
Test name
Test status
Simulation time 53898736415 ps
CPU time 468.11 seconds
Started Jul 09 07:03:34 PM PDT 24
Finished Jul 09 07:11:25 PM PDT 24
Peak memory 644948 kb
Host smart-891a0bef-0b22-4e34-aa0d-06fc79db0d3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2272171024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2272171024
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.934795510
Short name T425
Test name
Test status
Simulation time 25828838418 ps
CPU time 84.98 seconds
Started Jul 09 07:03:42 PM PDT 24
Finished Jul 09 07:05:08 PM PDT 24
Peak memory 200416 kb
Host smart-a78151d7-c88a-48c3-b0d7-1023b6d9813c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934795510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.934795510
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.70948010
Short name T182
Test name
Test status
Simulation time 429040661 ps
CPU time 6.19 seconds
Started Jul 09 07:03:36 PM PDT 24
Finished Jul 09 07:03:45 PM PDT 24
Peak memory 200336 kb
Host smart-a2f55f39-ef34-47ac-ba20-e95db29b1046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70948010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.70948010
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1583458232
Short name T173
Test name
Test status
Simulation time 506717565 ps
CPU time 12.03 seconds
Started Jul 09 07:03:36 PM PDT 24
Finished Jul 09 07:03:50 PM PDT 24
Peak memory 200304 kb
Host smart-9dff79e6-08ab-4578-a869-b3d6b17b7a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583458232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1583458232
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3847262607
Short name T27
Test name
Test status
Simulation time 49417253854 ps
CPU time 2672.03 seconds
Started Jul 09 07:03:35 PM PDT 24
Finished Jul 09 07:48:10 PM PDT 24
Peak memory 787568 kb
Host smart-5129ce25-0bc7-470e-9e28-51870cfc025d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847262607 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3847262607
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.495371995
Short name T336
Test name
Test status
Simulation time 10720263999 ps
CPU time 67.28 seconds
Started Jul 09 07:03:35 PM PDT 24
Finished Jul 09 07:04:45 PM PDT 24
Peak memory 200360 kb
Host smart-97f689b2-3973-42d8-b55b-e1584947ae78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495371995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.495371995
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.772153519
Short name T217
Test name
Test status
Simulation time 14547757 ps
CPU time 0.59 seconds
Started Jul 09 07:03:46 PM PDT 24
Finished Jul 09 07:03:47 PM PDT 24
Peak memory 195812 kb
Host smart-5ea82cf6-c0f0-4ba9-b747-5ca2a5a52825
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772153519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.772153519
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2166365738
Short name T10
Test name
Test status
Simulation time 10511082917 ps
CPU time 56.52 seconds
Started Jul 09 07:03:38 PM PDT 24
Finished Jul 09 07:04:36 PM PDT 24
Peak memory 200620 kb
Host smart-9e3898fe-e415-4969-be39-ba56f522e542
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2166365738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2166365738
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.880998824
Short name T52
Test name
Test status
Simulation time 38600128068 ps
CPU time 36.05 seconds
Started Jul 09 07:03:46 PM PDT 24
Finished Jul 09 07:04:23 PM PDT 24
Peak memory 200304 kb
Host smart-0d7e871f-8677-451d-abdf-722a0d9d0695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880998824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.880998824
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3397346352
Short name T486
Test name
Test status
Simulation time 68905800114 ps
CPU time 1380.88 seconds
Started Jul 09 07:03:44 PM PDT 24
Finished Jul 09 07:26:46 PM PDT 24
Peak memory 775756 kb
Host smart-917150ff-d896-4756-a1cb-b4a2ade45c3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3397346352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3397346352
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.133190243
Short name T283
Test name
Test status
Simulation time 21501572945 ps
CPU time 153.59 seconds
Started Jul 09 07:03:46 PM PDT 24
Finished Jul 09 07:06:20 PM PDT 24
Peak memory 200260 kb
Host smart-d8c4026c-692e-4f17-a501-122eb9461f0d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133190243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.133190243
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1318778355
Short name T466
Test name
Test status
Simulation time 45111385802 ps
CPU time 212.34 seconds
Started Jul 09 07:03:45 PM PDT 24
Finished Jul 09 07:07:18 PM PDT 24
Peak memory 200356 kb
Host smart-6b89327e-640d-4aa9-b3d5-81a56e975e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318778355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1318778355
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.570142219
Short name T174
Test name
Test status
Simulation time 453120836 ps
CPU time 9.3 seconds
Started Jul 09 07:03:40 PM PDT 24
Finished Jul 09 07:03:50 PM PDT 24
Peak memory 200332 kb
Host smart-e5629e31-77d6-4eee-ba62-7c5a511ac723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570142219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.570142219
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2131008664
Short name T72
Test name
Test status
Simulation time 22560715885 ps
CPU time 313.18 seconds
Started Jul 09 07:03:45 PM PDT 24
Finished Jul 09 07:08:59 PM PDT 24
Peak memory 200440 kb
Host smart-c19a44e2-2365-4198-a5f0-033fc1b7a664
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131008664 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2131008664
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2414605292
Short name T76
Test name
Test status
Simulation time 26230279571 ps
CPU time 40.46 seconds
Started Jul 09 07:04:22 PM PDT 24
Finished Jul 09 07:05:03 PM PDT 24
Peak memory 200388 kb
Host smart-30d9ef4d-3807-4994-8ead-5461bbef6f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414605292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2414605292
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.633472207
Short name T190
Test name
Test status
Simulation time 41422098 ps
CPU time 0.59 seconds
Started Jul 09 07:03:48 PM PDT 24
Finished Jul 09 07:03:49 PM PDT 24
Peak memory 196200 kb
Host smart-2ae0d399-374f-4495-8492-7b68d149f295
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633472207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.633472207
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.25074282
Short name T505
Test name
Test status
Simulation time 150083905 ps
CPU time 4.7 seconds
Started Jul 09 07:03:47 PM PDT 24
Finished Jul 09 07:03:52 PM PDT 24
Peak memory 200304 kb
Host smart-902fca16-ae5e-463e-a9ca-e579fcd595a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=25074282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.25074282
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2323591328
Short name T421
Test name
Test status
Simulation time 12051909856 ps
CPU time 59.02 seconds
Started Jul 09 07:03:45 PM PDT 24
Finished Jul 09 07:04:45 PM PDT 24
Peak memory 216744 kb
Host smart-eb1e8a93-02ad-4636-a3f1-0f3ad1a304f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323591328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2323591328
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3495363595
Short name T397
Test name
Test status
Simulation time 26425213261 ps
CPU time 1121.57 seconds
Started Jul 09 07:03:48 PM PDT 24
Finished Jul 09 07:22:31 PM PDT 24
Peak memory 751708 kb
Host smart-3fa3487e-c5de-4852-a870-46833940aa44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3495363595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3495363595
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.383734564
Short name T450
Test name
Test status
Simulation time 21882010752 ps
CPU time 78.73 seconds
Started Jul 09 07:03:46 PM PDT 24
Finished Jul 09 07:05:05 PM PDT 24
Peak memory 200412 kb
Host smart-2b150de9-9439-4f76-ab7a-2e20102da97a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383734564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.383734564
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.4161152928
Short name T34
Test name
Test status
Simulation time 19130931863 ps
CPU time 132.63 seconds
Started Jul 09 07:03:45 PM PDT 24
Finished Jul 09 07:05:59 PM PDT 24
Peak memory 200524 kb
Host smart-7aa9dc5a-3049-4cdf-bab8-959ccb84c9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161152928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.4161152928
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2098375739
Short name T293
Test name
Test status
Simulation time 258236478 ps
CPU time 3.94 seconds
Started Jul 09 07:03:50 PM PDT 24
Finished Jul 09 07:03:54 PM PDT 24
Peak memory 200336 kb
Host smart-1b82302a-5044-4acb-9d3f-2075cecdff96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098375739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2098375739
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.703008823
Short name T2
Test name
Test status
Simulation time 219272483552 ps
CPU time 2656.37 seconds
Started Jul 09 07:03:45 PM PDT 24
Finished Jul 09 07:48:02 PM PDT 24
Peak memory 792244 kb
Host smart-11c2007d-c6c0-4d58-a1e1-81af0b51d142
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703008823 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.703008823
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3991592084
Short name T189
Test name
Test status
Simulation time 3931318066 ps
CPU time 77.25 seconds
Started Jul 09 07:03:44 PM PDT 24
Finished Jul 09 07:05:02 PM PDT 24
Peak memory 200372 kb
Host smart-d275882b-4f0b-458f-84da-263d1609ff79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991592084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3991592084
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.470806901
Short name T141
Test name
Test status
Simulation time 14004297 ps
CPU time 0.57 seconds
Started Jul 09 07:03:53 PM PDT 24
Finished Jul 09 07:03:55 PM PDT 24
Peak memory 195200 kb
Host smart-1a99ae94-00ec-4004-a799-07e03c21f893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470806901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.470806901
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.83491839
Short name T230
Test name
Test status
Simulation time 2980209610 ps
CPU time 103.88 seconds
Started Jul 09 07:03:49 PM PDT 24
Finished Jul 09 07:05:34 PM PDT 24
Peak memory 200368 kb
Host smart-cd2542b1-8688-47f8-88df-3fc45e8e4edf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=83491839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.83491839
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.337486699
Short name T325
Test name
Test status
Simulation time 3986931595 ps
CPU time 51.24 seconds
Started Jul 09 07:03:49 PM PDT 24
Finished Jul 09 07:04:41 PM PDT 24
Peak memory 200448 kb
Host smart-09791213-9110-48bc-948c-0b5da0c01158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337486699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.337486699
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3196758810
Short name T159
Test name
Test status
Simulation time 21405471475 ps
CPU time 1526.11 seconds
Started Jul 09 07:03:51 PM PDT 24
Finished Jul 09 07:29:18 PM PDT 24
Peak memory 775148 kb
Host smart-89d833a5-7316-4335-bbc1-ea3951c0fcf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3196758810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3196758810
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2555079821
Short name T521
Test name
Test status
Simulation time 844259732 ps
CPU time 46.72 seconds
Started Jul 09 07:03:53 PM PDT 24
Finished Jul 09 07:04:41 PM PDT 24
Peak memory 200320 kb
Host smart-b5c1bce9-3741-4441-b6e0-ef4f5d6f7bc0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555079821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2555079821
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3609773570
Short name T160
Test name
Test status
Simulation time 1339594984 ps
CPU time 70.04 seconds
Started Jul 09 07:03:55 PM PDT 24
Finished Jul 09 07:05:06 PM PDT 24
Peak memory 200316 kb
Host smart-9be79ce6-b016-43da-8106-edd69a6bec1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609773570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3609773570
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.801962877
Short name T508
Test name
Test status
Simulation time 1217861487 ps
CPU time 17.89 seconds
Started Jul 09 07:03:46 PM PDT 24
Finished Jul 09 07:04:05 PM PDT 24
Peak memory 200392 kb
Host smart-966c45b6-9ba7-47c3-a249-97bab5fd8909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801962877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.801962877
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.240947749
Short name T30
Test name
Test status
Simulation time 6144816525 ps
CPU time 54.55 seconds
Started Jul 09 07:03:49 PM PDT 24
Finished Jul 09 07:04:45 PM PDT 24
Peak memory 200368 kb
Host smart-fa03ebcf-b554-456a-89f1-2a14b9ae7b2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240947749 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.240947749
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2596385465
Short name T271
Test name
Test status
Simulation time 1884375329 ps
CPU time 23.52 seconds
Started Jul 09 07:03:51 PM PDT 24
Finished Jul 09 07:04:16 PM PDT 24
Peak memory 200368 kb
Host smart-0132aa5d-cf70-4ed4-8917-4b6b29412cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596385465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2596385465
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2435361981
Short name T335
Test name
Test status
Simulation time 75694451 ps
CPU time 0.56 seconds
Started Jul 09 07:03:55 PM PDT 24
Finished Jul 09 07:03:57 PM PDT 24
Peak memory 195184 kb
Host smart-11653850-382a-41f9-a7c7-ec7d4c34c87d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435361981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2435361981
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3575619226
Short name T223
Test name
Test status
Simulation time 894245183 ps
CPU time 56.41 seconds
Started Jul 09 07:03:51 PM PDT 24
Finished Jul 09 07:04:48 PM PDT 24
Peak memory 200212 kb
Host smart-cf4216bf-9e7c-45d3-90f0-a143da7d8bb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3575619226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3575619226
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1850029591
Short name T456
Test name
Test status
Simulation time 6711525471 ps
CPU time 44.25 seconds
Started Jul 09 07:03:51 PM PDT 24
Finished Jul 09 07:04:36 PM PDT 24
Peak memory 200384 kb
Host smart-d3d2ed22-45fa-4545-81d3-33b7a69cdd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850029591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1850029591
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.348041990
Short name T503
Test name
Test status
Simulation time 3941445657 ps
CPU time 886.51 seconds
Started Jul 09 07:03:52 PM PDT 24
Finished Jul 09 07:18:40 PM PDT 24
Peak memory 696424 kb
Host smart-e65f530f-4271-42aa-82a3-f2a28241c927
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=348041990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.348041990
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.1297066518
Short name T459
Test name
Test status
Simulation time 4549878331 ps
CPU time 82.96 seconds
Started Jul 09 07:03:55 PM PDT 24
Finished Jul 09 07:05:19 PM PDT 24
Peak memory 200388 kb
Host smart-506e8f8b-6847-4330-8114-19e883511c55
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297066518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.1297066518
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3276220699
Short name T371
Test name
Test status
Simulation time 1342277854 ps
CPU time 74.71 seconds
Started Jul 09 07:03:52 PM PDT 24
Finished Jul 09 07:05:08 PM PDT 24
Peak memory 200376 kb
Host smart-32fc6ef5-d8f6-4b69-a563-4f0cd644c942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276220699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3276220699
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.843832788
Short name T396
Test name
Test status
Simulation time 18432627088 ps
CPU time 13.32 seconds
Started Jul 09 07:03:49 PM PDT 24
Finished Jul 09 07:04:03 PM PDT 24
Peak memory 200588 kb
Host smart-b005ab16-1169-4ab7-8900-9351259ec604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843832788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.843832788
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.616318230
Short name T483
Test name
Test status
Simulation time 70490503472 ps
CPU time 1749.88 seconds
Started Jul 09 07:03:55 PM PDT 24
Finished Jul 09 07:33:07 PM PDT 24
Peak memory 769876 kb
Host smart-47512223-0e0a-42d6-b997-fbd0d35bb360
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616318230 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.616318230
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3710223832
Short name T178
Test name
Test status
Simulation time 493923035 ps
CPU time 8.81 seconds
Started Jul 09 07:03:56 PM PDT 24
Finished Jul 09 07:04:06 PM PDT 24
Peak memory 200312 kb
Host smart-bc46acdd-d346-44bc-bc6a-b3fb7bc68fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710223832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3710223832
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3708620267
Short name T209
Test name
Test status
Simulation time 24825223 ps
CPU time 0.62 seconds
Started Jul 09 07:03:56 PM PDT 24
Finished Jul 09 07:03:58 PM PDT 24
Peak memory 196232 kb
Host smart-b8ba8a14-c6c1-4edf-886d-45af08f41753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708620267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3708620267
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3973196600
Short name T17
Test name
Test status
Simulation time 1128361364 ps
CPU time 57.06 seconds
Started Jul 09 07:03:56 PM PDT 24
Finished Jul 09 07:04:55 PM PDT 24
Peak memory 200324 kb
Host smart-bd185f81-e6b3-41b3-84c1-eb7faeee8a91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3973196600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3973196600
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.2206680546
Short name T22
Test name
Test status
Simulation time 109885751 ps
CPU time 5.76 seconds
Started Jul 09 07:03:57 PM PDT 24
Finished Jul 09 07:04:04 PM PDT 24
Peak memory 200344 kb
Host smart-2243caa9-16c1-41d1-9e27-665e07e83eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206680546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2206680546
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3168674513
Short name T329
Test name
Test status
Simulation time 11969275679 ps
CPU time 557.47 seconds
Started Jul 09 07:03:56 PM PDT 24
Finished Jul 09 07:13:15 PM PDT 24
Peak memory 678884 kb
Host smart-c7b4dbd2-4245-4f17-9b2a-491fe91bd5d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3168674513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3168674513
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.1015322226
Short name T358
Test name
Test status
Simulation time 52825009366 ps
CPU time 128.74 seconds
Started Jul 09 07:03:55 PM PDT 24
Finished Jul 09 07:06:05 PM PDT 24
Peak memory 200344 kb
Host smart-eee98aab-4ffb-4431-848d-bdc4e79168d4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015322226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.1015322226
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1755305434
Short name T69
Test name
Test status
Simulation time 2404261172 ps
CPU time 33.61 seconds
Started Jul 09 07:03:58 PM PDT 24
Finished Jul 09 07:04:32 PM PDT 24
Peak memory 200380 kb
Host smart-c0bffe5d-792d-4d8d-b324-46be657f8079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755305434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1755305434
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.621457769
Short name T499
Test name
Test status
Simulation time 1128960282 ps
CPU time 13.8 seconds
Started Jul 09 07:03:55 PM PDT 24
Finished Jul 09 07:04:09 PM PDT 24
Peak memory 200348 kb
Host smart-85d42bc9-8b44-45f0-bc01-bb2bb96a632d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621457769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.621457769
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.460645339
Short name T133
Test name
Test status
Simulation time 63897335932 ps
CPU time 1269.42 seconds
Started Jul 09 07:03:56 PM PDT 24
Finished Jul 09 07:25:07 PM PDT 24
Peak memory 671436 kb
Host smart-a3fa8312-2042-4975-8070-09249070db80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460645339 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.460645339
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.969225337
Short name T261
Test name
Test status
Simulation time 851904380 ps
CPU time 23.22 seconds
Started Jul 09 07:03:57 PM PDT 24
Finished Jul 09 07:04:21 PM PDT 24
Peak memory 200216 kb
Host smart-ccaffacf-c2b2-46aa-ab68-3383f3fba351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969225337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.969225337
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1512505054
Short name T218
Test name
Test status
Simulation time 13505747 ps
CPU time 0.59 seconds
Started Jul 09 07:04:04 PM PDT 24
Finished Jul 09 07:04:05 PM PDT 24
Peak memory 195156 kb
Host smart-149bfcf3-9c24-4153-bbab-90399c2e1e18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512505054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1512505054
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2578494755
Short name T389
Test name
Test status
Simulation time 732053139 ps
CPU time 44.72 seconds
Started Jul 09 07:04:00 PM PDT 24
Finished Jul 09 07:04:46 PM PDT 24
Peak memory 200304 kb
Host smart-1b4dda61-4131-4529-aa2e-86d0fbcaea60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2578494755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2578494755
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3680863662
Short name T492
Test name
Test status
Simulation time 224597935 ps
CPU time 11.45 seconds
Started Jul 09 07:04:02 PM PDT 24
Finished Jul 09 07:04:14 PM PDT 24
Peak memory 200328 kb
Host smart-056473f0-e7ba-459e-bba2-9e178b6bf522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680863662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3680863662
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.868950489
Short name T420
Test name
Test status
Simulation time 69279098204 ps
CPU time 1884.04 seconds
Started Jul 09 07:04:00 PM PDT 24
Finished Jul 09 07:35:25 PM PDT 24
Peak memory 739540 kb
Host smart-5bf1bbea-cb7a-40c8-bc32-17d0df661110
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=868950489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.868950489
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.145302457
Short name T436
Test name
Test status
Simulation time 596720674 ps
CPU time 32.31 seconds
Started Jul 09 07:04:02 PM PDT 24
Finished Jul 09 07:04:35 PM PDT 24
Peak memory 200240 kb
Host smart-baa9cb4f-4bd9-4cb4-8865-4a7e307ffd37
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145302457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.145302457
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.716653824
Short name T302
Test name
Test status
Simulation time 36871583215 ps
CPU time 145.11 seconds
Started Jul 09 07:04:01 PM PDT 24
Finished Jul 09 07:06:27 PM PDT 24
Peak memory 200404 kb
Host smart-6bc07103-da19-4c12-bce6-1a6c41dc458c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716653824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.716653824
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.3710356064
Short name T290
Test name
Test status
Simulation time 594964828 ps
CPU time 7.16 seconds
Started Jul 09 07:03:57 PM PDT 24
Finished Jul 09 07:04:05 PM PDT 24
Peak memory 200292 kb
Host smart-325bb2c7-0e8a-440e-b1ae-17c5b7c7d19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710356064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.3710356064
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.591994690
Short name T279
Test name
Test status
Simulation time 46510980656 ps
CPU time 517.53 seconds
Started Jul 09 07:04:00 PM PDT 24
Finished Jul 09 07:12:39 PM PDT 24
Peak memory 200312 kb
Host smart-181355bd-78f5-4456-82e7-d753ddfa901d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591994690 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.591994690
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.165898042
Short name T80
Test name
Test status
Simulation time 2437437663 ps
CPU time 31.05 seconds
Started Jul 09 07:04:00 PM PDT 24
Finished Jul 09 07:04:31 PM PDT 24
Peak memory 200392 kb
Host smart-57666bfd-fa8c-4465-8fb5-7c9986241dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165898042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.165898042
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.652303141
Short name T355
Test name
Test status
Simulation time 12366171 ps
CPU time 0.59 seconds
Started Jul 09 07:02:57 PM PDT 24
Finished Jul 09 07:03:00 PM PDT 24
Peak memory 195228 kb
Host smart-ecce5c7c-fb2e-4e5b-b41c-ade9676102bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652303141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.652303141
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2641025072
Short name T192
Test name
Test status
Simulation time 2842125054 ps
CPU time 42.08 seconds
Started Jul 09 07:02:55 PM PDT 24
Finished Jul 09 07:03:39 PM PDT 24
Peak memory 200368 kb
Host smart-ad0c4ac0-3826-4892-9bc0-b3d6eaa17386
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2641025072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2641025072
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2656664081
Short name T395
Test name
Test status
Simulation time 2019276530 ps
CPU time 9.55 seconds
Started Jul 09 07:02:53 PM PDT 24
Finished Jul 09 07:03:04 PM PDT 24
Peak memory 200340 kb
Host smart-78a5f2bf-b043-4c04-ba83-4057ef9e8afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656664081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2656664081
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2141494087
Short name T398
Test name
Test status
Simulation time 16126721090 ps
CPU time 1529.52 seconds
Started Jul 09 07:02:51 PM PDT 24
Finished Jul 09 07:28:22 PM PDT 24
Peak memory 792692 kb
Host smart-f2ea6cb3-b70c-4c4c-9ae0-afbfa0932416
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2141494087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2141494087
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2453796946
Short name T350
Test name
Test status
Simulation time 2533961568 ps
CPU time 140.09 seconds
Started Jul 09 07:03:02 PM PDT 24
Finished Jul 09 07:05:27 PM PDT 24
Peak memory 200388 kb
Host smart-4d597cc7-0abe-40fe-a3ec-c670d509585c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453796946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2453796946
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.386916075
Short name T391
Test name
Test status
Simulation time 15816149719 ps
CPU time 126.75 seconds
Started Jul 09 07:02:49 PM PDT 24
Finished Jul 09 07:04:57 PM PDT 24
Peak memory 200388 kb
Host smart-ccf6d026-06f9-4b99-bc57-2a72bc310046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386916075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.386916075
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2473651355
Short name T50
Test name
Test status
Simulation time 229215424 ps
CPU time 1.11 seconds
Started Jul 09 07:02:58 PM PDT 24
Finished Jul 09 07:03:02 PM PDT 24
Peak memory 218344 kb
Host smart-9cc4a350-48f0-4fb4-8cd6-fca2fd962b10
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473651355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2473651355
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1204236008
Short name T324
Test name
Test status
Simulation time 4464719881 ps
CPU time 13.15 seconds
Started Jul 09 07:02:52 PM PDT 24
Finished Jul 09 07:03:07 PM PDT 24
Peak memory 200380 kb
Host smart-ba8e5563-2824-4138-bddb-cc666e731c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204236008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1204236008
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2329640937
Short name T58
Test name
Test status
Simulation time 11248162506 ps
CPU time 688.37 seconds
Started Jul 09 07:02:52 PM PDT 24
Finished Jul 09 07:14:22 PM PDT 24
Peak memory 352836 kb
Host smart-ff5bae6b-343e-463f-8d7b-c76780d539e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329640937 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2329640937
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.3937556051
Short name T65
Test name
Test status
Simulation time 96440734457 ps
CPU time 3207.91 seconds
Started Jul 09 07:02:52 PM PDT 24
Finished Jul 09 07:56:23 PM PDT 24
Peak memory 834944 kb
Host smart-974cf1ae-99dc-4c9b-a9b2-8540da11d842
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3937556051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.3937556051
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.2459601509
Short name T331
Test name
Test status
Simulation time 8245408248 ps
CPU time 83.44 seconds
Started Jul 09 07:02:51 PM PDT 24
Finished Jul 09 07:04:16 PM PDT 24
Peak memory 200352 kb
Host smart-2c1dc810-40fd-47db-b494-5b82b0d5073f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2459601509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.2459601509
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.1621728118
Short name T184
Test name
Test status
Simulation time 11736937191 ps
CPU time 85.02 seconds
Started Jul 09 07:02:49 PM PDT 24
Finished Jul 09 07:04:15 PM PDT 24
Peak memory 200332 kb
Host smart-26dca4a4-d510-40e6-8b67-c563665b8e8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1621728118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.1621728118
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.10745463
Short name T248
Test name
Test status
Simulation time 10166380260 ps
CPU time 123.3 seconds
Started Jul 09 07:02:55 PM PDT 24
Finished Jul 09 07:05:00 PM PDT 24
Peak memory 200372 kb
Host smart-0297bfa5-47f0-458e-9d63-3ab494538104
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=10745463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.10745463
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.2067739068
Short name T321
Test name
Test status
Simulation time 118533384628 ps
CPU time 532.53 seconds
Started Jul 09 07:02:49 PM PDT 24
Finished Jul 09 07:11:42 PM PDT 24
Peak memory 200376 kb
Host smart-e7ffba9b-7d0f-441d-9514-c9eab7317070
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2067739068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.2067739068
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.2338568023
Short name T208
Test name
Test status
Simulation time 128557168869 ps
CPU time 2373.33 seconds
Started Jul 09 07:02:52 PM PDT 24
Finished Jul 09 07:42:27 PM PDT 24
Peak memory 215940 kb
Host smart-8824c64b-2f81-4419-ac2c-d92d6912cfb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2338568023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.2338568023
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.338064338
Short name T493
Test name
Test status
Simulation time 809402342987 ps
CPU time 2490.23 seconds
Started Jul 09 07:02:57 PM PDT 24
Finished Jul 09 07:44:30 PM PDT 24
Peak memory 215944 kb
Host smart-1689c6ae-53d7-4062-83bc-40bba72871a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_200_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=338064338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.338064338
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2117953714
Short name T327
Test name
Test status
Simulation time 1303816319 ps
CPU time 21.08 seconds
Started Jul 09 07:02:59 PM PDT 24
Finished Jul 09 07:03:22 PM PDT 24
Peak memory 200216 kb
Host smart-170d6648-c320-4993-9fce-c68c390c113f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117953714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2117953714
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2099795869
Short name T181
Test name
Test status
Simulation time 24643391 ps
CPU time 0.64 seconds
Started Jul 09 07:04:01 PM PDT 24
Finished Jul 09 07:04:03 PM PDT 24
Peak memory 196724 kb
Host smart-55191793-6635-4174-8b18-e5783bc92f6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099795869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2099795869
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.808621805
Short name T433
Test name
Test status
Simulation time 404306142 ps
CPU time 11.9 seconds
Started Jul 09 07:04:01 PM PDT 24
Finished Jul 09 07:04:14 PM PDT 24
Peak memory 200248 kb
Host smart-5ba8e2dc-bff2-44b4-a23f-d62bbd514b09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=808621805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.808621805
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3050759387
Short name T166
Test name
Test status
Simulation time 1944624490 ps
CPU time 17.16 seconds
Started Jul 09 07:04:01 PM PDT 24
Finished Jul 09 07:04:19 PM PDT 24
Peak memory 200320 kb
Host smart-a8e60cac-b04f-4809-8588-a9a06b910638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050759387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3050759387
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1801298143
Short name T187
Test name
Test status
Simulation time 21926646888 ps
CPU time 797.72 seconds
Started Jul 09 07:04:01 PM PDT 24
Finished Jul 09 07:17:19 PM PDT 24
Peak memory 713872 kb
Host smart-95b48028-ad61-4307-a059-5aaf47b4bf18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1801298143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1801298143
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.4169879687
Short name T295
Test name
Test status
Simulation time 3459302009 ps
CPU time 44.4 seconds
Started Jul 09 07:04:01 PM PDT 24
Finished Jul 09 07:04:46 PM PDT 24
Peak memory 200304 kb
Host smart-087dded4-6403-4f4a-9bff-63ba58c8bf7a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169879687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.4169879687
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.683393191
Short name T495
Test name
Test status
Simulation time 8208200618 ps
CPU time 51.17 seconds
Started Jul 09 07:04:00 PM PDT 24
Finished Jul 09 07:04:52 PM PDT 24
Peak memory 200424 kb
Host smart-c54cc252-151c-4543-888f-647a4be81c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683393191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.683393191
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2422600503
Short name T33
Test name
Test status
Simulation time 725386324 ps
CPU time 7.79 seconds
Started Jul 09 07:04:01 PM PDT 24
Finished Jul 09 07:04:09 PM PDT 24
Peak memory 200392 kb
Host smart-e47d6c06-c31d-400e-8a93-7c8d8c68e5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422600503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2422600503
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1883317443
Short name T86
Test name
Test status
Simulation time 67246366918 ps
CPU time 609.14 seconds
Started Jul 09 07:04:03 PM PDT 24
Finished Jul 09 07:14:12 PM PDT 24
Peak memory 200268 kb
Host smart-807cea9b-a738-4bb8-a3fd-586ac2d05959
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883317443 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1883317443
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3390781317
Short name T318
Test name
Test status
Simulation time 909941360 ps
CPU time 24.35 seconds
Started Jul 09 07:04:00 PM PDT 24
Finished Jul 09 07:04:26 PM PDT 24
Peak memory 200372 kb
Host smart-e94ba4f9-6027-4e74-93d7-f13615edd02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390781317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3390781317
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1474282495
Short name T412
Test name
Test status
Simulation time 13950973 ps
CPU time 0.6 seconds
Started Jul 09 07:04:07 PM PDT 24
Finished Jul 09 07:04:08 PM PDT 24
Peak memory 196088 kb
Host smart-9cc1d957-6525-4eb3-9336-d9da3d0e54b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474282495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1474282495
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.135060858
Short name T137
Test name
Test status
Simulation time 959273172 ps
CPU time 25.51 seconds
Started Jul 09 07:04:08 PM PDT 24
Finished Jul 09 07:04:35 PM PDT 24
Peak memory 200332 kb
Host smart-1c34a075-f379-49db-bff6-bb7177dc9f86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=135060858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.135060858
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2480095427
Short name T57
Test name
Test status
Simulation time 13030445 ps
CPU time 0.69 seconds
Started Jul 09 07:04:09 PM PDT 24
Finished Jul 09 07:04:10 PM PDT 24
Peak memory 196700 kb
Host smart-1dd37b9f-07b7-41b1-bfdb-bdc021097281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480095427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2480095427
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1466531504
Short name T411
Test name
Test status
Simulation time 3683925213 ps
CPU time 800.25 seconds
Started Jul 09 07:04:05 PM PDT 24
Finished Jul 09 07:17:26 PM PDT 24
Peak memory 738720 kb
Host smart-dc9bc24a-c2c9-4d78-89f1-ae4b021c0ac4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1466531504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1466531504
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2660562409
Short name T213
Test name
Test status
Simulation time 5878783418 ps
CPU time 112.12 seconds
Started Jul 09 07:04:07 PM PDT 24
Finished Jul 09 07:06:00 PM PDT 24
Peak memory 200348 kb
Host smart-99c15410-2d81-42bb-a60a-7c305639027d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660562409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2660562409
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.4032015280
Short name T5
Test name
Test status
Simulation time 2162299931 ps
CPU time 118.6 seconds
Started Jul 09 07:04:07 PM PDT 24
Finished Jul 09 07:06:06 PM PDT 24
Peak memory 200332 kb
Host smart-d743fe4d-9834-4379-a2c8-434e1e30881f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032015280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.4032015280
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.692483202
Short name T322
Test name
Test status
Simulation time 278325598 ps
CPU time 4.22 seconds
Started Jul 09 07:04:07 PM PDT 24
Finished Jul 09 07:04:12 PM PDT 24
Peak memory 200288 kb
Host smart-ac7ac999-9f54-4316-9e47-e485bff6da4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692483202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.692483202
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.757518230
Short name T74
Test name
Test status
Simulation time 78695471918 ps
CPU time 3305.93 seconds
Started Jul 09 07:04:08 PM PDT 24
Finished Jul 09 07:59:16 PM PDT 24
Peak memory 835756 kb
Host smart-587eaf1d-ec70-441d-a635-30e6b91ac75a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757518230 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.757518230
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.837639046
Short name T233
Test name
Test status
Simulation time 617394952 ps
CPU time 24.25 seconds
Started Jul 09 07:04:07 PM PDT 24
Finished Jul 09 07:04:31 PM PDT 24
Peak memory 200368 kb
Host smart-de2fb596-8f20-4388-8ad4-e81e6143447a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837639046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.837639046
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2949502857
Short name T253
Test name
Test status
Simulation time 21600670 ps
CPU time 0.57 seconds
Started Jul 09 07:04:12 PM PDT 24
Finished Jul 09 07:04:14 PM PDT 24
Peak memory 195864 kb
Host smart-0a485c73-647d-4001-a97f-3500d880a29f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949502857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2949502857
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.3498678023
Short name T464
Test name
Test status
Simulation time 2724169524 ps
CPU time 41.52 seconds
Started Jul 09 07:04:06 PM PDT 24
Finished Jul 09 07:04:48 PM PDT 24
Peak memory 200384 kb
Host smart-3d6a07d9-6bab-4fad-a631-a0fb5ea905b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3498678023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.3498678023
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2974084379
Short name T526
Test name
Test status
Simulation time 1932054045 ps
CPU time 27.3 seconds
Started Jul 09 07:04:08 PM PDT 24
Finished Jul 09 07:04:36 PM PDT 24
Peak memory 200264 kb
Host smart-fe6d069c-694f-4580-8a40-124f50a45923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974084379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2974084379
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.2407288568
Short name T202
Test name
Test status
Simulation time 15053831881 ps
CPU time 659.55 seconds
Started Jul 09 07:04:07 PM PDT 24
Finished Jul 09 07:15:08 PM PDT 24
Peak memory 707212 kb
Host smart-37ac0669-32f7-46d2-bd1a-33fbf776d62b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2407288568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.2407288568
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.4105710157
Short name T272
Test name
Test status
Simulation time 7012280911 ps
CPU time 85.68 seconds
Started Jul 09 07:04:12 PM PDT 24
Finished Jul 09 07:05:39 PM PDT 24
Peak memory 200404 kb
Host smart-7cdc7b73-6ed7-4b82-801c-906cf4bc1ca4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105710157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.4105710157
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.4224472926
Short name T152
Test name
Test status
Simulation time 30860801746 ps
CPU time 105.47 seconds
Started Jul 09 07:04:06 PM PDT 24
Finished Jul 09 07:05:53 PM PDT 24
Peak memory 200380 kb
Host smart-cead3662-7f3c-409c-b2c2-3ca7094dd03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224472926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.4224472926
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2954299637
Short name T227
Test name
Test status
Simulation time 1769679563 ps
CPU time 8 seconds
Started Jul 09 07:04:07 PM PDT 24
Finished Jul 09 07:04:16 PM PDT 24
Peak memory 200488 kb
Host smart-ee3136f6-a810-424a-bdba-f9a9bf3bdf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954299637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2954299637
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.237878971
Short name T172
Test name
Test status
Simulation time 160407195089 ps
CPU time 715.45 seconds
Started Jul 09 07:04:12 PM PDT 24
Finished Jul 09 07:16:09 PM PDT 24
Peak memory 216784 kb
Host smart-18f8cd1d-48e7-4f1b-89aa-9d587ddd058c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237878971 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.237878971
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1973162399
Short name T496
Test name
Test status
Simulation time 50637139 ps
CPU time 0.85 seconds
Started Jul 09 07:04:12 PM PDT 24
Finished Jul 09 07:04:15 PM PDT 24
Peak memory 198736 kb
Host smart-332c3f8b-36b6-41ee-8ed0-d9f17b058246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973162399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1973162399
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1809236194
Short name T332
Test name
Test status
Simulation time 31304521 ps
CPU time 0.6 seconds
Started Jul 09 07:04:12 PM PDT 24
Finished Jul 09 07:04:14 PM PDT 24
Peak memory 196216 kb
Host smart-0c7e25b0-eebd-4a5c-9662-ce3148500585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809236194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1809236194
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2457358258
Short name T390
Test name
Test status
Simulation time 277470723 ps
CPU time 6.01 seconds
Started Jul 09 07:04:11 PM PDT 24
Finished Jul 09 07:04:19 PM PDT 24
Peak memory 200332 kb
Host smart-4c014288-3e91-4023-aad2-d8545d5d7242
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2457358258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2457358258
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.83813915
Short name T254
Test name
Test status
Simulation time 189347390 ps
CPU time 3.99 seconds
Started Jul 09 07:04:12 PM PDT 24
Finished Jul 09 07:04:17 PM PDT 24
Peak memory 200284 kb
Host smart-0e7a8936-ae2b-4cba-8caf-481082acae3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83813915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.83813915
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.4223839397
Short name T169
Test name
Test status
Simulation time 7060982173 ps
CPU time 1512.28 seconds
Started Jul 09 07:04:12 PM PDT 24
Finished Jul 09 07:29:26 PM PDT 24
Peak memory 765480 kb
Host smart-c49470f0-3f87-4b51-9602-e786db76a1fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4223839397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.4223839397
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1739777966
Short name T440
Test name
Test status
Simulation time 1979015580 ps
CPU time 109.5 seconds
Started Jul 09 07:04:11 PM PDT 24
Finished Jul 09 07:06:02 PM PDT 24
Peak memory 200328 kb
Host smart-a1a36aeb-2f1f-4aaa-9fcd-224b0ed65bb9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739777966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1739777966
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.664379267
Short name T444
Test name
Test status
Simulation time 10498617555 ps
CPU time 85.66 seconds
Started Jul 09 07:04:12 PM PDT 24
Finished Jul 09 07:05:40 PM PDT 24
Peak memory 200372 kb
Host smart-8745809d-4247-45f9-ac87-5a86729da6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664379267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.664379267
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.986520985
Short name T278
Test name
Test status
Simulation time 2338595453 ps
CPU time 10.07 seconds
Started Jul 09 07:04:10 PM PDT 24
Finished Jul 09 07:04:21 PM PDT 24
Peak memory 200372 kb
Host smart-04208135-9012-40b9-bab1-ba2300daddb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986520985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.986520985
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2831643035
Short name T176
Test name
Test status
Simulation time 51020170098 ps
CPU time 1665.16 seconds
Started Jul 09 07:04:11 PM PDT 24
Finished Jul 09 07:31:58 PM PDT 24
Peak memory 734220 kb
Host smart-0e18e5bc-777d-4ba7-b366-c6befd2812d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831643035 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2831643035
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1732927224
Short name T116
Test name
Test status
Simulation time 2212321896 ps
CPU time 23.5 seconds
Started Jul 09 07:04:11 PM PDT 24
Finished Jul 09 07:04:36 PM PDT 24
Peak memory 200448 kb
Host smart-3adc6dbc-1ae3-4509-b747-3f56049b65c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732927224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1732927224
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2650971720
Short name T231
Test name
Test status
Simulation time 46453465 ps
CPU time 0.6 seconds
Started Jul 09 07:04:18 PM PDT 24
Finished Jul 09 07:04:19 PM PDT 24
Peak memory 196100 kb
Host smart-cfd2666b-385f-4c60-ade6-d4d99fd5ea1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650971720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2650971720
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.1505046458
Short name T523
Test name
Test status
Simulation time 1754922956 ps
CPU time 52.98 seconds
Started Jul 09 07:04:11 PM PDT 24
Finished Jul 09 07:05:05 PM PDT 24
Peak memory 200272 kb
Host smart-f475e88c-ec19-4b7e-82fc-e22e2482c5c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1505046458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1505046458
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3770781444
Short name T522
Test name
Test status
Simulation time 1227544882 ps
CPU time 35.6 seconds
Started Jul 09 07:04:16 PM PDT 24
Finished Jul 09 07:04:53 PM PDT 24
Peak memory 200304 kb
Host smart-c8bb5764-87be-4bae-8aea-0250369ad975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770781444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3770781444
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.3206348619
Short name T374
Test name
Test status
Simulation time 52834919182 ps
CPU time 712.73 seconds
Started Jul 09 07:04:12 PM PDT 24
Finished Jul 09 07:16:06 PM PDT 24
Peak memory 673896 kb
Host smart-c8d7d72d-a4ae-441e-9872-d3f75728a6e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3206348619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.3206348619
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1098912445
Short name T424
Test name
Test status
Simulation time 3995801559 ps
CPU time 225.06 seconds
Started Jul 09 07:04:16 PM PDT 24
Finished Jul 09 07:08:02 PM PDT 24
Peak memory 200348 kb
Host smart-e5cda90f-0444-48f1-bf17-dfd3e0097700
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098912445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1098912445
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2151723929
Short name T252
Test name
Test status
Simulation time 45277337642 ps
CPU time 135.39 seconds
Started Jul 09 07:04:13 PM PDT 24
Finished Jul 09 07:06:30 PM PDT 24
Peak memory 200448 kb
Host smart-4e495ec3-ac28-45f7-b1a8-b63ed57a2d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151723929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2151723929
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2837239586
Short name T200
Test name
Test status
Simulation time 879368987 ps
CPU time 14.56 seconds
Started Jul 09 07:04:17 PM PDT 24
Finished Jul 09 07:04:33 PM PDT 24
Peak memory 200348 kb
Host smart-5ffafe11-1d2f-4c43-95c3-3a850b25102d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837239586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2837239586
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2577476799
Short name T81
Test name
Test status
Simulation time 38612278598 ps
CPU time 2529.99 seconds
Started Jul 09 07:04:15 PM PDT 24
Finished Jul 09 07:46:27 PM PDT 24
Peak memory 816328 kb
Host smart-d0e4d0ea-6143-4aff-a1ce-83e63626e7b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577476799 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2577476799
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1506208247
Short name T114
Test name
Test status
Simulation time 6810729811 ps
CPU time 94.74 seconds
Started Jul 09 07:04:16 PM PDT 24
Finished Jul 09 07:05:51 PM PDT 24
Peak memory 200376 kb
Host smart-8c72b272-dca6-4ff1-83ef-4c751aeee85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506208247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1506208247
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2537229485
Short name T298
Test name
Test status
Simulation time 26453291 ps
CPU time 0.59 seconds
Started Jul 09 07:04:16 PM PDT 24
Finished Jul 09 07:04:18 PM PDT 24
Peak memory 196056 kb
Host smart-2cbdae0b-7001-4a8f-86a2-547b7d7ba0ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537229485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2537229485
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3238960831
Short name T362
Test name
Test status
Simulation time 497742615 ps
CPU time 27.17 seconds
Started Jul 09 07:04:20 PM PDT 24
Finished Jul 09 07:04:49 PM PDT 24
Peak memory 200304 kb
Host smart-5860e962-70ce-48a9-ad4e-a6ffb8b0eaba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3238960831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3238960831
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.245600226
Short name T198
Test name
Test status
Simulation time 23839998839 ps
CPU time 77.32 seconds
Started Jul 09 07:04:16 PM PDT 24
Finished Jul 09 07:05:34 PM PDT 24
Peak memory 208600 kb
Host smart-279f2fd5-cb1b-4fd6-888a-3cc642b6560d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245600226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.245600226
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3356524778
Short name T383
Test name
Test status
Simulation time 2446609895 ps
CPU time 550.54 seconds
Started Jul 09 07:04:17 PM PDT 24
Finished Jul 09 07:13:29 PM PDT 24
Peak memory 719456 kb
Host smart-0de642c1-a12e-4bdf-8100-4f67062604e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3356524778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3356524778
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.981080
Short name T247
Test name
Test status
Simulation time 50069033991 ps
CPU time 157.07 seconds
Started Jul 09 07:04:19 PM PDT 24
Finished Jul 09 07:06:58 PM PDT 24
Peak memory 200344 kb
Host smart-e32daa69-abfa-4049-a8d5-16973e8ed38a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.981080
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3050543625
Short name T320
Test name
Test status
Simulation time 26768350364 ps
CPU time 200.35 seconds
Started Jul 09 07:04:16 PM PDT 24
Finished Jul 09 07:07:37 PM PDT 24
Peak memory 208848 kb
Host smart-d6be41db-53b8-412e-b1a6-309cfe900def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050543625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3050543625
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2319327292
Short name T224
Test name
Test status
Simulation time 1031789955 ps
CPU time 13.69 seconds
Started Jul 09 07:04:17 PM PDT 24
Finished Jul 09 07:04:32 PM PDT 24
Peak memory 200396 kb
Host smart-a8b7a93c-4979-4716-b374-21050bd9a4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319327292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2319327292
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.3165301067
Short name T447
Test name
Test status
Simulation time 85238833997 ps
CPU time 3793.61 seconds
Started Jul 09 07:04:16 PM PDT 24
Finished Jul 09 08:07:31 PM PDT 24
Peak memory 862024 kb
Host smart-a1dd239c-75f1-4525-977f-9c8e2ef2b619
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165301067 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.3165301067
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.3928713876
Short name T56
Test name
Test status
Simulation time 12221305833 ps
CPU time 165.29 seconds
Started Jul 09 07:04:16 PM PDT 24
Finished Jul 09 07:07:02 PM PDT 24
Peak memory 200428 kb
Host smart-b7e2c0b3-2af7-47f3-89aa-033bcc6b4c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928713876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.3928713876
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3109688398
Short name T304
Test name
Test status
Simulation time 15568969 ps
CPU time 0.61 seconds
Started Jul 09 07:04:21 PM PDT 24
Finished Jul 09 07:04:23 PM PDT 24
Peak memory 196160 kb
Host smart-791be444-3533-49bf-bcff-61732103fecd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109688398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3109688398
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.776162019
Short name T167
Test name
Test status
Simulation time 1461397673 ps
CPU time 4.57 seconds
Started Jul 09 07:04:20 PM PDT 24
Finished Jul 09 07:04:26 PM PDT 24
Peak memory 200200 kb
Host smart-74ef5563-3dd7-47f8-91c2-3a49b413e0ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=776162019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.776162019
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.332783564
Short name T461
Test name
Test status
Simulation time 5437525506 ps
CPU time 48.9 seconds
Started Jul 09 07:04:21 PM PDT 24
Finished Jul 09 07:05:11 PM PDT 24
Peak memory 200412 kb
Host smart-efe98b59-24b6-4fb5-a2dd-e9d41be6a906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332783564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.332783564
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2749016080
Short name T306
Test name
Test status
Simulation time 3862453004 ps
CPU time 834.08 seconds
Started Jul 09 07:04:24 PM PDT 24
Finished Jul 09 07:18:20 PM PDT 24
Peak memory 684352 kb
Host smart-056ad624-f809-4a3c-9823-99dec6b6b0c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2749016080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2749016080
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.801275597
Short name T140
Test name
Test status
Simulation time 106377578794 ps
CPU time 130.67 seconds
Started Jul 09 07:04:23 PM PDT 24
Finished Jul 09 07:06:35 PM PDT 24
Peak memory 200356 kb
Host smart-3b51a40a-36e2-4a06-b7d6-e63c82f92241
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801275597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.801275597
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1355826400
Short name T214
Test name
Test status
Simulation time 4690213753 ps
CPU time 93.99 seconds
Started Jul 09 07:04:24 PM PDT 24
Finished Jul 09 07:05:59 PM PDT 24
Peak memory 200436 kb
Host smart-283a95d8-167d-43ef-bf0b-a14015f2ffd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355826400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1355826400
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1513581947
Short name T326
Test name
Test status
Simulation time 1805825264 ps
CPU time 5.82 seconds
Started Jul 09 07:04:20 PM PDT 24
Finished Jul 09 07:04:27 PM PDT 24
Peak memory 200324 kb
Host smart-5b250736-5078-4056-8f3f-ee1264f33b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513581947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1513581947
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3781683632
Short name T455
Test name
Test status
Simulation time 5601227598 ps
CPU time 70 seconds
Started Jul 09 07:04:22 PM PDT 24
Finished Jul 09 07:05:34 PM PDT 24
Peak memory 200420 kb
Host smart-6c95e395-ff1d-4a28-8dcb-5370461a82e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781683632 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3781683632
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.3641607502
Short name T285
Test name
Test status
Simulation time 1820509655 ps
CPU time 42.44 seconds
Started Jul 09 07:04:23 PM PDT 24
Finished Jul 09 07:05:06 PM PDT 24
Peak memory 200288 kb
Host smart-0b6893cb-f8f5-4add-9bdc-b9b5a571388b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641607502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.3641607502
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.4155808198
Short name T158
Test name
Test status
Simulation time 19809261 ps
CPU time 0.58 seconds
Started Jul 09 07:04:20 PM PDT 24
Finished Jul 09 07:04:22 PM PDT 24
Peak memory 196168 kb
Host smart-24ef1cd4-b9b5-4782-b5f5-51eb82e7f447
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155808198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.4155808198
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1523572059
Short name T66
Test name
Test status
Simulation time 1298637968 ps
CPU time 20 seconds
Started Jul 09 07:04:22 PM PDT 24
Finished Jul 09 07:04:44 PM PDT 24
Peak memory 200324 kb
Host smart-52305d91-a9e9-489b-9bbb-5191e47a768d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1523572059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1523572059
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3155120574
Short name T41
Test name
Test status
Simulation time 4931073249 ps
CPU time 77.26 seconds
Started Jul 09 07:04:24 PM PDT 24
Finished Jul 09 07:05:43 PM PDT 24
Peak memory 200360 kb
Host smart-1c1e6341-7bf7-4ec4-8721-7fd7dd6f36c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155120574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3155120574
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.92458695
Short name T377
Test name
Test status
Simulation time 9087636163 ps
CPU time 354.45 seconds
Started Jul 09 07:04:21 PM PDT 24
Finished Jul 09 07:10:17 PM PDT 24
Peak memory 596472 kb
Host smart-673ffc4d-34e0-4943-a577-ee907f69a0b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=92458695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.92458695
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3962855885
Short name T435
Test name
Test status
Simulation time 7160984509 ps
CPU time 206 seconds
Started Jul 09 07:04:22 PM PDT 24
Finished Jul 09 07:07:49 PM PDT 24
Peak memory 200348 kb
Host smart-7e0a0efc-e07d-4373-83b1-cb17428a9f2a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962855885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3962855885
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1028709718
Short name T263
Test name
Test status
Simulation time 19148046032 ps
CPU time 164.72 seconds
Started Jul 09 07:04:23 PM PDT 24
Finished Jul 09 07:07:08 PM PDT 24
Peak memory 208624 kb
Host smart-e26953d6-b1a1-4cf9-bd74-fea3769388fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028709718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1028709718
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.607170794
Short name T527
Test name
Test status
Simulation time 445575348 ps
CPU time 10.13 seconds
Started Jul 09 07:04:21 PM PDT 24
Finished Jul 09 07:04:33 PM PDT 24
Peak memory 200340 kb
Host smart-bdf3e4b9-4efe-4afd-a25a-3df3956957ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607170794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.607170794
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.4076452818
Short name T373
Test name
Test status
Simulation time 22919352833 ps
CPU time 3537.9 seconds
Started Jul 09 07:04:23 PM PDT 24
Finished Jul 09 08:03:23 PM PDT 24
Peak memory 817572 kb
Host smart-9e727b6f-8cd9-4a56-8d27-666725bf8017
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076452818 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.4076452818
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.2310199449
Short name T144
Test name
Test status
Simulation time 1549623347 ps
CPU time 10.84 seconds
Started Jul 09 07:04:22 PM PDT 24
Finished Jul 09 07:04:34 PM PDT 24
Peak memory 200532 kb
Host smart-2ea7834f-0c05-413c-89e7-d40652881d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310199449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2310199449
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3088761107
Short name T453
Test name
Test status
Simulation time 41270856 ps
CPU time 0.54 seconds
Started Jul 09 07:04:26 PM PDT 24
Finished Jul 09 07:04:29 PM PDT 24
Peak memory 195204 kb
Host smart-1b5ac7d3-6101-412c-bfbb-108bcc4c8c08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088761107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3088761107
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2251003362
Short name T238
Test name
Test status
Simulation time 2996394595 ps
CPU time 21.59 seconds
Started Jul 09 07:04:23 PM PDT 24
Finished Jul 09 07:04:46 PM PDT 24
Peak memory 200408 kb
Host smart-41010ca7-fa13-4b40-85e9-74c04aae1576
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2251003362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2251003362
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1187751582
Short name T500
Test name
Test status
Simulation time 3805677962 ps
CPU time 26.91 seconds
Started Jul 09 07:04:21 PM PDT 24
Finished Jul 09 07:04:49 PM PDT 24
Peak memory 200364 kb
Host smart-e27a1449-d324-4c40-9b22-7b9770fdb4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187751582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1187751582
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2901927721
Short name T385
Test name
Test status
Simulation time 7037256196 ps
CPU time 1540.9 seconds
Started Jul 09 07:04:23 PM PDT 24
Finished Jul 09 07:30:06 PM PDT 24
Peak memory 769920 kb
Host smart-b3d08985-284c-423f-92b9-0ea3ac94066e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2901927721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2901927721
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.2723502989
Short name T343
Test name
Test status
Simulation time 11061116075 ps
CPU time 149.86 seconds
Started Jul 09 07:04:26 PM PDT 24
Finished Jul 09 07:06:57 PM PDT 24
Peak memory 200384 kb
Host smart-fbc03383-1f56-4351-8472-c994886dadb2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723502989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2723502989
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1741605077
Short name T528
Test name
Test status
Simulation time 3405046885 ps
CPU time 45.4 seconds
Started Jul 09 07:04:24 PM PDT 24
Finished Jul 09 07:05:11 PM PDT 24
Peak memory 200376 kb
Host smart-2f5b5c89-46ad-4765-883f-7f5e37263b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741605077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1741605077
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1259553642
Short name T25
Test name
Test status
Simulation time 1743047100 ps
CPU time 12.23 seconds
Started Jul 09 07:04:23 PM PDT 24
Finished Jul 09 07:04:36 PM PDT 24
Peak memory 200372 kb
Host smart-ad017774-2a90-42ed-9d27-57821dbaf942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259553642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1259553642
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2383008153
Short name T346
Test name
Test status
Simulation time 14459582291 ps
CPU time 1699.33 seconds
Started Jul 09 07:04:27 PM PDT 24
Finished Jul 09 07:32:49 PM PDT 24
Peak memory 707112 kb
Host smart-ca92d797-cedc-488b-8ac8-dde84e2ea57a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383008153 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2383008153
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1028594300
Short name T87
Test name
Test status
Simulation time 112082637183 ps
CPU time 108.12 seconds
Started Jul 09 07:04:27 PM PDT 24
Finished Jul 09 07:06:18 PM PDT 24
Peak memory 200548 kb
Host smart-a35f74b9-e082-43f1-9bf5-975ef11260f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028594300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1028594300
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1954730527
Short name T311
Test name
Test status
Simulation time 29383145 ps
CPU time 0.58 seconds
Started Jul 09 07:04:25 PM PDT 24
Finished Jul 09 07:04:27 PM PDT 24
Peak memory 196160 kb
Host smart-ca411d45-4703-4c30-b8da-72b2ea803597
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954730527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1954730527
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.821783189
Short name T131
Test name
Test status
Simulation time 1469909032 ps
CPU time 80.44 seconds
Started Jul 09 07:04:27 PM PDT 24
Finished Jul 09 07:05:49 PM PDT 24
Peak memory 200360 kb
Host smart-524ad1cf-ab5c-416b-8848-b0dc2f863d54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=821783189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.821783189
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.4233270342
Short name T257
Test name
Test status
Simulation time 660131351 ps
CPU time 5.34 seconds
Started Jul 09 07:04:24 PM PDT 24
Finished Jul 09 07:04:30 PM PDT 24
Peak memory 200264 kb
Host smart-f217a53e-f453-4f46-b7e0-207a3189ae24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233270342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.4233270342
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2577166906
Short name T384
Test name
Test status
Simulation time 11837161633 ps
CPU time 510.58 seconds
Started Jul 09 07:04:27 PM PDT 24
Finished Jul 09 07:12:59 PM PDT 24
Peak memory 674184 kb
Host smart-4f5f4774-1b6c-4266-8bd1-10e152718fab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2577166906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2577166906
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2509115973
Short name T237
Test name
Test status
Simulation time 381383107 ps
CPU time 6.03 seconds
Started Jul 09 07:04:27 PM PDT 24
Finished Jul 09 07:04:35 PM PDT 24
Peak memory 200072 kb
Host smart-2ff31181-a1a8-44ea-8205-9a30e860e150
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509115973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2509115973
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1643247208
Short name T442
Test name
Test status
Simulation time 2821711228 ps
CPU time 50.89 seconds
Started Jul 09 07:04:26 PM PDT 24
Finished Jul 09 07:05:18 PM PDT 24
Peak memory 200440 kb
Host smart-4ddd55f8-8d80-4798-823b-db6af0df588a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643247208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1643247208
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3053220301
Short name T274
Test name
Test status
Simulation time 145318073 ps
CPU time 0.89 seconds
Started Jul 09 07:04:29 PM PDT 24
Finished Jul 09 07:04:31 PM PDT 24
Peak memory 198908 kb
Host smart-ed9a4565-89ce-4e78-822f-b6f25544f8ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053220301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3053220301
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.3717848048
Short name T75
Test name
Test status
Simulation time 262475612741 ps
CPU time 1681.62 seconds
Started Jul 09 07:04:29 PM PDT 24
Finished Jul 09 07:32:32 PM PDT 24
Peak memory 652912 kb
Host smart-823f97ca-0db2-4491-be90-8afb600f85ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717848048 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3717848048
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3101333333
Short name T407
Test name
Test status
Simulation time 38828704619 ps
CPU time 130.38 seconds
Started Jul 09 07:04:26 PM PDT 24
Finished Jul 09 07:06:38 PM PDT 24
Peak memory 200340 kb
Host smart-a2136394-859d-4e35-934a-d8da1fa5860a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101333333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3101333333
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.45165019
Short name T46
Test name
Test status
Simulation time 18003898 ps
CPU time 0.59 seconds
Started Jul 09 07:03:00 PM PDT 24
Finished Jul 09 07:03:03 PM PDT 24
Peak memory 196020 kb
Host smart-9a1a830c-ead9-483c-80a4-03f62767aae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45165019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.45165019
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.812025301
Short name T199
Test name
Test status
Simulation time 381314109 ps
CPU time 7.03 seconds
Started Jul 09 07:03:00 PM PDT 24
Finished Jul 09 07:03:10 PM PDT 24
Peak memory 200224 kb
Host smart-84b849fb-a44a-4ab3-8144-196f7d4e516f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=812025301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.812025301
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.158058143
Short name T518
Test name
Test status
Simulation time 781768744 ps
CPU time 21.64 seconds
Started Jul 09 07:02:59 PM PDT 24
Finished Jul 09 07:03:23 PM PDT 24
Peak memory 200376 kb
Host smart-036d02e1-9558-4e31-a067-7182bed20cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158058143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.158058143
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1292677206
Short name T153
Test name
Test status
Simulation time 26190945585 ps
CPU time 554.12 seconds
Started Jul 09 07:03:01 PM PDT 24
Finished Jul 09 07:12:19 PM PDT 24
Peak memory 653356 kb
Host smart-3c8a1c69-3bfd-451e-a624-966a1d84a3ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1292677206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1292677206
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.840055217
Short name T179
Test name
Test status
Simulation time 31532051957 ps
CPU time 91.44 seconds
Started Jul 09 07:03:01 PM PDT 24
Finished Jul 09 07:04:37 PM PDT 24
Peak memory 200376 kb
Host smart-2ef41833-a90b-47bb-ac4a-0c209a23830f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840055217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.840055217
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1870474158
Short name T135
Test name
Test status
Simulation time 2802518438 ps
CPU time 39.74 seconds
Started Jul 09 07:03:02 PM PDT 24
Finished Jul 09 07:03:47 PM PDT 24
Peak memory 200364 kb
Host smart-40ecdc72-29b4-45a7-b459-6f76de5611cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870474158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1870474158
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2070537248
Short name T429
Test name
Test status
Simulation time 277259481 ps
CPU time 8.75 seconds
Started Jul 09 07:03:00 PM PDT 24
Finished Jul 09 07:03:12 PM PDT 24
Peak memory 200340 kb
Host smart-c226a777-d2fd-41ba-8adc-ad73f5f36e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070537248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2070537248
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3340830679
Short name T352
Test name
Test status
Simulation time 1282229670 ps
CPU time 23.44 seconds
Started Jul 09 07:03:08 PM PDT 24
Finished Jul 09 07:03:36 PM PDT 24
Peak memory 200304 kb
Host smart-13e1052e-74ae-41e4-8c63-b62dd17936c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340830679 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3340830679
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.3114987659
Short name T20
Test name
Test status
Simulation time 202922342404 ps
CPU time 4625.91 seconds
Started Jul 09 07:02:57 PM PDT 24
Finished Jul 09 08:20:06 PM PDT 24
Peak memory 434812 kb
Host smart-94a0d630-dee1-4f88-a3df-7dd14807f225
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3114987659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.3114987659
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2336551195
Short name T203
Test name
Test status
Simulation time 503768555 ps
CPU time 6.95 seconds
Started Jul 09 07:03:01 PM PDT 24
Finished Jul 09 07:03:11 PM PDT 24
Peak memory 200284 kb
Host smart-719099fb-c0a5-4b77-a81f-d65f6d686a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336551195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2336551195
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.918182690
Short name T330
Test name
Test status
Simulation time 33097037 ps
CPU time 0.58 seconds
Started Jul 09 07:03:01 PM PDT 24
Finished Jul 09 07:03:06 PM PDT 24
Peak memory 195868 kb
Host smart-1b5384ab-079c-4358-a2d8-071a42644f04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918182690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.918182690
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3950838388
Short name T26
Test name
Test status
Simulation time 15685753550 ps
CPU time 111.57 seconds
Started Jul 09 07:03:00 PM PDT 24
Finished Jul 09 07:04:54 PM PDT 24
Peak memory 208668 kb
Host smart-7d35c8cc-93e9-48dc-b62a-af9eff29f5b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3950838388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3950838388
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2361760283
Short name T132
Test name
Test status
Simulation time 778023829 ps
CPU time 43.36 seconds
Started Jul 09 07:03:00 PM PDT 24
Finished Jul 09 07:03:46 PM PDT 24
Peak memory 200212 kb
Host smart-f86c1131-e128-4ebb-bb78-33f781bbffe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361760283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2361760283
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2099513850
Short name T366
Test name
Test status
Simulation time 22368344501 ps
CPU time 308.3 seconds
Started Jul 09 07:03:00 PM PDT 24
Finished Jul 09 07:08:11 PM PDT 24
Peak memory 632836 kb
Host smart-55c11cd1-156f-40ff-8d26-fed09efecf72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2099513850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2099513850
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3636070655
Short name T460
Test name
Test status
Simulation time 11895992292 ps
CPU time 167.23 seconds
Started Jul 09 07:03:03 PM PDT 24
Finished Jul 09 07:05:56 PM PDT 24
Peak memory 200388 kb
Host smart-4a5cac5b-f4b4-4c53-8f4b-0d5bbeaa54a0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636070655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3636070655
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3650732663
Short name T191
Test name
Test status
Simulation time 2127778033 ps
CPU time 13.53 seconds
Started Jul 09 07:03:01 PM PDT 24
Finished Jul 09 07:03:17 PM PDT 24
Peak memory 200244 kb
Host smart-1e382d21-599a-4fcc-a601-00de0ea7c732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650732663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3650732663
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_stress_all.4134406678
Short name T211
Test name
Test status
Simulation time 60067895498 ps
CPU time 367.38 seconds
Started Jul 09 07:03:02 PM PDT 24
Finished Jul 09 07:09:14 PM PDT 24
Peak memory 200340 kb
Host smart-68716f4f-f9b9-465b-a986-45f7ac553cb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134406678 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.4134406678
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.3382559779
Short name T195
Test name
Test status
Simulation time 10454602515 ps
CPU time 16.55 seconds
Started Jul 09 07:03:01 PM PDT 24
Finished Jul 09 07:03:22 PM PDT 24
Peak memory 200380 kb
Host smart-33c89692-7382-4742-9dfc-37b83e7acf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382559779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.3382559779
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2142219596
Short name T439
Test name
Test status
Simulation time 56321223 ps
CPU time 0.56 seconds
Started Jul 09 07:03:17 PM PDT 24
Finished Jul 09 07:03:19 PM PDT 24
Peak memory 195128 kb
Host smart-390b46e4-c514-405a-bfbb-b6129287752b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142219596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2142219596
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.4268244218
Short name T222
Test name
Test status
Simulation time 2849284406 ps
CPU time 39.79 seconds
Started Jul 09 07:03:03 PM PDT 24
Finished Jul 09 07:03:48 PM PDT 24
Peak memory 200340 kb
Host smart-5dba0cc0-cc50-4bbb-8ba4-409f80910ba8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4268244218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.4268244218
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3370037710
Short name T23
Test name
Test status
Simulation time 2461199876 ps
CPU time 30.17 seconds
Started Jul 09 07:03:00 PM PDT 24
Finished Jul 09 07:03:33 PM PDT 24
Peak memory 200384 kb
Host smart-4e4a0e9b-de63-49b1-bbe9-537522749140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370037710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3370037710
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1382985066
Short name T40
Test name
Test status
Simulation time 21289849858 ps
CPU time 1051.35 seconds
Started Jul 09 07:02:56 PM PDT 24
Finished Jul 09 07:20:29 PM PDT 24
Peak memory 725596 kb
Host smart-6221c85a-51e3-4879-ad0f-8b0b37415a4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1382985066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1382985066
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2097920183
Short name T256
Test name
Test status
Simulation time 4098564043 ps
CPU time 50.36 seconds
Started Jul 09 07:02:58 PM PDT 24
Finished Jul 09 07:03:51 PM PDT 24
Peak memory 200344 kb
Host smart-64b1e2c7-56eb-408c-a8a9-dcb1e95b57d6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097920183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2097920183
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.730277754
Short name T393
Test name
Test status
Simulation time 1798064531 ps
CPU time 83.88 seconds
Started Jul 09 07:03:00 PM PDT 24
Finished Jul 09 07:04:26 PM PDT 24
Peak memory 200312 kb
Host smart-abd36506-de0e-4645-9136-6561c9874f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730277754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.730277754
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.79303772
Short name T485
Test name
Test status
Simulation time 2840363428 ps
CPU time 13.75 seconds
Started Jul 09 07:03:02 PM PDT 24
Finished Jul 09 07:03:20 PM PDT 24
Peak memory 200452 kb
Host smart-7cf4f775-302e-42fc-a337-010161046ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79303772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.79303772
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.4122108219
Short name T388
Test name
Test status
Simulation time 7882419390 ps
CPU time 972.85 seconds
Started Jul 09 07:02:59 PM PDT 24
Finished Jul 09 07:19:14 PM PDT 24
Peak memory 681884 kb
Host smart-39478ca1-d116-4469-bdba-657331fa2c7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122108219 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.4122108219
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.1977837049
Short name T21
Test name
Test status
Simulation time 59297034049 ps
CPU time 1558.13 seconds
Started Jul 09 07:02:59 PM PDT 24
Finished Jul 09 07:28:59 PM PDT 24
Peak memory 751732 kb
Host smart-138917c4-49f4-4270-a451-1eb220213476
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1977837049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.1977837049
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2923367026
Short name T117
Test name
Test status
Simulation time 4698062128 ps
CPU time 85.48 seconds
Started Jul 09 07:03:01 PM PDT 24
Finished Jul 09 07:04:30 PM PDT 24
Peak memory 200360 kb
Host smart-8a06cf09-2086-42d7-9b01-2a7559cb6a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923367026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2923367026
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2335130821
Short name T488
Test name
Test status
Simulation time 43529791 ps
CPU time 0.58 seconds
Started Jul 09 07:03:05 PM PDT 24
Finished Jul 09 07:03:10 PM PDT 24
Peak memory 196204 kb
Host smart-8e8dad97-2556-4d0f-ba47-c53769ce1bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335130821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2335130821
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.794692107
Short name T479
Test name
Test status
Simulation time 2744025345 ps
CPU time 38.29 seconds
Started Jul 09 07:03:01 PM PDT 24
Finished Jul 09 07:03:43 PM PDT 24
Peak memory 200356 kb
Host smart-11d29e33-8d65-4e1d-985c-463c0b90e4ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=794692107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.794692107
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1488845972
Short name T145
Test name
Test status
Simulation time 3831610548 ps
CPU time 30.06 seconds
Started Jul 09 07:03:21 PM PDT 24
Finished Jul 09 07:03:52 PM PDT 24
Peak memory 200368 kb
Host smart-d41a3475-e31e-4cc2-bf45-facb5f16d94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488845972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1488845972
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.967307516
Short name T313
Test name
Test status
Simulation time 7402118521 ps
CPU time 1385.68 seconds
Started Jul 09 07:02:58 PM PDT 24
Finished Jul 09 07:26:06 PM PDT 24
Peak memory 695796 kb
Host smart-073df996-e68a-4ec3-bb8f-6169bfb67407
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=967307516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.967307516
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2300299752
Short name T489
Test name
Test status
Simulation time 2067340595 ps
CPU time 116.5 seconds
Started Jul 09 07:03:06 PM PDT 24
Finished Jul 09 07:05:07 PM PDT 24
Peak memory 200328 kb
Host smart-40c09103-0b85-4435-ae52-89a597e98857
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300299752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2300299752
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.2646041784
Short name T375
Test name
Test status
Simulation time 5747501954 ps
CPU time 104.44 seconds
Started Jul 09 07:03:03 PM PDT 24
Finished Jul 09 07:04:53 PM PDT 24
Peak memory 208572 kb
Host smart-ada1c602-ec13-47f9-91d5-b27012547db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646041784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2646041784
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1102749008
Short name T353
Test name
Test status
Simulation time 91529058 ps
CPU time 4.37 seconds
Started Jul 09 07:03:00 PM PDT 24
Finished Jul 09 07:03:07 PM PDT 24
Peak memory 200068 kb
Host smart-4b7d8d47-de2e-4e2d-9dfd-33ea7b1d90ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102749008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1102749008
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1063743455
Short name T368
Test name
Test status
Simulation time 7887597317 ps
CPU time 960.09 seconds
Started Jul 09 07:03:01 PM PDT 24
Finished Jul 09 07:19:04 PM PDT 24
Peak memory 775044 kb
Host smart-12867970-5b0d-4f01-a0b2-87a881846141
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063743455 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1063743455
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.2224607496
Short name T64
Test name
Test status
Simulation time 77383425908 ps
CPU time 673.54 seconds
Started Jul 09 07:03:03 PM PDT 24
Finished Jul 09 07:14:22 PM PDT 24
Peak memory 355996 kb
Host smart-9b31d3c7-bad7-4ccd-8c29-cfb5599c4e0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2224607496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.2224607496
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2158757419
Short name T78
Test name
Test status
Simulation time 1061901131 ps
CPU time 60.2 seconds
Started Jul 09 07:03:07 PM PDT 24
Finished Jul 09 07:04:12 PM PDT 24
Peak memory 200284 kb
Host smart-fecf6e88-f1eb-40be-b9fc-7a243303faa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158757419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2158757419
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2250188708
Short name T146
Test name
Test status
Simulation time 21888175 ps
CPU time 0.6 seconds
Started Jul 09 07:03:08 PM PDT 24
Finished Jul 09 07:03:13 PM PDT 24
Peak memory 196200 kb
Host smart-cd686461-410e-4225-8428-2c6ee22a98e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250188708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2250188708
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2772307326
Short name T351
Test name
Test status
Simulation time 2655469699 ps
CPU time 78.61 seconds
Started Jul 09 07:03:14 PM PDT 24
Finished Jul 09 07:04:34 PM PDT 24
Peak memory 200332 kb
Host smart-266a26e1-c358-4567-a379-14e9916a20aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2772307326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2772307326
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2023270198
Short name T381
Test name
Test status
Simulation time 1656566242 ps
CPU time 23.62 seconds
Started Jul 09 07:03:14 PM PDT 24
Finished Jul 09 07:03:39 PM PDT 24
Peak memory 200368 kb
Host smart-7a774400-a54a-459b-8aac-d7e76427bcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023270198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2023270198
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1864794080
Short name T269
Test name
Test status
Simulation time 13923306961 ps
CPU time 178.3 seconds
Started Jul 09 07:03:06 PM PDT 24
Finished Jul 09 07:06:09 PM PDT 24
Peak memory 390864 kb
Host smart-f7be6a0b-b5b5-4a40-b9eb-c44434fb4457
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1864794080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1864794080
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.971186384
Short name T448
Test name
Test status
Simulation time 39449659322 ps
CPU time 226.17 seconds
Started Jul 09 07:03:01 PM PDT 24
Finished Jul 09 07:06:51 PM PDT 24
Peak memory 200340 kb
Host smart-e5cbf91e-a87b-46e9-8441-00cc66ea5fb9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971186384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.971186384
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.1811885792
Short name T157
Test name
Test status
Simulation time 5828584236 ps
CPU time 64.87 seconds
Started Jul 09 07:03:02 PM PDT 24
Finished Jul 09 07:04:12 PM PDT 24
Peak memory 200320 kb
Host smart-21edc58c-e266-45cc-bd8a-767b8a70d052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811885792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.1811885792
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2250796535
Short name T319
Test name
Test status
Simulation time 451416123 ps
CPU time 5.34 seconds
Started Jul 09 07:03:02 PM PDT 24
Finished Jul 09 07:03:11 PM PDT 24
Peak memory 200368 kb
Host smart-4b1c6d32-4f71-4ef3-85ab-2ef542fbf189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250796535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2250796535
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3926263678
Short name T423
Test name
Test status
Simulation time 88542017621 ps
CPU time 3140.1 seconds
Started Jul 09 07:03:01 PM PDT 24
Finished Jul 09 07:55:25 PM PDT 24
Peak memory 797188 kb
Host smart-14100154-c6e5-4031-bf07-b1784e44fa61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926263678 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3926263678
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3086770174
Short name T315
Test name
Test status
Simulation time 10289200051 ps
CPU time 110.64 seconds
Started Jul 09 07:03:02 PM PDT 24
Finished Jul 09 07:04:58 PM PDT 24
Peak memory 200436 kb
Host smart-80fddcaf-0a1e-4418-8e69-a72e434e8568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086770174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3086770174
Directory /workspace/9.hmac_wipe_secret/latest
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