Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	19478905	1			T1	102		T2	32276		T4	7686
all_values[1]	19478905	1			T1	102		T2	32276		T4	7686
all_values[2]	19478905	1			T1	102		T2	32276		T4	7686

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

210450

1

T2

3427

T5

858

T6

425

auto[1]

58226265

1

T1

306

T2

93401

T4

23058

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49762604

1

T1

249

T2

72665

T4

18743

auto[1]

8674111

1

T1

57

T2

24163

T4

4315

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	69082	1			T6	163		T19	1031		T39	8476
all_values[0]	auto[0]	auto[1]	329	1			T5	1		T6	2		T19	5
all_values[0]	auto[1]	auto[0]	19388958	1			T1	99		T2	32269		T4	7665
all_values[0]	auto[1]	auto[1]	20536	1			T1	3		T2	7		T4	21
all_values[1]	auto[0]	auto[0]	79215	1			T2	3427		T5	827		T6	260
all_values[1]	auto[0]	auto[1]	178	1			T5	2		T19	4		T39	2
all_values[1]	auto[1]	auto[0]	19399206	1			T1	102		T2	28849		T4	7686
all_values[1]	auto[1]	auto[1]	306	1			T5	1		T19	19		T39	3
all_values[2]	auto[0]	auto[0]	34091	1			T5	7		T19	380		T39	971
all_values[2]	auto[0]	auto[1]	27555	1			T5	21		T19	3		T39	2
all_values[2]	auto[1]	auto[0]	10792052	1			T1	48		T2	8120		T4	3392
all_values[2]	auto[1]	auto[1]	8625207	1			T1	54		T2	24156		T4	4294