Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

118845

1

T1

6

T2

22

T4

24

auto[1]

124032

1

T2

32

T4

22

T8

32

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	93725	1			T2	19		T4	20		T7	52
len_1026_2046	5488	1			T7	1		T8	6		T5	7
len_514_1022	3501	1			T2	5		T7	60		T18	3
len_2_510	3067	1			T7	59		T8	1		T17	2
len_2056	216	1			T5	3		T19	2		T10	6
len_2048	336	1			T4	1		T18	2		T5	1
len_2040	183	1			T18	1		T6	2		T19	9
len_1032	172	1			T19	6		T37	1		T10	10
len_1024	2002	1			T4	1		T7	2		T18	2
len_1016	190	1			T7	1		T5	2		T19	6
len_520	205	1			T1	1		T7	1		T18	5
len_512	416	1			T7	1		T18	1		T19	15
len_504	213	1			T7	2		T19	2		T60	4
len_8	1321	1			T5	23		T25	4		T35	11
len_0	10405	1			T1	2		T2	3		T4	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

115

1

T6

2

T19

1

T37

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	47005	1			T2	7		T4	10		T7	52
auto[0]	len_1026_2046	2526	1			T7	1		T8	4		T5	5
auto[0]	len_514_1022	1964	1			T2	2		T7	60		T5	3
auto[0]	len_2_510	2178	1			T7	59		T18	2		T5	4
auto[0]	len_2056	111	1			T19	1		T10	5		T60	5
auto[0]	len_2048	178	1			T4	1		T18	1		T19	4
auto[0]	len_2040	96	1			T18	1		T6	2		T19	5
auto[0]	len_1032	84	1			T19	4		T37	1		T10	2
auto[0]	len_1024	249	1			T7	2		T18	2		T6	1
auto[0]	len_1016	113	1			T7	1		T19	5		T10	3
auto[0]	len_520	115	1			T1	1		T7	1		T18	1
auto[0]	len_512	217	1			T7	1		T19	7		T50	1
auto[0]	len_504	130	1			T7	2		T19	2		T60	4
auto[0]	len_8	22	1			T64	1		T110	1		T111	1
auto[0]	len_0	4436	1			T1	2		T2	2		T4	1
auto[1]	len_2050_plus	46720	1			T2	12		T4	10		T8	9
auto[1]	len_1026_2046	2962	1			T8	2		T5	2		T6	1
auto[1]	len_514_1022	1537	1			T2	3		T18	3		T5	1
auto[1]	len_2_510	889	1			T8	1		T17	2		T18	1
auto[1]	len_2056	105	1			T5	3		T19	1		T10	1
auto[1]	len_2048	158	1			T18	1		T5	1		T19	5
auto[1]	len_2040	87	1			T19	4		T10	4		T60	2
auto[1]	len_1032	88	1			T19	2		T10	8		T112	1
auto[1]	len_1024	1753	1			T4	1		T5	1		T19	7
auto[1]	len_1016	77	1			T5	2		T19	1		T10	5
auto[1]	len_520	90	1			T18	4		T10	19		T60	2
auto[1]	len_512	199	1			T18	1		T19	8		T50	1
auto[1]	len_504	83	1			T74	2		T113	1		T114	1
auto[1]	len_8	1299	1			T5	23		T25	4		T35	11
auto[1]	len_0	5969	1			T2	1		T8	4		T9	2

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

78

1

T6

2

T19

1

T38

1

auto[1]

len_upper

37

1

T37

1

T60

2

T115

1