Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4905466 1 T1 10 T2 1078 T4 16
auto[1] 3158630 1 T1 35 T2 3992 T4 14


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3171440 1 T1 33 T2 3879 T4 18
auto[1] 4892656 1 T1 12 T2 1191 T4 12


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3366915 1 T1 22 T2 3887 T4 15
auto[1] 4697181 1 T1 23 T2 1183 T4 15


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4955939 1 T1 43 T2 2997 T4 20
auto[1] 3108157 1 T1 2 T2 2073 T4 10


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 7308626 1 T1 45 T2 4936 T4 25
fifo_depth[1] 127646 1 T2 96 T4 1 T7 2582
fifo_depth[2] 98013 1 T2 30 T7 812 T8 257
fifo_depth[3] 78714 1 T2 7 T7 182 T8 239
fifo_depth[4] 71314 1 T2 1 T7 35 T8 237
fifo_depth[5] 57119 1 T7 10 T8 200 T9 55
fifo_depth[6] 45826 1 T8 187 T9 41 T18 6
fifo_depth[7] 30918 1 T8 104 T9 26 T18 5


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 755470 1 T2 134 T4 5 T7 3621
auto[1] 7308626 1 T1 45 T2 4936 T4 25


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8052454 1 T1 45 T2 5070 T4 30
auto[1] 11642 1 T19 1654 T10 976 T23 665


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 39009 1 T4 1 T8 19 T9 197
auto[0] auto[0] auto[0] auto[0] auto[1] 32783 1 T2 2 T8 205 T17 18
auto[0] auto[0] auto[0] auto[1] auto[0] 34748 1 T2 73 T8 310 T9 96
auto[0] auto[0] auto[0] auto[1] auto[1] 34423 1 T4 1 T8 187 T17 50
auto[0] auto[0] auto[1] auto[0] auto[0] 163827 1 T7 3621 T17 42 T5 23
auto[0] auto[0] auto[1] auto[0] auto[1] 30988 1 T4 1 T8 94 T17 11
auto[0] auto[0] auto[1] auto[1] auto[0] 27525 1 T17 7 T5 19 T19 3767
auto[0] auto[0] auto[1] auto[1] auto[1] 34453 1 T8 77 T17 17 T18 26
auto[0] auto[1] auto[0] auto[0] auto[0] 42425 1 T4 1 T9 112 T17 16
auto[0] auto[1] auto[0] auto[0] auto[1] 39126 1 T8 62 T9 2 T18 5
auto[0] auto[1] auto[0] auto[1] auto[0] 42129 1 T18 6 T5 60 T6 55
auto[0] auto[1] auto[0] auto[1] auto[1] 45619 1 T8 106 T17 3 T5 41
auto[0] auto[1] auto[1] auto[0] auto[0] 55928 1 T8 2 T17 48 T5 136
auto[0] auto[1] auto[1] auto[0] auto[1] 50520 1 T8 327 T17 21 T18 5
auto[0] auto[1] auto[1] auto[1] auto[0] 41051 1 T4 1 T8 86 T9 51
auto[0] auto[1] auto[1] auto[1] auto[1] 40916 1 T2 59 T8 98 T18 9
auto[1] auto[0] auto[0] auto[0] auto[0] 175356 1 T1 10 T2 638 T4 2
auto[1] auto[0] auto[0] auto[0] auto[1] 188850 1 T2 415 T4 3 T8 819
auto[1] auto[0] auto[0] auto[1] auto[0] 184885 1 T2 2271 T4 1 T8 1558
auto[1] auto[0] auto[0] auto[1] auto[1] 183831 1 T2 467 T4 2 T8 575
auto[1] auto[0] auto[1] auto[0] auto[0] 1722665 1 T2 2 T4 2 T7 144287
auto[1] auto[0] auto[1] auto[0] auto[1] 158781 1 T2 15 T8 303 T9 454
auto[1] auto[0] auto[1] auto[1] auto[0] 182472 1 T1 10 T4 2 T8 248
auto[1] auto[0] auto[1] auto[1] auto[1] 172319 1 T1 2 T2 4 T8 396
auto[1] auto[1] auto[0] auto[0] auto[0] 563575 1 T2 2 T4 2 T9 340
auto[1] auto[1] auto[0] auto[0] auto[1] 458528 1 T2 2 T4 2 T8 909
auto[1] auto[1] auto[0] auto[1] auto[0] 586774 1 T1 23 T2 8 T4 3
auto[1] auto[1] auto[0] auto[1] auto[1] 519379 1 T2 1 T8 777 T9 387
auto[1] auto[1] auto[1] auto[0] auto[0] 609586 1 T2 1 T4 1 T9 216
auto[1] auto[1] auto[1] auto[0] auto[1] 573519 1 T2 1 T4 1 T8 1628
auto[1] auto[1] auto[1] auto[1] auto[0] 483984 1 T2 2 T4 4 T8 595
auto[1] auto[1] auto[1] auto[1] auto[1] 544122 1 T2 1107 T8 542 T9 465


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 212972 1 T1 10 T2 638 T4 3
auto[0] auto[0] auto[0] auto[0] auto[1] 220775 1 T2 417 T4 3 T8 1024
auto[0] auto[0] auto[0] auto[1] auto[0] 218444 1 T2 2344 T4 1 T8 1868
auto[0] auto[0] auto[0] auto[1] auto[1] 217921 1 T2 467 T4 3 T8 762
auto[0] auto[0] auto[1] auto[0] auto[0] 1885187 1 T2 2 T4 2 T7 147908
auto[0] auto[0] auto[1] auto[0] auto[1] 189106 1 T2 15 T4 1 T8 397
auto[0] auto[0] auto[1] auto[1] auto[0] 209724 1 T1 10 T4 2 T8 248
auto[0] auto[0] auto[1] auto[1] auto[1] 206198 1 T1 2 T2 4 T8 473
auto[0] auto[1] auto[0] auto[0] auto[0] 605679 1 T2 2 T4 3 T9 452
auto[0] auto[1] auto[0] auto[0] auto[1] 497224 1 T2 2 T4 2 T8 971
auto[0] auto[1] auto[0] auto[1] auto[0] 628631 1 T1 23 T2 8 T4 3
auto[0] auto[1] auto[0] auto[1] auto[1] 563505 1 T2 1 T8 883 T9 387
auto[0] auto[1] auto[1] auto[0] auto[0] 664726 1 T2 1 T4 1 T8 2
auto[0] auto[1] auto[1] auto[0] auto[1] 623577 1 T2 1 T4 1 T8 1955
auto[0] auto[1] auto[1] auto[1] auto[0] 524689 1 T2 2 T4 5 T8 681
auto[0] auto[1] auto[1] auto[1] auto[1] 584096 1 T2 1166 T8 640 T9 465
auto[1] auto[0] auto[0] auto[0] auto[0] 1393 1 T19 60 T10 22 T20 20
auto[1] auto[0] auto[0] auto[0] auto[1] 858 1 T19 5 T10 358 T20 2
auto[1] auto[0] auto[0] auto[1] auto[0] 1189 1 T19 160 T10 143 T13 1
auto[1] auto[0] auto[0] auto[1] auto[1] 333 1 T19 5 T10 29 T24 1
auto[1] auto[0] auto[1] auto[0] auto[0] 1305 1 T19 658 T10 18 T13 108
auto[1] auto[0] auto[1] auto[0] auto[1] 663 1 T20 2 T24 212 T117 13
auto[1] auto[0] auto[1] auto[1] auto[0] 273 1 T19 1 T10 77 T24 5
auto[1] auto[0] auto[1] auto[1] auto[1] 574 1 T19 15 T10 63 T13 92
auto[1] auto[1] auto[0] auto[0] auto[0] 321 1 T19 84 T23 4 T20 14
auto[1] auto[1] auto[0] auto[0] auto[1] 430 1 T19 7 T10 8 T24 298
auto[1] auto[1] auto[0] auto[1] auto[0] 272 1 T19 24 T10 25 T23 32
auto[1] auto[1] auto[0] auto[1] auto[1] 1493 1 T19 476 T10 4 T24 853
auto[1] auto[1] auto[1] auto[0] auto[0] 788 1 T19 69 T10 102 T24 323
auto[1] auto[1] auto[1] auto[0] auto[1] 462 1 T19 2 T10 5 T23 7
auto[1] auto[1] auto[1] auto[1] auto[0] 346 1 T19 88 T10 4 T20 10
auto[1] auto[1] auto[1] auto[1] auto[1] 942 1 T10 118 T23 622 T118 90


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 175356 1 T1 10 T2 638 T4 2
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 188850 1 T2 415 T4 3 T8 819
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 184885 1 T2 2271 T4 1 T8 1558
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 183831 1 T2 467 T4 2 T8 575
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1722665 1 T2 2 T4 2 T7 144287
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 158781 1 T2 15 T8 303 T9 454
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 182472 1 T1 10 T4 2 T8 248
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 172319 1 T1 2 T2 4 T8 396
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 563575 1 T2 2 T4 2 T9 340
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 458528 1 T2 2 T4 2 T8 909
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 586774 1 T1 23 T2 8 T4 3
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 519379 1 T2 1 T8 777 T9 387
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 609586 1 T2 1 T4 1 T9 216
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 573519 1 T2 1 T4 1 T8 1628
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 483984 1 T2 2 T4 4 T8 595
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 544122 1 T2 1107 T8 542 T9 465
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 3746 1 T8 4 T9 32 T5 7
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 3982 1 T2 1 T8 33 T17 12
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 3939 1 T2 60 T8 48 T9 18
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 3938 1 T8 34 T17 27 T5 22
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 42237 1 T7 2582 T17 23 T5 14
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 3428 1 T8 11 T17 8 T5 22
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 3798 1 T17 6 T5 12 T19 152
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 4176 1 T8 18 T17 9 T18 1
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 6594 1 T4 1 T9 21 T17 6
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 6388 1 T8 6 T9 2 T5 136
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 6722 1 T5 37 T6 5 T35 43
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 7126 1 T8 15 T17 2 T5 29
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 10428 1 T17 33 T5 109 T35 222
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 8160 1 T8 50 T17 10 T18 2
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 5876 1 T8 11 T9 10 T17 8
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 7108 1 T2 35 T8 14 T18 1
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 2728 1 T8 2 T9 33 T5 5
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 3135 1 T2 1 T8 36 T17 4
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 2844 1 T2 10 T8 38 T9 14
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 3077 1 T8 34 T17 19 T5 6
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 29102 1 T7 812 T17 13 T5 9
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 2706 1 T8 16 T17 2 T5 3
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 2927 1 T17 1 T5 5 T19 86
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 3536 1 T8 17 T17 2 T18 5
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 5497 1 T9 15 T17 7 T5 33
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 5361 1 T8 11 T18 1 T5 35
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 5441 1 T5 18 T6 9 T35 37
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 5833 1 T8 16 T5 11 T35 356
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 8000 1 T17 14 T5 26 T35 192
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 6996 1 T8 52 T17 10 T5 10
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 5021 1 T8 18 T9 6 T17 2
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 5809 1 T2 19 T8 17 T18 2
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 2104 1 T8 1 T9 39 T5 1
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 2164 1 T8 38 T17 1 T5 1
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 2036 1 T2 3 T8 34 T9 18
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 2446 1 T8 36 T17 4 T5 1
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 22828 1 T7 182 T17 4 T6 40
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 2124 1 T8 18 T17 1 T19 17
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 2221 1 T5 2 T19 140 T39 15
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 2751 1 T8 11 T17 4 T18 5
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 4603 1 T9 22 T17 2 T5 5
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 4484 1 T8 6 T18 1 T5 5
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 4530 1 T18 1 T5 3 T6 10
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 5139 1 T8 15 T17 1 T5 1
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 6246 1 T8 2 T17 1 T5 1
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 5913 1 T8 50 T17 1 T5 3
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 4296 1 T8 12 T9 3 T5 5
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 4829 1 T2 4 T8 16 T18 2
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2069 1 T8 4 T9 40 T19 82
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 2316 1 T8 31 T17 1 T6 5
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 2055 1 T8 44 T9 13 T5 6
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 2413 1 T8 29 T6 7 T19 25
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 17351 1 T7 35 T17 2 T6 33
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 2011 1 T8 15 T19 12 T38 47
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 2095 1 T19 84 T39 3 T38 21
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 2948 1 T8 18 T17 2 T18 4
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 4495 1 T9 15 T17 1 T5 2
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 4362 1 T8 3 T18 3 T19 140
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 4192 1 T18 2 T5 1 T6 7
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 4830 1 T8 19 T35 372 T19 219
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 5636 1 T35 220 T19 40 T39 6
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 5627 1 T8 50 T35 68 T19 21
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 4395 1 T8 10 T9 7 T5 2
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 4519 1 T2 1 T8 14 T18 2
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 1621 1 T8 2 T9 24 T6 1
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 1637 1 T8 25 T19 74 T39 4
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1569 1 T8 34 T9 12 T5 1
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 1992 1 T8 21 T6 5 T19 36
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 12613 1 T7 10 T6 25 T19 74
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 1702 1 T8 14 T19 44 T37 1
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 1630 1 T19 110 T38 17 T50 2
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 2216 1 T8 5 T18 3 T19 142
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 3812 1 T9 13 T5 1 T35 81
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 3612 1 T8 10 T19 67 T38 4
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 3532 1 T6 6 T35 41 T19 45
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 4249 1 T8 18 T35 329 T19 123
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 4607 1 T35 161 T19 78 T39 3
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 4679 1 T8 47 T35 71 T19 27
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 3520 1 T8 12 T9 6 T19 10
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 4128 1 T8 12 T35 66 T19 25
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1417 1 T8 3 T9 19 T19 70
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1447 1 T8 20 T6 1 T19 28
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1525 1 T8 47 T9 9 T5 1
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1634 1 T8 23 T6 8 T19 30
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 9001 1 T6 15 T19 89 T47 10
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1324 1 T8 11 T19 12 T38 47
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1255 1 T19 58 T38 20 T50 2
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1875 1 T8 5 T18 2 T5 3
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 3196 1 T9 8 T35 69 T19 48
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 2784 1 T8 10 T19 91 T38 1
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 2991 1 T18 1 T5 1 T6 7
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 3420 1 T8 10 T35 266 T19 63
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3611 1 T35 120 T19 30 T37 1
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 3883 1 T8 35 T18 2 T35 37
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 3112 1 T8 5 T9 5 T19 8
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 3351 1 T8 18 T18 1 T35 36
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 991 1 T8 2 T9 4 T19 45
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 935 1 T8 13 T19 44 T39 1
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 1090 1 T8 27 T9 9 T5 1
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 1099 1 T8 5 T6 9 T19 40
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 5673 1 T6 6 T19 58 T47 6
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 971 1 T8 5 T19 41 T38 26
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 805 1 T19 92 T38 11 T50 1
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 1302 1 T8 3 T18 4 T19 65
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 2204 1 T9 7 T35 51 T19 34
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 1916 1 T8 7 T19 69 T49 39
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 2134 1 T6 7 T35 31 T19 38
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 2225 1 T8 5 T35 157 T19 50
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2520 1 T35 81 T19 72 T37 2
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 2654 1 T8 25 T35 29 T19 18
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 2089 1 T8 9 T9 6 T19 4
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 2310 1 T8 3 T18 1 T35 18

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