Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	19478905	1			T1	102		T2	32276		T4	7686
all_pins[1]	19478905	1			T1	102		T2	32276		T4	7686
all_pins[2]	19478905	1			T1	102		T2	32276		T4	7686

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	49789781	1			T1	249		T2	72665		T4	18739
values[0x1]	8646934	1			T1	57		T2	24163		T4	4319
transitions[0x0=>0x1]	8646774	1			T1	57		T2	24163		T4	4319
transitions[0x1=>0x0]	8646785	1			T1	57		T2	24163		T4	4319

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	19457509	1			T1	99		T2	32269		T4	7661
all_pins[0]	values[0x1]	21396	1			T1	3		T2	7		T4	25
all_pins[0]	transitions[0x0=>0x1]	21323	1			T1	3		T2	7		T4	25
all_pins[0]	transitions[0x1=>0x0]	8625145	1			T1	54		T2	24156		T4	4294
all_pins[1]	values[0x0]	19478574	1			T1	102		T2	32276		T4	7686
all_pins[1]	values[0x1]	331	1			T5	1		T19	20		T39	3
all_pins[1]	transitions[0x0=>0x1]	288	1			T5	1		T19	20		T39	2
all_pins[1]	transitions[0x1=>0x0]	21353	1			T1	3		T2	7		T4	25
all_pins[2]	values[0x0]	10853698	1			T1	48		T2	8120		T4	3392
all_pins[2]	values[0x1]	8625207	1			T1	54		T2	24156		T4	4294
all_pins[2]	transitions[0x0=>0x1]	8625163	1			T1	54		T2	24156		T4	4294
all_pins[2]	transitions[0x1=>0x0]	287	1			T5	1		T19	20		T39	1