Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 839 1 T5 8 T19 14 T39 14
all_values[1] 839 1 T5 8 T19 14 T39 14
all_values[2] 839 1 T5 8 T19 14 T39 14


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1269 1 T5 12 T19 23 T39 19
auto[1] 1248 1 T5 12 T19 19 T39 23


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 845 1 T5 8 T19 14 T39 12
auto[1] 1672 1 T5 16 T19 28 T39 30


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1423 1 T5 15 T19 25 T39 19
auto[1] 1094 1 T5 9 T19 17 T39 23


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 160 1 T19 2 T39 2 T10 2
all_values[0] auto[0] auto[0] auto[1] 77 1 T19 2 T39 1 T10 3
all_values[0] auto[0] auto[1] auto[0] 123 1 T5 2 T19 3 T39 1
all_values[0] auto[0] auto[1] auto[1] 110 1 T5 2 T19 1 T39 1
all_values[0] auto[1] auto[0] auto[1] 178 1 T5 2 T19 3 T39 4
all_values[0] auto[1] auto[1] auto[1] 191 1 T5 2 T19 3 T39 5
all_values[1] auto[0] auto[0] auto[0] 128 1 T5 1 T39 3 T10 3
all_values[1] auto[0] auto[0] auto[1] 107 1 T5 1 T19 3 T39 2
all_values[1] auto[0] auto[1] auto[0] 138 1 T5 2 T19 2 T39 2
all_values[1] auto[0] auto[1] auto[1] 110 1 T5 1 T19 2 T39 2
all_values[1] auto[1] auto[0] auto[1] 181 1 T5 3 T19 4 T39 2
all_values[1] auto[1] auto[1] auto[1] 175 1 T19 3 T39 3 T10 9
all_values[2] auto[0] auto[0] auto[0] 160 1 T5 1 T19 5 T39 1
all_values[2] auto[0] auto[0] auto[1] 95 1 T5 3 T19 2 T10 2
all_values[2] auto[0] auto[1] auto[0] 136 1 T5 2 T19 2 T39 3
all_values[2] auto[0] auto[1] auto[1] 79 1 T19 1 T39 1 T60 1
all_values[2] auto[1] auto[0] auto[1] 183 1 T5 1 T19 2 T39 4
all_values[2] auto[1] auto[1] auto[1] 186 1 T5 1 T19 2 T39 5


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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