Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4416	1			T2	3		T4	8		T8	9
sha2_none	4383	1			T1	1		T2	1		T4	3
sha2_512	7851	1			T1	1		T2	1		T4	2
sha2_384	7653	1			T1	1		T2	8		T4	9
sha2_256	6630	1			T1	2		T2	10		T4	10

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19327

1

T1

1

T2

8

T4

18

auto[1]

12006

1

T1

4

T2

15

T4

15

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11949

1

T1

2

T2

13

T4

21

auto[1]

19384

1

T1

3

T2

10

T4

12

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

16537

1

T1

1

T2

7

T4

17

disabled

14796

1

T1

4

T2

16

T4

16

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	4876	1			T1	2		T2	5		T4	4
key_none	7896	1			T1	2		T2	1		T4	7
key_1024	4497	1			T2	4		T4	3		T8	7
key_512	3896	1			T2	3		T4	6		T8	5
key_384	3583	1			T1	1		T2	3		T4	4
key_256	3334	1			T2	2		T4	4		T8	9
key_128	3170	1			T2	5		T4	5		T8	3

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19545

1

T1

3

T2

9

T4

23

auto[1]

11788

1

T1

2

T2

14

T4

10

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

31159

1

T1

5

T2

22

T4

33

disabled

174

1

T2

1

T19

3

T39

4

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1795

1

T2

1

T4

4

T9

1

enabled

auto[0]

auto[0]

auto[1]

1614

1

T4

2

T8

3

T9

2

enabled

auto[0]

auto[1]

auto[0]

1771

1

T1

1

T2

1

T4

4

enabled

auto[0]

auto[1]

auto[1]

1704

1

T8

2

T9

1

T17

4

enabled

auto[1]

auto[0]

auto[0]

4420

1

T4

1

T8

1

T9

2

enabled

auto[1]

auto[0]

auto[1]

1734

1

T4

1

T8

7

T17

4

enabled

auto[1]

auto[1]

auto[0]

1718

1

T2

1

T4

5

T8

3

enabled

auto[1]

auto[1]

auto[1]

1781

1

T2

4

T8

2

T9

1

disabled

auto[0]

auto[0]

auto[0]

1236

1

T1

1

T2

2

T4

4

disabled

auto[0]

auto[0]

auto[1]

1269

1

T2

3

T4

3

T8

3

disabled

auto[0]

auto[1]

auto[0]

1298

1

T2

4

T4

1

T8

6

disabled

auto[0]

auto[1]

auto[1]

1262

1

T2

2

T4

3

T8

4

disabled

auto[1]

auto[0]

auto[0]

6078

1

T4

2

T7

386

T8

1

disabled

auto[1]

auto[0]

auto[1]

1181

1

T2

2

T4

1

T8

3

disabled

auto[1]

auto[1]

auto[0]

1229

1

T1

1

T4

2

T8

1

disabled

auto[1]

auto[1]

auto[1]

1243

1

T1

2

T2

3

T8

3

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

16468

1

T1

1

T2

7

T4

17

enabled

disabled

69

1

T39

2

T10

3

T61

1

disabled

disabled

105

1

T2

1

T19

3

T39

2

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

14691

1

T1

4

T2

15

T4

16

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1190	1			T2	2		T4	1		T8	4
key_invalid	sha2_none	846	1			T1	1		T8	1		T9	1
key_invalid	sha2_512	920	1			T2	1		T4	1		T8	2
key_invalid	sha2_384	903	1			T1	1		T2	2		T8	1
key_invalid	sha2_256	916	1			T4	2		T8	1		T18	2
key_none	sha2_invalid	508	1			T4	1		T17	1		T18	2
key_none	sha2_none	544	1			T8	1		T17	1		T5	6
key_none	sha2_512	2588	1			T1	1		T7	386		T8	2
key_none	sha2_384	2579	1			T4	1		T17	2		T18	1
key_none	sha2_256	1626	1			T1	1		T2	1		T4	5
key_1024	sha2_invalid	501	1			T4	1		T8	1		T17	1
key_1024	sha2_none	596	1			T8	2		T18	3		T5	4
key_1024	sha2_512	1737	1			T8	1		T17	2		T5	7
key_1024	sha2_384	977	1			T2	2		T4	1		T5	4
key_512	sha2_invalid	550	1			T4	2		T8	1		T9	1
key_512	sha2_none	563	1			T4	1		T8	2		T5	4
key_512	sha2_512	658	1			T4	1		T5	2		T19	12
key_512	sha2_384	1222	1			T2	1		T4	1		T8	2
key_512	sha2_256	854	1			T2	2		T4	1		T5	3
key_384	sha2_invalid	535	1			T4	1		T8	2		T9	1
key_384	sha2_none	637	1			T2	1		T8	1		T17	3
key_384	sha2_512	626	1			T8	3		T17	3		T5	6
key_384	sha2_384	616	1			T4	3		T8	1		T17	2
key_384	sha2_256	1118	1			T1	1		T2	2		T17	2
key_256	sha2_invalid	559	1			T2	1		T4	1		T8	1
key_256	sha2_none	608	1			T4	1		T8	2		T9	1
key_256	sha2_512	647	1			T9	1		T17	3		T18	1
key_256	sha2_384	669	1			T4	2		T8	3		T17	1
key_256	sha2_256	808	1			T2	1		T8	3		T9	1
key_128	sha2_invalid	555	1			T4	1		T9	2		T17	1
key_128	sha2_none	579	1			T4	1		T17	2		T18	1
key_128	sha2_512	656	1			T8	1		T9	1		T5	9
key_128	sha2_384	670	1			T2	3		T4	1		T9	2
key_128	sha2_256	655	1			T2	2		T4	1		T8	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

638

1

T2

2

T4

1

T8

3

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1190	1			T2	2		T4	1		T8	4
key_invalid	sha2_none	846	1			T1	1		T8	1		T9	1
key_invalid	sha2_512	920	1			T2	1		T4	1		T8	2
key_invalid	sha2_384	903	1			T1	1		T2	2		T8	1
key_invalid	sha2_256	916	1			T4	2		T8	1		T18	2
key_none	sha2_invalid	508	1			T4	1		T17	1		T18	2
key_none	sha2_none	544	1			T8	1		T17	1		T5	6
key_none	sha2_512	2588	1			T1	1		T7	386		T8	2
key_none	sha2_384	2579	1			T4	1		T17	2		T18	1
key_none	sha2_256	1626	1			T1	1		T2	1		T4	5
key_1024	sha2_invalid	501	1			T4	1		T8	1		T17	1
key_1024	sha2_none	596	1			T8	2		T18	3		T5	4
key_1024	sha2_512	1737	1			T8	1		T17	2		T5	7
key_1024	sha2_384	977	1			T2	2		T4	1		T5	4
key_1024	sha2_256	638	1			T2	2		T4	1		T8	3
key_512	sha2_invalid	550	1			T4	2		T8	1		T9	1
key_512	sha2_none	563	1			T4	1		T8	2		T5	4
key_512	sha2_512	658	1			T4	1		T5	2		T19	12
key_512	sha2_384	1222	1			T2	1		T4	1		T8	2
key_512	sha2_256	854	1			T2	2		T4	1		T5	3
key_384	sha2_invalid	535	1			T4	1		T8	2		T9	1
key_384	sha2_none	637	1			T2	1		T8	1		T17	3
key_384	sha2_512	626	1			T8	3		T17	3		T5	6
key_384	sha2_384	616	1			T4	3		T8	1		T17	2
key_384	sha2_256	1118	1			T1	1		T2	2		T17	2
key_256	sha2_invalid	559	1			T2	1		T4	1		T8	1
key_256	sha2_none	608	1			T4	1		T8	2		T9	1
key_256	sha2_512	647	1			T9	1		T17	3		T18	1
key_256	sha2_384	669	1			T4	2		T8	3		T17	1
key_256	sha2_256	808	1			T2	1		T8	3		T9	1
key_128	sha2_invalid	555	1			T4	1		T9	2		T17	1
key_128	sha2_none	579	1			T4	1		T17	2		T18	1
key_128	sha2_512	656	1			T8	1		T9	1		T5	9
key_128	sha2_384	670	1			T2	3		T4	1		T9	2
key_128	sha2_256	655	1			T2	2		T4	1		T8	2