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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.45 95.40 97.17 100.00 100.00 98.27 98.48 99.85


Total test records in report: 657
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T530 /workspace/coverage/cover_reg_top/1.hmac_intr_test.218018543 Jul 10 05:09:29 PM PDT 24 Jul 10 05:09:33 PM PDT 24 30096910 ps
T81 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1780272130 Jul 10 05:09:32 PM PDT 24 Jul 10 05:09:46 PM PDT 24 2396284305 ps
T82 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2656729865 Jul 10 05:09:45 PM PDT 24 Jul 10 05:09:53 PM PDT 24 16504555 ps
T83 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1582768430 Jul 10 05:09:30 PM PDT 24 Jul 10 05:09:42 PM PDT 24 461660229 ps
T531 /workspace/coverage/cover_reg_top/2.hmac_intr_test.3414129544 Jul 10 05:09:30 PM PDT 24 Jul 10 05:09:34 PM PDT 24 43318347 ps
T89 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3119252069 Jul 10 05:09:34 PM PDT 24 Jul 10 05:09:44 PM PDT 24 113683578 ps
T532 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3151629962 Jul 10 05:09:29 PM PDT 24 Jul 10 05:09:33 PM PDT 24 27468624 ps
T94 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1814963350 Jul 10 05:09:43 PM PDT 24 Jul 10 05:09:51 PM PDT 24 198035659 ps
T52 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2853484922 Jul 10 05:09:45 PM PDT 24 Jul 10 05:09:54 PM PDT 24 772695689 ps
T95 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1044850013 Jul 10 05:09:38 PM PDT 24 Jul 10 05:09:45 PM PDT 24 84626478 ps
T533 /workspace/coverage/cover_reg_top/28.hmac_intr_test.843968379 Jul 10 05:09:50 PM PDT 24 Jul 10 05:09:59 PM PDT 24 47620169 ps
T96 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.43980027 Jul 10 05:09:45 PM PDT 24 Jul 10 05:09:54 PM PDT 24 316282522 ps
T53 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2220281012 Jul 10 05:09:47 PM PDT 24 Jul 10 05:09:59 PM PDT 24 609263274 ps
T534 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1991634829 Jul 10 05:09:31 PM PDT 24 Jul 10 05:20:19 PM PDT 24 124861625160 ps
T97 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3294090155 Jul 10 05:09:30 PM PDT 24 Jul 10 05:09:36 PM PDT 24 635233214 ps
T535 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3920706987 Jul 10 05:09:34 PM PDT 24 Jul 10 05:09:44 PM PDT 24 220651125 ps
T84 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1109284932 Jul 10 05:09:30 PM PDT 24 Jul 10 05:09:34 PM PDT 24 53851837 ps
T536 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.954080995 Jul 10 05:09:30 PM PDT 24 Jul 10 05:09:36 PM PDT 24 85960086 ps
T537 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.64862508 Jul 10 05:09:31 PM PDT 24 Jul 10 05:09:38 PM PDT 24 82790198 ps
T538 /workspace/coverage/cover_reg_top/9.hmac_intr_test.4261212224 Jul 10 05:09:45 PM PDT 24 Jul 10 05:09:53 PM PDT 24 11869446 ps
T539 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1399281489 Jul 10 05:09:52 PM PDT 24 Jul 10 05:10:00 PM PDT 24 14857550 ps
T540 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2785668941 Jul 10 05:09:34 PM PDT 24 Jul 10 05:09:39 PM PDT 24 48597205 ps
T85 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2633796399 Jul 10 05:09:33 PM PDT 24 Jul 10 05:09:46 PM PDT 24 158790365 ps
T86 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.220759357 Jul 10 05:09:40 PM PDT 24 Jul 10 05:09:46 PM PDT 24 43093291 ps
T541 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3943134520 Jul 10 05:09:50 PM PDT 24 Jul 10 05:09:59 PM PDT 24 47377859 ps
T542 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3172846318 Jul 10 05:09:52 PM PDT 24 Jul 10 05:10:02 PM PDT 24 64911148 ps
T543 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2903198952 Jul 10 05:09:46 PM PDT 24 Jul 10 05:09:58 PM PDT 24 330551171 ps
T90 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.285572938 Jul 10 05:09:30 PM PDT 24 Jul 10 05:09:40 PM PDT 24 556283927 ps
T544 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2993822238 Jul 10 05:09:44 PM PDT 24 Jul 10 05:09:52 PM PDT 24 32390617 ps
T545 /workspace/coverage/cover_reg_top/17.hmac_intr_test.3224874455 Jul 10 05:09:49 PM PDT 24 Jul 10 05:09:58 PM PDT 24 14966502 ps
T87 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.133384518 Jul 10 05:09:35 PM PDT 24 Jul 10 05:09:40 PM PDT 24 156518998 ps
T546 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1862319902 Jul 10 05:09:49 PM PDT 24 Jul 10 05:09:59 PM PDT 24 25541423 ps
T54 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.487534764 Jul 10 05:09:32 PM PDT 24 Jul 10 05:09:39 PM PDT 24 101154773 ps
T547 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1603602383 Jul 10 05:10:11 PM PDT 24 Jul 10 05:10:16 PM PDT 24 63138805 ps
T548 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2065862526 Jul 10 05:09:43 PM PDT 24 Jul 10 05:09:50 PM PDT 24 25780770 ps
T98 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1990899058 Jul 10 05:09:37 PM PDT 24 Jul 10 05:09:44 PM PDT 24 74432980 ps
T549 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.47539047 Jul 10 05:09:31 PM PDT 24 Jul 10 05:09:37 PM PDT 24 31314934 ps
T100 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2024008263 Jul 10 05:09:38 PM PDT 24 Jul 10 05:09:48 PM PDT 24 446706669 ps
T550 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1304763989 Jul 10 05:09:48 PM PDT 24 Jul 10 05:09:59 PM PDT 24 495970926 ps
T551 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.513521039 Jul 10 05:09:34 PM PDT 24 Jul 10 05:09:41 PM PDT 24 88123356 ps
T552 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.909004245 Jul 10 05:09:44 PM PDT 24 Jul 10 05:09:54 PM PDT 24 91113564 ps
T553 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1591396529 Jul 10 05:09:46 PM PDT 24 Jul 10 05:09:55 PM PDT 24 60931294 ps
T104 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1472501998 Jul 10 05:09:46 PM PDT 24 Jul 10 05:09:56 PM PDT 24 168007607 ps
T554 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3742798719 Jul 10 05:09:31 PM PDT 24 Jul 10 05:09:35 PM PDT 24 47406105 ps
T88 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.416460110 Jul 10 05:09:33 PM PDT 24 Jul 10 05:09:39 PM PDT 24 20374536 ps
T555 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.863726603 Jul 10 05:09:35 PM PDT 24 Jul 10 05:09:43 PM PDT 24 872614356 ps
T556 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.936042106 Jul 10 05:09:52 PM PDT 24 Jul 10 05:10:01 PM PDT 24 170503457 ps
T557 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1247958923 Jul 10 05:09:40 PM PDT 24 Jul 10 05:09:48 PM PDT 24 61348160 ps
T558 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1233399478 Jul 10 05:09:29 PM PDT 24 Jul 10 05:09:33 PM PDT 24 37048387 ps
T559 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3011965557 Jul 10 05:09:44 PM PDT 24 Jul 10 05:09:53 PM PDT 24 198010517 ps
T560 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1965619953 Jul 10 05:09:50 PM PDT 24 Jul 10 05:09:59 PM PDT 24 38992042 ps
T105 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1960935091 Jul 10 05:09:30 PM PDT 24 Jul 10 05:09:37 PM PDT 24 266428416 ps
T561 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1624964907 Jul 10 05:09:45 PM PDT 24 Jul 10 05:09:56 PM PDT 24 787746275 ps
T562 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.803181383 Jul 10 05:09:31 PM PDT 24 Jul 10 05:09:38 PM PDT 24 43656347 ps
T563 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2736927636 Jul 10 05:09:45 PM PDT 24 Jul 10 05:09:54 PM PDT 24 66711418 ps
T564 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2649006317 Jul 10 05:09:34 PM PDT 24 Jul 10 05:09:40 PM PDT 24 14258951 ps
T565 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1580686858 Jul 10 05:09:45 PM PDT 24 Jul 10 05:09:54 PM PDT 24 129012893 ps
T566 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.413606721 Jul 10 05:09:46 PM PDT 24 Jul 10 05:09:56 PM PDT 24 87166845 ps
T102 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.208931401 Jul 10 05:09:31 PM PDT 24 Jul 10 05:09:38 PM PDT 24 1056923340 ps
T567 /workspace/coverage/cover_reg_top/19.hmac_intr_test.3304405607 Jul 10 05:09:50 PM PDT 24 Jul 10 05:10:00 PM PDT 24 13799282 ps
T568 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.4119766325 Jul 10 05:09:32 PM PDT 24 Jul 10 05:09:39 PM PDT 24 235909767 ps
T91 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.670751192 Jul 10 05:09:33 PM PDT 24 Jul 10 05:09:46 PM PDT 24 220844997 ps
T569 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2788879941 Jul 10 05:09:37 PM PDT 24 Jul 10 05:09:45 PM PDT 24 87848202 ps
T570 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3938477239 Jul 10 05:09:44 PM PDT 24 Jul 10 05:09:52 PM PDT 24 26582893 ps
T106 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3342426385 Jul 10 05:09:48 PM PDT 24 Jul 10 05:10:00 PM PDT 24 256337919 ps
T571 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1107351310 Jul 10 05:09:33 PM PDT 24 Jul 10 05:09:40 PM PDT 24 301181116 ps
T572 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2625852583 Jul 10 05:09:49 PM PDT 24 Jul 10 05:10:00 PM PDT 24 305165708 ps
T107 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1262752861 Jul 10 05:09:30 PM PDT 24 Jul 10 05:09:38 PM PDT 24 135193167 ps
T573 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1817730241 Jul 10 05:09:49 PM PDT 24 Jul 10 05:09:58 PM PDT 24 56926882 ps
T574 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1980397710 Jul 10 05:09:31 PM PDT 24 Jul 10 05:09:41 PM PDT 24 432064648 ps
T575 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.4276046280 Jul 10 05:09:46 PM PDT 24 Jul 10 05:24:51 PM PDT 24 117599657956 ps
T576 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1082630978 Jul 10 05:09:46 PM PDT 24 Jul 10 05:09:54 PM PDT 24 29125425 ps
T577 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3953318100 Jul 10 05:09:39 PM PDT 24 Jul 10 05:09:47 PM PDT 24 463827593 ps
T578 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1045759214 Jul 10 05:09:46 PM PDT 24 Jul 10 05:09:55 PM PDT 24 14730237 ps
T579 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3757496098 Jul 10 05:09:30 PM PDT 24 Jul 10 05:09:34 PM PDT 24 35410047 ps
T580 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1289943492 Jul 10 05:09:44 PM PDT 24 Jul 10 05:09:54 PM PDT 24 1005016877 ps
T581 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3857406413 Jul 10 05:09:54 PM PDT 24 Jul 10 05:10:03 PM PDT 24 28581063 ps
T582 /workspace/coverage/cover_reg_top/36.hmac_intr_test.442641854 Jul 10 05:09:51 PM PDT 24 Jul 10 05:10:00 PM PDT 24 16508945 ps
T583 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3490719347 Jul 10 05:09:29 PM PDT 24 Jul 10 05:09:36 PM PDT 24 974783930 ps
T584 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.491871227 Jul 10 05:09:31 PM PDT 24 Jul 10 05:09:40 PM PDT 24 536459599 ps
T585 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2643674267 Jul 10 05:09:48 PM PDT 24 Jul 10 05:09:58 PM PDT 24 47181605 ps
T586 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1398843841 Jul 10 05:09:47 PM PDT 24 Jul 10 05:09:57 PM PDT 24 236857939 ps
T587 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3767074760 Jul 10 05:09:34 PM PDT 24 Jul 10 05:09:40 PM PDT 24 169593784 ps
T588 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3266583295 Jul 10 05:09:47 PM PDT 24 Jul 10 05:09:56 PM PDT 24 45245978 ps
T589 /workspace/coverage/cover_reg_top/46.hmac_intr_test.2385827441 Jul 10 05:09:51 PM PDT 24 Jul 10 05:10:00 PM PDT 24 48376715 ps
T590 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1308764080 Jul 10 05:09:45 PM PDT 24 Jul 10 05:09:54 PM PDT 24 47780207 ps
T591 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3527624420 Jul 10 05:09:44 PM PDT 24 Jul 10 05:09:50 PM PDT 24 22906416 ps
T592 /workspace/coverage/cover_reg_top/41.hmac_intr_test.281374516 Jul 10 05:10:07 PM PDT 24 Jul 10 05:10:13 PM PDT 24 15931127 ps
T593 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.4242161027 Jul 10 05:09:44 PM PDT 24 Jul 10 05:09:51 PM PDT 24 333707407 ps
T594 /workspace/coverage/cover_reg_top/48.hmac_intr_test.262572094 Jul 10 05:09:54 PM PDT 24 Jul 10 05:10:02 PM PDT 24 49549653 ps
T595 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2491701049 Jul 10 05:09:36 PM PDT 24 Jul 10 05:09:43 PM PDT 24 132852500 ps
T596 /workspace/coverage/cover_reg_top/44.hmac_intr_test.1459372247 Jul 10 05:09:51 PM PDT 24 Jul 10 05:10:00 PM PDT 24 17027376 ps
T597 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.381460499 Jul 10 05:09:33 PM PDT 24 Jul 10 05:09:38 PM PDT 24 190945786 ps
T598 /workspace/coverage/cover_reg_top/10.hmac_intr_test.85702171 Jul 10 05:09:44 PM PDT 24 Jul 10 05:09:51 PM PDT 24 51432954 ps
T599 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2855979635 Jul 10 05:09:23 PM PDT 24 Jul 10 05:09:27 PM PDT 24 155779026 ps
T600 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2032312479 Jul 10 05:09:40 PM PDT 24 Jul 10 05:09:48 PM PDT 24 397807150 ps
T601 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.322036612 Jul 10 05:09:49 PM PDT 24 Jul 10 05:10:01 PM PDT 24 141162923 ps
T602 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1720777741 Jul 10 05:09:50 PM PDT 24 Jul 10 05:09:59 PM PDT 24 38366310 ps
T603 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3546085695 Jul 10 05:09:31 PM PDT 24 Jul 10 05:09:37 PM PDT 24 121965560 ps
T101 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.4228404557 Jul 10 05:09:41 PM PDT 24 Jul 10 05:09:50 PM PDT 24 154190296 ps
T604 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3974528588 Jul 10 05:10:11 PM PDT 24 Jul 10 05:10:16 PM PDT 24 36996249 ps
T108 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4121055719 Jul 10 05:09:49 PM PDT 24 Jul 10 05:10:00 PM PDT 24 352499947 ps
T605 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2477020811 Jul 10 05:09:45 PM PDT 24 Jul 10 05:09:56 PM PDT 24 796898983 ps
T606 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.904722367 Jul 10 05:09:31 PM PDT 24 Jul 10 05:09:38 PM PDT 24 679830626 ps
T607 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2959264926 Jul 10 05:09:30 PM PDT 24 Jul 10 05:09:34 PM PDT 24 76806617 ps
T608 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4072267800 Jul 10 05:09:49 PM PDT 24 Jul 10 05:10:00 PM PDT 24 403392331 ps
T609 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3062366575 Jul 10 05:09:33 PM PDT 24 Jul 10 05:09:39 PM PDT 24 22653159 ps
T610 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1542145961 Jul 10 05:09:45 PM PDT 24 Jul 10 05:09:54 PM PDT 24 33538745 ps
T611 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3149255938 Jul 10 05:09:45 PM PDT 24 Jul 10 05:09:53 PM PDT 24 23007143 ps
T612 /workspace/coverage/cover_reg_top/16.hmac_intr_test.553315389 Jul 10 05:09:48 PM PDT 24 Jul 10 05:09:56 PM PDT 24 33276152 ps
T613 /workspace/coverage/cover_reg_top/29.hmac_intr_test.880063697 Jul 10 05:09:54 PM PDT 24 Jul 10 05:10:03 PM PDT 24 15899816 ps
T614 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1296087656 Jul 10 05:09:32 PM PDT 24 Jul 10 05:09:47 PM PDT 24 1445966792 ps
T615 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1789968319 Jul 10 05:09:46 PM PDT 24 Jul 10 05:09:56 PM PDT 24 325523734 ps
T616 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3239945474 Jul 10 05:09:50 PM PDT 24 Jul 10 05:09:59 PM PDT 24 98623681 ps
T617 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.246362492 Jul 10 05:09:46 PM PDT 24 Jul 10 05:09:55 PM PDT 24 70230240 ps
T618 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2173708065 Jul 10 05:09:51 PM PDT 24 Jul 10 05:10:00 PM PDT 24 20452009 ps
T619 /workspace/coverage/cover_reg_top/20.hmac_intr_test.580002692 Jul 10 05:09:55 PM PDT 24 Jul 10 05:10:04 PM PDT 24 15303272 ps
T103 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.634668931 Jul 10 05:09:44 PM PDT 24 Jul 10 05:09:53 PM PDT 24 56638231 ps
T620 /workspace/coverage/cover_reg_top/18.hmac_intr_test.3204761141 Jul 10 05:09:47 PM PDT 24 Jul 10 05:09:55 PM PDT 24 12805710 ps
T621 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2334161292 Jul 10 05:09:44 PM PDT 24 Jul 10 05:09:51 PM PDT 24 52054165 ps
T622 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2934586243 Jul 10 05:09:29 PM PDT 24 Jul 10 05:09:34 PM PDT 24 170175503 ps
T623 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.4281606234 Jul 10 05:09:30 PM PDT 24 Jul 10 05:09:37 PM PDT 24 3100378510 ps
T624 /workspace/coverage/cover_reg_top/11.hmac_intr_test.3551553221 Jul 10 05:09:46 PM PDT 24 Jul 10 05:09:54 PM PDT 24 55657177 ps
T625 /workspace/coverage/cover_reg_top/14.hmac_intr_test.503940198 Jul 10 05:09:44 PM PDT 24 Jul 10 05:09:51 PM PDT 24 51024495 ps
T626 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3323293468 Jul 10 05:09:49 PM PDT 24 Jul 10 05:09:59 PM PDT 24 38760173 ps
T627 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1474386747 Jul 10 05:09:29 PM PDT 24 Jul 10 05:09:32 PM PDT 24 33636798 ps
T628 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.996148055 Jul 10 05:09:45 PM PDT 24 Jul 10 05:09:53 PM PDT 24 16136902 ps
T629 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3174262083 Jul 10 05:09:45 PM PDT 24 Jul 10 05:09:54 PM PDT 24 85430682 ps
T630 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.172523336 Jul 10 05:09:42 PM PDT 24 Jul 10 05:09:52 PM PDT 24 95664566 ps
T631 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2654449148 Jul 10 05:09:33 PM PDT 24 Jul 10 05:09:39 PM PDT 24 36558151 ps
T632 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3597229056 Jul 10 05:09:36 PM PDT 24 Jul 10 05:09:43 PM PDT 24 32967782 ps
T109 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1616764460 Jul 10 05:09:37 PM PDT 24 Jul 10 05:09:45 PM PDT 24 375364041 ps
T633 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.866357191 Jul 10 05:09:30 PM PDT 24 Jul 10 05:09:34 PM PDT 24 20409906 ps
T634 /workspace/coverage/cover_reg_top/32.hmac_intr_test.368258908 Jul 10 05:09:48 PM PDT 24 Jul 10 05:09:57 PM PDT 24 14373449 ps
T635 /workspace/coverage/cover_reg_top/39.hmac_intr_test.1181087934 Jul 10 05:09:50 PM PDT 24 Jul 10 05:09:59 PM PDT 24 18825554 ps
T636 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2357392967 Jul 10 05:09:49 PM PDT 24 Jul 10 05:09:57 PM PDT 24 35299573 ps
T637 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.976783045 Jul 10 05:09:45 PM PDT 24 Jul 10 05:09:53 PM PDT 24 50867877 ps
T638 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.991996144 Jul 10 05:09:34 PM PDT 24 Jul 10 05:09:41 PM PDT 24 36218958 ps
T639 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3919054308 Jul 10 05:09:31 PM PDT 24 Jul 10 05:09:42 PM PDT 24 106320092 ps
T640 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3032350310 Jul 10 05:09:40 PM PDT 24 Jul 10 05:09:47 PM PDT 24 62160663 ps
T641 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.804128323 Jul 10 05:09:47 PM PDT 24 Jul 10 05:09:57 PM PDT 24 196305495 ps
T642 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.812204872 Jul 10 05:09:45 PM PDT 24 Jul 10 05:09:54 PM PDT 24 52380161 ps
T643 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1758559747 Jul 10 05:09:39 PM PDT 24 Jul 10 05:09:45 PM PDT 24 54678133 ps
T644 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3544816166 Jul 10 05:09:28 PM PDT 24 Jul 10 05:09:32 PM PDT 24 50326196 ps
T645 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3355768929 Jul 10 05:09:50 PM PDT 24 Jul 10 05:09:59 PM PDT 24 43903973 ps
T646 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3491557049 Jul 10 05:09:52 PM PDT 24 Jul 10 05:10:00 PM PDT 24 13375568 ps
T647 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2526296600 Jul 10 05:09:33 PM PDT 24 Jul 10 05:09:39 PM PDT 24 21973660 ps
T648 /workspace/coverage/cover_reg_top/42.hmac_intr_test.4195902676 Jul 10 05:10:11 PM PDT 24 Jul 10 05:10:16 PM PDT 24 60902876 ps
T649 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3812259091 Jul 10 05:09:39 PM PDT 24 Jul 10 05:09:47 PM PDT 24 357612407 ps
T650 /workspace/coverage/cover_reg_top/27.hmac_intr_test.989635242 Jul 10 05:09:54 PM PDT 24 Jul 10 05:10:03 PM PDT 24 35648327 ps
T651 /workspace/coverage/cover_reg_top/49.hmac_intr_test.3129979051 Jul 10 05:09:52 PM PDT 24 Jul 10 05:10:00 PM PDT 24 14061604 ps
T652 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.855457416 Jul 10 05:09:45 PM PDT 24 Jul 10 05:09:55 PM PDT 24 49684136 ps
T653 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3565853143 Jul 10 05:09:38 PM PDT 24 Jul 10 05:09:46 PM PDT 24 243064596 ps
T654 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3250931601 Jul 10 05:09:39 PM PDT 24 Jul 10 05:09:46 PM PDT 24 399809396 ps
T655 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4092347606 Jul 10 05:09:44 PM PDT 24 Jul 10 05:09:53 PM PDT 24 213085902 ps
T656 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3040217739 Jul 10 05:09:33 PM PDT 24 Jul 10 05:09:39 PM PDT 24 157642105 ps
T657 /workspace/coverage/cover_reg_top/35.hmac_intr_test.511825484 Jul 10 05:09:51 PM PDT 24 Jul 10 05:10:00 PM PDT 24 24547351 ps

Test location /workspace/coverage/default/38.hmac_stress_all.3404385428
Short name T5
Test name
Test status
Simulation time 81076756124 ps
CPU time 2519.39 seconds
Started Jul 10 05:11:27 PM PDT 24
Finished Jul 10 05:53:27 PM PDT 24
Peak memory 787080 kb
Host smart-2de32124-a538-4cf2-ac92-50eb86439369
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404385428 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.3404385428
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.87368453
Short name T10
Test name
Test status
Simulation time 414541121064 ps
CPU time 7058.24 seconds
Started Jul 10 05:10:11 PM PDT 24
Finished Jul 10 07:07:55 PM PDT 24
Peak memory 845268 kb
Host smart-c0fab3d0-2b12-433d-ae87-b688421ab5ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=87368453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.87368453
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3043709205
Short name T19
Test name
Test status
Simulation time 63613640076 ps
CPU time 1085.5 seconds
Started Jul 10 05:10:22 PM PDT 24
Finished Jul 10 05:28:32 PM PDT 24
Peak memory 640584 kb
Host smart-ee60ab3f-c192-40f9-95e6-82a14003d1ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043709205 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3043709205
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1472501998
Short name T104
Test name
Test status
Simulation time 168007607 ps
CPU time 3.06 seconds
Started Jul 10 05:09:46 PM PDT 24
Finished Jul 10 05:09:56 PM PDT 24
Peak memory 200296 kb
Host smart-88d37b98-cbc8-4012-849a-81d0c932429c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472501998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1472501998
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.4054299390
Short name T22
Test name
Test status
Simulation time 131884739472 ps
CPU time 4159.43 seconds
Started Jul 10 05:10:15 PM PDT 24
Finished Jul 10 06:19:41 PM PDT 24
Peak memory 836120 kb
Host smart-ecbf8b23-82d5-4e8b-84aa-06bcebc35be2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4054299390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.4054299390
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.806504647
Short name T42
Test name
Test status
Simulation time 74437336 ps
CPU time 0.89 seconds
Started Jul 10 05:09:59 PM PDT 24
Finished Jul 10 05:10:07 PM PDT 24
Peak memory 218132 kb
Host smart-a3f3cef1-8e38-4b76-b395-1023eac5f511
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806504647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.806504647
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1921065832
Short name T13
Test name
Test status
Simulation time 52855865650 ps
CPU time 3530.67 seconds
Started Jul 10 05:10:40 PM PDT 24
Finished Jul 10 06:09:32 PM PDT 24
Peak memory 813828 kb
Host smart-75d4fbcd-ac6d-495c-906c-b00c6380f7e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921065832 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1921065832
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.220759357
Short name T86
Test name
Test status
Simulation time 43093291 ps
CPU time 0.68 seconds
Started Jul 10 05:09:40 PM PDT 24
Finished Jul 10 05:09:46 PM PDT 24
Peak memory 198068 kb
Host smart-cd9e60d3-a695-4a5c-852f-8ec769e254b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220759357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.220759357
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2794420887
Short name T169
Test name
Test status
Simulation time 11840183 ps
CPU time 0.59 seconds
Started Jul 10 05:09:56 PM PDT 24
Finished Jul 10 05:10:04 PM PDT 24
Peak memory 196860 kb
Host smart-8187c9a2-4524-4ba5-94c6-9c91ee9368eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794420887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2794420887
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.2941470406
Short name T11
Test name
Test status
Simulation time 66848028617 ps
CPU time 1319.85 seconds
Started Jul 10 05:10:02 PM PDT 24
Finished Jul 10 05:32:07 PM PDT 24
Peak memory 659444 kb
Host smart-205dd755-5a20-4f8e-b7e5-ebce37ed5a5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2941470406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.2941470406
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2220281012
Short name T53
Test name
Test status
Simulation time 609263274 ps
CPU time 4.51 seconds
Started Jul 10 05:09:47 PM PDT 24
Finished Jul 10 05:09:59 PM PDT 24
Peak memory 200228 kb
Host smart-6e3c3ff3-e416-47b4-87c2-9c6ad9fef4c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220281012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2220281012
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.634668931
Short name T103
Test name
Test status
Simulation time 56638231 ps
CPU time 1.81 seconds
Started Jul 10 05:09:44 PM PDT 24
Finished Jul 10 05:09:53 PM PDT 24
Peak memory 200172 kb
Host smart-d18b779d-7cad-46df-aa54-e4034649dde7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634668931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.634668931
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2853484922
Short name T52
Test name
Test status
Simulation time 772695689 ps
CPU time 2.04 seconds
Started Jul 10 05:09:45 PM PDT 24
Finished Jul 10 05:09:54 PM PDT 24
Peak memory 200280 kb
Host smart-3f2647e8-7b74-48c1-82df-8ae62c822278
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853484922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2853484922
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.4121055719
Short name T108
Test name
Test status
Simulation time 352499947 ps
CPU time 1.81 seconds
Started Jul 10 05:09:49 PM PDT 24
Finished Jul 10 05:10:00 PM PDT 24
Peak memory 200248 kb
Host smart-568b40d8-ce01-4870-a954-fe082cc92c53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121055719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.4121055719
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_stress_all.501826952
Short name T60
Test name
Test status
Simulation time 301984044556 ps
CPU time 1836.79 seconds
Started Jul 10 05:09:59 PM PDT 24
Finished Jul 10 05:40:42 PM PDT 24
Peak memory 758648 kb
Host smart-2078a476-21da-4bee-bcb5-60166a4d6644
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501826952 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.501826952
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.2979796289
Short name T56
Test name
Test status
Simulation time 129307513642 ps
CPU time 4322.84 seconds
Started Jul 10 05:09:59 PM PDT 24
Finished Jul 10 06:22:09 PM PDT 24
Peak memory 767668 kb
Host smart-7dd89dd3-d6fd-4f7d-9b1b-d9e8b7c5f69e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979796289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.2979796289
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2633796399
Short name T85
Test name
Test status
Simulation time 158790365 ps
CPU time 8.46 seconds
Started Jul 10 05:09:33 PM PDT 24
Finished Jul 10 05:09:46 PM PDT 24
Peak memory 200200 kb
Host smart-9587c5b6-ea37-443e-8a0f-b27f4fdb59e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633796399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2633796399
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3119252069
Short name T89
Test name
Test status
Simulation time 113683578 ps
CPU time 5.32 seconds
Started Jul 10 05:09:34 PM PDT 24
Finished Jul 10 05:09:44 PM PDT 24
Peak memory 200256 kb
Host smart-41b25d80-bbcc-481b-aecd-149ab932eeca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119252069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3119252069
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1233399478
Short name T558
Test name
Test status
Simulation time 37048387 ps
CPU time 1.01 seconds
Started Jul 10 05:09:29 PM PDT 24
Finished Jul 10 05:09:33 PM PDT 24
Peak memory 199868 kb
Host smart-3d455b2a-3162-404c-8cbb-b18bb12e683c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233399478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1233399478
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1107351310
Short name T571
Test name
Test status
Simulation time 301181116 ps
CPU time 1.75 seconds
Started Jul 10 05:09:33 PM PDT 24
Finished Jul 10 05:09:40 PM PDT 24
Peak memory 200092 kb
Host smart-b5bf8ae6-7763-40c7-8e60-2bba949dfc9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107351310 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1107351310
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.133384518
Short name T87
Test name
Test status
Simulation time 156518998 ps
CPU time 0.7 seconds
Started Jul 10 05:09:35 PM PDT 24
Finished Jul 10 05:09:40 PM PDT 24
Peak memory 198400 kb
Host smart-c6c3bb14-e08d-4164-b660-2e6934daced8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133384518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.133384518
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2526296600
Short name T647
Test name
Test status
Simulation time 21973660 ps
CPU time 0.61 seconds
Started Jul 10 05:09:33 PM PDT 24
Finished Jul 10 05:09:39 PM PDT 24
Peak memory 195140 kb
Host smart-2fcaf16a-8810-4ad6-80ad-c1fc390e0093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526296600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2526296600
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.4119766325
Short name T568
Test name
Test status
Simulation time 235909767 ps
CPU time 2.42 seconds
Started Jul 10 05:09:32 PM PDT 24
Finished Jul 10 05:09:39 PM PDT 24
Peak memory 200168 kb
Host smart-24b6d7e8-054a-4dc6-afbf-897a2df83313
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119766325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.4119766325
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.954080995
Short name T536
Test name
Test status
Simulation time 85960086 ps
CPU time 1.81 seconds
Started Jul 10 05:09:30 PM PDT 24
Finished Jul 10 05:09:36 PM PDT 24
Peak memory 200320 kb
Host smart-73452b69-bb5a-41bb-a7a8-88fb82fb1b71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954080995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.954080995
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2855979635
Short name T599
Test name
Test status
Simulation time 155779026 ps
CPU time 1.72 seconds
Started Jul 10 05:09:23 PM PDT 24
Finished Jul 10 05:09:27 PM PDT 24
Peak memory 200288 kb
Host smart-0b391295-836b-47dd-8872-e763beb0f562
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855979635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2855979635
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.1582768430
Short name T83
Test name
Test status
Simulation time 461660229 ps
CPU time 8.84 seconds
Started Jul 10 05:09:30 PM PDT 24
Finished Jul 10 05:09:42 PM PDT 24
Peak memory 200204 kb
Host smart-616e3911-2c7b-4c27-bda2-1c0c6d61694d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582768430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.1582768430
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1980397710
Short name T574
Test name
Test status
Simulation time 432064648 ps
CPU time 5.35 seconds
Started Jul 10 05:09:31 PM PDT 24
Finished Jul 10 05:09:41 PM PDT 24
Peak memory 200160 kb
Host smart-6daed4c6-cd36-4178-a7b8-43387915cbcd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980397710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1980397710
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.866357191
Short name T633
Test name
Test status
Simulation time 20409906 ps
CPU time 0.74 seconds
Started Jul 10 05:09:30 PM PDT 24
Finished Jul 10 05:09:34 PM PDT 24
Peak memory 198000 kb
Host smart-4581d874-3c27-4be8-86da-83c3dce26cba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866357191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.866357191
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.991996144
Short name T638
Test name
Test status
Simulation time 36218958 ps
CPU time 2.38 seconds
Started Jul 10 05:09:34 PM PDT 24
Finished Jul 10 05:09:41 PM PDT 24
Peak memory 208504 kb
Host smart-c49fca57-60d6-437e-ae4a-5dd696109310
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991996144 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.991996144
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3062366575
Short name T609
Test name
Test status
Simulation time 22653159 ps
CPU time 0.83 seconds
Started Jul 10 05:09:33 PM PDT 24
Finished Jul 10 05:09:39 PM PDT 24
Peak memory 199800 kb
Host smart-9c0b5042-9fa2-4833-9247-55a8d513f8db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062366575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3062366575
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.218018543
Short name T530
Test name
Test status
Simulation time 30096910 ps
CPU time 0.61 seconds
Started Jul 10 05:09:29 PM PDT 24
Finished Jul 10 05:09:33 PM PDT 24
Peak memory 195188 kb
Host smart-81908e1e-bfbb-421a-be72-e7dbf57bc95f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218018543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.218018543
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2831711731
Short name T92
Test name
Test status
Simulation time 37400489 ps
CPU time 1.72 seconds
Started Jul 10 05:09:35 PM PDT 24
Finished Jul 10 05:09:42 PM PDT 24
Peak memory 200240 kb
Host smart-c1b9312a-0623-4ebd-9c5a-7f74b5b450ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831711731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2831711731
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.64862508
Short name T537
Test name
Test status
Simulation time 82790198 ps
CPU time 1.99 seconds
Started Jul 10 05:09:31 PM PDT 24
Finished Jul 10 05:09:38 PM PDT 24
Peak memory 200172 kb
Host smart-3c026dc5-362e-4965-893a-41ed82169ae6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64862508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.64862508
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.904722367
Short name T606
Test name
Test status
Simulation time 679830626 ps
CPU time 3.08 seconds
Started Jul 10 05:09:31 PM PDT 24
Finished Jul 10 05:09:38 PM PDT 24
Peak memory 200168 kb
Host smart-b44f90ed-add9-4ddd-8257-553aa5992054
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904722367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.904722367
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.909004245
Short name T552
Test name
Test status
Simulation time 91113564 ps
CPU time 2.26 seconds
Started Jul 10 05:09:44 PM PDT 24
Finished Jul 10 05:09:54 PM PDT 24
Peak memory 200316 kb
Host smart-9b1bffca-52a3-438d-a0ec-3daf7b43e662
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909004245 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.909004245
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.85702171
Short name T598
Test name
Test status
Simulation time 51432954 ps
CPU time 0.6 seconds
Started Jul 10 05:09:44 PM PDT 24
Finished Jul 10 05:09:51 PM PDT 24
Peak memory 195108 kb
Host smart-1ac21d77-63a4-4bce-8f0c-d283fec87ba4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85702171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.85702171
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.43980027
Short name T96
Test name
Test status
Simulation time 316282522 ps
CPU time 2.51 seconds
Started Jul 10 05:09:45 PM PDT 24
Finished Jul 10 05:09:54 PM PDT 24
Peak memory 200180 kb
Host smart-1b541cfa-1181-4796-82fc-40d74ba14226
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43980027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr_
outstanding.43980027
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3812259091
Short name T649
Test name
Test status
Simulation time 357612407 ps
CPU time 3.28 seconds
Started Jul 10 05:09:39 PM PDT 24
Finished Jul 10 05:09:47 PM PDT 24
Peak memory 200192 kb
Host smart-53c55643-c01c-4144-8c35-cc4a34e662a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812259091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3812259091
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2024008263
Short name T100
Test name
Test status
Simulation time 446706669 ps
CPU time 4.18 seconds
Started Jul 10 05:09:38 PM PDT 24
Finished Jul 10 05:09:48 PM PDT 24
Peak memory 200172 kb
Host smart-783ebbf3-5c2c-4783-950e-7606c5b9b702
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024008263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2024008263
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.936042106
Short name T556
Test name
Test status
Simulation time 170503457 ps
CPU time 1.25 seconds
Started Jul 10 05:09:52 PM PDT 24
Finished Jul 10 05:10:01 PM PDT 24
Peak memory 200232 kb
Host smart-10b3af37-5d29-4958-8cd7-27610531e8e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936042106 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.936042106
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.996148055
Short name T628
Test name
Test status
Simulation time 16136902 ps
CPU time 0.81 seconds
Started Jul 10 05:09:45 PM PDT 24
Finished Jul 10 05:09:53 PM PDT 24
Peak memory 199596 kb
Host smart-40a18e33-fbbd-49e6-9429-f29fe814d871
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996148055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.996148055
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.3551553221
Short name T624
Test name
Test status
Simulation time 55657177 ps
CPU time 0.63 seconds
Started Jul 10 05:09:46 PM PDT 24
Finished Jul 10 05:09:54 PM PDT 24
Peak memory 195184 kb
Host smart-9e2842e7-f873-4ea8-a305-6dee7ae37e06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551553221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3551553221
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1542145961
Short name T610
Test name
Test status
Simulation time 33538745 ps
CPU time 1.61 seconds
Started Jul 10 05:09:45 PM PDT 24
Finished Jul 10 05:09:54 PM PDT 24
Peak memory 200268 kb
Host smart-4b4296d7-c910-4203-b045-b469184c16de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542145961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.1542145961
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1624964907
Short name T561
Test name
Test status
Simulation time 787746275 ps
CPU time 3.78 seconds
Started Jul 10 05:09:45 PM PDT 24
Finished Jul 10 05:09:56 PM PDT 24
Peak memory 200316 kb
Host smart-b2bfe2dc-7cc2-4ccd-a05f-aa074a87bf5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624964907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1624964907
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.976783045
Short name T637
Test name
Test status
Simulation time 50867877 ps
CPU time 1.75 seconds
Started Jul 10 05:09:45 PM PDT 24
Finished Jul 10 05:09:53 PM PDT 24
Peak memory 200276 kb
Host smart-a2378291-af52-4e65-a66d-eb9a00cbe481
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976783045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.976783045
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1398843841
Short name T586
Test name
Test status
Simulation time 236857939 ps
CPU time 1.87 seconds
Started Jul 10 05:09:47 PM PDT 24
Finished Jul 10 05:09:57 PM PDT 24
Peak memory 200308 kb
Host smart-396b51a4-e29f-4e58-8d59-a1dba50d6127
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398843841 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1398843841
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2993822238
Short name T544
Test name
Test status
Simulation time 32390617 ps
CPU time 0.99 seconds
Started Jul 10 05:09:44 PM PDT 24
Finished Jul 10 05:09:52 PM PDT 24
Peak memory 200100 kb
Host smart-9b1c3e4b-a34f-450d-b05b-9fc7fd2897db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993822238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2993822238
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2065862526
Short name T548
Test name
Test status
Simulation time 25780770 ps
CPU time 0.57 seconds
Started Jul 10 05:09:43 PM PDT 24
Finished Jul 10 05:09:50 PM PDT 24
Peak memory 195120 kb
Host smart-9db4e656-f6f7-473e-b59b-106ac7db4dd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065862526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2065862526
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1789968319
Short name T615
Test name
Test status
Simulation time 325523734 ps
CPU time 2.22 seconds
Started Jul 10 05:09:46 PM PDT 24
Finished Jul 10 05:09:56 PM PDT 24
Peak memory 200164 kb
Host smart-bdf3688f-e0d3-4ef2-9067-17d264524f30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789968319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1789968319
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.823245170
Short name T527
Test name
Test status
Simulation time 72504104 ps
CPU time 3.54 seconds
Started Jul 10 05:09:47 PM PDT 24
Finished Jul 10 05:09:59 PM PDT 24
Peak memory 200296 kb
Host smart-cca13e4d-98f8-4006-bec4-d69af9f4d2aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823245170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.823245170
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3342426385
Short name T106
Test name
Test status
Simulation time 256337919 ps
CPU time 4.32 seconds
Started Jul 10 05:09:48 PM PDT 24
Finished Jul 10 05:10:00 PM PDT 24
Peak memory 200320 kb
Host smart-27a77749-c9c4-48f3-9370-4549a4f57553
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342426385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3342426385
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.413606721
Short name T566
Test name
Test status
Simulation time 87166845 ps
CPU time 2.45 seconds
Started Jul 10 05:09:46 PM PDT 24
Finished Jul 10 05:09:56 PM PDT 24
Peak memory 200356 kb
Host smart-a2fd92ec-d7b0-4f8c-86f6-6d88b8a0bb8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413606721 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.413606721
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2334161292
Short name T621
Test name
Test status
Simulation time 52054165 ps
CPU time 0.99 seconds
Started Jul 10 05:09:44 PM PDT 24
Finished Jul 10 05:09:51 PM PDT 24
Peak memory 200076 kb
Host smart-98c9117d-9746-4c47-ac9e-0be2eb884d59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334161292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2334161292
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3938477239
Short name T570
Test name
Test status
Simulation time 26582893 ps
CPU time 0.62 seconds
Started Jul 10 05:09:44 PM PDT 24
Finished Jul 10 05:09:52 PM PDT 24
Peak memory 195304 kb
Host smart-d3d861f1-1e96-481b-b2c9-d5e8a3777faa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938477239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3938477239
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1308764080
Short name T590
Test name
Test status
Simulation time 47780207 ps
CPU time 2.25 seconds
Started Jul 10 05:09:45 PM PDT 24
Finished Jul 10 05:09:54 PM PDT 24
Peak memory 200168 kb
Host smart-abf4cabd-559b-42d8-b922-a7c94d4da6f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308764080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1308764080
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2903198952
Short name T543
Test name
Test status
Simulation time 330551171 ps
CPU time 4.22 seconds
Started Jul 10 05:09:46 PM PDT 24
Finished Jul 10 05:09:58 PM PDT 24
Peak memory 200172 kb
Host smart-61af9f32-189e-4642-b938-67aa04ff947d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903198952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2903198952
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.855457416
Short name T652
Test name
Test status
Simulation time 49684136 ps
CPU time 2.96 seconds
Started Jul 10 05:09:45 PM PDT 24
Finished Jul 10 05:09:55 PM PDT 24
Peak memory 208404 kb
Host smart-be081faf-b6ac-4a95-a283-1dc796f25471
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855457416 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.855457416
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1591396529
Short name T553
Test name
Test status
Simulation time 60931294 ps
CPU time 0.72 seconds
Started Jul 10 05:09:46 PM PDT 24
Finished Jul 10 05:09:55 PM PDT 24
Peak memory 198440 kb
Host smart-e153c44f-ac7f-48ce-ad33-e904476ba570
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591396529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1591396529
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.503940198
Short name T625
Test name
Test status
Simulation time 51024495 ps
CPU time 0.61 seconds
Started Jul 10 05:09:44 PM PDT 24
Finished Jul 10 05:09:51 PM PDT 24
Peak memory 195040 kb
Host smart-0e7d748b-1462-4ed1-95f1-a6eee6e1cf07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503940198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.503940198
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3149255938
Short name T611
Test name
Test status
Simulation time 23007143 ps
CPU time 1.08 seconds
Started Jul 10 05:09:45 PM PDT 24
Finished Jul 10 05:09:53 PM PDT 24
Peak memory 200204 kb
Host smart-fd04c29a-d21a-4d07-ae88-52390e961cf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149255938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3149255938
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3536280914
Short name T58
Test name
Test status
Simulation time 61352774 ps
CPU time 3.29 seconds
Started Jul 10 05:09:45 PM PDT 24
Finished Jul 10 05:09:56 PM PDT 24
Peak memory 200212 kb
Host smart-f151877b-2839-4b88-ab08-9f9d2882d755
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536280914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3536280914
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.172523336
Short name T630
Test name
Test status
Simulation time 95664566 ps
CPU time 3.36 seconds
Started Jul 10 05:09:42 PM PDT 24
Finished Jul 10 05:09:52 PM PDT 24
Peak memory 200216 kb
Host smart-398f04ba-17e5-45fa-b485-45ff8e1818ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172523336 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.172523336
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2656729865
Short name T82
Test name
Test status
Simulation time 16504555 ps
CPU time 0.92 seconds
Started Jul 10 05:09:45 PM PDT 24
Finished Jul 10 05:09:53 PM PDT 24
Peak memory 200100 kb
Host smart-7d31563f-5f91-4049-bda2-3a2e8995e6cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656729865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2656729865
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3527624420
Short name T591
Test name
Test status
Simulation time 22906416 ps
CPU time 0.59 seconds
Started Jul 10 05:09:44 PM PDT 24
Finished Jul 10 05:09:50 PM PDT 24
Peak memory 195108 kb
Host smart-69073a7a-6fb2-44fb-9550-de766368cd08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527624420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3527624420
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.118199120
Short name T93
Test name
Test status
Simulation time 275071575 ps
CPU time 2.43 seconds
Started Jul 10 05:09:45 PM PDT 24
Finished Jul 10 05:09:55 PM PDT 24
Peak memory 200264 kb
Host smart-0aebf7ea-6394-4ec5-8bf2-235ff8f41f1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118199120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.118199120
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2477020811
Short name T605
Test name
Test status
Simulation time 796898983 ps
CPU time 3.64 seconds
Started Jul 10 05:09:45 PM PDT 24
Finished Jul 10 05:09:56 PM PDT 24
Peak memory 200232 kb
Host smart-71977dc1-d2b5-4aa0-8185-fdd7dca45a7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477020811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2477020811
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.4072267800
Short name T608
Test name
Test status
Simulation time 403392331 ps
CPU time 2.84 seconds
Started Jul 10 05:09:49 PM PDT 24
Finished Jul 10 05:10:00 PM PDT 24
Peak memory 200268 kb
Host smart-80d64c3b-92f5-4d9c-91b8-e893a2e07488
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072267800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.4072267800
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3266583295
Short name T588
Test name
Test status
Simulation time 45245978 ps
CPU time 1.24 seconds
Started Jul 10 05:09:47 PM PDT 24
Finished Jul 10 05:09:56 PM PDT 24
Peak memory 199992 kb
Host smart-4efcb183-38bc-4082-a821-338b7caef2fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266583295 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3266583295
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1045759214
Short name T578
Test name
Test status
Simulation time 14730237 ps
CPU time 0.81 seconds
Started Jul 10 05:09:46 PM PDT 24
Finished Jul 10 05:09:55 PM PDT 24
Peak memory 199404 kb
Host smart-18e47a10-e849-46f6-8e01-3b152c1b0fbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045759214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1045759214
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.553315389
Short name T612
Test name
Test status
Simulation time 33276152 ps
CPU time 0.6 seconds
Started Jul 10 05:09:48 PM PDT 24
Finished Jul 10 05:09:56 PM PDT 24
Peak memory 195188 kb
Host smart-efc9325d-6f02-49f7-b7e4-091001c58056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553315389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.553315389
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2643674267
Short name T585
Test name
Test status
Simulation time 47181605 ps
CPU time 2.14 seconds
Started Jul 10 05:09:48 PM PDT 24
Finished Jul 10 05:09:58 PM PDT 24
Peak memory 200296 kb
Host smart-7fd2314d-5857-4cf3-876c-873c62660d64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643674267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.2643674267
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.246362492
Short name T617
Test name
Test status
Simulation time 70230240 ps
CPU time 1.52 seconds
Started Jul 10 05:09:46 PM PDT 24
Finished Jul 10 05:09:55 PM PDT 24
Peak memory 200324 kb
Host smart-3337c1f9-5a44-45da-9b06-9f83a67dd9ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246362492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.246362492
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2736927636
Short name T563
Test name
Test status
Simulation time 66711418 ps
CPU time 1.65 seconds
Started Jul 10 05:09:45 PM PDT 24
Finished Jul 10 05:09:54 PM PDT 24
Peak memory 200176 kb
Host smart-b52fc4ff-8a08-43e1-afbd-a5fb299d228e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736927636 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2736927636
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.812204872
Short name T642
Test name
Test status
Simulation time 52380161 ps
CPU time 0.72 seconds
Started Jul 10 05:09:45 PM PDT 24
Finished Jul 10 05:09:54 PM PDT 24
Peak memory 198044 kb
Host smart-7702e63f-5139-4823-88d5-a658795d42fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812204872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.812204872
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3224874455
Short name T545
Test name
Test status
Simulation time 14966502 ps
CPU time 0.63 seconds
Started Jul 10 05:09:49 PM PDT 24
Finished Jul 10 05:09:58 PM PDT 24
Peak memory 195320 kb
Host smart-587b99ac-83f0-4c48-b028-a3d3462e8373
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224874455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3224874455
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1814963350
Short name T94
Test name
Test status
Simulation time 198035659 ps
CPU time 2.22 seconds
Started Jul 10 05:09:43 PM PDT 24
Finished Jul 10 05:09:51 PM PDT 24
Peak memory 200172 kb
Host smart-db256681-8272-4f4b-afbd-56e7d6dae8cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814963350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1814963350
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1289943492
Short name T580
Test name
Test status
Simulation time 1005016877 ps
CPU time 4.78 seconds
Started Jul 10 05:09:44 PM PDT 24
Finished Jul 10 05:09:54 PM PDT 24
Peak memory 200236 kb
Host smart-68384a77-5946-4509-8fe0-acd6766e3ca3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289943492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1289943492
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.804128323
Short name T641
Test name
Test status
Simulation time 196305495 ps
CPU time 1.75 seconds
Started Jul 10 05:09:47 PM PDT 24
Finished Jul 10 05:09:57 PM PDT 24
Peak memory 200164 kb
Host smart-29ce34c7-b02d-4f6d-9f32-54af254968ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804128323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.804128323
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.4276046280
Short name T575
Test name
Test status
Simulation time 117599657956 ps
CPU time 897.25 seconds
Started Jul 10 05:09:46 PM PDT 24
Finished Jul 10 05:24:51 PM PDT 24
Peak memory 216680 kb
Host smart-cbdd0b80-275c-469b-81db-9147d8217aa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276046280 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.4276046280
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1082630978
Short name T576
Test name
Test status
Simulation time 29125425 ps
CPU time 0.71 seconds
Started Jul 10 05:09:46 PM PDT 24
Finished Jul 10 05:09:54 PM PDT 24
Peak memory 198160 kb
Host smart-a405043a-0a6f-4618-9ae3-8164ac381449
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082630978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1082630978
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.3204761141
Short name T620
Test name
Test status
Simulation time 12805710 ps
CPU time 0.6 seconds
Started Jul 10 05:09:47 PM PDT 24
Finished Jul 10 05:09:55 PM PDT 24
Peak memory 195100 kb
Host smart-daae20e6-a282-4698-9971-d4bf024a45b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204761141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.3204761141
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3011965557
Short name T559
Test name
Test status
Simulation time 198010517 ps
CPU time 1.77 seconds
Started Jul 10 05:09:44 PM PDT 24
Finished Jul 10 05:09:53 PM PDT 24
Peak memory 200088 kb
Host smart-a88d8df3-3a26-4769-927b-8c2e800c121e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011965557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3011965557
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.322036612
Short name T601
Test name
Test status
Simulation time 141162923 ps
CPU time 3.56 seconds
Started Jul 10 05:09:49 PM PDT 24
Finished Jul 10 05:10:01 PM PDT 24
Peak memory 200312 kb
Host smart-f4db3f4a-4277-4ab2-b969-1c64bd185b80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322036612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.322036612
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2625852583
Short name T572
Test name
Test status
Simulation time 305165708 ps
CPU time 1.75 seconds
Started Jul 10 05:09:49 PM PDT 24
Finished Jul 10 05:10:00 PM PDT 24
Peak memory 200272 kb
Host smart-e85ce295-983e-40ab-b928-34b77245da74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625852583 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2625852583
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3355768929
Short name T645
Test name
Test status
Simulation time 43903973 ps
CPU time 0.66 seconds
Started Jul 10 05:09:50 PM PDT 24
Finished Jul 10 05:09:59 PM PDT 24
Peak memory 197912 kb
Host smart-bcff1a0d-c062-4f30-b520-8f05b9889e80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355768929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3355768929
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3304405607
Short name T567
Test name
Test status
Simulation time 13799282 ps
CPU time 0.61 seconds
Started Jul 10 05:09:50 PM PDT 24
Finished Jul 10 05:10:00 PM PDT 24
Peak memory 195272 kb
Host smart-7ce2b532-164c-484d-9ed9-9a6a0ba1479f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304405607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3304405607
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1304763989
Short name T550
Test name
Test status
Simulation time 495970926 ps
CPU time 2.34 seconds
Started Jul 10 05:09:48 PM PDT 24
Finished Jul 10 05:09:59 PM PDT 24
Peak memory 200152 kb
Host smart-cb8174f5-bf58-4cf0-9e18-10e250f1ec40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304763989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1304763989
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1580686858
Short name T565
Test name
Test status
Simulation time 129012893 ps
CPU time 1.93 seconds
Started Jul 10 05:09:45 PM PDT 24
Finished Jul 10 05:09:54 PM PDT 24
Peak memory 200256 kb
Host smart-04cb6433-d1b6-42c8-b72c-29c21656d995
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580686858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1580686858
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.670751192
Short name T91
Test name
Test status
Simulation time 220844997 ps
CPU time 8.09 seconds
Started Jul 10 05:09:33 PM PDT 24
Finished Jul 10 05:09:46 PM PDT 24
Peak memory 200140 kb
Host smart-cf694b80-1c3c-4aea-aba4-015773a521cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670751192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.670751192
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3920706987
Short name T535
Test name
Test status
Simulation time 220651125 ps
CPU time 5.24 seconds
Started Jul 10 05:09:34 PM PDT 24
Finished Jul 10 05:09:44 PM PDT 24
Peak memory 199248 kb
Host smart-41c2c7fc-a476-454f-bd05-71366088b8b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920706987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3920706987
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3544816166
Short name T644
Test name
Test status
Simulation time 50326196 ps
CPU time 0.89 seconds
Started Jul 10 05:09:28 PM PDT 24
Finished Jul 10 05:09:32 PM PDT 24
Peak memory 199328 kb
Host smart-733aa20b-2500-466e-a0f2-803003aa7518
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544816166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3544816166
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3767074760
Short name T587
Test name
Test status
Simulation time 169593784 ps
CPU time 1.15 seconds
Started Jul 10 05:09:34 PM PDT 24
Finished Jul 10 05:09:40 PM PDT 24
Peak memory 200068 kb
Host smart-2b42076d-023f-4e1d-a8cf-508e2b3c691a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767074760 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3767074760
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.416460110
Short name T88
Test name
Test status
Simulation time 20374536 ps
CPU time 0.7 seconds
Started Jul 10 05:09:33 PM PDT 24
Finished Jul 10 05:09:39 PM PDT 24
Peak memory 198180 kb
Host smart-862c52e2-352e-429d-8721-60d474954e26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416460110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.416460110
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3414129544
Short name T531
Test name
Test status
Simulation time 43318347 ps
CPU time 0.61 seconds
Started Jul 10 05:09:30 PM PDT 24
Finished Jul 10 05:09:34 PM PDT 24
Peak memory 195224 kb
Host smart-edbf7568-206f-472b-b3ad-0c39a1d773ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414129544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3414129544
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3294090155
Short name T97
Test name
Test status
Simulation time 635233214 ps
CPU time 1.81 seconds
Started Jul 10 05:09:30 PM PDT 24
Finished Jul 10 05:09:36 PM PDT 24
Peak memory 200244 kb
Host smart-a123d367-1f21-4b15-b1a6-99039fb69a06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294090155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3294090155
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3546085695
Short name T603
Test name
Test status
Simulation time 121965560 ps
CPU time 2.75 seconds
Started Jul 10 05:09:31 PM PDT 24
Finished Jul 10 05:09:37 PM PDT 24
Peak memory 200168 kb
Host smart-79c27ea3-7bd2-4d5c-a7be-4ca6404077d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546085695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3546085695
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.208931401
Short name T102
Test name
Test status
Simulation time 1056923340 ps
CPU time 3.12 seconds
Started Jul 10 05:09:31 PM PDT 24
Finished Jul 10 05:09:38 PM PDT 24
Peak memory 200264 kb
Host smart-01823614-d1c8-4530-b19b-d50a8fa7fd31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208931401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.208931401
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.580002692
Short name T619
Test name
Test status
Simulation time 15303272 ps
CPU time 0.6 seconds
Started Jul 10 05:09:55 PM PDT 24
Finished Jul 10 05:10:04 PM PDT 24
Peak memory 195476 kb
Host smart-7752045d-0981-44cb-a3de-d40d82dfb415
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580002692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.580002692
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2357392967
Short name T636
Test name
Test status
Simulation time 35299573 ps
CPU time 0.57 seconds
Started Jul 10 05:09:49 PM PDT 24
Finished Jul 10 05:09:57 PM PDT 24
Peak memory 195140 kb
Host smart-d941bfd8-1b17-414a-80a8-f800e0adc30a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357392967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2357392967
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3491557049
Short name T646
Test name
Test status
Simulation time 13375568 ps
CPU time 0.58 seconds
Started Jul 10 05:09:52 PM PDT 24
Finished Jul 10 05:10:00 PM PDT 24
Peak memory 195124 kb
Host smart-aef602ec-85e2-4571-8f80-8df36c202871
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491557049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3491557049
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2173708065
Short name T618
Test name
Test status
Simulation time 20452009 ps
CPU time 0.57 seconds
Started Jul 10 05:09:51 PM PDT 24
Finished Jul 10 05:10:00 PM PDT 24
Peak memory 195124 kb
Host smart-9f2785ea-64a0-47f8-83e2-f7953ba5b560
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173708065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2173708065
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1817730241
Short name T573
Test name
Test status
Simulation time 56926882 ps
CPU time 0.57 seconds
Started Jul 10 05:09:49 PM PDT 24
Finished Jul 10 05:09:58 PM PDT 24
Peak memory 195116 kb
Host smart-4df48a4e-3b4e-4366-b14e-de78d6be4991
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817730241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1817730241
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3974528588
Short name T604
Test name
Test status
Simulation time 36996249 ps
CPU time 0.66 seconds
Started Jul 10 05:10:11 PM PDT 24
Finished Jul 10 05:10:16 PM PDT 24
Peak memory 195148 kb
Host smart-654df2c2-d357-4f45-881d-42a0395f2b72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974528588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3974528588
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3239945474
Short name T616
Test name
Test status
Simulation time 98623681 ps
CPU time 0.62 seconds
Started Jul 10 05:09:50 PM PDT 24
Finished Jul 10 05:09:59 PM PDT 24
Peak memory 195076 kb
Host smart-69eed405-4928-4dd3-931a-4953abfee1ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239945474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3239945474
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.989635242
Short name T650
Test name
Test status
Simulation time 35648327 ps
CPU time 0.62 seconds
Started Jul 10 05:09:54 PM PDT 24
Finished Jul 10 05:10:03 PM PDT 24
Peak memory 195104 kb
Host smart-906b88b6-1243-4574-97d4-f1502e22437a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989635242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.989635242
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.843968379
Short name T533
Test name
Test status
Simulation time 47620169 ps
CPU time 0.62 seconds
Started Jul 10 05:09:50 PM PDT 24
Finished Jul 10 05:09:59 PM PDT 24
Peak memory 195128 kb
Host smart-624080dc-a19a-46da-855c-e8c8a3b80c6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843968379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.843968379
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.880063697
Short name T613
Test name
Test status
Simulation time 15899816 ps
CPU time 0.64 seconds
Started Jul 10 05:09:54 PM PDT 24
Finished Jul 10 05:10:03 PM PDT 24
Peak memory 195072 kb
Host smart-c7b50727-80aa-40b3-ae0f-c73a1adcb12a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880063697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.880063697
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1780272130
Short name T81
Test name
Test status
Simulation time 2396284305 ps
CPU time 9.17 seconds
Started Jul 10 05:09:32 PM PDT 24
Finished Jul 10 05:09:46 PM PDT 24
Peak memory 200252 kb
Host smart-716ed0c6-9c00-4a1d-a84d-92af7677fccc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780272130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1780272130
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1296087656
Short name T614
Test name
Test status
Simulation time 1445966792 ps
CPU time 10.7 seconds
Started Jul 10 05:09:32 PM PDT 24
Finished Jul 10 05:09:47 PM PDT 24
Peak memory 199312 kb
Host smart-f1487f71-4e31-4eb5-87ae-0fe31eb90853
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296087656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1296087656
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.381460499
Short name T597
Test name
Test status
Simulation time 190945786 ps
CPU time 0.73 seconds
Started Jul 10 05:09:33 PM PDT 24
Finished Jul 10 05:09:38 PM PDT 24
Peak memory 198164 kb
Host smart-d07dadae-526a-4fe5-9ff9-8e20860c333a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381460499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.381460499
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.47539047
Short name T549
Test name
Test status
Simulation time 31314934 ps
CPU time 1.81 seconds
Started Jul 10 05:09:31 PM PDT 24
Finished Jul 10 05:09:37 PM PDT 24
Peak memory 200216 kb
Host smart-e883ca38-4b44-47c0-bcd1-7d55800843ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47539047 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.47539047
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2959264926
Short name T607
Test name
Test status
Simulation time 76806617 ps
CPU time 0.84 seconds
Started Jul 10 05:09:30 PM PDT 24
Finished Jul 10 05:09:34 PM PDT 24
Peak memory 199836 kb
Host smart-bf7df56e-a2ec-4246-b36a-c7f90dabadfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959264926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2959264926
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2785668941
Short name T540
Test name
Test status
Simulation time 48597205 ps
CPU time 0.59 seconds
Started Jul 10 05:09:34 PM PDT 24
Finished Jul 10 05:09:39 PM PDT 24
Peak memory 195104 kb
Host smart-8a1f59af-6e0f-4ab4-b0d9-8a269f60e12d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785668941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2785668941
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3757496098
Short name T579
Test name
Test status
Simulation time 35410047 ps
CPU time 1.63 seconds
Started Jul 10 05:09:30 PM PDT 24
Finished Jul 10 05:09:34 PM PDT 24
Peak memory 200168 kb
Host smart-a83c4671-8f76-4fd5-9c09-77cad95e5ac2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757496098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3757496098
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.491871227
Short name T584
Test name
Test status
Simulation time 536459599 ps
CPU time 4.1 seconds
Started Jul 10 05:09:31 PM PDT 24
Finished Jul 10 05:09:40 PM PDT 24
Peak memory 200312 kb
Host smart-32f509c3-fb4b-44d9-98c5-fe3558399c6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491871227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.491871227
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1960935091
Short name T105
Test name
Test status
Simulation time 266428416 ps
CPU time 4.4 seconds
Started Jul 10 05:09:30 PM PDT 24
Finished Jul 10 05:09:37 PM PDT 24
Peak memory 200236 kb
Host smart-95166640-9fd1-44d1-990a-3715aefc9b4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960935091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1960935091
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1603602383
Short name T547
Test name
Test status
Simulation time 63138805 ps
CPU time 0.64 seconds
Started Jul 10 05:10:11 PM PDT 24
Finished Jul 10 05:10:16 PM PDT 24
Peak memory 195076 kb
Host smart-991d6a4a-8db4-4efc-9e17-d3f5cb89e287
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603602383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1603602383
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1720777741
Short name T602
Test name
Test status
Simulation time 38366310 ps
CPU time 0.54 seconds
Started Jul 10 05:09:50 PM PDT 24
Finished Jul 10 05:09:59 PM PDT 24
Peak memory 195136 kb
Host smart-2c1334c4-d3ea-44bf-b8a6-b080a047fe2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720777741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1720777741
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.368258908
Short name T634
Test name
Test status
Simulation time 14373449 ps
CPU time 0.58 seconds
Started Jul 10 05:09:48 PM PDT 24
Finished Jul 10 05:09:57 PM PDT 24
Peak memory 195148 kb
Host smart-511e50cf-0ff1-4009-824a-8c215cff29b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368258908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.368258908
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3172846318
Short name T542
Test name
Test status
Simulation time 64911148 ps
CPU time 0.65 seconds
Started Jul 10 05:09:52 PM PDT 24
Finished Jul 10 05:10:02 PM PDT 24
Peak memory 195104 kb
Host smart-5afa37b2-30ea-4db1-b179-bea4ecbe62e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172846318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3172846318
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1862319902
Short name T546
Test name
Test status
Simulation time 25541423 ps
CPU time 0.64 seconds
Started Jul 10 05:09:49 PM PDT 24
Finished Jul 10 05:09:59 PM PDT 24
Peak memory 195220 kb
Host smart-ff786c1b-7739-4d8f-8a7f-e0950b39570d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862319902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1862319902
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.511825484
Short name T657
Test name
Test status
Simulation time 24547351 ps
CPU time 0.59 seconds
Started Jul 10 05:09:51 PM PDT 24
Finished Jul 10 05:10:00 PM PDT 24
Peak memory 195140 kb
Host smart-ae3e0a7f-09fb-4071-99ca-42fe4173e688
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511825484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.511825484
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.442641854
Short name T582
Test name
Test status
Simulation time 16508945 ps
CPU time 0.63 seconds
Started Jul 10 05:09:51 PM PDT 24
Finished Jul 10 05:10:00 PM PDT 24
Peak memory 195116 kb
Host smart-eea1c8eb-3084-4cb1-a4b4-7adb20527de0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442641854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.442641854
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1399281489
Short name T539
Test name
Test status
Simulation time 14857550 ps
CPU time 0.6 seconds
Started Jul 10 05:09:52 PM PDT 24
Finished Jul 10 05:10:00 PM PDT 24
Peak memory 195068 kb
Host smart-29a744e9-8701-4b8b-a0a7-ef9d238ac78c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399281489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1399281489
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2224238949
Short name T526
Test name
Test status
Simulation time 54552551 ps
CPU time 0.59 seconds
Started Jul 10 05:09:47 PM PDT 24
Finished Jul 10 05:09:56 PM PDT 24
Peak memory 195220 kb
Host smart-0eae93ba-7664-4a71-81e8-2e1615ad94ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224238949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2224238949
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.1181087934
Short name T635
Test name
Test status
Simulation time 18825554 ps
CPU time 0.58 seconds
Started Jul 10 05:09:50 PM PDT 24
Finished Jul 10 05:09:59 PM PDT 24
Peak memory 195140 kb
Host smart-b4fc124d-2a51-42ff-a105-6e5d320662fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181087934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.1181087934
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3919054308
Short name T639
Test name
Test status
Simulation time 106320092 ps
CPU time 5.64 seconds
Started Jul 10 05:09:31 PM PDT 24
Finished Jul 10 05:09:42 PM PDT 24
Peak memory 200228 kb
Host smart-4668c1e8-6fa7-46a1-a1aa-ed441868ec41
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919054308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3919054308
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.285572938
Short name T90
Test name
Test status
Simulation time 556283927 ps
CPU time 5.96 seconds
Started Jul 10 05:09:30 PM PDT 24
Finished Jul 10 05:09:40 PM PDT 24
Peak memory 200168 kb
Host smart-ffb051ae-670b-475b-8ed5-cb6817bf005e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285572938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.285572938
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2654449148
Short name T631
Test name
Test status
Simulation time 36558151 ps
CPU time 1.11 seconds
Started Jul 10 05:09:33 PM PDT 24
Finished Jul 10 05:09:39 PM PDT 24
Peak memory 199868 kb
Host smart-9ff638ad-9d02-416f-bad8-8954ee050ca9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654449148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2654449148
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1991634829
Short name T534
Test name
Test status
Simulation time 124861625160 ps
CPU time 642.68 seconds
Started Jul 10 05:09:31 PM PDT 24
Finished Jul 10 05:20:19 PM PDT 24
Peak memory 216752 kb
Host smart-8b2a6602-5080-4575-a42b-895c96d38c1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991634829 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1991634829
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3742798719
Short name T554
Test name
Test status
Simulation time 47406105 ps
CPU time 0.86 seconds
Started Jul 10 05:09:31 PM PDT 24
Finished Jul 10 05:09:35 PM PDT 24
Peak memory 199428 kb
Host smart-143e8f91-9524-44e6-b340-59f6bcf5a012
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742798719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3742798719
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3151629962
Short name T532
Test name
Test status
Simulation time 27468624 ps
CPU time 0.66 seconds
Started Jul 10 05:09:29 PM PDT 24
Finished Jul 10 05:09:33 PM PDT 24
Peak memory 195216 kb
Host smart-8f04af89-9f89-42f3-a78e-c65f9dfada79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151629962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3151629962
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.863726603
Short name T555
Test name
Test status
Simulation time 872614356 ps
CPU time 2.35 seconds
Started Jul 10 05:09:35 PM PDT 24
Finished Jul 10 05:09:43 PM PDT 24
Peak memory 200260 kb
Host smart-83904247-8819-4e96-91d7-e2eee2bf665b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863726603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_
outstanding.863726603
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.513521039
Short name T551
Test name
Test status
Simulation time 88123356 ps
CPU time 1.82 seconds
Started Jul 10 05:09:34 PM PDT 24
Finished Jul 10 05:09:41 PM PDT 24
Peak memory 200308 kb
Host smart-11bbc1da-45e9-4869-9be2-58afd4c2dfc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513521039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.513521039
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.487534764
Short name T54
Test name
Test status
Simulation time 101154773 ps
CPU time 1.86 seconds
Started Jul 10 05:09:32 PM PDT 24
Finished Jul 10 05:09:39 PM PDT 24
Peak memory 200172 kb
Host smart-8f70503e-afc3-4b4f-b288-f244a87d173e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487534764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.487534764
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3857406413
Short name T581
Test name
Test status
Simulation time 28581063 ps
CPU time 0.64 seconds
Started Jul 10 05:09:54 PM PDT 24
Finished Jul 10 05:10:03 PM PDT 24
Peak memory 195024 kb
Host smart-d2a701e5-a21a-47c3-bbee-5a07cdf321cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857406413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3857406413
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.281374516
Short name T592
Test name
Test status
Simulation time 15931127 ps
CPU time 0.61 seconds
Started Jul 10 05:10:07 PM PDT 24
Finished Jul 10 05:10:13 PM PDT 24
Peak memory 195296 kb
Host smart-52774665-0cd3-464f-bdcc-330380b85fb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281374516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.281374516
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.4195902676
Short name T648
Test name
Test status
Simulation time 60902876 ps
CPU time 0.63 seconds
Started Jul 10 05:10:11 PM PDT 24
Finished Jul 10 05:10:16 PM PDT 24
Peak memory 195180 kb
Host smart-dac5bb4c-db63-4208-9e0b-17e9a4566433
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195902676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.4195902676
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1965619953
Short name T560
Test name
Test status
Simulation time 38992042 ps
CPU time 0.61 seconds
Started Jul 10 05:09:50 PM PDT 24
Finished Jul 10 05:09:59 PM PDT 24
Peak memory 195388 kb
Host smart-6fcd0ea9-26b6-4158-bede-8cd8a0c1d261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965619953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1965619953
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.1459372247
Short name T596
Test name
Test status
Simulation time 17027376 ps
CPU time 0.62 seconds
Started Jul 10 05:09:51 PM PDT 24
Finished Jul 10 05:10:00 PM PDT 24
Peak memory 195276 kb
Host smart-f5c20ae6-41d7-4080-9ffb-0cec3493afef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459372247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1459372247
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3323293468
Short name T626
Test name
Test status
Simulation time 38760173 ps
CPU time 0.59 seconds
Started Jul 10 05:09:49 PM PDT 24
Finished Jul 10 05:09:59 PM PDT 24
Peak memory 195048 kb
Host smart-56697af6-947a-429d-9a12-f1a456520f6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323293468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3323293468
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.2385827441
Short name T589
Test name
Test status
Simulation time 48376715 ps
CPU time 0.59 seconds
Started Jul 10 05:09:51 PM PDT 24
Finished Jul 10 05:10:00 PM PDT 24
Peak memory 195144 kb
Host smart-4a763646-0c48-45a8-add6-11f35addfc95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385827441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2385827441
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3943134520
Short name T541
Test name
Test status
Simulation time 47377859 ps
CPU time 0.59 seconds
Started Jul 10 05:09:50 PM PDT 24
Finished Jul 10 05:09:59 PM PDT 24
Peak memory 195124 kb
Host smart-dc294000-4bdd-433b-afeb-0e39f1da22a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943134520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3943134520
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.262572094
Short name T594
Test name
Test status
Simulation time 49549653 ps
CPU time 0.68 seconds
Started Jul 10 05:09:54 PM PDT 24
Finished Jul 10 05:10:02 PM PDT 24
Peak memory 195076 kb
Host smart-d1764210-866e-4298-b7f6-5f6345646d17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262572094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.262572094
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3129979051
Short name T651
Test name
Test status
Simulation time 14061604 ps
CPU time 0.61 seconds
Started Jul 10 05:09:52 PM PDT 24
Finished Jul 10 05:10:00 PM PDT 24
Peak memory 195124 kb
Host smart-6742a955-7652-48cb-96ae-018d5a6e62e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129979051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3129979051
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2934586243
Short name T622
Test name
Test status
Simulation time 170175503 ps
CPU time 2.32 seconds
Started Jul 10 05:09:29 PM PDT 24
Finished Jul 10 05:09:34 PM PDT 24
Peak memory 200240 kb
Host smart-cb02fcf2-1a4e-4770-aced-7787e0e75f83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934586243 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2934586243
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1474386747
Short name T627
Test name
Test status
Simulation time 33636798 ps
CPU time 0.7 seconds
Started Jul 10 05:09:29 PM PDT 24
Finished Jul 10 05:09:32 PM PDT 24
Peak memory 198344 kb
Host smart-32d924eb-7fac-4898-aec9-220ac88d3d23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474386747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1474386747
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2649006317
Short name T564
Test name
Test status
Simulation time 14258951 ps
CPU time 0.58 seconds
Started Jul 10 05:09:34 PM PDT 24
Finished Jul 10 05:09:40 PM PDT 24
Peak memory 195172 kb
Host smart-0ca8e9a7-7058-4f82-b5f6-0227bdaa56d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649006317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2649006317
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.803181383
Short name T562
Test name
Test status
Simulation time 43656347 ps
CPU time 2.15 seconds
Started Jul 10 05:09:31 PM PDT 24
Finished Jul 10 05:09:38 PM PDT 24
Peak memory 200264 kb
Host smart-cda170c6-0923-4598-869c-2e060e904fd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803181383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr_
outstanding.803181383
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.4281606234
Short name T623
Test name
Test status
Simulation time 3100378510 ps
CPU time 3.83 seconds
Started Jul 10 05:09:30 PM PDT 24
Finished Jul 10 05:09:37 PM PDT 24
Peak memory 200356 kb
Host smart-17693e9f-7973-4cf6-85da-808df22430ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281606234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.4281606234
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1262752861
Short name T107
Test name
Test status
Simulation time 135193167 ps
CPU time 3.96 seconds
Started Jul 10 05:09:30 PM PDT 24
Finished Jul 10 05:09:38 PM PDT 24
Peak memory 200192 kb
Host smart-fec9c6bf-111b-4235-8742-06aeddf2bdf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262752861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1262752861
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2032312479
Short name T600
Test name
Test status
Simulation time 397807150 ps
CPU time 1.67 seconds
Started Jul 10 05:09:40 PM PDT 24
Finished Jul 10 05:09:48 PM PDT 24
Peak memory 200236 kb
Host smart-99eedbf5-4811-490f-be68-3cd1527d63a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032312479 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2032312479
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1109284932
Short name T84
Test name
Test status
Simulation time 53851837 ps
CPU time 0.9 seconds
Started Jul 10 05:09:30 PM PDT 24
Finished Jul 10 05:09:34 PM PDT 24
Peak memory 199692 kb
Host smart-ecccb889-6299-4dcc-a8b5-23f47807b1b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109284932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1109284932
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2438048087
Short name T529
Test name
Test status
Simulation time 125851379 ps
CPU time 0.64 seconds
Started Jul 10 05:09:30 PM PDT 24
Finished Jul 10 05:09:34 PM PDT 24
Peak memory 195160 kb
Host smart-8aeb2e7c-508a-4678-8b23-71f06bf67934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438048087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2438048087
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1990899058
Short name T98
Test name
Test status
Simulation time 74432980 ps
CPU time 1.11 seconds
Started Jul 10 05:09:37 PM PDT 24
Finished Jul 10 05:09:44 PM PDT 24
Peak memory 200044 kb
Host smart-9212c55e-d6b8-4bbe-8c8d-39c2c44914b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990899058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1990899058
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3040217739
Short name T656
Test name
Test status
Simulation time 157642105 ps
CPU time 1.81 seconds
Started Jul 10 05:09:33 PM PDT 24
Finished Jul 10 05:09:39 PM PDT 24
Peak memory 200144 kb
Host smart-929758a2-7d00-403f-9efb-dd6f58baa035
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040217739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3040217739
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3490719347
Short name T583
Test name
Test status
Simulation time 974783930 ps
CPU time 4.05 seconds
Started Jul 10 05:09:29 PM PDT 24
Finished Jul 10 05:09:36 PM PDT 24
Peak memory 200300 kb
Host smart-ae10d81f-f6fd-4cf0-81cd-9ad8a9ecae94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490719347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3490719347
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4092347606
Short name T655
Test name
Test status
Simulation time 213085902 ps
CPU time 1.59 seconds
Started Jul 10 05:09:44 PM PDT 24
Finished Jul 10 05:09:53 PM PDT 24
Peak memory 200244 kb
Host smart-59648257-2958-45a8-a1db-7ff4b420c938
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092347606 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.4092347606
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3538322057
Short name T80
Test name
Test status
Simulation time 33875834 ps
CPU time 0.99 seconds
Started Jul 10 05:09:40 PM PDT 24
Finished Jul 10 05:09:46 PM PDT 24
Peak memory 200028 kb
Host smart-e8158704-7cbf-48e6-b6f1-2dd47f60ad13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538322057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3538322057
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1758559747
Short name T643
Test name
Test status
Simulation time 54678133 ps
CPU time 0.62 seconds
Started Jul 10 05:09:39 PM PDT 24
Finished Jul 10 05:09:45 PM PDT 24
Peak memory 195288 kb
Host smart-a8f271cc-c67b-4520-90e4-fa72f3f8632c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758559747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1758559747
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.4242161027
Short name T593
Test name
Test status
Simulation time 333707407 ps
CPU time 1.71 seconds
Started Jul 10 05:09:44 PM PDT 24
Finished Jul 10 05:09:51 PM PDT 24
Peak memory 200184 kb
Host smart-6cff73a0-5881-40f5-857f-a599a97f0afb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242161027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.4242161027
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.3565853143
Short name T653
Test name
Test status
Simulation time 243064596 ps
CPU time 2.56 seconds
Started Jul 10 05:09:38 PM PDT 24
Finished Jul 10 05:09:46 PM PDT 24
Peak memory 200224 kb
Host smart-5fe5e142-d5f4-4f2c-82d1-dadcc2a177f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565853143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.3565853143
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3174262083
Short name T629
Test name
Test status
Simulation time 85430682 ps
CPU time 1.86 seconds
Started Jul 10 05:09:45 PM PDT 24
Finished Jul 10 05:09:54 PM PDT 24
Peak memory 200036 kb
Host smart-322aea50-da87-4809-9539-6ac13b357fd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174262083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3174262083
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2788879941
Short name T569
Test name
Test status
Simulation time 87848202 ps
CPU time 1.61 seconds
Started Jul 10 05:09:37 PM PDT 24
Finished Jul 10 05:09:45 PM PDT 24
Peak memory 200324 kb
Host smart-55feeed7-7619-45d9-80f8-05adf79e1318
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788879941 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2788879941
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3597229056
Short name T632
Test name
Test status
Simulation time 32967782 ps
CPU time 0.92 seconds
Started Jul 10 05:09:36 PM PDT 24
Finished Jul 10 05:09:43 PM PDT 24
Peak memory 200100 kb
Host smart-d8fba8ad-47ba-47be-bbce-fdf8990e0048
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597229056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3597229056
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3032350310
Short name T640
Test name
Test status
Simulation time 62160663 ps
CPU time 0.62 seconds
Started Jul 10 05:09:40 PM PDT 24
Finished Jul 10 05:09:47 PM PDT 24
Peak memory 195144 kb
Host smart-bb054432-73ea-4ae2-a199-ea0e908685ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032350310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3032350310
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3953318100
Short name T577
Test name
Test status
Simulation time 463827593 ps
CPU time 2.33 seconds
Started Jul 10 05:09:39 PM PDT 24
Finished Jul 10 05:09:47 PM PDT 24
Peak memory 200456 kb
Host smart-d7251315-7879-4140-b4fc-0ddc83489098
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953318100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3953318100
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.3250931601
Short name T654
Test name
Test status
Simulation time 399809396 ps
CPU time 1.71 seconds
Started Jul 10 05:09:39 PM PDT 24
Finished Jul 10 05:09:46 PM PDT 24
Peak memory 200252 kb
Host smart-62901b66-b47e-4b94-8ced-df7e5cb1f5d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250931601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.3250931601
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1616764460
Short name T109
Test name
Test status
Simulation time 375364041 ps
CPU time 1.85 seconds
Started Jul 10 05:09:37 PM PDT 24
Finished Jul 10 05:09:45 PM PDT 24
Peak memory 200300 kb
Host smart-fd7e60da-6231-4707-8429-4222611a2032
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616764460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1616764460
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1247958923
Short name T557
Test name
Test status
Simulation time 61348160 ps
CPU time 2.66 seconds
Started Jul 10 05:09:40 PM PDT 24
Finished Jul 10 05:09:48 PM PDT 24
Peak memory 200156 kb
Host smart-e202271f-6711-46c9-939d-91c6c3204a59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247958923 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1247958923
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2343811605
Short name T528
Test name
Test status
Simulation time 238699822 ps
CPU time 1.02 seconds
Started Jul 10 05:09:39 PM PDT 24
Finished Jul 10 05:09:46 PM PDT 24
Peak memory 200020 kb
Host smart-257b1b89-4c23-44a8-a1ac-a0250148775e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343811605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2343811605
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.4261212224
Short name T538
Test name
Test status
Simulation time 11869446 ps
CPU time 0.61 seconds
Started Jul 10 05:09:45 PM PDT 24
Finished Jul 10 05:09:53 PM PDT 24
Peak memory 194928 kb
Host smart-d9829747-fe65-4775-800a-8181b1563de0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261212224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.4261212224
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1044850013
Short name T95
Test name
Test status
Simulation time 84626478 ps
CPU time 1.12 seconds
Started Jul 10 05:09:38 PM PDT 24
Finished Jul 10 05:09:45 PM PDT 24
Peak memory 200252 kb
Host smart-e7d44743-ae80-45f8-9307-b734d2c654c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044850013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1044850013
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2491701049
Short name T595
Test name
Test status
Simulation time 132852500 ps
CPU time 1.66 seconds
Started Jul 10 05:09:36 PM PDT 24
Finished Jul 10 05:09:43 PM PDT 24
Peak memory 200168 kb
Host smart-9ff5c17f-99f7-428b-b4e1-9b49e0c1553d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491701049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2491701049
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.4228404557
Short name T101
Test name
Test status
Simulation time 154190296 ps
CPU time 2.92 seconds
Started Jul 10 05:09:41 PM PDT 24
Finished Jul 10 05:09:50 PM PDT 24
Peak memory 200328 kb
Host smart-eb87eee4-d5ff-4237-8291-223efdf04d39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228404557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.4228404557
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.1617963522
Short name T292
Test name
Test status
Simulation time 18328089634 ps
CPU time 82.19 seconds
Started Jul 10 05:09:48 PM PDT 24
Finished Jul 10 05:11:18 PM PDT 24
Peak memory 216516 kb
Host smart-59f6337b-42a4-4956-9115-f14a33a60079
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1617963522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1617963522
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.955695943
Short name T327
Test name
Test status
Simulation time 1113362369 ps
CPU time 3.39 seconds
Started Jul 10 05:09:52 PM PDT 24
Finished Jul 10 05:10:03 PM PDT 24
Peak memory 200216 kb
Host smart-10a7fd56-9974-462e-8186-fb2819c446e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955695943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.955695943
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1201197936
Short name T473
Test name
Test status
Simulation time 2055142241 ps
CPU time 91.49 seconds
Started Jul 10 05:09:50 PM PDT 24
Finished Jul 10 05:11:30 PM PDT 24
Peak memory 438792 kb
Host smart-f0b2a9d2-157e-4675-aa99-d77e1b369e12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1201197936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1201197936
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.3953762940
Short name T185
Test name
Test status
Simulation time 17481597478 ps
CPU time 156.11 seconds
Started Jul 10 05:09:58 PM PDT 24
Finished Jul 10 05:12:41 PM PDT 24
Peak memory 200324 kb
Host smart-5a7abe73-6db2-498d-96ca-1523c9794106
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953762940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.3953762940
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1165032526
Short name T427
Test name
Test status
Simulation time 12336419608 ps
CPU time 162.35 seconds
Started Jul 10 05:09:54 PM PDT 24
Finished Jul 10 05:12:44 PM PDT 24
Peak memory 208488 kb
Host smart-49befff8-20e5-40ce-92cb-1ca2eb0d9213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165032526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1165032526
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.463791475
Short name T346
Test name
Test status
Simulation time 258014065 ps
CPU time 11.3 seconds
Started Jul 10 05:10:11 PM PDT 24
Finished Jul 10 05:10:27 PM PDT 24
Peak memory 200264 kb
Host smart-6b6db3ad-e136-4b98-8e1b-8584e55fa08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463791475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.463791475
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.627065774
Short name T451
Test name
Test status
Simulation time 95740893468 ps
CPU time 1708.49 seconds
Started Jul 10 05:10:02 PM PDT 24
Finished Jul 10 05:38:36 PM PDT 24
Peak memory 200284 kb
Host smart-af181945-1f13-4278-a70c-eb8d51dcafbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627065774 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.627065774
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.955760943
Short name T459
Test name
Test status
Simulation time 12034980719 ps
CPU time 43.55 seconds
Started Jul 10 05:09:58 PM PDT 24
Finished Jul 10 05:10:49 PM PDT 24
Peak memory 200332 kb
Host smart-b2a30896-01d3-41f5-aba1-aed8978df94e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=955760943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.955760943
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.3309261149
Short name T430
Test name
Test status
Simulation time 2338228385 ps
CPU time 87.48 seconds
Started Jul 10 05:10:06 PM PDT 24
Finished Jul 10 05:11:38 PM PDT 24
Peak memory 200240 kb
Host smart-9473048d-cfd5-45cb-b080-ac9a4c240b9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3309261149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.3309261149
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.110519269
Short name T356
Test name
Test status
Simulation time 57097048520 ps
CPU time 108.19 seconds
Started Jul 10 05:09:58 PM PDT 24
Finished Jul 10 05:11:53 PM PDT 24
Peak memory 200340 kb
Host smart-944836f0-3b7d-4c50-a52b-28c3c3f4bea5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=110519269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.110519269
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.2242933716
Short name T435
Test name
Test status
Simulation time 145796159444 ps
CPU time 617.87 seconds
Started Jul 10 05:09:53 PM PDT 24
Finished Jul 10 05:20:19 PM PDT 24
Peak memory 200260 kb
Host smart-cfa50d0d-4f67-49da-8409-fca16a7cda70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2242933716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.2242933716
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.3748866788
Short name T455
Test name
Test status
Simulation time 55907524466 ps
CPU time 2065.49 seconds
Started Jul 10 05:10:02 PM PDT 24
Finished Jul 10 05:44:33 PM PDT 24
Peak memory 215852 kb
Host smart-f3d7fdc1-4b23-4e46-b83c-171771f6256b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3748866788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.3748866788
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.636719959
Short name T7
Test name
Test status
Simulation time 148705464001 ps
CPU time 2557.81 seconds
Started Jul 10 05:09:54 PM PDT 24
Finished Jul 10 05:52:40 PM PDT 24
Peak memory 216296 kb
Host smart-43e7b8d3-e961-4be0-9bb5-51844426dd30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=636719959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.636719959
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1153165580
Short name T172
Test name
Test status
Simulation time 42514992698 ps
CPU time 141.48 seconds
Started Jul 10 05:09:56 PM PDT 24
Finished Jul 10 05:12:25 PM PDT 24
Peak memory 200396 kb
Host smart-0043bb9c-eab0-4493-b59b-b9bb3b965e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153165580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1153165580
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3807308280
Short name T476
Test name
Test status
Simulation time 39684799 ps
CPU time 0.58 seconds
Started Jul 10 05:09:56 PM PDT 24
Finished Jul 10 05:10:04 PM PDT 24
Peak memory 196176 kb
Host smart-4b87eeae-e3eb-4523-b62b-7551e6a6ab93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807308280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3807308280
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2200123099
Short name T335
Test name
Test status
Simulation time 6998953725 ps
CPU time 49.92 seconds
Started Jul 10 05:09:58 PM PDT 24
Finished Jul 10 05:10:55 PM PDT 24
Peak memory 216668 kb
Host smart-1cc10caf-76d3-4663-9229-de4957615d90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2200123099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2200123099
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1877132665
Short name T200
Test name
Test status
Simulation time 4490860922 ps
CPU time 21.58 seconds
Started Jul 10 05:09:54 PM PDT 24
Finished Jul 10 05:10:24 PM PDT 24
Peak memory 200260 kb
Host smart-c2aea4a7-f9f4-402d-abc1-2450d5e454e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877132665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1877132665
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.907839963
Short name T342
Test name
Test status
Simulation time 13712233841 ps
CPU time 695.79 seconds
Started Jul 10 05:09:56 PM PDT 24
Finished Jul 10 05:21:40 PM PDT 24
Peak memory 684724 kb
Host smart-35e4c94c-1ea4-4478-afd8-13c87046eaa1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=907839963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.907839963
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1067356320
Short name T501
Test name
Test status
Simulation time 9855957455 ps
CPU time 132.83 seconds
Started Jul 10 05:09:57 PM PDT 24
Finished Jul 10 05:12:18 PM PDT 24
Peak memory 200336 kb
Host smart-a12855d3-39f0-49f5-93ea-046729f8ea6f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067356320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1067356320
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3816257268
Short name T301
Test name
Test status
Simulation time 1380959299 ps
CPU time 14.42 seconds
Started Jul 10 05:09:59 PM PDT 24
Finished Jul 10 05:10:20 PM PDT 24
Peak memory 200260 kb
Host smart-503970d1-c4bc-4094-b8d1-f8e25775023e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816257268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3816257268
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3557828630
Short name T43
Test name
Test status
Simulation time 64806470 ps
CPU time 0.87 seconds
Started Jul 10 05:10:02 PM PDT 24
Finished Jul 10 05:10:08 PM PDT 24
Peak memory 218208 kb
Host smart-2e3018ef-b918-44e9-be24-7399157e90ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557828630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3557828630
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1170368438
Short name T18
Test name
Test status
Simulation time 174688095 ps
CPU time 8 seconds
Started Jul 10 05:10:01 PM PDT 24
Finished Jul 10 05:10:15 PM PDT 24
Peak memory 200216 kb
Host smart-14d4ff64-01c2-4f77-a271-926dedea0c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170368438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1170368438
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.793745420
Short name T159
Test name
Test status
Simulation time 3132232333 ps
CPU time 62.68 seconds
Started Jul 10 05:10:07 PM PDT 24
Finished Jul 10 05:11:15 PM PDT 24
Peak memory 200340 kb
Host smart-846fc47e-4cb7-478f-8867-24f248ab0b10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=793745420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.793745420
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.238860643
Short name T351
Test name
Test status
Simulation time 57546136600 ps
CPU time 58.27 seconds
Started Jul 10 05:10:05 PM PDT 24
Finished Jul 10 05:11:08 PM PDT 24
Peak memory 200240 kb
Host smart-11327f64-2dcc-4b4c-bb42-9b2472fefa9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=238860643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.238860643
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.3308600779
Short name T509
Test name
Test status
Simulation time 6964631409 ps
CPU time 79.57 seconds
Started Jul 10 05:09:58 PM PDT 24
Finished Jul 10 05:11:24 PM PDT 24
Peak memory 200332 kb
Host smart-0ea69473-cebc-416c-b79c-8bb8034685cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3308600779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.3308600779
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.2795330348
Short name T340
Test name
Test status
Simulation time 41783534587 ps
CPU time 583.14 seconds
Started Jul 10 05:10:02 PM PDT 24
Finished Jul 10 05:19:50 PM PDT 24
Peak memory 200296 kb
Host smart-7d615a88-bd30-4c47-a417-894ed295619d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2795330348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.2795330348
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.1411145299
Short name T368
Test name
Test status
Simulation time 142440414336 ps
CPU time 2523.67 seconds
Started Jul 10 05:10:02 PM PDT 24
Finished Jul 10 05:52:11 PM PDT 24
Peak memory 215948 kb
Host smart-a2115506-16d8-4d21-9da3-19cb2b3879ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1411145299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.1411145299
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.3087106534
Short name T64
Test name
Test status
Simulation time 1549675128625 ps
CPU time 2755.45 seconds
Started Jul 10 05:10:10 PM PDT 24
Finished Jul 10 05:56:11 PM PDT 24
Peak memory 215688 kb
Host smart-f647a78f-92a7-4039-bb4c-8eedbc46059e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3087106534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.3087106534
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.915475166
Short name T485
Test name
Test status
Simulation time 1074369567 ps
CPU time 18.88 seconds
Started Jul 10 05:09:56 PM PDT 24
Finished Jul 10 05:10:22 PM PDT 24
Peak memory 200280 kb
Host smart-1581f63a-0563-49f1-a37a-fdf002d6fa8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915475166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.915475166
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3959322269
Short name T428
Test name
Test status
Simulation time 23704488 ps
CPU time 0.59 seconds
Started Jul 10 05:10:20 PM PDT 24
Finished Jul 10 05:10:26 PM PDT 24
Peak memory 196176 kb
Host smart-fb1783f3-b182-456b-bfc5-0ed09238806f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959322269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3959322269
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.66457727
Short name T487
Test name
Test status
Simulation time 5516169100 ps
CPU time 83.9 seconds
Started Jul 10 05:10:20 PM PDT 24
Finished Jul 10 05:11:49 PM PDT 24
Peak memory 200520 kb
Host smart-763b5d8a-1fe3-4a51-995c-914d15297dc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=66457727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.66457727
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2440405968
Short name T117
Test name
Test status
Simulation time 1848510037 ps
CPU time 25.19 seconds
Started Jul 10 05:10:21 PM PDT 24
Finished Jul 10 05:10:52 PM PDT 24
Peak memory 200272 kb
Host smart-4c61ca08-3f9a-4393-bdb2-b7fd1eacbb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440405968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2440405968
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1201298341
Short name T440
Test name
Test status
Simulation time 3375285647 ps
CPU time 207.54 seconds
Started Jul 10 05:10:16 PM PDT 24
Finished Jul 10 05:13:49 PM PDT 24
Peak memory 610980 kb
Host smart-ed4cc87e-53b2-4e31-82d2-d1988d4ac398
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1201298341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1201298341
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3046775247
Short name T63
Test name
Test status
Simulation time 6490431731 ps
CPU time 111.12 seconds
Started Jul 10 05:10:24 PM PDT 24
Finished Jul 10 05:12:20 PM PDT 24
Peak memory 200312 kb
Host smart-14d0479a-dbb5-467d-a7ca-f9600e8037a5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046775247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3046775247
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.541549520
Short name T307
Test name
Test status
Simulation time 3769199221 ps
CPU time 155.29 seconds
Started Jul 10 05:10:16 PM PDT 24
Finished Jul 10 05:12:56 PM PDT 24
Peak memory 200340 kb
Host smart-612e65d9-47af-4f34-be3a-24e68a6956a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541549520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.541549520
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1856156185
Short name T316
Test name
Test status
Simulation time 2594406298 ps
CPU time 7.64 seconds
Started Jul 10 05:10:16 PM PDT 24
Finished Jul 10 05:10:29 PM PDT 24
Peak memory 200280 kb
Host smart-cb278ccb-ca05-4025-8b3f-b883ca5fea51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856156185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1856156185
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.990463432
Short name T439
Test name
Test status
Simulation time 83738438020 ps
CPU time 277.7 seconds
Started Jul 10 05:10:19 PM PDT 24
Finished Jul 10 05:15:01 PM PDT 24
Peak memory 200344 kb
Host smart-a1ad9398-f273-4e73-b868-b1183e589784
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990463432 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.990463432
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.855736012
Short name T150
Test name
Test status
Simulation time 9907936440 ps
CPU time 112.09 seconds
Started Jul 10 05:10:23 PM PDT 24
Finished Jul 10 05:12:20 PM PDT 24
Peak memory 200396 kb
Host smart-bd5b6361-6e21-4ed0-a109-2cae218b1a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855736012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.855736012
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2573867038
Short name T364
Test name
Test status
Simulation time 14716651 ps
CPU time 0.57 seconds
Started Jul 10 05:10:35 PM PDT 24
Finished Jul 10 05:10:38 PM PDT 24
Peak memory 195688 kb
Host smart-27cb5020-80e3-45ac-8446-6081cb835eb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573867038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2573867038
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1461745129
Short name T51
Test name
Test status
Simulation time 902566207 ps
CPU time 28.65 seconds
Started Jul 10 05:10:21 PM PDT 24
Finished Jul 10 05:10:55 PM PDT 24
Peak memory 200316 kb
Host smart-3c43008a-58d4-4feb-a1e1-248e293a8842
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1461745129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1461745129
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.537202493
Short name T291
Test name
Test status
Simulation time 656771381 ps
CPU time 35.57 seconds
Started Jul 10 05:10:27 PM PDT 24
Finished Jul 10 05:11:06 PM PDT 24
Peak memory 200340 kb
Host smart-8c52d430-d3b4-4f83-b4da-7022c01b35af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537202493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.537202493
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.354409552
Short name T313
Test name
Test status
Simulation time 43654359243 ps
CPU time 1387.99 seconds
Started Jul 10 05:10:23 PM PDT 24
Finished Jul 10 05:33:36 PM PDT 24
Peak memory 747576 kb
Host smart-973e867f-157a-4066-b2cc-3ed1f96538cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=354409552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.354409552
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.3492195486
Short name T240
Test name
Test status
Simulation time 13372208463 ps
CPU time 63.15 seconds
Started Jul 10 05:10:35 PM PDT 24
Finished Jul 10 05:11:41 PM PDT 24
Peak memory 200224 kb
Host smart-bf782c39-0e5d-44b9-a83a-2ff54b05c2fd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492195486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3492195486
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2128187696
Short name T432
Test name
Test status
Simulation time 2925896517 ps
CPU time 92.98 seconds
Started Jul 10 05:10:18 PM PDT 24
Finished Jul 10 05:11:56 PM PDT 24
Peak memory 200272 kb
Host smart-5d2e6fe2-82f1-4204-8be8-3ef58c7d20d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128187696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2128187696
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.630808680
Short name T191
Test name
Test status
Simulation time 929221337 ps
CPU time 10.31 seconds
Started Jul 10 05:10:27 PM PDT 24
Finished Jul 10 05:10:41 PM PDT 24
Peak memory 200248 kb
Host smart-82286624-24df-4b24-8432-51461c55e00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630808680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.630808680
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3036758159
Short name T209
Test name
Test status
Simulation time 9108883863 ps
CPU time 1008.46 seconds
Started Jul 10 05:10:26 PM PDT 24
Finished Jul 10 05:27:19 PM PDT 24
Peak memory 663032 kb
Host smart-05c7870b-e485-44d7-b00f-f06e597eecb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036758159 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3036758159
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1663584095
Short name T236
Test name
Test status
Simulation time 10020020655 ps
CPU time 39.99 seconds
Started Jul 10 05:10:24 PM PDT 24
Finished Jul 10 05:11:08 PM PDT 24
Peak memory 200276 kb
Host smart-1d176662-36cf-4ed5-a142-eec86c927a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663584095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1663584095
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.4080435879
Short name T29
Test name
Test status
Simulation time 11356199 ps
CPU time 0.6 seconds
Started Jul 10 05:10:20 PM PDT 24
Finished Jul 10 05:10:26 PM PDT 24
Peak memory 196184 kb
Host smart-51bacf34-d2b0-43e3-bf2e-84a1e05a9ba0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080435879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.4080435879
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.292852345
Short name T278
Test name
Test status
Simulation time 70420733 ps
CPU time 4.37 seconds
Started Jul 10 05:10:26 PM PDT 24
Finished Jul 10 05:10:35 PM PDT 24
Peak memory 200216 kb
Host smart-2e4ca128-83f2-4b46-974c-c4bf2cda6846
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=292852345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.292852345
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1771920481
Short name T494
Test name
Test status
Simulation time 153248988 ps
CPU time 7.12 seconds
Started Jul 10 05:10:21 PM PDT 24
Finished Jul 10 05:10:33 PM PDT 24
Peak memory 200216 kb
Host smart-608d92b1-1da3-4350-b7d2-dcf4515a51b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771920481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1771920481
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.4454129
Short name T506
Test name
Test status
Simulation time 2880893751 ps
CPU time 516.79 seconds
Started Jul 10 05:10:34 PM PDT 24
Finished Jul 10 05:19:14 PM PDT 24
Peak memory 665304 kb
Host smart-f43d96fe-6c3c-4a02-b9c0-ce0bdefb06c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4454129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.4454129
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1443291292
Short name T412
Test name
Test status
Simulation time 3474186771 ps
CPU time 80.79 seconds
Started Jul 10 05:10:22 PM PDT 24
Finished Jul 10 05:11:48 PM PDT 24
Peak memory 200332 kb
Host smart-8c805073-761e-433a-93d5-93bdb1507e2c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443291292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1443291292
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1790427887
Short name T258
Test name
Test status
Simulation time 4917996525 ps
CPU time 21.93 seconds
Started Jul 10 05:10:21 PM PDT 24
Finished Jul 10 05:10:48 PM PDT 24
Peak memory 200396 kb
Host smart-a06da177-d31e-4af2-a327-5d3319f5b4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790427887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1790427887
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2625506924
Short name T453
Test name
Test status
Simulation time 1611959195 ps
CPU time 13.34 seconds
Started Jul 10 05:10:26 PM PDT 24
Finished Jul 10 05:10:43 PM PDT 24
Peak memory 200220 kb
Host smart-87818ec0-717f-4774-8900-2dc9fdcf13a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625506924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2625506924
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3406425120
Short name T321
Test name
Test status
Simulation time 389571638834 ps
CPU time 2453.15 seconds
Started Jul 10 05:10:35 PM PDT 24
Finished Jul 10 05:51:31 PM PDT 24
Peak memory 731444 kb
Host smart-d2bbfc57-7a10-4d8a-aefb-60884ce23b4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406425120 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3406425120
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3273412532
Short name T360
Test name
Test status
Simulation time 2114315457 ps
CPU time 76.45 seconds
Started Jul 10 05:10:22 PM PDT 24
Finished Jul 10 05:11:43 PM PDT 24
Peak memory 200276 kb
Host smart-032339c7-6aa8-4c9a-ab1f-f6084c47d80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273412532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3273412532
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2777479642
Short name T3
Test name
Test status
Simulation time 100047039 ps
CPU time 0.57 seconds
Started Jul 10 05:10:21 PM PDT 24
Finished Jul 10 05:10:26 PM PDT 24
Peak memory 195776 kb
Host smart-732affdf-8882-4a5f-a7b0-b7ecdac9a428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777479642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2777479642
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3627117449
Short name T420
Test name
Test status
Simulation time 5038115132 ps
CPU time 71.95 seconds
Started Jul 10 05:10:27 PM PDT 24
Finished Jul 10 05:11:43 PM PDT 24
Peak memory 216636 kb
Host smart-8a71607f-a222-46fb-9baa-62a6c3bbe0b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3627117449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3627117449
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.230710490
Short name T491
Test name
Test status
Simulation time 2501728998 ps
CPU time 456.29 seconds
Started Jul 10 05:10:24 PM PDT 24
Finished Jul 10 05:18:05 PM PDT 24
Peak memory 676676 kb
Host smart-0f903ba1-c916-4189-b815-4b7dcc5d8785
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=230710490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.230710490
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.354706716
Short name T376
Test name
Test status
Simulation time 35608095389 ps
CPU time 123.12 seconds
Started Jul 10 05:10:34 PM PDT 24
Finished Jul 10 05:12:40 PM PDT 24
Peak memory 199932 kb
Host smart-3db90386-f869-487c-a0ee-d0f8ee78a4f8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354706716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.354706716
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2394824675
Short name T26
Test name
Test status
Simulation time 10507432864 ps
CPU time 197.92 seconds
Started Jul 10 05:10:35 PM PDT 24
Finished Jul 10 05:13:55 PM PDT 24
Peak memory 216616 kb
Host smart-9598fa66-7308-47b9-b98e-fc22ed238a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394824675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2394824675
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.24847050
Short name T363
Test name
Test status
Simulation time 302504016 ps
CPU time 12.76 seconds
Started Jul 10 05:10:35 PM PDT 24
Finished Jul 10 05:10:50 PM PDT 24
Peak memory 200212 kb
Host smart-39f8b713-f906-45cd-aaef-aa0855f4928f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24847050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.24847050
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.3710193500
Short name T413
Test name
Test status
Simulation time 240660394444 ps
CPU time 5652.83 seconds
Started Jul 10 05:10:26 PM PDT 24
Finished Jul 10 06:44:43 PM PDT 24
Peak memory 883284 kb
Host smart-baa2634d-4084-49f2-aa00-1bd7a4629130
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710193500 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.3710193500
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3089690977
Short name T198
Test name
Test status
Simulation time 1876309570 ps
CPU time 93.68 seconds
Started Jul 10 05:10:27 PM PDT 24
Finished Jul 10 05:12:04 PM PDT 24
Peak memory 200288 kb
Host smart-1c18fd09-a279-41e9-8cf9-1c06765496c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089690977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3089690977
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1814235561
Short name T177
Test name
Test status
Simulation time 49895722 ps
CPU time 0.6 seconds
Started Jul 10 05:10:26 PM PDT 24
Finished Jul 10 05:10:31 PM PDT 24
Peak memory 196080 kb
Host smart-2d002782-56b7-42e1-8c1b-499c97fec912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814235561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1814235561
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.88806370
Short name T227
Test name
Test status
Simulation time 1283526529 ps
CPU time 73.08 seconds
Started Jul 10 05:10:20 PM PDT 24
Finished Jul 10 05:11:38 PM PDT 24
Peak memory 200212 kb
Host smart-55326537-c7e3-4627-86c2-f16396e83f89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=88806370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.88806370
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.507072421
Short name T512
Test name
Test status
Simulation time 2128922261 ps
CPU time 43.18 seconds
Started Jul 10 05:10:26 PM PDT 24
Finished Jul 10 05:11:13 PM PDT 24
Peak memory 200308 kb
Host smart-6c67516c-59bd-4486-9aad-055baffcc157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507072421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.507072421
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2489898498
Short name T34
Test name
Test status
Simulation time 22382870145 ps
CPU time 702.82 seconds
Started Jul 10 05:10:34 PM PDT 24
Finished Jul 10 05:22:20 PM PDT 24
Peak memory 525300 kb
Host smart-49259848-7e01-43d4-9339-1f9f614bee36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2489898498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2489898498
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3592904556
Short name T146
Test name
Test status
Simulation time 18439963416 ps
CPU time 229.04 seconds
Started Jul 10 05:10:27 PM PDT 24
Finished Jul 10 05:14:19 PM PDT 24
Peak memory 200336 kb
Host smart-e8cf3f18-bc6e-4411-bab2-238d155aff36
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592904556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3592904556
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2993958307
Short name T235
Test name
Test status
Simulation time 11224218614 ps
CPU time 153.99 seconds
Started Jul 10 05:10:24 PM PDT 24
Finished Jul 10 05:13:02 PM PDT 24
Peak memory 200276 kb
Host smart-961568d8-1d48-470c-a0ef-adb2dfd73554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993958307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2993958307
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2588229240
Short name T510
Test name
Test status
Simulation time 4298238083 ps
CPU time 7.03 seconds
Started Jul 10 05:10:21 PM PDT 24
Finished Jul 10 05:10:33 PM PDT 24
Peak memory 200288 kb
Host smart-2627addc-16a7-45cc-a0b0-163f45078780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588229240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2588229240
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2275740301
Short name T329
Test name
Test status
Simulation time 44666132676 ps
CPU time 1874.36 seconds
Started Jul 10 05:10:27 PM PDT 24
Finished Jul 10 05:41:45 PM PDT 24
Peak memory 793296 kb
Host smart-3186c37a-e380-4bbd-8855-34c04b208473
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275740301 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2275740301
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.4112090237
Short name T490
Test name
Test status
Simulation time 2558484284 ps
CPU time 8.11 seconds
Started Jul 10 05:10:26 PM PDT 24
Finished Jul 10 05:10:38 PM PDT 24
Peak memory 200320 kb
Host smart-15c0bc85-a0d0-48d0-b19a-1fcf4153abfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112090237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.4112090237
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.252974912
Short name T454
Test name
Test status
Simulation time 24248034 ps
CPU time 0.59 seconds
Started Jul 10 05:10:27 PM PDT 24
Finished Jul 10 05:10:31 PM PDT 24
Peak memory 195744 kb
Host smart-9e34531f-3f8c-4d59-9f94-a80e247eb472
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252974912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.252974912
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1618908679
Short name T370
Test name
Test status
Simulation time 3933448133 ps
CPU time 118.99 seconds
Started Jul 10 05:10:29 PM PDT 24
Finished Jul 10 05:12:31 PM PDT 24
Peak memory 200336 kb
Host smart-e59aab11-d436-4b1d-8255-f713df0beeae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1618908679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1618908679
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2486606318
Short name T249
Test name
Test status
Simulation time 11791552625 ps
CPU time 59.76 seconds
Started Jul 10 05:10:25 PM PDT 24
Finished Jul 10 05:11:29 PM PDT 24
Peak memory 200368 kb
Host smart-99705442-1b47-4fa8-89dd-8e64562e1686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486606318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2486606318
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.1488386613
Short name T383
Test name
Test status
Simulation time 1067555299 ps
CPU time 73.75 seconds
Started Jul 10 05:10:32 PM PDT 24
Finished Jul 10 05:11:48 PM PDT 24
Peak memory 342656 kb
Host smart-72e7a840-cf48-4596-9009-f04643eb3263
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1488386613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.1488386613
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.722745587
Short name T133
Test name
Test status
Simulation time 8594692568 ps
CPU time 127.94 seconds
Started Jul 10 05:10:28 PM PDT 24
Finished Jul 10 05:12:39 PM PDT 24
Peak memory 200256 kb
Host smart-a4ab65b9-4a67-4d08-acb1-1b54101bb2b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722745587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.722745587
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3091424918
Short name T228
Test name
Test status
Simulation time 69999415736 ps
CPU time 205.08 seconds
Started Jul 10 05:10:31 PM PDT 24
Finished Jul 10 05:13:58 PM PDT 24
Peak memory 200396 kb
Host smart-c4b1d6a9-5cee-48d5-bee0-96dfa7c39dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091424918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3091424918
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.4221824459
Short name T194
Test name
Test status
Simulation time 2926839010 ps
CPU time 14.66 seconds
Started Jul 10 05:10:27 PM PDT 24
Finished Jul 10 05:10:46 PM PDT 24
Peak memory 200268 kb
Host smart-f6de0739-b630-41b5-a202-e0b5bfc9d7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221824459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.4221824459
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2603041079
Short name T289
Test name
Test status
Simulation time 90870106336 ps
CPU time 3671.7 seconds
Started Jul 10 05:10:27 PM PDT 24
Finished Jul 10 06:11:42 PM PDT 24
Peak memory 768332 kb
Host smart-b1df0908-fb45-43a9-b67f-1b6739a8defe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603041079 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2603041079
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.732194727
Short name T499
Test name
Test status
Simulation time 4248382091 ps
CPU time 23.98 seconds
Started Jul 10 05:10:27 PM PDT 24
Finished Jul 10 05:10:55 PM PDT 24
Peak memory 200312 kb
Host smart-cc232cee-b830-4148-af32-d6e5ca37d736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732194727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.732194727
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3102433798
Short name T261
Test name
Test status
Simulation time 50316485 ps
CPU time 0.59 seconds
Started Jul 10 05:10:27 PM PDT 24
Finished Jul 10 05:10:31 PM PDT 24
Peak memory 196184 kb
Host smart-8e149870-125b-4a2d-8617-dcbb3ef5193c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102433798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3102433798
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.449634882
Short name T398
Test name
Test status
Simulation time 4522371335 ps
CPU time 51.09 seconds
Started Jul 10 05:10:32 PM PDT 24
Finished Jul 10 05:11:25 PM PDT 24
Peak memory 208528 kb
Host smart-176ce669-a75e-482c-b19b-81be0f579150
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=449634882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.449634882
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3967129434
Short name T139
Test name
Test status
Simulation time 1555865819 ps
CPU time 20.59 seconds
Started Jul 10 05:10:28 PM PDT 24
Finished Jul 10 05:10:52 PM PDT 24
Peak memory 200240 kb
Host smart-3df5d523-41d0-481c-b11d-be9d2fc13b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967129434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3967129434
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.1522323474
Short name T130
Test name
Test status
Simulation time 35349094484 ps
CPU time 1250.65 seconds
Started Jul 10 05:10:29 PM PDT 24
Finished Jul 10 05:31:22 PM PDT 24
Peak memory 735576 kb
Host smart-96c5adf5-739b-48ec-9c10-a5c526bd1068
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1522323474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1522323474
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.4043586749
Short name T252
Test name
Test status
Simulation time 43338000924 ps
CPU time 199.74 seconds
Started Jul 10 05:10:32 PM PDT 24
Finished Jul 10 05:13:54 PM PDT 24
Peak memory 200292 kb
Host smart-69180d32-73e2-4758-96e0-7bf9f06ab447
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043586749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.4043586749
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2448050849
Short name T492
Test name
Test status
Simulation time 7003595457 ps
CPU time 57.64 seconds
Started Jul 10 05:10:28 PM PDT 24
Finished Jul 10 05:11:29 PM PDT 24
Peak memory 200420 kb
Host smart-c420dc89-3ca5-483d-8bdb-d5231dc030ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448050849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2448050849
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1677625883
Short name T204
Test name
Test status
Simulation time 834118641 ps
CPU time 4.93 seconds
Started Jul 10 05:10:27 PM PDT 24
Finished Jul 10 05:10:36 PM PDT 24
Peak memory 199916 kb
Host smart-46f518d2-2edf-41cc-9206-7f87ffdcb1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677625883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1677625883
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3532431327
Short name T343
Test name
Test status
Simulation time 129498465785 ps
CPU time 2289.72 seconds
Started Jul 10 05:10:31 PM PDT 24
Finished Jul 10 05:48:43 PM PDT 24
Peak memory 669240 kb
Host smart-a136a574-db4d-413c-83e9-70222f34ea70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532431327 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3532431327
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.446318048
Short name T331
Test name
Test status
Simulation time 1625534075 ps
CPU time 79.86 seconds
Started Jul 10 05:10:28 PM PDT 24
Finished Jul 10 05:11:51 PM PDT 24
Peak memory 200232 kb
Host smart-9d71918a-056b-4b4e-a605-503863d1310d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446318048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.446318048
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3327912978
Short name T520
Test name
Test status
Simulation time 23143977 ps
CPU time 0.59 seconds
Started Jul 10 05:10:33 PM PDT 24
Finished Jul 10 05:10:36 PM PDT 24
Peak memory 195076 kb
Host smart-59ce6373-a9f7-49c7-ae7c-d1700e26703a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327912978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3327912978
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1774345414
Short name T168
Test name
Test status
Simulation time 1275815129 ps
CPU time 67.08 seconds
Started Jul 10 05:10:35 PM PDT 24
Finished Jul 10 05:11:44 PM PDT 24
Peak memory 200288 kb
Host smart-8c3c0044-6f39-49cd-a7fd-a041f649e43e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1774345414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1774345414
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3433428742
Short name T357
Test name
Test status
Simulation time 1507498276 ps
CPU time 36.55 seconds
Started Jul 10 05:10:33 PM PDT 24
Finished Jul 10 05:11:11 PM PDT 24
Peak memory 200216 kb
Host smart-f8ae0ffd-0bf9-4aff-821c-f7a84f483992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433428742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3433428742
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3170407327
Short name T380
Test name
Test status
Simulation time 1478636467 ps
CPU time 234.15 seconds
Started Jul 10 05:10:31 PM PDT 24
Finished Jul 10 05:14:27 PM PDT 24
Peak memory 455180 kb
Host smart-079f6dea-759c-4b59-8d4e-b63fb7d55ea5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3170407327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3170407327
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1112542331
Short name T416
Test name
Test status
Simulation time 7857338850 ps
CPU time 141.39 seconds
Started Jul 10 05:10:37 PM PDT 24
Finished Jul 10 05:13:00 PM PDT 24
Peak memory 200336 kb
Host smart-673344cf-c712-4bcd-bdb5-0165196821f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112542331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1112542331
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2881808974
Short name T49
Test name
Test status
Simulation time 1803706647 ps
CPU time 100.85 seconds
Started Jul 10 05:10:34 PM PDT 24
Finished Jul 10 05:12:17 PM PDT 24
Peak memory 200292 kb
Host smart-8d04c5a0-ad3a-4f33-91d9-5773c994e930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881808974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2881808974
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.1384306711
Short name T1
Test name
Test status
Simulation time 326290638 ps
CPU time 1.62 seconds
Started Jul 10 05:10:28 PM PDT 24
Finished Jul 10 05:10:33 PM PDT 24
Peak memory 200232 kb
Host smart-c93b4b8a-93cd-4e81-9096-d9a8936b725f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384306711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1384306711
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3592701174
Short name T418
Test name
Test status
Simulation time 7251269799 ps
CPU time 112.37 seconds
Started Jul 10 05:10:33 PM PDT 24
Finished Jul 10 05:12:27 PM PDT 24
Peak memory 200452 kb
Host smart-d22db2de-356a-4a6b-9730-c50c28d1bb3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592701174 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3592701174
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3855302540
Short name T426
Test name
Test status
Simulation time 16623517109 ps
CPU time 76.91 seconds
Started Jul 10 05:10:33 PM PDT 24
Finished Jul 10 05:11:52 PM PDT 24
Peak memory 200352 kb
Host smart-8615ebc8-c109-465e-8bb0-db078d485778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855302540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3855302540
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2011001403
Short name T417
Test name
Test status
Simulation time 22323470 ps
CPU time 0.58 seconds
Started Jul 10 05:10:36 PM PDT 24
Finished Jul 10 05:10:39 PM PDT 24
Peak memory 195828 kb
Host smart-12d8d4b4-12e9-4ed3-b514-e5725bf25100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011001403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2011001403
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1404289282
Short name T339
Test name
Test status
Simulation time 1413217610 ps
CPU time 83.43 seconds
Started Jul 10 05:10:32 PM PDT 24
Finished Jul 10 05:11:58 PM PDT 24
Peak memory 200288 kb
Host smart-cc79b82b-ddd0-48a5-88ed-c143c34d6f81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1404289282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1404289282
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3490115437
Short name T271
Test name
Test status
Simulation time 1526567914 ps
CPU time 20.09 seconds
Started Jul 10 05:10:37 PM PDT 24
Finished Jul 10 05:10:59 PM PDT 24
Peak memory 200292 kb
Host smart-388041b4-1be1-45dd-a9cc-2e878d787288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490115437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3490115437
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2261874826
Short name T35
Test name
Test status
Simulation time 7203143135 ps
CPU time 1425.42 seconds
Started Jul 10 05:10:31 PM PDT 24
Finished Jul 10 05:34:18 PM PDT 24
Peak memory 792228 kb
Host smart-d972a0fd-6cc9-4573-9b4d-d2ba366e1d88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2261874826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2261874826
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.3484042179
Short name T306
Test name
Test status
Simulation time 2896690947 ps
CPU time 34.57 seconds
Started Jul 10 05:10:35 PM PDT 24
Finished Jul 10 05:11:12 PM PDT 24
Peak memory 200256 kb
Host smart-b434b1eb-e49f-47d4-bffe-d8a708cf4f2d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484042179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.3484042179
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1349588019
Short name T513
Test name
Test status
Simulation time 4551865251 ps
CPU time 58.65 seconds
Started Jul 10 05:10:35 PM PDT 24
Finished Jul 10 05:11:36 PM PDT 24
Peak memory 200348 kb
Host smart-55ecfaea-381f-46e9-8af8-534246e12869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349588019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1349588019
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3296117351
Short name T388
Test name
Test status
Simulation time 975353584 ps
CPU time 4.52 seconds
Started Jul 10 05:10:35 PM PDT 24
Finished Jul 10 05:10:42 PM PDT 24
Peak memory 200296 kb
Host smart-8941242f-a3e9-4cf8-bb91-1c853467b4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296117351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3296117351
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3476216049
Short name T325
Test name
Test status
Simulation time 42343877659 ps
CPU time 3916.23 seconds
Started Jul 10 05:10:33 PM PDT 24
Finished Jul 10 06:15:51 PM PDT 24
Peak memory 857532 kb
Host smart-6d28a9dd-df08-47f3-ba57-4570e82c2df0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476216049 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3476216049
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3093586827
Short name T125
Test name
Test status
Simulation time 3071906407 ps
CPU time 34.59 seconds
Started Jul 10 05:10:34 PM PDT 24
Finished Jul 10 05:11:11 PM PDT 24
Peak memory 200276 kb
Host smart-14f7e81f-d022-4ce7-92cf-35a7e477347e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093586827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3093586827
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2874707790
Short name T431
Test name
Test status
Simulation time 13218853 ps
CPU time 0.59 seconds
Started Jul 10 05:10:31 PM PDT 24
Finished Jul 10 05:10:33 PM PDT 24
Peak memory 195076 kb
Host smart-ce6ead45-ec4c-4c71-85e9-b33716da6ba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874707790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2874707790
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.1271978798
Short name T369
Test name
Test status
Simulation time 9847412669 ps
CPU time 78.67 seconds
Started Jul 10 05:10:41 PM PDT 24
Finished Jul 10 05:12:01 PM PDT 24
Peak memory 200260 kb
Host smart-21d657e7-d8c1-4021-bfc6-99b69d2a53a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1271978798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1271978798
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.232347290
Short name T138
Test name
Test status
Simulation time 6966409113 ps
CPU time 48.55 seconds
Started Jul 10 05:10:36 PM PDT 24
Finished Jul 10 05:11:27 PM PDT 24
Peak memory 200372 kb
Host smart-be512267-fb34-44dd-ac45-1bb462f4e008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232347290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.232347290
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2227662216
Short name T25
Test name
Test status
Simulation time 4045618009 ps
CPU time 145.85 seconds
Started Jul 10 05:10:40 PM PDT 24
Finished Jul 10 05:13:07 PM PDT 24
Peak memory 384540 kb
Host smart-61afdf41-4137-47b4-b616-428118c706c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2227662216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2227662216
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2828369861
Short name T224
Test name
Test status
Simulation time 277852383 ps
CPU time 15.7 seconds
Started Jul 10 05:10:34 PM PDT 24
Finished Jul 10 05:10:52 PM PDT 24
Peak memory 200196 kb
Host smart-0bf64081-08a3-47f6-95f6-e9a447401669
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828369861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2828369861
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1475163041
Short name T449
Test name
Test status
Simulation time 10510645204 ps
CPU time 42.35 seconds
Started Jul 10 05:10:32 PM PDT 24
Finished Jul 10 05:11:16 PM PDT 24
Peak memory 200288 kb
Host smart-cea36beb-bbe6-47e7-a392-c70366a36fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475163041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1475163041
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1298887123
Short name T353
Test name
Test status
Simulation time 320001328 ps
CPU time 5.67 seconds
Started Jul 10 05:10:33 PM PDT 24
Finished Jul 10 05:10:40 PM PDT 24
Peak memory 200348 kb
Host smart-9be3c108-308d-4fd9-80e8-d911b947e3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298887123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1298887123
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1254403230
Short name T423
Test name
Test status
Simulation time 41297215698 ps
CPU time 3427.11 seconds
Started Jul 10 05:10:34 PM PDT 24
Finished Jul 10 06:07:44 PM PDT 24
Peak memory 793076 kb
Host smart-9ea0d794-6951-40eb-8826-11ac96abf521
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254403230 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1254403230
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.649627885
Short name T262
Test name
Test status
Simulation time 40640013591 ps
CPU time 126.33 seconds
Started Jul 10 05:10:32 PM PDT 24
Finished Jul 10 05:12:41 PM PDT 24
Peak memory 200396 kb
Host smart-7abec7d8-47f0-4fd7-98d7-12440cafc17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649627885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.649627885
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3629380313
Short name T519
Test name
Test status
Simulation time 21856757 ps
CPU time 0.61 seconds
Started Jul 10 05:10:02 PM PDT 24
Finished Jul 10 05:10:08 PM PDT 24
Peak memory 196108 kb
Host smart-a90547cf-f70f-43a1-b7c3-8a9d71476687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629380313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3629380313
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3176684113
Short name T515
Test name
Test status
Simulation time 645263229 ps
CPU time 27.5 seconds
Started Jul 10 05:09:58 PM PDT 24
Finished Jul 10 05:10:33 PM PDT 24
Peak memory 200240 kb
Host smart-35455811-2357-4b5e-99a7-3cfb8d801881
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3176684113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3176684113
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1810469462
Short name T337
Test name
Test status
Simulation time 11028910783 ps
CPU time 34.35 seconds
Started Jul 10 05:10:05 PM PDT 24
Finished Jul 10 05:10:44 PM PDT 24
Peak memory 200256 kb
Host smart-cfc57ec0-3b6b-4b8b-8abc-de87a9339787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810469462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1810469462
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.4069755853
Short name T425
Test name
Test status
Simulation time 1647015064 ps
CPU time 130.37 seconds
Started Jul 10 05:09:58 PM PDT 24
Finished Jul 10 05:12:15 PM PDT 24
Peak memory 431100 kb
Host smart-989a66f4-5e78-495b-ac43-c899aed4d895
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4069755853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.4069755853
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1904589474
Short name T66
Test name
Test status
Simulation time 4352091034 ps
CPU time 54.25 seconds
Started Jul 10 05:10:07 PM PDT 24
Finished Jul 10 05:11:07 PM PDT 24
Peak memory 200320 kb
Host smart-771fd86c-ca0d-4510-a259-ac8236841330
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904589474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1904589474
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3164449456
Short name T154
Test name
Test status
Simulation time 14022649760 ps
CPU time 115.07 seconds
Started Jul 10 05:09:54 PM PDT 24
Finished Jul 10 05:11:57 PM PDT 24
Peak memory 200272 kb
Host smart-f256cc89-0d4b-47aa-a54d-2d4e5d427ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164449456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3164449456
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1613816896
Short name T45
Test name
Test status
Simulation time 822274727 ps
CPU time 1.01 seconds
Started Jul 10 05:10:05 PM PDT 24
Finished Jul 10 05:10:11 PM PDT 24
Peak memory 219420 kb
Host smart-fa6224d0-2050-4523-ae59-7a6ae6dce548
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613816896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1613816896
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.4206679469
Short name T112
Test name
Test status
Simulation time 1822627376 ps
CPU time 15.74 seconds
Started Jul 10 05:10:07 PM PDT 24
Finished Jul 10 05:10:28 PM PDT 24
Peak memory 200192 kb
Host smart-2b4f4849-c2b8-4c2c-a0eb-0c52b27145e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206679469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.4206679469
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3303454499
Short name T70
Test name
Test status
Simulation time 1765920366 ps
CPU time 20.78 seconds
Started Jul 10 05:10:06 PM PDT 24
Finished Jul 10 05:10:32 PM PDT 24
Peak memory 200292 kb
Host smart-e1a67633-c62b-4eff-837d-43f0b28a3f06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303454499 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3303454499
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.1615996849
Short name T55
Test name
Test status
Simulation time 56342376166 ps
CPU time 2003.42 seconds
Started Jul 10 05:10:05 PM PDT 24
Finished Jul 10 05:43:34 PM PDT 24
Peak memory 737020 kb
Host smart-b39daf9a-c0a0-4950-9d6f-09e560475c4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1615996849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.1615996849
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.3075541913
Short name T372
Test name
Test status
Simulation time 6634548522 ps
CPU time 68.94 seconds
Started Jul 10 05:10:06 PM PDT 24
Finished Jul 10 05:11:20 PM PDT 24
Peak memory 200340 kb
Host smart-5c6ab644-7a42-41e5-a9fe-45e73dcd9e41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3075541913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3075541913
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.1036667523
Short name T31
Test name
Test status
Simulation time 22350987048 ps
CPU time 66.78 seconds
Started Jul 10 05:10:02 PM PDT 24
Finished Jul 10 05:11:15 PM PDT 24
Peak memory 200328 kb
Host smart-a16fee1d-d5de-4d58-bc44-a23be2d4ddd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1036667523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.1036667523
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.558830151
Short name T281
Test name
Test status
Simulation time 2061997717 ps
CPU time 69.54 seconds
Started Jul 10 05:10:07 PM PDT 24
Finished Jul 10 05:11:22 PM PDT 24
Peak memory 200488 kb
Host smart-9771346a-8f56-4104-8335-7eb7b3c8dba2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=558830151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.558830151
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.230937707
Short name T384
Test name
Test status
Simulation time 103953592128 ps
CPU time 658.14 seconds
Started Jul 10 05:09:57 PM PDT 24
Finished Jul 10 05:21:02 PM PDT 24
Peak memory 200336 kb
Host smart-6946434d-f178-4b74-a754-4b60d8e204fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=230937707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.230937707
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.3525433729
Short name T229
Test name
Test status
Simulation time 279186596863 ps
CPU time 2216.93 seconds
Started Jul 10 05:10:05 PM PDT 24
Finished Jul 10 05:47:07 PM PDT 24
Peak memory 216764 kb
Host smart-25f1b9d7-64a6-421d-9350-3c1941565fdf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3525433729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.3525433729
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.1758963748
Short name T320
Test name
Test status
Simulation time 38565580556 ps
CPU time 2089.67 seconds
Started Jul 10 05:10:05 PM PDT 24
Finished Jul 10 05:44:59 PM PDT 24
Peak memory 216040 kb
Host smart-2d8f6ab7-d666-465d-8b1d-961ae97f2bc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1758963748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1758963748
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1404465160
Short name T47
Test name
Test status
Simulation time 412229178 ps
CPU time 20.4 seconds
Started Jul 10 05:09:54 PM PDT 24
Finished Jul 10 05:10:22 PM PDT 24
Peak memory 200212 kb
Host smart-73f1fd37-29b9-4cc0-b583-59a137a19d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404465160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1404465160
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1631216391
Short name T471
Test name
Test status
Simulation time 20390734 ps
CPU time 0.58 seconds
Started Jul 10 05:10:41 PM PDT 24
Finished Jul 10 05:10:43 PM PDT 24
Peak memory 195076 kb
Host smart-50c80102-a10d-4810-8a81-107ac996533a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631216391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1631216391
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.457117168
Short name T385
Test name
Test status
Simulation time 2826396022 ps
CPU time 39.36 seconds
Started Jul 10 05:10:36 PM PDT 24
Finished Jul 10 05:11:17 PM PDT 24
Peak memory 200348 kb
Host smart-d9c2cf3c-f44f-469f-bd82-f0acc1d781df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=457117168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.457117168
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2833341648
Short name T243
Test name
Test status
Simulation time 3616272304 ps
CPU time 47.44 seconds
Started Jul 10 05:10:35 PM PDT 24
Finished Jul 10 05:11:24 PM PDT 24
Peak memory 200332 kb
Host smart-276d29d7-93d2-4b18-aa02-7684557ff9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833341648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2833341648
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.878102575
Short name T408
Test name
Test status
Simulation time 25689962950 ps
CPU time 323.86 seconds
Started Jul 10 05:10:41 PM PDT 24
Finished Jul 10 05:16:07 PM PDT 24
Peak memory 463056 kb
Host smart-6936fbc0-5df8-4ac3-840f-89bd1318a726
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=878102575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.878102575
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2660720693
Short name T2
Test name
Test status
Simulation time 18235982954 ps
CPU time 174.59 seconds
Started Jul 10 05:10:35 PM PDT 24
Finished Jul 10 05:13:32 PM PDT 24
Peak memory 200376 kb
Host smart-f0f6252c-5fb7-4f5a-8cfb-3700136a5a3c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660720693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2660720693
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.112828615
Short name T152
Test name
Test status
Simulation time 106937984026 ps
CPU time 96.99 seconds
Started Jul 10 05:10:34 PM PDT 24
Finished Jul 10 05:12:13 PM PDT 24
Peak memory 200412 kb
Host smart-20b031f5-905a-425e-a0fe-52e576e630ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112828615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.112828615
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1539030018
Short name T268
Test name
Test status
Simulation time 756412095 ps
CPU time 9.57 seconds
Started Jul 10 05:10:36 PM PDT 24
Finished Jul 10 05:10:48 PM PDT 24
Peak memory 200264 kb
Host smart-9c2b810f-fcd8-46a4-8d6b-633873464e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539030018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1539030018
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.79345872
Short name T140
Test name
Test status
Simulation time 66207999476 ps
CPU time 1725.81 seconds
Started Jul 10 05:10:32 PM PDT 24
Finished Jul 10 05:39:19 PM PDT 24
Peak memory 533572 kb
Host smart-0baea377-c1d7-45a2-81ee-5fd410fcd424
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79345872 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.79345872
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.254268847
Short name T272
Test name
Test status
Simulation time 89307889532 ps
CPU time 110.69 seconds
Started Jul 10 05:10:35 PM PDT 24
Finished Jul 10 05:12:28 PM PDT 24
Peak memory 200340 kb
Host smart-5c21de46-2be4-455e-8062-db56219642c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254268847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.254268847
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1757159360
Short name T305
Test name
Test status
Simulation time 43302181 ps
CPU time 0.56 seconds
Started Jul 10 05:10:37 PM PDT 24
Finished Jul 10 05:10:39 PM PDT 24
Peak memory 195076 kb
Host smart-4f93c097-f451-426a-acb9-7593f4749a85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757159360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1757159360
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.2314268379
Short name T233
Test name
Test status
Simulation time 4712312007 ps
CPU time 48.61 seconds
Started Jul 10 05:10:39 PM PDT 24
Finished Jul 10 05:11:29 PM PDT 24
Peak memory 200304 kb
Host smart-b51aa9e0-e278-4f6b-be26-b896541d122a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2314268379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2314268379
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2341342164
Short name T212
Test name
Test status
Simulation time 258444676 ps
CPU time 1.69 seconds
Started Jul 10 05:10:42 PM PDT 24
Finished Jul 10 05:10:46 PM PDT 24
Peak memory 200440 kb
Host smart-9a74bd93-e4aa-478b-a054-86c953432453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341342164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2341342164
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2701657106
Short name T115
Test name
Test status
Simulation time 37502655190 ps
CPU time 405.97 seconds
Started Jul 10 05:10:32 PM PDT 24
Finished Jul 10 05:17:19 PM PDT 24
Peak memory 625820 kb
Host smart-d81a8cfc-d6d5-4153-a145-1e011f21b796
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2701657106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2701657106
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.339602431
Short name T441
Test name
Test status
Simulation time 13888528454 ps
CPU time 186.11 seconds
Started Jul 10 05:10:39 PM PDT 24
Finished Jul 10 05:13:47 PM PDT 24
Peak memory 200260 kb
Host smart-28fde455-5c77-42f9-8d8f-12017c52e2c7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339602431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.339602431
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.3503983436
Short name T303
Test name
Test status
Simulation time 15441165991 ps
CPU time 138.9 seconds
Started Jul 10 05:10:34 PM PDT 24
Finished Jul 10 05:12:56 PM PDT 24
Peak memory 200356 kb
Host smart-b61564b0-dae4-4ef6-a322-5cc74445b0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503983436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3503983436
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3519736406
Short name T479
Test name
Test status
Simulation time 576578238 ps
CPU time 3.22 seconds
Started Jul 10 05:10:40 PM PDT 24
Finished Jul 10 05:10:45 PM PDT 24
Peak memory 200504 kb
Host smart-fe9bca8a-3f72-42ed-8c4e-7372e27793b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519736406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3519736406
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2229725333
Short name T69
Test name
Test status
Simulation time 208358507100 ps
CPU time 2723.55 seconds
Started Jul 10 05:10:42 PM PDT 24
Finished Jul 10 05:56:07 PM PDT 24
Peak memory 771384 kb
Host smart-2d367bee-5944-45f0-841e-7ba76ee1de1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229725333 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2229725333
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.366801781
Short name T79
Test name
Test status
Simulation time 6321025331 ps
CPU time 74.95 seconds
Started Jul 10 05:10:39 PM PDT 24
Finished Jul 10 05:11:55 PM PDT 24
Peak memory 200320 kb
Host smart-b6cd5522-76e2-48c8-9018-29524779645d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366801781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.366801781
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1994953951
Short name T41
Test name
Test status
Simulation time 140051863 ps
CPU time 0.58 seconds
Started Jul 10 05:10:41 PM PDT 24
Finished Jul 10 05:10:43 PM PDT 24
Peak memory 196104 kb
Host smart-2e1cc894-fc8a-404f-aa0b-4358b70cb9fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994953951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1994953951
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.481602078
Short name T15
Test name
Test status
Simulation time 16345678991 ps
CPU time 64.65 seconds
Started Jul 10 05:10:37 PM PDT 24
Finished Jul 10 05:11:43 PM PDT 24
Peak memory 200420 kb
Host smart-fbecf3aa-8d1b-4eb4-a4d2-074d2714e19c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=481602078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.481602078
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1511573273
Short name T269
Test name
Test status
Simulation time 3723125341 ps
CPU time 13.25 seconds
Started Jul 10 05:10:37 PM PDT 24
Finished Jul 10 05:10:53 PM PDT 24
Peak memory 200372 kb
Host smart-97b763b7-3d84-4e30-ac99-d2180df4a20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511573273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1511573273
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3466188891
Short name T465
Test name
Test status
Simulation time 799296800 ps
CPU time 156.68 seconds
Started Jul 10 05:10:39 PM PDT 24
Finished Jul 10 05:13:17 PM PDT 24
Peak memory 469368 kb
Host smart-adb33cfb-7e91-4813-bc78-d03b902c63ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3466188891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3466188891
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.993839722
Short name T59
Test name
Test status
Simulation time 5421007632 ps
CPU time 144.77 seconds
Started Jul 10 05:10:42 PM PDT 24
Finished Jul 10 05:13:09 PM PDT 24
Peak memory 200336 kb
Host smart-b81284b9-221c-485c-b8db-3b4ef84b2e1b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993839722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.993839722
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3611312952
Short name T345
Test name
Test status
Simulation time 9884497165 ps
CPU time 83.18 seconds
Started Jul 10 05:10:42 PM PDT 24
Finished Jul 10 05:12:07 PM PDT 24
Peak memory 200368 kb
Host smart-3a169154-a3f7-4756-8c1f-5f37f35abb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611312952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3611312952
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1641854041
Short name T315
Test name
Test status
Simulation time 2067985573 ps
CPU time 8.97 seconds
Started Jul 10 05:10:36 PM PDT 24
Finished Jul 10 05:10:48 PM PDT 24
Peak memory 200340 kb
Host smart-2628a8eb-d1d8-4da4-9e34-20b5ccb946ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641854041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1641854041
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3467923401
Short name T468
Test name
Test status
Simulation time 42689082975 ps
CPU time 286.56 seconds
Started Jul 10 05:10:40 PM PDT 24
Finished Jul 10 05:15:29 PM PDT 24
Peak memory 200248 kb
Host smart-301da192-b073-45c3-bb44-2d5940fd45cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467923401 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3467923401
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1817049640
Short name T469
Test name
Test status
Simulation time 5064652257 ps
CPU time 91.5 seconds
Started Jul 10 05:10:44 PM PDT 24
Finished Jul 10 05:12:17 PM PDT 24
Peak memory 200280 kb
Host smart-a9feb303-c63a-4340-921a-337596f30c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817049640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1817049640
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3755853474
Short name T403
Test name
Test status
Simulation time 13223284 ps
CPU time 0.6 seconds
Started Jul 10 05:10:39 PM PDT 24
Finished Jul 10 05:10:41 PM PDT 24
Peak memory 195828 kb
Host smart-c84c16db-f529-4f98-a037-6e3fa70c40c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755853474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3755853474
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.4087494148
Short name T415
Test name
Test status
Simulation time 366555411 ps
CPU time 22.66 seconds
Started Jul 10 05:10:44 PM PDT 24
Finished Jul 10 05:11:09 PM PDT 24
Peak memory 200272 kb
Host smart-ddff4ab2-e6b0-4553-a0eb-ec0b91de4eca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4087494148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.4087494148
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1571755189
Short name T326
Test name
Test status
Simulation time 642306135 ps
CPU time 34.01 seconds
Started Jul 10 05:10:40 PM PDT 24
Finished Jul 10 05:11:16 PM PDT 24
Peak memory 200240 kb
Host smart-3c4826d2-a9d5-4fc5-aa91-338bed7bf86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571755189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1571755189
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.820491265
Short name T402
Test name
Test status
Simulation time 15165542454 ps
CPU time 732.44 seconds
Started Jul 10 05:10:42 PM PDT 24
Finished Jul 10 05:22:56 PM PDT 24
Peak memory 718008 kb
Host smart-bf0bf5a0-52bf-4573-8284-5c375aade462
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=820491265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.820491265
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1367358965
Short name T498
Test name
Test status
Simulation time 2821228306 ps
CPU time 84.19 seconds
Started Jul 10 05:10:43 PM PDT 24
Finished Jul 10 05:12:09 PM PDT 24
Peak memory 200360 kb
Host smart-ce173822-2ace-4ce8-be49-d6b18cf4f191
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367358965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1367358965
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.2009380322
Short name T324
Test name
Test status
Simulation time 8239312419 ps
CPU time 109.97 seconds
Started Jul 10 05:10:40 PM PDT 24
Finished Jul 10 05:12:31 PM PDT 24
Peak memory 200356 kb
Host smart-38caa9ce-33f8-4072-ba12-be451750f9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009380322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.2009380322
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.752370659
Short name T349
Test name
Test status
Simulation time 955424801 ps
CPU time 3.45 seconds
Started Jul 10 05:10:47 PM PDT 24
Finished Jul 10 05:10:53 PM PDT 24
Peak memory 200288 kb
Host smart-fc46629c-11fc-4d2c-ba4a-dba5bef3f734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752370659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.752370659
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1624612112
Short name T17
Test name
Test status
Simulation time 8460093157 ps
CPU time 109.05 seconds
Started Jul 10 05:10:42 PM PDT 24
Finished Jul 10 05:12:33 PM PDT 24
Peak memory 200336 kb
Host smart-6463397f-bdd1-423d-bd66-15bb0bde4d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624612112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1624612112
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.550135384
Short name T40
Test name
Test status
Simulation time 13130088 ps
CPU time 0.58 seconds
Started Jul 10 05:10:44 PM PDT 24
Finished Jul 10 05:10:47 PM PDT 24
Peak memory 196784 kb
Host smart-9ccde8a9-0b61-429f-af07-8ec5f2750b21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550135384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.550135384
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2340107062
Short name T176
Test name
Test status
Simulation time 427800673 ps
CPU time 26.96 seconds
Started Jul 10 05:10:40 PM PDT 24
Finished Jul 10 05:11:09 PM PDT 24
Peak memory 200228 kb
Host smart-2628de8e-6d2d-45fa-bc2b-f034a5c0ba76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2340107062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2340107062
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2978089825
Short name T214
Test name
Test status
Simulation time 686648905 ps
CPU time 8.94 seconds
Started Jul 10 05:10:37 PM PDT 24
Finished Jul 10 05:10:48 PM PDT 24
Peak memory 200232 kb
Host smart-7e9db756-56ec-4988-a1dc-2e619f202652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978089825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2978089825
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.1902578666
Short name T187
Test name
Test status
Simulation time 353430676 ps
CPU time 68.81 seconds
Started Jul 10 05:10:47 PM PDT 24
Finished Jul 10 05:11:58 PM PDT 24
Peak memory 393220 kb
Host smart-86c86cd3-e50e-4638-9645-7e4305b0234e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1902578666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.1902578666
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.3055052926
Short name T392
Test name
Test status
Simulation time 2758993067 ps
CPU time 160.36 seconds
Started Jul 10 05:10:42 PM PDT 24
Finished Jul 10 05:13:23 PM PDT 24
Peak memory 200388 kb
Host smart-40a9595c-50cb-4b13-9f5a-615ece89503b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055052926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.3055052926
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.4156857675
Short name T242
Test name
Test status
Simulation time 5116545996 ps
CPU time 132.52 seconds
Started Jul 10 05:10:45 PM PDT 24
Finished Jul 10 05:13:00 PM PDT 24
Peak memory 200280 kb
Host smart-157dbef8-461d-47b0-ad97-14b47afb9f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156857675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.4156857675
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3059754387
Short name T508
Test name
Test status
Simulation time 580655757 ps
CPU time 12.11 seconds
Started Jul 10 05:10:40 PM PDT 24
Finished Jul 10 05:10:54 PM PDT 24
Peak memory 200340 kb
Host smart-40a65302-c50b-4c55-9925-bb9a03b7d56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059754387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3059754387
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.848254605
Short name T77
Test name
Test status
Simulation time 45207069168 ps
CPU time 54.85 seconds
Started Jul 10 05:10:37 PM PDT 24
Finished Jul 10 05:11:34 PM PDT 24
Peak memory 200344 kb
Host smart-16fb0cde-cbd3-4d15-82ce-2f2af30e91a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848254605 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.848254605
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3181534339
Short name T448
Test name
Test status
Simulation time 14891016940 ps
CPU time 131.42 seconds
Started Jul 10 05:10:45 PM PDT 24
Finished Jul 10 05:12:59 PM PDT 24
Peak memory 200356 kb
Host smart-25b42d39-7040-4854-84bc-90716c029cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181534339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3181534339
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.4123612669
Short name T503
Test name
Test status
Simulation time 21902598 ps
CPU time 0.62 seconds
Started Jul 10 05:10:45 PM PDT 24
Finished Jul 10 05:10:48 PM PDT 24
Peak memory 195152 kb
Host smart-fb4babde-5229-4fed-94ab-b1accd3cb2ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123612669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.4123612669
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.827162694
Short name T460
Test name
Test status
Simulation time 5448553246 ps
CPU time 78.02 seconds
Started Jul 10 05:10:37 PM PDT 24
Finished Jul 10 05:11:57 PM PDT 24
Peak memory 200512 kb
Host smart-9c276164-e019-4420-9b41-b3afbb96e03f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=827162694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.827162694
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1518765976
Short name T118
Test name
Test status
Simulation time 2224065769 ps
CPU time 29.32 seconds
Started Jul 10 05:10:45 PM PDT 24
Finished Jul 10 05:11:16 PM PDT 24
Peak memory 200280 kb
Host smart-75448c47-3662-429a-b026-9d016b90246e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518765976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1518765976
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2952815121
Short name T184
Test name
Test status
Simulation time 2404331038 ps
CPU time 387.96 seconds
Started Jul 10 05:10:44 PM PDT 24
Finished Jul 10 05:17:15 PM PDT 24
Peak memory 627332 kb
Host smart-81a338ab-157f-4ca0-b57d-f9484fe9cf42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2952815121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2952815121
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3329562034
Short name T241
Test name
Test status
Simulation time 2444446593 ps
CPU time 131.5 seconds
Started Jul 10 05:10:42 PM PDT 24
Finished Jul 10 05:12:55 PM PDT 24
Peak memory 200288 kb
Host smart-cbd4d3f8-a203-4a5e-b2c3-952207e96c92
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329562034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3329562034
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3450116210
Short name T6
Test name
Test status
Simulation time 1489367059 ps
CPU time 36.16 seconds
Started Jul 10 05:10:38 PM PDT 24
Finished Jul 10 05:11:16 PM PDT 24
Peak memory 200204 kb
Host smart-809498b8-5558-45e6-9e5e-4eba0972213d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450116210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3450116210
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3721640193
Short name T226
Test name
Test status
Simulation time 1204589148 ps
CPU time 14.84 seconds
Started Jul 10 05:10:45 PM PDT 24
Finished Jul 10 05:11:03 PM PDT 24
Peak memory 200280 kb
Host smart-bf6ed415-3000-4808-877e-98e214fdc0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721640193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3721640193
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1319830139
Short name T208
Test name
Test status
Simulation time 55370834654 ps
CPU time 111.24 seconds
Started Jul 10 05:10:46 PM PDT 24
Finished Jul 10 05:12:39 PM PDT 24
Peak memory 200256 kb
Host smart-4cd41d5d-023c-42c3-8610-1f772d4cf236
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319830139 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1319830139
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2558560730
Short name T419
Test name
Test status
Simulation time 1563132029 ps
CPU time 77.63 seconds
Started Jul 10 05:10:43 PM PDT 24
Finished Jul 10 05:12:03 PM PDT 24
Peak memory 200252 kb
Host smart-2586f299-7983-4853-a527-0db89f0d32e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558560730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2558560730
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2355084138
Short name T158
Test name
Test status
Simulation time 49535112 ps
CPU time 0.6 seconds
Started Jul 10 05:10:43 PM PDT 24
Finished Jul 10 05:10:46 PM PDT 24
Peak memory 196116 kb
Host smart-6fb9c89b-6b99-4d12-a8bc-386d81f7172e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355084138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2355084138
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2740495445
Short name T193
Test name
Test status
Simulation time 6068092964 ps
CPU time 88.76 seconds
Started Jul 10 05:10:42 PM PDT 24
Finished Jul 10 05:12:13 PM PDT 24
Peak memory 200624 kb
Host smart-bd96b88b-dd64-4021-a2e2-0c9b57848ec4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2740495445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2740495445
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.412201226
Short name T495
Test name
Test status
Simulation time 20895817289 ps
CPU time 57.07 seconds
Started Jul 10 05:10:45 PM PDT 24
Finished Jul 10 05:11:45 PM PDT 24
Peak memory 208620 kb
Host smart-070bb6f0-a6a7-47b3-a5d0-ae97cf6b828a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412201226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.412201226
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.4096882490
Short name T434
Test name
Test status
Simulation time 64589103 ps
CPU time 0.84 seconds
Started Jul 10 05:10:37 PM PDT 24
Finished Jul 10 05:10:40 PM PDT 24
Peak memory 199024 kb
Host smart-e673fa61-bac6-4bba-9a1f-1c32d8156f1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4096882490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.4096882490
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.451363405
Short name T160
Test name
Test status
Simulation time 2872287431 ps
CPU time 42.72 seconds
Started Jul 10 05:10:48 PM PDT 24
Finished Jul 10 05:11:33 PM PDT 24
Peak memory 200392 kb
Host smart-b865d942-273b-4463-a1d6-384b53d462f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451363405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.451363405
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1121370828
Short name T516
Test name
Test status
Simulation time 7266471168 ps
CPU time 139.14 seconds
Started Jul 10 05:10:44 PM PDT 24
Finished Jul 10 05:13:05 PM PDT 24
Peak memory 200356 kb
Host smart-70b7f77b-76d5-4830-8fc0-ed0e581b4962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121370828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1121370828
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.195836935
Short name T464
Test name
Test status
Simulation time 381951352 ps
CPU time 5.45 seconds
Started Jul 10 05:10:44 PM PDT 24
Finished Jul 10 05:10:51 PM PDT 24
Peak memory 200260 kb
Host smart-df42a033-f8f1-459e-94d9-e43a900623a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195836935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.195836935
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.4056689556
Short name T296
Test name
Test status
Simulation time 61971815 ps
CPU time 0.62 seconds
Started Jul 10 05:10:47 PM PDT 24
Finished Jul 10 05:10:49 PM PDT 24
Peak memory 195832 kb
Host smart-5216a77d-f5f6-4973-a6dd-e7012bc1ec6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056689556 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.4056689556
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3053858110
Short name T65
Test name
Test status
Simulation time 6624647626 ps
CPU time 85.43 seconds
Started Jul 10 05:10:45 PM PDT 24
Finished Jul 10 05:12:12 PM PDT 24
Peak memory 200300 kb
Host smart-942be77d-c33b-4c4b-af85-e0b7f6893133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053858110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3053858110
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.25564362
Short name T178
Test name
Test status
Simulation time 55254331 ps
CPU time 0.59 seconds
Started Jul 10 05:10:50 PM PDT 24
Finished Jul 10 05:10:52 PM PDT 24
Peak memory 194996 kb
Host smart-2f1d25a2-0dbf-4a8d-b176-f7659270b360
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25564362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.25564362
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.4056223939
Short name T480
Test name
Test status
Simulation time 4000834415 ps
CPU time 83.03 seconds
Started Jul 10 05:10:48 PM PDT 24
Finished Jul 10 05:12:13 PM PDT 24
Peak memory 200336 kb
Host smart-3e7c41aa-fd95-403e-8431-07e29e4a146b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4056223939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.4056223939
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2709817934
Short name T511
Test name
Test status
Simulation time 15626801757 ps
CPU time 67.12 seconds
Started Jul 10 05:10:47 PM PDT 24
Finished Jul 10 05:11:56 PM PDT 24
Peak memory 216660 kb
Host smart-75c29e1a-60d3-460f-975b-1ee1638f6e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709817934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2709817934
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2870943624
Short name T171
Test name
Test status
Simulation time 1713746354 ps
CPU time 333.65 seconds
Started Jul 10 05:10:45 PM PDT 24
Finished Jul 10 05:16:21 PM PDT 24
Peak memory 611192 kb
Host smart-ca1639f5-886e-47d1-bf56-069288716a87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2870943624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2870943624
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1227719526
Short name T155
Test name
Test status
Simulation time 17914877845 ps
CPU time 96.95 seconds
Started Jul 10 05:10:44 PM PDT 24
Finished Jul 10 05:12:23 PM PDT 24
Peak memory 200312 kb
Host smart-739b0643-8cd9-425e-b303-1afe058ec07c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227719526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1227719526
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3107501152
Short name T244
Test name
Test status
Simulation time 17946548542 ps
CPU time 39.93 seconds
Started Jul 10 05:10:48 PM PDT 24
Finished Jul 10 05:11:30 PM PDT 24
Peak memory 200452 kb
Host smart-09a7e24c-1966-499b-a39c-27296e258c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107501152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3107501152
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1480125312
Short name T179
Test name
Test status
Simulation time 872975055 ps
CPU time 10.4 seconds
Started Jul 10 05:10:44 PM PDT 24
Finished Jul 10 05:10:56 PM PDT 24
Peak memory 200220 kb
Host smart-61589bcf-aa42-4cfd-8165-c05d15c041dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480125312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1480125312
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2798157817
Short name T39
Test name
Test status
Simulation time 98277256529 ps
CPU time 4378.95 seconds
Started Jul 10 05:10:49 PM PDT 24
Finished Jul 10 06:23:50 PM PDT 24
Peak memory 838368 kb
Host smart-4c800843-4c2b-45d8-8434-3bfc5c4e6b8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798157817 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2798157817
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3002788567
Short name T442
Test name
Test status
Simulation time 8140197373 ps
CPU time 140.31 seconds
Started Jul 10 05:10:47 PM PDT 24
Finished Jul 10 05:13:09 PM PDT 24
Peak memory 200404 kb
Host smart-22f9213d-39d8-4e20-ad78-2a24ec79fa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002788567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3002788567
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.3922121031
Short name T288
Test name
Test status
Simulation time 29029571 ps
CPU time 0.6 seconds
Started Jul 10 05:10:54 PM PDT 24
Finished Jul 10 05:10:56 PM PDT 24
Peak memory 196176 kb
Host smart-f1281034-2f50-4a18-b982-7c48645189a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922121031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3922121031
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.4049408578
Short name T199
Test name
Test status
Simulation time 1683461052 ps
CPU time 97.28 seconds
Started Jul 10 05:10:51 PM PDT 24
Finished Jul 10 05:12:29 PM PDT 24
Peak memory 200272 kb
Host smart-2366a337-bdba-4247-ae10-a95f51914778
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4049408578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.4049408578
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.435166704
Short name T186
Test name
Test status
Simulation time 3109551717 ps
CPU time 42.61 seconds
Started Jul 10 05:10:53 PM PDT 24
Finished Jul 10 05:11:36 PM PDT 24
Peak memory 200360 kb
Host smart-95a19d92-8ba2-4437-a206-968bf76406dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435166704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.435166704
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2254603450
Short name T410
Test name
Test status
Simulation time 18499707847 ps
CPU time 740.38 seconds
Started Jul 10 05:10:50 PM PDT 24
Finished Jul 10 05:23:11 PM PDT 24
Peak memory 698640 kb
Host smart-57c7b4eb-e180-44b2-bd60-d060b7b427a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2254603450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2254603450
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3924531609
Short name T127
Test name
Test status
Simulation time 7744284153 ps
CPU time 97.86 seconds
Started Jul 10 05:10:50 PM PDT 24
Finished Jul 10 05:12:29 PM PDT 24
Peak memory 200384 kb
Host smart-b73bd7fe-bb98-460b-8c12-d5c0daa357c2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924531609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3924531609
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2839658800
Short name T255
Test name
Test status
Simulation time 3815655882 ps
CPU time 26.08 seconds
Started Jul 10 05:10:51 PM PDT 24
Finished Jul 10 05:11:18 PM PDT 24
Peak memory 200264 kb
Host smart-cbc8e7db-4876-484e-a754-e0808a31d09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839658800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2839658800
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2826464355
Short name T285
Test name
Test status
Simulation time 279388874 ps
CPU time 11.89 seconds
Started Jul 10 05:10:57 PM PDT 24
Finished Jul 10 05:11:09 PM PDT 24
Peak memory 200296 kb
Host smart-b486db2c-bbbb-4f50-974e-a7a69d044423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826464355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2826464355
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.216853196
Short name T232
Test name
Test status
Simulation time 28504270790 ps
CPU time 1022.31 seconds
Started Jul 10 05:10:50 PM PDT 24
Finished Jul 10 05:27:54 PM PDT 24
Peak memory 645412 kb
Host smart-5958106a-32f8-4de0-9106-3d08c49b45b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216853196 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.216853196
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2005187691
Short name T75
Test name
Test status
Simulation time 65214524655 ps
CPU time 150.37 seconds
Started Jul 10 05:10:50 PM PDT 24
Finished Jul 10 05:13:22 PM PDT 24
Peak memory 200280 kb
Host smart-7cb4d586-45dc-4c35-8d20-bfcfb9664c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005187691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2005187691
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3149494779
Short name T391
Test name
Test status
Simulation time 42764755 ps
CPU time 0.56 seconds
Started Jul 10 05:10:58 PM PDT 24
Finished Jul 10 05:10:59 PM PDT 24
Peak memory 195152 kb
Host smart-e18e44a3-4fe9-4237-9d48-935bf0605097
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149494779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3149494779
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1878898610
Short name T211
Test name
Test status
Simulation time 3732722170 ps
CPU time 49.18 seconds
Started Jul 10 05:10:59 PM PDT 24
Finished Jul 10 05:11:49 PM PDT 24
Peak memory 200264 kb
Host smart-6bf53827-0917-4003-823c-cf3f2694141e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1878898610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1878898610
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2231606508
Short name T137
Test name
Test status
Simulation time 9272549516 ps
CPU time 56.43 seconds
Started Jul 10 05:10:55 PM PDT 24
Finished Jul 10 05:11:53 PM PDT 24
Peak memory 200340 kb
Host smart-e6a9f137-8b69-44ce-a739-0cb9ca4c4759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231606508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2231606508
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.803697463
Short name T279
Test name
Test status
Simulation time 4572199252 ps
CPU time 194.67 seconds
Started Jul 10 05:10:56 PM PDT 24
Finished Jul 10 05:14:12 PM PDT 24
Peak memory 435564 kb
Host smart-a3b8f335-b5f7-4704-8a4a-65fefee61bed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=803697463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.803697463
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1506274378
Short name T397
Test name
Test status
Simulation time 11238700144 ps
CPU time 18.73 seconds
Started Jul 10 05:10:59 PM PDT 24
Finished Jul 10 05:11:18 PM PDT 24
Peak memory 200296 kb
Host smart-916bd1e6-73fc-4688-aaf9-92b8e76ac7a6
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506274378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1506274378
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2050370340
Short name T358
Test name
Test status
Simulation time 1772740023 ps
CPU time 23.48 seconds
Started Jul 10 05:10:58 PM PDT 24
Finished Jul 10 05:11:22 PM PDT 24
Peak memory 200300 kb
Host smart-fb02752d-966b-40e0-aed4-0c474578d78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050370340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2050370340
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.260989306
Short name T220
Test name
Test status
Simulation time 210832577 ps
CPU time 7.19 seconds
Started Jul 10 05:10:57 PM PDT 24
Finished Jul 10 05:11:05 PM PDT 24
Peak memory 200316 kb
Host smart-84373360-84de-41c2-83b3-52f1b972fec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260989306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.260989306
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.377455596
Short name T192
Test name
Test status
Simulation time 131874452287 ps
CPU time 3771.98 seconds
Started Jul 10 05:10:57 PM PDT 24
Finished Jul 10 06:13:51 PM PDT 24
Peak memory 839396 kb
Host smart-1eea95ca-1105-4ce2-975f-38ff42454649
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377455596 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.377455596
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.4214056471
Short name T259
Test name
Test status
Simulation time 7956728262 ps
CPU time 76.89 seconds
Started Jul 10 05:10:56 PM PDT 24
Finished Jul 10 05:12:14 PM PDT 24
Peak memory 200400 kb
Host smart-18bf1ccf-36a3-4e74-8220-0a57f685f7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214056471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.4214056471
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.245508400
Short name T142
Test name
Test status
Simulation time 154461589 ps
CPU time 0.58 seconds
Started Jul 10 05:10:11 PM PDT 24
Finished Jul 10 05:10:16 PM PDT 24
Peak memory 195140 kb
Host smart-63329d13-d869-45ca-b802-1a1db72d129b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245508400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.245508400
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.1867536315
Short name T32
Test name
Test status
Simulation time 48753407 ps
CPU time 2.76 seconds
Started Jul 10 05:10:05 PM PDT 24
Finished Jul 10 05:10:12 PM PDT 24
Peak memory 200276 kb
Host smart-c5001c95-b056-4439-96e8-b65a84a42bee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1867536315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.1867536315
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.702669985
Short name T20
Test name
Test status
Simulation time 828995244 ps
CPU time 43.14 seconds
Started Jul 10 05:10:10 PM PDT 24
Finished Jul 10 05:10:58 PM PDT 24
Peak memory 200256 kb
Host smart-a9983338-53bc-42d0-8bf6-cf2ea4aa0c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702669985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.702669985
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.3949717611
Short name T463
Test name
Test status
Simulation time 11578962890 ps
CPU time 1006 seconds
Started Jul 10 05:10:10 PM PDT 24
Finished Jul 10 05:27:02 PM PDT 24
Peak memory 769928 kb
Host smart-d5e68d31-657a-4817-89a7-3b8fcd63ac49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3949717611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.3949717611
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.598654718
Short name T136
Test name
Test status
Simulation time 14992151283 ps
CPU time 48.61 seconds
Started Jul 10 05:10:02 PM PDT 24
Finished Jul 10 05:10:56 PM PDT 24
Peak memory 200256 kb
Host smart-b672efe6-b7ab-4c55-ab39-83e56477dedb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598654718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.598654718
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3082888931
Short name T270
Test name
Test status
Simulation time 7849702706 ps
CPU time 105.25 seconds
Started Jul 10 05:10:03 PM PDT 24
Finished Jul 10 05:11:53 PM PDT 24
Peak memory 200292 kb
Host smart-69f0d21a-768c-42a3-a12e-6b75970fed43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082888931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3082888931
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.195734005
Short name T44
Test name
Test status
Simulation time 108855815 ps
CPU time 0.93 seconds
Started Jul 10 05:10:14 PM PDT 24
Finished Jul 10 05:10:21 PM PDT 24
Peak memory 218188 kb
Host smart-7bd3e172-eadf-4488-b556-f1df0b094e91
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195734005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.195734005
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1589998345
Short name T28
Test name
Test status
Simulation time 1170716767 ps
CPU time 4.95 seconds
Started Jul 10 05:10:05 PM PDT 24
Finished Jul 10 05:10:14 PM PDT 24
Peak memory 200212 kb
Host smart-e8637af5-762a-451d-87f6-37509e856a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589998345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1589998345
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.3214716288
Short name T149
Test name
Test status
Simulation time 17503117464 ps
CPU time 77.26 seconds
Started Jul 10 05:10:05 PM PDT 24
Finished Jul 10 05:11:26 PM PDT 24
Peak memory 200320 kb
Host smart-d7180a2d-7444-46b2-92b7-ae4e1f4e6a18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214716288 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.3214716288
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.3124786501
Short name T250
Test name
Test status
Simulation time 4889355954 ps
CPU time 43.25 seconds
Started Jul 10 05:10:03 PM PDT 24
Finished Jul 10 05:10:51 PM PDT 24
Peak memory 200260 kb
Host smart-bf716412-0257-4d82-9c3a-fda95d7aa247
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3124786501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.3124786501
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.1441654321
Short name T336
Test name
Test status
Simulation time 6451125352 ps
CPU time 56.14 seconds
Started Jul 10 05:10:04 PM PDT 24
Finished Jul 10 05:11:05 PM PDT 24
Peak memory 200264 kb
Host smart-70fac73f-6197-4fd0-8a4e-4441dd283ce1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1441654321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.1441654321
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.185047429
Short name T347
Test name
Test status
Simulation time 93260787743 ps
CPU time 133.22 seconds
Started Jul 10 05:10:03 PM PDT 24
Finished Jul 10 05:12:22 PM PDT 24
Peak memory 200304 kb
Host smart-5406dc8f-080e-4da2-92ba-dec3ea5abc67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=185047429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.185047429
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.3828799311
Short name T132
Test name
Test status
Simulation time 215316990639 ps
CPU time 624.45 seconds
Started Jul 10 05:10:05 PM PDT 24
Finished Jul 10 05:20:34 PM PDT 24
Peak memory 200304 kb
Host smart-a092908a-1995-4967-8a5d-8c6c4e3fad25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3828799311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.3828799311
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.1789306096
Short name T111
Test name
Test status
Simulation time 844610150097 ps
CPU time 2810.82 seconds
Started Jul 10 05:10:03 PM PDT 24
Finished Jul 10 05:57:00 PM PDT 24
Peak memory 216712 kb
Host smart-0ba4ed8a-d16c-459a-ab3d-a32d86c509dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1789306096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.1789306096
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.433730272
Short name T390
Test name
Test status
Simulation time 83137264292 ps
CPU time 2379.95 seconds
Started Jul 10 05:10:03 PM PDT 24
Finished Jul 10 05:49:49 PM PDT 24
Peak memory 215784 kb
Host smart-e20bfbe3-d58e-41ff-b9ae-4d1822ea7400
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=433730272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.433730272
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2948274278
Short name T170
Test name
Test status
Simulation time 14191782829 ps
CPU time 101.53 seconds
Started Jul 10 05:10:04 PM PDT 24
Finished Jul 10 05:11:51 PM PDT 24
Peak memory 200344 kb
Host smart-7d40c61a-1962-4a28-93ba-becf403fd78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948274278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2948274278
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.3714184584
Short name T424
Test name
Test status
Simulation time 12998395 ps
CPU time 0.59 seconds
Started Jul 10 05:11:04 PM PDT 24
Finished Jul 10 05:11:05 PM PDT 24
Peak memory 195724 kb
Host smart-9a7ff0f7-77b4-4053-83db-f3cdd149647c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714184584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3714184584
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.361645384
Short name T162
Test name
Test status
Simulation time 1332982434 ps
CPU time 74.57 seconds
Started Jul 10 05:11:04 PM PDT 24
Finished Jul 10 05:12:20 PM PDT 24
Peak memory 200276 kb
Host smart-12c2e623-61c6-459a-98f0-2ff075f98e03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=361645384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.361645384
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2953123058
Short name T429
Test name
Test status
Simulation time 39097846971 ps
CPU time 652.71 seconds
Started Jul 10 05:11:01 PM PDT 24
Finished Jul 10 05:21:54 PM PDT 24
Peak memory 742400 kb
Host smart-bb58494f-7f76-486c-bb89-c3c9b285f87e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2953123058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2953123058
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.2090817920
Short name T299
Test name
Test status
Simulation time 13097767420 ps
CPU time 115.19 seconds
Started Jul 10 05:11:00 PM PDT 24
Finished Jul 10 05:12:56 PM PDT 24
Peak memory 200264 kb
Host smart-c7197ca3-8dae-49fe-b07f-6cfa1b7539e2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090817920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2090817920
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1472598352
Short name T62
Test name
Test status
Simulation time 3599661489 ps
CPU time 51.96 seconds
Started Jul 10 05:11:02 PM PDT 24
Finished Jul 10 05:11:55 PM PDT 24
Peak memory 200276 kb
Host smart-1a161e0d-0f3a-4833-8bc1-cb214d757f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472598352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1472598352
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.4044696988
Short name T406
Test name
Test status
Simulation time 125112386 ps
CPU time 2.97 seconds
Started Jul 10 05:10:57 PM PDT 24
Finished Jul 10 05:11:01 PM PDT 24
Peak memory 200208 kb
Host smart-80a40784-eb42-4833-a405-703ee4434839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044696988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.4044696988
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3741674706
Short name T71
Test name
Test status
Simulation time 22559735656 ps
CPU time 281.95 seconds
Started Jul 10 05:11:02 PM PDT 24
Finished Jul 10 05:15:45 PM PDT 24
Peak memory 200384 kb
Host smart-c58bf53f-2151-441e-b7ae-1e49cbfe21a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741674706 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3741674706
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.494568877
Short name T461
Test name
Test status
Simulation time 11562142574 ps
CPU time 36.98 seconds
Started Jul 10 05:11:02 PM PDT 24
Finished Jul 10 05:11:40 PM PDT 24
Peak memory 200268 kb
Host smart-ce1e283b-c51b-4dcc-a03f-ba82ecf22eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494568877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.494568877
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1840742908
Short name T409
Test name
Test status
Simulation time 32555817 ps
CPU time 0.59 seconds
Started Jul 10 05:11:01 PM PDT 24
Finished Jul 10 05:11:02 PM PDT 24
Peak memory 195140 kb
Host smart-2282a7b2-c0b1-4834-9e14-4edc23425a23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840742908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1840742908
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1004880131
Short name T507
Test name
Test status
Simulation time 21792765750 ps
CPU time 83.18 seconds
Started Jul 10 05:11:02 PM PDT 24
Finished Jul 10 05:12:26 PM PDT 24
Peak memory 200376 kb
Host smart-69cf0bea-233a-4b19-945b-a446577ee4d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004880131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1004880131
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1137269669
Short name T394
Test name
Test status
Simulation time 3065148487 ps
CPU time 39.46 seconds
Started Jul 10 05:11:01 PM PDT 24
Finished Jul 10 05:11:42 PM PDT 24
Peak memory 200320 kb
Host smart-670e4c62-12a4-49d4-b3b7-497b60142993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137269669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1137269669
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3617186856
Short name T323
Test name
Test status
Simulation time 23043442324 ps
CPU time 1079.79 seconds
Started Jul 10 05:11:02 PM PDT 24
Finished Jul 10 05:29:03 PM PDT 24
Peak memory 643692 kb
Host smart-78febcc1-cb93-4e4b-ad25-de55b8d2b3b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3617186856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3617186856
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3098222064
Short name T437
Test name
Test status
Simulation time 2591445858 ps
CPU time 145.54 seconds
Started Jul 10 05:11:02 PM PDT 24
Finished Jul 10 05:13:29 PM PDT 24
Peak memory 200328 kb
Host smart-501cd1d8-fec5-4788-9e77-831d3c6bd024
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098222064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3098222064
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.2717437659
Short name T362
Test name
Test status
Simulation time 1464550296 ps
CPU time 83.46 seconds
Started Jul 10 05:11:03 PM PDT 24
Finished Jul 10 05:12:28 PM PDT 24
Peak memory 200296 kb
Host smart-89fe5631-4e86-4053-a10d-8d2469fa6ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717437659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2717437659
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.45505085
Short name T483
Test name
Test status
Simulation time 1441105699 ps
CPU time 18.87 seconds
Started Jul 10 05:11:03 PM PDT 24
Finished Jul 10 05:11:23 PM PDT 24
Peak memory 200300 kb
Host smart-20ec8638-ff59-4e57-a4d4-57cd59110ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45505085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.45505085
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1294293062
Short name T247
Test name
Test status
Simulation time 18846143204 ps
CPU time 275.67 seconds
Started Jul 10 05:11:00 PM PDT 24
Finished Jul 10 05:15:37 PM PDT 24
Peak memory 265944 kb
Host smart-28e8388a-b4cb-4b80-aaa5-2a900193f948
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294293062 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1294293062
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1978688150
Short name T251
Test name
Test status
Simulation time 3934770995 ps
CPU time 92.81 seconds
Started Jul 10 05:11:06 PM PDT 24
Finished Jul 10 05:12:39 PM PDT 24
Peak memory 200316 kb
Host smart-3abdb18f-e2e4-4f0a-9745-dbd4bc1e63bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978688150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1978688150
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.712521300
Short name T447
Test name
Test status
Simulation time 23258414 ps
CPU time 0.58 seconds
Started Jul 10 05:11:09 PM PDT 24
Finished Jul 10 05:11:12 PM PDT 24
Peak memory 195076 kb
Host smart-be84d662-b513-41c7-b7bf-fcb0bd9d1494
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712521300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.712521300
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1379922183
Short name T196
Test name
Test status
Simulation time 3372543378 ps
CPU time 81.96 seconds
Started Jul 10 05:11:10 PM PDT 24
Finished Jul 10 05:12:34 PM PDT 24
Peak memory 208552 kb
Host smart-e365ccb9-2c73-4f51-a3df-9ebd0832778b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1379922183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1379922183
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.2861992118
Short name T189
Test name
Test status
Simulation time 6323311807 ps
CPU time 55.05 seconds
Started Jul 10 05:11:08 PM PDT 24
Finished Jul 10 05:12:05 PM PDT 24
Peak memory 208620 kb
Host smart-9ca51979-e970-4b45-b977-9bfa8b3743b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861992118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.2861992118
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1781659314
Short name T400
Test name
Test status
Simulation time 9771075722 ps
CPU time 953.85 seconds
Started Jul 10 05:11:10 PM PDT 24
Finished Jul 10 05:27:06 PM PDT 24
Peak memory 752596 kb
Host smart-3db6133e-1cdc-4555-9f29-af4141b0fa39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1781659314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1781659314
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3712021568
Short name T145
Test name
Test status
Simulation time 4445268991 ps
CPU time 21.15 seconds
Started Jul 10 05:11:13 PM PDT 24
Finished Jul 10 05:11:37 PM PDT 24
Peak memory 200316 kb
Host smart-a438d988-cc2a-4d83-92c7-fb6e3dfb0e46
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712021568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3712021568
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1523015954
Short name T38
Test name
Test status
Simulation time 49003390709 ps
CPU time 136.34 seconds
Started Jul 10 05:11:07 PM PDT 24
Finished Jul 10 05:13:25 PM PDT 24
Peak memory 200420 kb
Host smart-c7332292-daa1-48ee-8c58-06192256fee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523015954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1523015954
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1145703461
Short name T181
Test name
Test status
Simulation time 1680352400 ps
CPU time 5.24 seconds
Started Jul 10 05:11:09 PM PDT 24
Finished Jul 10 05:11:17 PM PDT 24
Peak memory 200220 kb
Host smart-52fd02f0-e5e4-45df-8161-e6064920c02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145703461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1145703461
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2546145012
Short name T74
Test name
Test status
Simulation time 29588544048 ps
CPU time 1169.82 seconds
Started Jul 10 05:11:06 PM PDT 24
Finished Jul 10 05:30:37 PM PDT 24
Peak memory 689244 kb
Host smart-1e3240b2-35eb-4012-87d2-43fcfab0729e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546145012 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2546145012
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.167502889
Short name T328
Test name
Test status
Simulation time 2672518451 ps
CPU time 32.85 seconds
Started Jul 10 05:11:13 PM PDT 24
Finished Jul 10 05:11:48 PM PDT 24
Peak memory 200352 kb
Host smart-d0451795-e45f-4962-92fe-15d0df7537e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167502889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.167502889
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.3328173046
Short name T477
Test name
Test status
Simulation time 27189599 ps
CPU time 0.62 seconds
Started Jul 10 05:11:12 PM PDT 24
Finished Jul 10 05:11:14 PM PDT 24
Peak memory 196164 kb
Host smart-2b93a875-101b-4260-8204-91d3c1eab780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328173046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3328173046
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.174110990
Short name T213
Test name
Test status
Simulation time 321503034 ps
CPU time 8.85 seconds
Started Jul 10 05:11:06 PM PDT 24
Finished Jul 10 05:11:16 PM PDT 24
Peak memory 200276 kb
Host smart-c3e789b7-95a6-43cf-beb0-54f2e1e348ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=174110990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.174110990
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.3867515783
Short name T293
Test name
Test status
Simulation time 23949589644 ps
CPU time 37.66 seconds
Started Jul 10 05:11:13 PM PDT 24
Finished Jul 10 05:11:53 PM PDT 24
Peak memory 200396 kb
Host smart-1d468d28-53e2-41e6-a0b4-8225b9e3cb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867515783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.3867515783
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2713632447
Short name T273
Test name
Test status
Simulation time 15676549809 ps
CPU time 243.07 seconds
Started Jul 10 05:11:13 PM PDT 24
Finished Jul 10 05:15:19 PM PDT 24
Peak memory 442488 kb
Host smart-172a5cb2-9c11-460d-a48c-44da046a05af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713632447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2713632447
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1499095382
Short name T300
Test name
Test status
Simulation time 2005328771 ps
CPU time 33.65 seconds
Started Jul 10 05:11:13 PM PDT 24
Finished Jul 10 05:11:49 PM PDT 24
Peak memory 200272 kb
Host smart-2ad6f9c7-5a23-4985-b7cf-a93553a3ec80
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499095382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1499095382
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.187652769
Short name T309
Test name
Test status
Simulation time 5397027673 ps
CPU time 81.06 seconds
Started Jul 10 05:11:07 PM PDT 24
Finished Jul 10 05:12:30 PM PDT 24
Peak memory 208532 kb
Host smart-7b407c90-be24-4587-874c-6979b72281d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187652769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.187652769
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.4033875813
Short name T275
Test name
Test status
Simulation time 206932520 ps
CPU time 9.87 seconds
Started Jul 10 05:11:07 PM PDT 24
Finished Jul 10 05:11:18 PM PDT 24
Peak memory 200328 kb
Host smart-da95a891-9b0d-4aa9-ba14-c6b867e9ecda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033875813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.4033875813
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.2485348473
Short name T76
Test name
Test status
Simulation time 8415990410 ps
CPU time 420.28 seconds
Started Jul 10 05:11:14 PM PDT 24
Finished Jul 10 05:18:17 PM PDT 24
Peak memory 200464 kb
Host smart-0213f685-1229-48df-bb77-fc61ba139aea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485348473 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.2485348473
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.4115992527
Short name T141
Test name
Test status
Simulation time 6345179875 ps
CPU time 42.52 seconds
Started Jul 10 05:11:15 PM PDT 24
Finished Jul 10 05:12:00 PM PDT 24
Peak memory 200352 kb
Host smart-928aa889-f7e1-4489-93ad-1b71d4ab0657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115992527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.4115992527
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.690253311
Short name T496
Test name
Test status
Simulation time 13550489 ps
CPU time 0.56 seconds
Started Jul 10 05:11:13 PM PDT 24
Finished Jul 10 05:11:16 PM PDT 24
Peak memory 195152 kb
Host smart-954d2b4d-95b0-4770-8712-256b4e785475
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690253311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.690253311
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.4128196485
Short name T365
Test name
Test status
Simulation time 783776803 ps
CPU time 2.63 seconds
Started Jul 10 05:11:16 PM PDT 24
Finished Jul 10 05:11:20 PM PDT 24
Peak memory 200192 kb
Host smart-53ab2508-964a-42b4-9e23-b89007b59340
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4128196485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.4128196485
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.1807032766
Short name T116
Test name
Test status
Simulation time 18928331926 ps
CPU time 91.4 seconds
Started Jul 10 05:11:14 PM PDT 24
Finished Jul 10 05:12:48 PM PDT 24
Peak memory 216672 kb
Host smart-d05d332a-5bfa-4f7e-83d3-7590e55414be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807032766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.1807032766
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.463020693
Short name T124
Test name
Test status
Simulation time 1382450066 ps
CPU time 35.27 seconds
Started Jul 10 05:11:15 PM PDT 24
Finished Jul 10 05:11:52 PM PDT 24
Peak memory 242644 kb
Host smart-1d7dd2bf-9368-4800-b9b4-19094b410b85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=463020693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.463020693
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3666667147
Short name T333
Test name
Test status
Simulation time 28443715269 ps
CPU time 123.43 seconds
Started Jul 10 05:11:12 PM PDT 24
Finished Jul 10 05:13:17 PM PDT 24
Peak memory 200256 kb
Host smart-88336056-766c-45c5-b636-f2f74c357191
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666667147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3666667147
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1042664227
Short name T304
Test name
Test status
Simulation time 5510683118 ps
CPU time 21.09 seconds
Started Jul 10 05:11:13 PM PDT 24
Finished Jul 10 05:11:36 PM PDT 24
Peak memory 200292 kb
Host smart-dd81aa5e-b54a-4fb9-b2dc-c2710deeebaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042664227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1042664227
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.728679765
Short name T128
Test name
Test status
Simulation time 1182000447 ps
CPU time 3.98 seconds
Started Jul 10 05:11:11 PM PDT 24
Finished Jul 10 05:11:17 PM PDT 24
Peak memory 200212 kb
Host smart-e25123e7-91c5-4ad6-80ea-ec2dd8cffccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728679765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.728679765
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.4279706780
Short name T371
Test name
Test status
Simulation time 60603444944 ps
CPU time 2545.78 seconds
Started Jul 10 05:11:12 PM PDT 24
Finished Jul 10 05:53:40 PM PDT 24
Peak memory 771700 kb
Host smart-830b7b20-1cdc-463f-99dd-b5e09fda0471
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279706780 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.4279706780
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.4107842331
Short name T8
Test name
Test status
Simulation time 2119657797 ps
CPU time 102.09 seconds
Started Jul 10 05:11:13 PM PDT 24
Finished Jul 10 05:12:58 PM PDT 24
Peak memory 200296 kb
Host smart-176c4e27-0a17-48f0-b57c-0db0b6f0b7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107842331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.4107842331
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.320558809
Short name T374
Test name
Test status
Simulation time 39822367 ps
CPU time 0.57 seconds
Started Jul 10 05:11:20 PM PDT 24
Finished Jul 10 05:11:22 PM PDT 24
Peak memory 195152 kb
Host smart-a58dcb37-c53e-42b4-8baf-73c26961e0a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320558809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.320558809
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.677720035
Short name T14
Test name
Test status
Simulation time 639014698 ps
CPU time 34.61 seconds
Started Jul 10 05:11:17 PM PDT 24
Finished Jul 10 05:11:53 PM PDT 24
Peak memory 200288 kb
Host smart-a85e01a2-96b0-4aa1-9b7e-16955536e7d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=677720035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.677720035
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1364451707
Short name T265
Test name
Test status
Simulation time 7861359298 ps
CPU time 26.27 seconds
Started Jul 10 05:11:21 PM PDT 24
Finished Jul 10 05:11:49 PM PDT 24
Peak memory 200332 kb
Host smart-1de551c4-0660-4783-a9d9-01da7ae98a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364451707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1364451707
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.107831352
Short name T239
Test name
Test status
Simulation time 7451547458 ps
CPU time 377.4 seconds
Started Jul 10 05:11:13 PM PDT 24
Finished Jul 10 05:17:32 PM PDT 24
Peak memory 636108 kb
Host smart-bd246ebf-d452-4566-883d-a2b0ac4b72b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=107831352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.107831352
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1549349297
Short name T405
Test name
Test status
Simulation time 21277758647 ps
CPU time 130.74 seconds
Started Jul 10 05:11:20 PM PDT 24
Finished Jul 10 05:13:32 PM PDT 24
Peak memory 200300 kb
Host smart-c7783db9-2f20-4cb9-8bcf-2b66bc7d6904
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549349297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1549349297
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.4110541471
Short name T27
Test name
Test status
Simulation time 5987164110 ps
CPU time 78.92 seconds
Started Jul 10 05:11:13 PM PDT 24
Finished Jul 10 05:12:35 PM PDT 24
Peak memory 200404 kb
Host smart-ec3adf40-2fd0-47c1-8299-291576b2592c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110541471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.4110541471
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.735455952
Short name T378
Test name
Test status
Simulation time 2171971849 ps
CPU time 14.61 seconds
Started Jul 10 05:11:13 PM PDT 24
Finished Jul 10 05:11:30 PM PDT 24
Peak memory 200288 kb
Host smart-a2ef9372-db9b-4340-b8de-e4a0317bfd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735455952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.735455952
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.1199883584
Short name T231
Test name
Test status
Simulation time 29157759821 ps
CPU time 447.91 seconds
Started Jul 10 05:11:22 PM PDT 24
Finished Jul 10 05:18:51 PM PDT 24
Peak memory 200236 kb
Host smart-40dc87b1-1934-415b-ae4b-7bba51db7f74
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199883584 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.1199883584
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2932303465
Short name T221
Test name
Test status
Simulation time 38555610816 ps
CPU time 79.5 seconds
Started Jul 10 05:11:20 PM PDT 24
Finished Jul 10 05:12:41 PM PDT 24
Peak memory 200400 kb
Host smart-484c7b34-274f-4f0a-ba78-2ea75e4b673a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932303465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2932303465
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.686744682
Short name T386
Test name
Test status
Simulation time 38342310 ps
CPU time 0.57 seconds
Started Jul 10 05:11:21 PM PDT 24
Finished Jul 10 05:11:23 PM PDT 24
Peak memory 196100 kb
Host smart-3b25f371-9947-4290-898f-9a8b1dff70c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686744682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.686744682
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1140296507
Short name T456
Test name
Test status
Simulation time 319012407 ps
CPU time 18.98 seconds
Started Jul 10 05:11:19 PM PDT 24
Finished Jul 10 05:11:39 PM PDT 24
Peak memory 200276 kb
Host smart-e3feea4e-bb27-4d06-bcda-a64d2628f913
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1140296507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1140296507
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.3325419695
Short name T396
Test name
Test status
Simulation time 3814275954 ps
CPU time 32.03 seconds
Started Jul 10 05:11:20 PM PDT 24
Finished Jul 10 05:11:53 PM PDT 24
Peak memory 200324 kb
Host smart-68c6bce1-ea62-49f0-93fe-08dca10daafe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325419695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3325419695
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1023725740
Short name T481
Test name
Test status
Simulation time 72840880907 ps
CPU time 1700.98 seconds
Started Jul 10 05:11:20 PM PDT 24
Finished Jul 10 05:39:43 PM PDT 24
Peak memory 770884 kb
Host smart-fe3927c4-f8f5-4930-a01c-58548d576152
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1023725740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1023725740
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1792148637
Short name T207
Test name
Test status
Simulation time 35511181173 ps
CPU time 166.66 seconds
Started Jul 10 05:11:21 PM PDT 24
Finished Jul 10 05:14:09 PM PDT 24
Peak memory 200316 kb
Host smart-0e20ec13-fa4a-480c-b823-2a664dfe045f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792148637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1792148637
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2128440809
Short name T151
Test name
Test status
Simulation time 3483249597 ps
CPU time 39.14 seconds
Started Jul 10 05:11:21 PM PDT 24
Finished Jul 10 05:12:01 PM PDT 24
Peak memory 200364 kb
Host smart-0b4f1e63-486b-4d4e-92da-c0e2858a305e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128440809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2128440809
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2830061345
Short name T373
Test name
Test status
Simulation time 264082049 ps
CPU time 11.05 seconds
Started Jul 10 05:11:20 PM PDT 24
Finished Jul 10 05:11:32 PM PDT 24
Peak memory 200272 kb
Host smart-6bf3fb53-b817-4d5c-8647-fa3d86773410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830061345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2830061345
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.390802704
Short name T525
Test name
Test status
Simulation time 80359550970 ps
CPU time 1113.91 seconds
Started Jul 10 05:11:22 PM PDT 24
Finished Jul 10 05:29:58 PM PDT 24
Peak memory 208504 kb
Host smart-a70bfbfc-da65-4356-bc59-0a540a25f9fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390802704 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.390802704
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2082275767
Short name T438
Test name
Test status
Simulation time 7414966757 ps
CPU time 72.38 seconds
Started Jul 10 05:11:21 PM PDT 24
Finished Jul 10 05:12:35 PM PDT 24
Peak memory 200268 kb
Host smart-b4d4ecf5-6f27-417f-9bba-b77a489f4b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082275767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2082275767
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.25047493
Short name T217
Test name
Test status
Simulation time 19373369 ps
CPU time 0.63 seconds
Started Jul 10 05:11:26 PM PDT 24
Finished Jul 10 05:11:28 PM PDT 24
Peak memory 196176 kb
Host smart-6c5c5a6c-7621-4ae9-aebe-64cd366799a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25047493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.25047493
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2537899101
Short name T393
Test name
Test status
Simulation time 659199013 ps
CPU time 39.1 seconds
Started Jul 10 05:11:27 PM PDT 24
Finished Jul 10 05:12:07 PM PDT 24
Peak memory 200252 kb
Host smart-1eb14b6f-289d-402c-833d-7241e538b11f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2537899101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2537899101
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1787841738
Short name T73
Test name
Test status
Simulation time 15554575 ps
CPU time 0.76 seconds
Started Jul 10 05:11:27 PM PDT 24
Finished Jul 10 05:11:29 PM PDT 24
Peak memory 198244 kb
Host smart-eeb119fa-50da-415b-9695-9e657cb80412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787841738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1787841738
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1715686783
Short name T297
Test name
Test status
Simulation time 22318815398 ps
CPU time 1048.4 seconds
Started Jul 10 05:11:31 PM PDT 24
Finished Jul 10 05:29:00 PM PDT 24
Peak memory 685020 kb
Host smart-15b980e3-09a4-403d-90e0-a617d36704b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1715686783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1715686783
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.4262747486
Short name T246
Test name
Test status
Simulation time 33590275921 ps
CPU time 139.79 seconds
Started Jul 10 05:11:25 PM PDT 24
Finished Jul 10 05:13:45 PM PDT 24
Peak memory 200336 kb
Host smart-13c3f0b5-da5c-44f6-a2ca-b28a93c7332a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262747486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.4262747486
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.653310429
Short name T202
Test name
Test status
Simulation time 567893710 ps
CPU time 31.64 seconds
Started Jul 10 05:11:20 PM PDT 24
Finished Jul 10 05:11:52 PM PDT 24
Peak memory 200268 kb
Host smart-489290ba-5f76-442e-aab1-b808811bd7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653310429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.653310429
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2983949264
Short name T366
Test name
Test status
Simulation time 551126385 ps
CPU time 6.67 seconds
Started Jul 10 05:11:22 PM PDT 24
Finished Jul 10 05:11:30 PM PDT 24
Peak memory 200220 kb
Host smart-01820c8a-376b-401d-a4a9-354d54cc68d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983949264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2983949264
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3864945954
Short name T147
Test name
Test status
Simulation time 160074948602 ps
CPU time 1756.5 seconds
Started Jul 10 05:11:27 PM PDT 24
Finished Jul 10 05:40:45 PM PDT 24
Peak memory 774524 kb
Host smart-51493270-4024-4d78-842e-e3bd34231c63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864945954 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3864945954
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2754427233
Short name T338
Test name
Test status
Simulation time 1210593738 ps
CPU time 11.11 seconds
Started Jul 10 05:11:28 PM PDT 24
Finished Jul 10 05:11:41 PM PDT 24
Peak memory 200180 kb
Host smart-f48d86a4-54e9-4cf3-90a7-74a503753d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754427233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2754427233
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1071975460
Short name T375
Test name
Test status
Simulation time 13279641 ps
CPU time 0.61 seconds
Started Jul 10 05:11:27 PM PDT 24
Finished Jul 10 05:11:29 PM PDT 24
Peak memory 195076 kb
Host smart-ca2f51c6-bbd1-4332-91c8-b5a84f61d39c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071975460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1071975460
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2348710187
Short name T238
Test name
Test status
Simulation time 1123862476 ps
CPU time 18.02 seconds
Started Jul 10 05:11:26 PM PDT 24
Finished Jul 10 05:11:45 PM PDT 24
Peak memory 200276 kb
Host smart-c9ef67fa-a7b0-4a1f-b71b-437c9301009c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2348710187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2348710187
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.765507740
Short name T521
Test name
Test status
Simulation time 1907051099 ps
CPU time 8.71 seconds
Started Jul 10 05:11:26 PM PDT 24
Finished Jul 10 05:11:35 PM PDT 24
Peak memory 200340 kb
Host smart-0fb20c5c-9b14-46fe-9fa9-3f78ae3a10fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765507740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.765507740
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3753904675
Short name T524
Test name
Test status
Simulation time 4553820827 ps
CPU time 886 seconds
Started Jul 10 05:11:31 PM PDT 24
Finished Jul 10 05:26:18 PM PDT 24
Peak memory 722956 kb
Host smart-be1ec386-7da0-43c7-ad26-26bd088e2e41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3753904675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3753904675
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2885368875
Short name T421
Test name
Test status
Simulation time 7083301272 ps
CPU time 202.08 seconds
Started Jul 10 05:11:26 PM PDT 24
Finished Jul 10 05:14:49 PM PDT 24
Peak memory 200304 kb
Host smart-c57ac005-a720-4806-aeca-72444f49e9e0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885368875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2885368875
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3580426769
Short name T210
Test name
Test status
Simulation time 25051694465 ps
CPU time 113.6 seconds
Started Jul 10 05:11:33 PM PDT 24
Finished Jul 10 05:13:27 PM PDT 24
Peak memory 200356 kb
Host smart-a4fbd413-8fe0-4f71-9f7d-b5ec0a1d728a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580426769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3580426769
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2943413124
Short name T493
Test name
Test status
Simulation time 130809858 ps
CPU time 5.72 seconds
Started Jul 10 05:11:27 PM PDT 24
Finished Jul 10 05:11:34 PM PDT 24
Peak memory 200220 kb
Host smart-a59aedb4-dd7d-4869-b22a-bbd4fedca9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943413124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2943413124
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.319230613
Short name T283
Test name
Test status
Simulation time 1203621671 ps
CPU time 22.34 seconds
Started Jul 10 05:11:25 PM PDT 24
Finished Jul 10 05:11:48 PM PDT 24
Peak memory 200260 kb
Host smart-0b1f79a0-ada1-4ba3-a0c8-ae2574e8821e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319230613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.319230613
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.158120074
Short name T216
Test name
Test status
Simulation time 98872805 ps
CPU time 0.61 seconds
Started Jul 10 05:11:38 PM PDT 24
Finished Jul 10 05:11:40 PM PDT 24
Peak memory 196104 kb
Host smart-2d428169-a0b9-4695-a705-61fdf5c1fd57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158120074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.158120074
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2398997775
Short name T359
Test name
Test status
Simulation time 3512528362 ps
CPU time 11.77 seconds
Started Jul 10 05:11:35 PM PDT 24
Finished Jul 10 05:11:48 PM PDT 24
Peak memory 200256 kb
Host smart-d81da733-3efa-4c0e-a3a0-cdfc2e4cf49b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2398997775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2398997775
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3506038745
Short name T505
Test name
Test status
Simulation time 20159787770 ps
CPU time 70.29 seconds
Started Jul 10 05:11:31 PM PDT 24
Finished Jul 10 05:12:42 PM PDT 24
Peak memory 208564 kb
Host smart-26897c71-3a86-40e6-8c73-8cf57e54ceda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506038745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3506038745
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.811914006
Short name T355
Test name
Test status
Simulation time 7584985196 ps
CPU time 692.51 seconds
Started Jul 10 05:11:29 PM PDT 24
Finished Jul 10 05:23:03 PM PDT 24
Peak memory 675768 kb
Host smart-0145004d-4ad9-4210-98ff-0743e22baf6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=811914006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.811914006
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.4145044976
Short name T61
Test name
Test status
Simulation time 6257281345 ps
CPU time 111.95 seconds
Started Jul 10 05:11:32 PM PDT 24
Finished Jul 10 05:13:25 PM PDT 24
Peak memory 200308 kb
Host smart-864e412a-d5d8-429d-8737-d68baa010b92
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145044976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.4145044976
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.4029964606
Short name T254
Test name
Test status
Simulation time 7898036081 ps
CPU time 114.89 seconds
Started Jul 10 05:11:35 PM PDT 24
Finished Jul 10 05:13:31 PM PDT 24
Peak memory 200292 kb
Host smart-3e7b1054-8418-498e-bc27-33ec46ae7be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029964606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.4029964606
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.455310448
Short name T341
Test name
Test status
Simulation time 1251284433 ps
CPU time 8.24 seconds
Started Jul 10 05:11:31 PM PDT 24
Finished Jul 10 05:11:41 PM PDT 24
Peak memory 200272 kb
Host smart-5d4b2282-abe1-42c8-bf3c-590dd3bbb125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455310448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.455310448
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3072264475
Short name T188
Test name
Test status
Simulation time 13333983283 ps
CPU time 1279.11 seconds
Started Jul 10 05:11:36 PM PDT 24
Finished Jul 10 05:32:56 PM PDT 24
Peak memory 712540 kb
Host smart-a4a0ef35-8e0b-4a5a-a78f-3fae5027b6fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072264475 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3072264475
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3316575697
Short name T377
Test name
Test status
Simulation time 12624883617 ps
CPU time 83.48 seconds
Started Jul 10 05:11:31 PM PDT 24
Finished Jul 10 05:12:55 PM PDT 24
Peak memory 200352 kb
Host smart-8e8e0e1f-95de-45d4-8e72-560317a513e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316575697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3316575697
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2905596198
Short name T164
Test name
Test status
Simulation time 50153272 ps
CPU time 0.58 seconds
Started Jul 10 05:10:11 PM PDT 24
Finished Jul 10 05:10:16 PM PDT 24
Peak memory 196176 kb
Host smart-fcfc295e-64d7-4cc9-9257-5e44221803d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905596198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2905596198
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3461432335
Short name T523
Test name
Test status
Simulation time 3630850645 ps
CPU time 53.76 seconds
Started Jul 10 05:10:11 PM PDT 24
Finished Jul 10 05:11:10 PM PDT 24
Peak memory 208464 kb
Host smart-02f70520-d752-4459-a61b-0a551b395f31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3461432335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3461432335
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.551088402
Short name T163
Test name
Test status
Simulation time 1086698813 ps
CPU time 15.19 seconds
Started Jul 10 05:10:15 PM PDT 24
Finished Jul 10 05:10:35 PM PDT 24
Peak memory 200312 kb
Host smart-0f382b1b-be01-49d2-855d-016bbce41440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551088402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.551088402
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2738685059
Short name T312
Test name
Test status
Simulation time 18784173583 ps
CPU time 779.45 seconds
Started Jul 10 05:10:13 PM PDT 24
Finished Jul 10 05:23:18 PM PDT 24
Peak memory 710404 kb
Host smart-7e5fd31d-5535-4fbb-8824-933ab5d6d82b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2738685059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2738685059
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3354479067
Short name T143
Test name
Test status
Simulation time 5582967864 ps
CPU time 38.63 seconds
Started Jul 10 05:10:14 PM PDT 24
Finished Jul 10 05:10:58 PM PDT 24
Peak memory 200208 kb
Host smart-7cfb1ab6-0eca-423f-af01-9efe56e864f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354479067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3354479067
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.4265918205
Short name T148
Test name
Test status
Simulation time 429532381 ps
CPU time 24.71 seconds
Started Jul 10 05:10:15 PM PDT 24
Finished Jul 10 05:10:45 PM PDT 24
Peak memory 200336 kb
Host smart-54408be5-074c-4af7-8894-c8e364e9f924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265918205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.4265918205
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.259370047
Short name T46
Test name
Test status
Simulation time 90198946 ps
CPU time 0.99 seconds
Started Jul 10 05:10:13 PM PDT 24
Finished Jul 10 05:10:20 PM PDT 24
Peak memory 219500 kb
Host smart-852a0445-dd02-4333-bf15-cc28a6b753f5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259370047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.259370047
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.55348182
Short name T474
Test name
Test status
Simulation time 2443078395 ps
CPU time 4.06 seconds
Started Jul 10 05:10:13 PM PDT 24
Finished Jul 10 05:10:22 PM PDT 24
Peak memory 200352 kb
Host smart-c5d21861-0b0f-4b1a-90fd-a3519ef8f794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55348182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.55348182
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.3782731799
Short name T286
Test name
Test status
Simulation time 36538344094 ps
CPU time 168.79 seconds
Started Jul 10 05:10:16 PM PDT 24
Finished Jul 10 05:13:10 PM PDT 24
Peak memory 208548 kb
Host smart-977c5b0e-3994-4a25-baf6-5e4326df8b1d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782731799 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.3782731799
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.831398945
Short name T12
Test name
Test status
Simulation time 174521018797 ps
CPU time 282.82 seconds
Started Jul 10 05:10:15 PM PDT 24
Finished Jul 10 05:15:03 PM PDT 24
Peak memory 216884 kb
Host smart-5988a301-e5c1-447d-91d3-65c13a172dd6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=831398945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.831398945
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.1501285651
Short name T504
Test name
Test status
Simulation time 10884854020 ps
CPU time 51.7 seconds
Started Jul 10 05:10:16 PM PDT 24
Finished Jul 10 05:11:13 PM PDT 24
Peak memory 200340 kb
Host smart-584ccbb1-8a04-4e3a-81c1-82a78e8dc35c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1501285651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.1501285651
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.2246525375
Short name T195
Test name
Test status
Simulation time 6036110743 ps
CPU time 99.19 seconds
Started Jul 10 05:10:09 PM PDT 24
Finished Jul 10 05:11:53 PM PDT 24
Peak memory 200308 kb
Host smart-8e79edb8-589a-4092-a2c0-3b08f448a75f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2246525375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.2246525375
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.927824086
Short name T298
Test name
Test status
Simulation time 35274454046 ps
CPU time 147.55 seconds
Started Jul 10 05:10:20 PM PDT 24
Finished Jul 10 05:12:52 PM PDT 24
Peak memory 200584 kb
Host smart-456cc7f1-aed6-4fab-a042-0b4be0e7f892
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=927824086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.927824086
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.3160744332
Short name T450
Test name
Test status
Simulation time 204846942745 ps
CPU time 651.75 seconds
Started Jul 10 05:10:13 PM PDT 24
Finished Jul 10 05:21:10 PM PDT 24
Peak memory 200380 kb
Host smart-cc4200e0-5887-43e9-85a4-4964087e2ea9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3160744332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.3160744332
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.3593513957
Short name T110
Test name
Test status
Simulation time 648883363275 ps
CPU time 2753.78 seconds
Started Jul 10 05:10:17 PM PDT 24
Finished Jul 10 05:56:16 PM PDT 24
Peak memory 215848 kb
Host smart-38b15c2b-9d72-4873-ba94-7b976a679d39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3593513957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.3593513957
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.3541941340
Short name T399
Test name
Test status
Simulation time 171923047372 ps
CPU time 2380.65 seconds
Started Jul 10 05:10:20 PM PDT 24
Finished Jul 10 05:50:06 PM PDT 24
Peak memory 215996 kb
Host smart-17fd5432-d0d4-4729-b137-22da2ee7085e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3541941340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.3541941340
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.2157864324
Short name T484
Test name
Test status
Simulation time 11927414506 ps
CPU time 93.53 seconds
Started Jul 10 05:10:20 PM PDT 24
Finished Jul 10 05:11:59 PM PDT 24
Peak memory 200320 kb
Host smart-6c1cba77-0d7f-4772-ba44-d965d3b7c06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157864324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.2157864324
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2230788575
Short name T457
Test name
Test status
Simulation time 26024351 ps
CPU time 0.6 seconds
Started Jul 10 05:11:32 PM PDT 24
Finished Jul 10 05:11:34 PM PDT 24
Peak memory 196192 kb
Host smart-96c309f5-78d1-4898-be13-699343106906
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230788575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2230788575
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1458140945
Short name T4
Test name
Test status
Simulation time 839292214 ps
CPU time 43.92 seconds
Started Jul 10 05:11:33 PM PDT 24
Finished Jul 10 05:12:18 PM PDT 24
Peak memory 200196 kb
Host smart-7c95d80e-ca84-4856-bb77-61ad0af49ba7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1458140945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1458140945
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3472670658
Short name T517
Test name
Test status
Simulation time 7265134278 ps
CPU time 56.83 seconds
Started Jul 10 05:11:31 PM PDT 24
Finished Jul 10 05:12:29 PM PDT 24
Peak memory 200324 kb
Host smart-10953317-8a96-405c-982a-ce9255a55813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472670658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3472670658
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1547366602
Short name T367
Test name
Test status
Simulation time 2327316985 ps
CPU time 69.19 seconds
Started Jul 10 05:11:36 PM PDT 24
Finished Jul 10 05:12:46 PM PDT 24
Peak memory 259444 kb
Host smart-b954e050-fae0-408d-9367-520ad67ba3c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1547366602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1547366602
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.3363132413
Short name T433
Test name
Test status
Simulation time 10854496552 ps
CPU time 184.32 seconds
Started Jul 10 05:11:30 PM PDT 24
Finished Jul 10 05:14:35 PM PDT 24
Peak memory 200264 kb
Host smart-ec05ff16-236e-43f0-9b00-de719ed54d38
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363132413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3363132413
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1201008389
Short name T458
Test name
Test status
Simulation time 21009441263 ps
CPU time 137.95 seconds
Started Jul 10 05:11:32 PM PDT 24
Finished Jul 10 05:13:51 PM PDT 24
Peak memory 216492 kb
Host smart-2b69f42e-324e-4ba8-8a0e-934bb27a542b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201008389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1201008389
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.435782738
Short name T274
Test name
Test status
Simulation time 157529032 ps
CPU time 4.38 seconds
Started Jul 10 05:11:29 PM PDT 24
Finished Jul 10 05:11:35 PM PDT 24
Peak memory 200212 kb
Host smart-62d9fba0-b738-4d89-9cfb-33f6eaa4396f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435782738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.435782738
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.114764636
Short name T354
Test name
Test status
Simulation time 48455445013 ps
CPU time 3558.83 seconds
Started Jul 10 05:11:34 PM PDT 24
Finished Jul 10 06:10:54 PM PDT 24
Peak memory 834024 kb
Host smart-11905186-c40c-4710-8b7f-ef1320bab3d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114764636 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.114764636
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2677647475
Short name T9
Test name
Test status
Simulation time 970143422 ps
CPU time 43.23 seconds
Started Jul 10 05:11:31 PM PDT 24
Finished Jul 10 05:12:15 PM PDT 24
Peak memory 200316 kb
Host smart-2ad86417-b74c-46f2-87b0-48663dd5fdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677647475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2677647475
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1930477808
Short name T290
Test name
Test status
Simulation time 29425528 ps
CPU time 0.58 seconds
Started Jul 10 05:11:38 PM PDT 24
Finished Jul 10 05:11:40 PM PDT 24
Peak memory 195152 kb
Host smart-fb5d7bfa-e5c9-4876-88c7-026b5a4230b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930477808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1930477808
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.4189235634
Short name T201
Test name
Test status
Simulation time 123300983 ps
CPU time 7.24 seconds
Started Jul 10 05:11:43 PM PDT 24
Finished Jul 10 05:11:51 PM PDT 24
Peak memory 200232 kb
Host smart-fa56418c-8dae-457e-9322-179e5efff4c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4189235634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.4189235634
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.537113108
Short name T190
Test name
Test status
Simulation time 2536292566 ps
CPU time 42.15 seconds
Started Jul 10 05:11:38 PM PDT 24
Finished Jul 10 05:12:22 PM PDT 24
Peak memory 200372 kb
Host smart-f27f1642-3d86-4b1c-8600-68c7a45ba208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537113108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.537113108
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2773588012
Short name T486
Test name
Test status
Simulation time 1973900651 ps
CPU time 383.5 seconds
Started Jul 10 05:11:38 PM PDT 24
Finished Jul 10 05:18:03 PM PDT 24
Peak memory 674424 kb
Host smart-1a2386b6-ec4d-4846-9af5-6ec6e4a3fded
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2773588012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2773588012
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.868458159
Short name T308
Test name
Test status
Simulation time 1180224236 ps
CPU time 64.31 seconds
Started Jul 10 05:11:38 PM PDT 24
Finished Jul 10 05:12:44 PM PDT 24
Peak memory 200216 kb
Host smart-9bab572c-e44e-4341-8032-5c06d27902b1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868458159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.868458159
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.971488401
Short name T436
Test name
Test status
Simulation time 3179180348 ps
CPU time 173.84 seconds
Started Jul 10 05:11:32 PM PDT 24
Finished Jul 10 05:14:27 PM PDT 24
Peak memory 200360 kb
Host smart-7cdb4eed-cd07-4d18-9764-0482b016b553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971488401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.971488401
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3557203483
Short name T37
Test name
Test status
Simulation time 551025004 ps
CPU time 7.67 seconds
Started Jul 10 05:11:33 PM PDT 24
Finished Jul 10 05:11:41 PM PDT 24
Peak memory 200276 kb
Host smart-70e0f712-251c-4889-b2a4-d119a11a7e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557203483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3557203483
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1831259690
Short name T24
Test name
Test status
Simulation time 15093362680 ps
CPU time 1273 seconds
Started Jul 10 05:11:38 PM PDT 24
Finished Jul 10 05:32:52 PM PDT 24
Peak memory 663364 kb
Host smart-c205eac8-93f5-412d-805d-0e3069f443e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831259690 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1831259690
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3611153327
Short name T379
Test name
Test status
Simulation time 1529331056 ps
CPU time 72.78 seconds
Started Jul 10 05:11:37 PM PDT 24
Finished Jul 10 05:12:51 PM PDT 24
Peak memory 200220 kb
Host smart-f7a29804-7854-4aae-a47f-554da979bf99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611153327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3611153327
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1670968785
Short name T161
Test name
Test status
Simulation time 26715034 ps
CPU time 0.61 seconds
Started Jul 10 05:11:47 PM PDT 24
Finished Jul 10 05:11:49 PM PDT 24
Peak memory 196852 kb
Host smart-76738819-3543-4cd6-82f5-c9f22229d894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670968785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1670968785
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2121199141
Short name T157
Test name
Test status
Simulation time 408247238 ps
CPU time 23.81 seconds
Started Jul 10 05:11:38 PM PDT 24
Finished Jul 10 05:12:03 PM PDT 24
Peak memory 200320 kb
Host smart-50b3c3aa-0e95-441d-8311-ea10c6e5a676
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2121199141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2121199141
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.77029831
Short name T310
Test name
Test status
Simulation time 49861536 ps
CPU time 2.78 seconds
Started Jul 10 05:11:38 PM PDT 24
Finished Jul 10 05:11:41 PM PDT 24
Peak memory 200216 kb
Host smart-09eaccd8-e527-4c1e-bb02-35b25347f423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77029831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.77029831
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.852540506
Short name T522
Test name
Test status
Simulation time 7876299067 ps
CPU time 729.51 seconds
Started Jul 10 05:11:43 PM PDT 24
Finished Jul 10 05:23:54 PM PDT 24
Peak memory 725184 kb
Host smart-e55fe059-59fc-4c03-9ccd-a6cb92676f3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=852540506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.852540506
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2003211100
Short name T411
Test name
Test status
Simulation time 3053072091 ps
CPU time 79.91 seconds
Started Jul 10 05:11:37 PM PDT 24
Finished Jul 10 05:12:57 PM PDT 24
Peak memory 200324 kb
Host smart-b4c3e271-6704-41c3-932f-0edc1b1db656
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003211100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2003211100
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1746123289
Short name T352
Test name
Test status
Simulation time 4085350611 ps
CPU time 112.85 seconds
Started Jul 10 05:11:43 PM PDT 24
Finished Jul 10 05:13:37 PM PDT 24
Peak memory 200268 kb
Host smart-97e74484-51c9-43ca-a7b0-7e6ca3812028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746123289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1746123289
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.2227915828
Short name T482
Test name
Test status
Simulation time 908438588 ps
CPU time 6.68 seconds
Started Jul 10 05:11:37 PM PDT 24
Finished Jul 10 05:11:45 PM PDT 24
Peak memory 200340 kb
Host smart-adde938c-2b52-47fd-a2ce-28aeb73d18d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227915828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.2227915828
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3208898735
Short name T131
Test name
Test status
Simulation time 123830262207 ps
CPU time 1411.41 seconds
Started Jul 10 05:11:38 PM PDT 24
Finished Jul 10 05:35:10 PM PDT 24
Peak memory 691060 kb
Host smart-8a57a159-1ef4-4c0d-b21c-900de4e5cdd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208898735 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3208898735
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.4035131576
Short name T222
Test name
Test status
Simulation time 4247400099 ps
CPU time 45.64 seconds
Started Jul 10 05:11:39 PM PDT 24
Finished Jul 10 05:12:25 PM PDT 24
Peak memory 200356 kb
Host smart-6e71b201-cc40-447b-927f-da9cedbb82e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035131576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.4035131576
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1814744086
Short name T330
Test name
Test status
Simulation time 140543315 ps
CPU time 0.59 seconds
Started Jul 10 05:11:47 PM PDT 24
Finished Jul 10 05:11:49 PM PDT 24
Peak memory 195836 kb
Host smart-12a621a3-9086-47c4-8afa-076e3a451369
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814744086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1814744086
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.619136259
Short name T344
Test name
Test status
Simulation time 823372662 ps
CPU time 30.27 seconds
Started Jul 10 05:11:46 PM PDT 24
Finished Jul 10 05:12:17 PM PDT 24
Peak memory 200324 kb
Host smart-79b965c5-d951-48cd-b50a-67ddb8ba2825
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=619136259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.619136259
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.445777117
Short name T443
Test name
Test status
Simulation time 1789845139 ps
CPU time 34.66 seconds
Started Jul 10 05:11:46 PM PDT 24
Finished Jul 10 05:12:22 PM PDT 24
Peak memory 200352 kb
Host smart-c5101bda-84b2-4a6f-b6c1-95b86dd9d6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445777117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.445777117
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.3601563488
Short name T218
Test name
Test status
Simulation time 25514757430 ps
CPU time 601.51 seconds
Started Jul 10 05:11:45 PM PDT 24
Finished Jul 10 05:21:47 PM PDT 24
Peak memory 716780 kb
Host smart-880c3f82-de51-4ca0-b5f2-a132a7c3567b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3601563488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3601563488
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.843136662
Short name T514
Test name
Test status
Simulation time 8143716731 ps
CPU time 118.29 seconds
Started Jul 10 05:11:46 PM PDT 24
Finished Jul 10 05:13:45 PM PDT 24
Peak memory 200256 kb
Host smart-fde68f11-b8f6-4ef7-9cb6-5da2c584d7bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843136662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.843136662
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2683430938
Short name T182
Test name
Test status
Simulation time 19966472242 ps
CPU time 196.91 seconds
Started Jul 10 05:11:49 PM PDT 24
Finished Jul 10 05:15:07 PM PDT 24
Peak memory 208608 kb
Host smart-93a41ec5-532b-49bf-a059-4a342f4dbce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683430938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2683430938
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2736103255
Short name T248
Test name
Test status
Simulation time 1520384955 ps
CPU time 7.01 seconds
Started Jul 10 05:11:46 PM PDT 24
Finished Jul 10 05:11:55 PM PDT 24
Peak memory 200272 kb
Host smart-43ce39eb-a81f-4a0d-bf57-eb5b77919b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736103255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2736103255
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3313336467
Short name T68
Test name
Test status
Simulation time 130455634755 ps
CPU time 2162.41 seconds
Started Jul 10 05:11:48 PM PDT 24
Finished Jul 10 05:47:52 PM PDT 24
Peak memory 759688 kb
Host smart-c0368b4a-1c73-48d8-8c8b-c582182beb89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313336467 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3313336467
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1527529182
Short name T267
Test name
Test status
Simulation time 2373299771 ps
CPU time 32.56 seconds
Started Jul 10 05:11:47 PM PDT 24
Finished Jul 10 05:12:21 PM PDT 24
Peak memory 200320 kb
Host smart-6d614dc7-ee24-4e99-aec3-bb75abf984a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527529182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1527529182
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.3719195979
Short name T264
Test name
Test status
Simulation time 48823399 ps
CPU time 0.6 seconds
Started Jul 10 05:11:57 PM PDT 24
Finished Jul 10 05:11:59 PM PDT 24
Peak memory 196860 kb
Host smart-34e820ed-bf22-475b-ae05-466542066a96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719195979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.3719195979
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.4027859553
Short name T466
Test name
Test status
Simulation time 5886150409 ps
CPU time 82.77 seconds
Started Jul 10 05:11:45 PM PDT 24
Finished Jul 10 05:13:09 PM PDT 24
Peak memory 200260 kb
Host smart-b276bac5-0b8e-468b-8323-e6fa5eb5c68e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4027859553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.4027859553
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3553216385
Short name T219
Test name
Test status
Simulation time 393627610 ps
CPU time 22.38 seconds
Started Jul 10 05:11:46 PM PDT 24
Finished Jul 10 05:12:10 PM PDT 24
Peak memory 200492 kb
Host smart-0a4ca2fa-f141-44ed-9936-d89da99596fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553216385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3553216385
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.323261427
Short name T467
Test name
Test status
Simulation time 5150482707 ps
CPU time 132.6 seconds
Started Jul 10 05:11:46 PM PDT 24
Finished Jul 10 05:14:00 PM PDT 24
Peak memory 282612 kb
Host smart-8aa94ca4-b265-4f25-aef2-d83f06fe7cff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=323261427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.323261427
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1398412088
Short name T502
Test name
Test status
Simulation time 2073172255 ps
CPU time 108.42 seconds
Started Jul 10 05:11:51 PM PDT 24
Finished Jul 10 05:13:41 PM PDT 24
Peak memory 200296 kb
Host smart-d647969c-cda1-4779-820c-f2567efa4332
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398412088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1398412088
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.4095468188
Short name T404
Test name
Test status
Simulation time 1829499137 ps
CPU time 5.29 seconds
Started Jul 10 05:11:44 PM PDT 24
Finished Jul 10 05:11:51 PM PDT 24
Peak memory 200248 kb
Host smart-29405862-d659-4cc0-bf62-032a740bb0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095468188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.4095468188
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2242092073
Short name T153
Test name
Test status
Simulation time 1133571453 ps
CPU time 14.01 seconds
Started Jul 10 05:11:46 PM PDT 24
Finished Jul 10 05:12:02 PM PDT 24
Peak memory 200512 kb
Host smart-37917df7-e284-4ec6-a48c-984afbd6ae2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242092073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2242092073
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2209251345
Short name T23
Test name
Test status
Simulation time 24186513105 ps
CPU time 634.37 seconds
Started Jul 10 05:11:55 PM PDT 24
Finished Jul 10 05:22:30 PM PDT 24
Peak memory 200264 kb
Host smart-267876fb-ea25-4057-9691-c8d230e850dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209251345 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2209251345
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1465998123
Short name T518
Test name
Test status
Simulation time 1354069145 ps
CPU time 17.75 seconds
Started Jul 10 05:11:51 PM PDT 24
Finished Jul 10 05:12:10 PM PDT 24
Peak memory 200288 kb
Host smart-e0be63bb-d7bb-48df-90b7-78a2bc6591e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465998123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1465998123
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2378898912
Short name T295
Test name
Test status
Simulation time 54657480 ps
CPU time 0.6 seconds
Started Jul 10 05:11:58 PM PDT 24
Finished Jul 10 05:12:00 PM PDT 24
Peak memory 196192 kb
Host smart-32c4b3e2-f1a7-423c-b56d-3d31fdd769e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378898912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2378898912
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1134575324
Short name T135
Test name
Test status
Simulation time 474220026 ps
CPU time 6.66 seconds
Started Jul 10 05:11:52 PM PDT 24
Finished Jul 10 05:12:00 PM PDT 24
Peak memory 200208 kb
Host smart-117d1a6b-3dfc-432d-bcb5-281d8a6356c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1134575324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1134575324
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2379320748
Short name T230
Test name
Test status
Simulation time 10376365442 ps
CPU time 68.33 seconds
Started Jul 10 05:11:53 PM PDT 24
Finished Jul 10 05:13:03 PM PDT 24
Peak memory 200412 kb
Host smart-70cf7a50-2dfb-4bad-96e3-a53040e244b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379320748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2379320748
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.361493076
Short name T332
Test name
Test status
Simulation time 13450892085 ps
CPU time 526.21 seconds
Started Jul 10 05:11:58 PM PDT 24
Finished Jul 10 05:20:46 PM PDT 24
Peak memory 696620 kb
Host smart-89c4f7ee-3ee9-4071-87a6-ddf8d39bacb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=361493076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.361493076
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.4001372503
Short name T488
Test name
Test status
Simulation time 15932560180 ps
CPU time 135.09 seconds
Started Jul 10 05:11:51 PM PDT 24
Finished Jul 10 05:14:06 PM PDT 24
Peak memory 200256 kb
Host smart-71ce24cb-8cd9-451e-8f06-55345015fc1c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001372503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.4001372503
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.505352413
Short name T120
Test name
Test status
Simulation time 1460507152 ps
CPU time 78.13 seconds
Started Jul 10 05:11:53 PM PDT 24
Finished Jul 10 05:13:12 PM PDT 24
Peak memory 200296 kb
Host smart-025bb624-050f-432c-b621-97ed9f935ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505352413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.505352413
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1189786618
Short name T215
Test name
Test status
Simulation time 1273748984 ps
CPU time 7.81 seconds
Started Jul 10 05:11:50 PM PDT 24
Finished Jul 10 05:11:59 PM PDT 24
Peak memory 200216 kb
Host smart-f5bc9334-432f-428f-978d-b953854024a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189786618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1189786618
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2846538916
Short name T129
Test name
Test status
Simulation time 32612241445 ps
CPU time 836.55 seconds
Started Jul 10 05:11:51 PM PDT 24
Finished Jul 10 05:25:49 PM PDT 24
Peak memory 697788 kb
Host smart-c384d30e-324c-4783-88a9-d70a398ee6fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846538916 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2846538916
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.545621640
Short name T126
Test name
Test status
Simulation time 2032944537 ps
CPU time 37.76 seconds
Started Jul 10 05:11:52 PM PDT 24
Finished Jul 10 05:12:32 PM PDT 24
Peak memory 200268 kb
Host smart-f0ee27c9-f2ab-42f4-8b19-7acfb3a5b4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545621640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.545621640
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2626330650
Short name T414
Test name
Test status
Simulation time 72635853 ps
CPU time 0.58 seconds
Started Jul 10 05:11:58 PM PDT 24
Finished Jul 10 05:12:01 PM PDT 24
Peak memory 196116 kb
Host smart-0265c06e-d930-4f37-a682-99507ea41e8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626330650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2626330650
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.4115656135
Short name T36
Test name
Test status
Simulation time 1242266661 ps
CPU time 71.56 seconds
Started Jul 10 05:11:53 PM PDT 24
Finished Jul 10 05:13:05 PM PDT 24
Peak memory 200284 kb
Host smart-8ba5da2a-4d55-485e-8638-cd36b6d9aa0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4115656135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.4115656135
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.453598601
Short name T174
Test name
Test status
Simulation time 1407362857 ps
CPU time 19.68 seconds
Started Jul 10 05:11:51 PM PDT 24
Finished Jul 10 05:12:12 PM PDT 24
Peak memory 200272 kb
Host smart-caf57ae8-077c-48b9-b685-a6a5f532b14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453598601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.453598601
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.577531430
Short name T205
Test name
Test status
Simulation time 25225977281 ps
CPU time 1092.57 seconds
Started Jul 10 05:11:52 PM PDT 24
Finished Jul 10 05:30:06 PM PDT 24
Peak memory 734212 kb
Host smart-1805da85-0bdc-45a2-9dfd-3d46ea299b66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=577531430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.577531430
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2476547637
Short name T122
Test name
Test status
Simulation time 2494852602 ps
CPU time 32.42 seconds
Started Jul 10 05:11:58 PM PDT 24
Finished Jul 10 05:12:31 PM PDT 24
Peak memory 200308 kb
Host smart-89d3b341-d428-4b63-8e3c-eced274578c5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476547637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2476547637
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1603244909
Short name T462
Test name
Test status
Simulation time 3871837612 ps
CPU time 218.42 seconds
Started Jul 10 05:11:55 PM PDT 24
Finished Jul 10 05:15:34 PM PDT 24
Peak memory 216544 kb
Host smart-c15be892-b5d6-4116-bc52-641f17014957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603244909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1603244909
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1633904542
Short name T446
Test name
Test status
Simulation time 480830063 ps
CPU time 11.31 seconds
Started Jul 10 05:11:51 PM PDT 24
Finished Jul 10 05:12:04 PM PDT 24
Peak memory 200352 kb
Host smart-e4428be0-41c4-4e9b-b85f-58b9a42d9dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633904542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1633904542
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.265095910
Short name T72
Test name
Test status
Simulation time 56096441721 ps
CPU time 1898.71 seconds
Started Jul 10 05:11:52 PM PDT 24
Finished Jul 10 05:43:32 PM PDT 24
Peak memory 777032 kb
Host smart-a47208e3-48ff-4418-aca7-a14763dab947
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265095910 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.265095910
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.276651811
Short name T266
Test name
Test status
Simulation time 17167591485 ps
CPU time 50.07 seconds
Started Jul 10 05:11:51 PM PDT 24
Finished Jul 10 05:12:43 PM PDT 24
Peak memory 200332 kb
Host smart-2dfb65c6-3514-4f03-b065-196e01c313bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276651811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.276651811
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.4045644758
Short name T180
Test name
Test status
Simulation time 14227633 ps
CPU time 0.6 seconds
Started Jul 10 05:11:58 PM PDT 24
Finished Jul 10 05:12:01 PM PDT 24
Peak memory 196116 kb
Host smart-89003763-7bce-4017-8829-e84677d74f35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045644758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.4045644758
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.415343569
Short name T322
Test name
Test status
Simulation time 4227961157 ps
CPU time 61.73 seconds
Started Jul 10 05:11:58 PM PDT 24
Finished Jul 10 05:13:02 PM PDT 24
Peak memory 200388 kb
Host smart-2f3af790-4a84-4d7b-af8a-e313f8baf21a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=415343569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.415343569
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.3364952730
Short name T197
Test name
Test status
Simulation time 7729780850 ps
CPU time 67.11 seconds
Started Jul 10 05:11:59 PM PDT 24
Finished Jul 10 05:13:08 PM PDT 24
Peak memory 200244 kb
Host smart-24afff5b-76bf-46a3-a4e6-5880bb686bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364952730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.3364952730
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.2052433227
Short name T33
Test name
Test status
Simulation time 9116359687 ps
CPU time 903.34 seconds
Started Jul 10 05:11:58 PM PDT 24
Finished Jul 10 05:27:03 PM PDT 24
Peak memory 724124 kb
Host smart-10af4a48-3081-4a16-a430-0c4a27ac4846
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2052433227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.2052433227
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1447794377
Short name T387
Test name
Test status
Simulation time 63797243455 ps
CPU time 193.1 seconds
Started Jul 10 05:11:58 PM PDT 24
Finished Jul 10 05:15:13 PM PDT 24
Peak memory 200240 kb
Host smart-dfcd4a5d-c0a8-45ce-a294-27151be54769
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447794377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1447794377
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1278733926
Short name T422
Test name
Test status
Simulation time 6097565218 ps
CPU time 137.04 seconds
Started Jul 10 05:11:57 PM PDT 24
Finished Jul 10 05:14:15 PM PDT 24
Peak memory 200324 kb
Host smart-319b2e91-6f98-4b8b-8330-f0b7b0a63c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278733926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1278733926
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.4143958739
Short name T183
Test name
Test status
Simulation time 559664159 ps
CPU time 3.02 seconds
Started Jul 10 05:11:54 PM PDT 24
Finished Jul 10 05:11:58 PM PDT 24
Peak memory 200236 kb
Host smart-e74e9e4f-26c1-4403-968c-4faa57d16826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143958739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.4143958739
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.1169577518
Short name T78
Test name
Test status
Simulation time 94731264798 ps
CPU time 3023.25 seconds
Started Jul 10 05:11:58 PM PDT 24
Finished Jul 10 06:02:24 PM PDT 24
Peak memory 818360 kb
Host smart-35c4584a-899a-465a-b299-fe04e6630646
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169577518 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.1169577518
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1269409736
Short name T253
Test name
Test status
Simulation time 7652178049 ps
CPU time 34.17 seconds
Started Jul 10 05:11:58 PM PDT 24
Finished Jul 10 05:12:34 PM PDT 24
Peak memory 200276 kb
Host smart-62cc0042-95de-4df2-95b7-ddcfd3575533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269409736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1269409736
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.524402701
Short name T489
Test name
Test status
Simulation time 42590028 ps
CPU time 0.62 seconds
Started Jul 10 05:11:59 PM PDT 24
Finished Jul 10 05:12:01 PM PDT 24
Peak memory 195752 kb
Host smart-2578f3cc-dd32-41ca-8888-c1a23e66ec44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524402701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.524402701
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.584408557
Short name T470
Test name
Test status
Simulation time 345320243 ps
CPU time 9.39 seconds
Started Jul 10 05:11:59 PM PDT 24
Finished Jul 10 05:12:10 PM PDT 24
Peak memory 200192 kb
Host smart-af957c41-0bb0-4fa9-9842-f28bd41baf72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=584408557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.584408557
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.592367351
Short name T475
Test name
Test status
Simulation time 12943028107 ps
CPU time 23.2 seconds
Started Jul 10 05:11:57 PM PDT 24
Finished Jul 10 05:12:21 PM PDT 24
Peak memory 200380 kb
Host smart-c38981ca-d775-418e-90ad-dd7146aaae35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592367351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.592367351
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3205335984
Short name T389
Test name
Test status
Simulation time 5137733729 ps
CPU time 924.33 seconds
Started Jul 10 05:11:58 PM PDT 24
Finished Jul 10 05:27:24 PM PDT 24
Peak memory 684376 kb
Host smart-6a2c58bf-7f76-4abc-aced-efcb488d4a4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3205335984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3205335984
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3852715374
Short name T302
Test name
Test status
Simulation time 6129372587 ps
CPU time 71.59 seconds
Started Jul 10 05:11:56 PM PDT 24
Finished Jul 10 05:13:09 PM PDT 24
Peak memory 200320 kb
Host smart-ad93f3ee-130f-4d98-890d-c9b050086578
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852715374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3852715374
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.701724007
Short name T173
Test name
Test status
Simulation time 22170860179 ps
CPU time 161.05 seconds
Started Jul 10 05:11:58 PM PDT 24
Finished Jul 10 05:14:41 PM PDT 24
Peak memory 200284 kb
Host smart-f3a48e8a-e02c-4ab3-b3dd-d86d02a398ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701724007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.701724007
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1180467023
Short name T407
Test name
Test status
Simulation time 8073426888 ps
CPU time 10.08 seconds
Started Jul 10 05:12:03 PM PDT 24
Finished Jul 10 05:12:15 PM PDT 24
Peak memory 200400 kb
Host smart-b4acb995-68a5-4aae-a2b2-ac319757b572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180467023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1180467023
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2727142409
Short name T395
Test name
Test status
Simulation time 306767985 ps
CPU time 4.46 seconds
Started Jul 10 05:11:59 PM PDT 24
Finished Jul 10 05:12:05 PM PDT 24
Peak memory 200168 kb
Host smart-310e1060-724e-40d3-ae97-7e2641b2f9d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727142409 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2727142409
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.252075086
Short name T381
Test name
Test status
Simulation time 3398476034 ps
CPU time 43.28 seconds
Started Jul 10 05:11:58 PM PDT 24
Finished Jul 10 05:12:44 PM PDT 24
Peak memory 200292 kb
Host smart-407b340d-b9b1-4202-b29e-6e167f5acb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252075086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.252075086
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3342737441
Short name T452
Test name
Test status
Simulation time 27219679 ps
CPU time 0.59 seconds
Started Jul 10 05:12:05 PM PDT 24
Finished Jul 10 05:12:07 PM PDT 24
Peak memory 195076 kb
Host smart-5fc3304f-cfb7-414a-ad13-dd0466f38431
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342737441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3342737441
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2356644361
Short name T223
Test name
Test status
Simulation time 454556003 ps
CPU time 6.41 seconds
Started Jul 10 05:12:05 PM PDT 24
Finished Jul 10 05:12:13 PM PDT 24
Peak memory 200272 kb
Host smart-d39b41fd-3926-40c6-809e-e628357af10f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2356644361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2356644361
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2670161070
Short name T500
Test name
Test status
Simulation time 1653647191 ps
CPU time 26.66 seconds
Started Jul 10 05:12:04 PM PDT 24
Finished Jul 10 05:12:31 PM PDT 24
Peak memory 200224 kb
Host smart-3a0604ce-e9dc-4e8e-a207-2b1de226f13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670161070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2670161070
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3308257362
Short name T294
Test name
Test status
Simulation time 13223996235 ps
CPU time 1353.57 seconds
Started Jul 10 05:12:04 PM PDT 24
Finished Jul 10 05:34:39 PM PDT 24
Peak memory 732612 kb
Host smart-4897d7d2-25c4-4c11-ba7f-fa029dedbd57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3308257362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3308257362
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1461188938
Short name T284
Test name
Test status
Simulation time 1303093299 ps
CPU time 36.42 seconds
Started Jul 10 05:12:05 PM PDT 24
Finished Jul 10 05:12:43 PM PDT 24
Peak memory 200272 kb
Host smart-bcbacfd9-9956-4728-b254-0cc12965256b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461188938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1461188938
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2710113983
Short name T282
Test name
Test status
Simulation time 2005686884 ps
CPU time 125.6 seconds
Started Jul 10 05:12:03 PM PDT 24
Finished Jul 10 05:14:09 PM PDT 24
Peak memory 200268 kb
Host smart-4634d504-e47d-4cc8-a910-7bf8f69c3398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710113983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2710113983
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.1475442987
Short name T113
Test name
Test status
Simulation time 3472726072 ps
CPU time 14.11 seconds
Started Jul 10 05:12:03 PM PDT 24
Finished Jul 10 05:12:18 PM PDT 24
Peak memory 200356 kb
Host smart-2e093c67-f486-41f4-b363-aa956a9e0c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475442987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1475442987
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2735652450
Short name T99
Test name
Test status
Simulation time 76933250569 ps
CPU time 986.01 seconds
Started Jul 10 05:12:05 PM PDT 24
Finished Jul 10 05:28:32 PM PDT 24
Peak memory 711348 kb
Host smart-7fba14b0-add9-4c6a-b297-ea1ebfa708a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735652450 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2735652450
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3046873203
Short name T165
Test name
Test status
Simulation time 30394099905 ps
CPU time 109.72 seconds
Started Jul 10 05:12:03 PM PDT 24
Finished Jul 10 05:13:54 PM PDT 24
Peak memory 200272 kb
Host smart-60e73ac4-6418-43d6-9692-7212be26e05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046873203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3046873203
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.712960262
Short name T472
Test name
Test status
Simulation time 14731417 ps
CPU time 0.6 seconds
Started Jul 10 05:10:09 PM PDT 24
Finished Jul 10 05:10:14 PM PDT 24
Peak memory 195152 kb
Host smart-1d04df35-f68a-43a0-ae54-ef41176ccc24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712960262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.712960262
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.656904352
Short name T144
Test name
Test status
Simulation time 1753914470 ps
CPU time 95.06 seconds
Started Jul 10 05:10:14 PM PDT 24
Finished Jul 10 05:11:55 PM PDT 24
Peak memory 200312 kb
Host smart-a2292b6b-a265-42f3-8591-4615c7a96dd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=656904352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.656904352
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.927425927
Short name T257
Test name
Test status
Simulation time 2114377370 ps
CPU time 7.85 seconds
Started Jul 10 05:10:13 PM PDT 24
Finished Jul 10 05:10:27 PM PDT 24
Peak memory 200308 kb
Host smart-3f0e101a-ea06-4b9f-b551-7cc3250ac552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927425927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.927425927
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.255327121
Short name T319
Test name
Test status
Simulation time 16570495821 ps
CPU time 715.54 seconds
Started Jul 10 05:10:10 PM PDT 24
Finished Jul 10 05:22:11 PM PDT 24
Peak memory 620744 kb
Host smart-c6ec7bfb-5a4d-482a-9143-e63ea0f1c724
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=255327121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.255327121
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1023482979
Short name T203
Test name
Test status
Simulation time 140792321829 ps
CPU time 92.65 seconds
Started Jul 10 05:10:17 PM PDT 24
Finished Jul 10 05:11:55 PM PDT 24
Peak memory 200336 kb
Host smart-82a1cdbb-3c6c-4834-ab5e-ddc14273250c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023482979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1023482979
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.936433340
Short name T276
Test name
Test status
Simulation time 17818671620 ps
CPU time 155.46 seconds
Started Jul 10 05:10:13 PM PDT 24
Finished Jul 10 05:12:54 PM PDT 24
Peak memory 200248 kb
Host smart-425fd793-ba29-4691-9be0-b7de2014fb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936433340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.936433340
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2557396704
Short name T444
Test name
Test status
Simulation time 8453334091 ps
CPU time 14.72 seconds
Started Jul 10 05:10:21 PM PDT 24
Finished Jul 10 05:10:41 PM PDT 24
Peak memory 200328 kb
Host smart-d1c35848-838e-4245-8f3a-37663b7a3f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557396704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2557396704
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.2262742236
Short name T382
Test name
Test status
Simulation time 43931732639 ps
CPU time 73.49 seconds
Started Jul 10 05:10:10 PM PDT 24
Finished Jul 10 05:11:29 PM PDT 24
Peak memory 200304 kb
Host smart-9a72682c-3ad5-40ec-a0d9-1c495368ff66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262742236 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2262742236
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.657526509
Short name T497
Test name
Test status
Simulation time 213893039 ps
CPU time 5.09 seconds
Started Jul 10 05:10:15 PM PDT 24
Finished Jul 10 05:10:25 PM PDT 24
Peak memory 200352 kb
Host smart-e0f6e7b3-3b0c-4352-ab64-ebfdb86cb9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657526509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.657526509
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1743428041
Short name T225
Test name
Test status
Simulation time 71914439 ps
CPU time 0.58 seconds
Started Jul 10 05:10:17 PM PDT 24
Finished Jul 10 05:10:23 PM PDT 24
Peak memory 195152 kb
Host smart-76c09a3e-43b6-4b34-bc52-2fa788555d17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743428041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1743428041
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3084283503
Short name T260
Test name
Test status
Simulation time 760746963 ps
CPU time 45.19 seconds
Started Jul 10 05:10:20 PM PDT 24
Finished Jul 10 05:11:10 PM PDT 24
Peak memory 200488 kb
Host smart-ab9636a5-17ae-47fd-afd3-f5144606118f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3084283503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3084283503
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3394392469
Short name T166
Test name
Test status
Simulation time 2236131956 ps
CPU time 40.07 seconds
Started Jul 10 05:10:09 PM PDT 24
Finished Jul 10 05:10:54 PM PDT 24
Peak memory 200292 kb
Host smart-883cd1a2-1939-4b57-b8ee-797b5dd95d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394392469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3394392469
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1711715634
Short name T350
Test name
Test status
Simulation time 1278744235 ps
CPU time 214.17 seconds
Started Jul 10 05:10:13 PM PDT 24
Finished Jul 10 05:13:52 PM PDT 24
Peak memory 610252 kb
Host smart-eddd336f-f0d8-431f-9e49-72f57ea6d40a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1711715634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1711715634
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3802596342
Short name T445
Test name
Test status
Simulation time 1407215683 ps
CPU time 41.42 seconds
Started Jul 10 05:10:13 PM PDT 24
Finished Jul 10 05:11:00 PM PDT 24
Peak memory 200236 kb
Host smart-47822b81-0a9a-4284-8daa-828487ccfb3d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802596342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3802596342
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.2944444360
Short name T245
Test name
Test status
Simulation time 3506141523 ps
CPU time 16.48 seconds
Started Jul 10 05:10:23 PM PDT 24
Finished Jul 10 05:10:44 PM PDT 24
Peak memory 200352 kb
Host smart-b0b81d66-a3d0-4b0a-b1c4-074e8b8e8db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944444360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2944444360
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3047316030
Short name T263
Test name
Test status
Simulation time 5246668022 ps
CPU time 11.56 seconds
Started Jul 10 05:10:13 PM PDT 24
Finished Jul 10 05:10:30 PM PDT 24
Peak memory 200264 kb
Host smart-bfb649de-52cd-4d94-a6e6-10dd90fd2a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047316030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3047316030
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.993553005
Short name T16
Test name
Test status
Simulation time 164633975843 ps
CPU time 4093.76 seconds
Started Jul 10 05:10:19 PM PDT 24
Finished Jul 10 06:18:38 PM PDT 24
Peak memory 750936 kb
Host smart-7e63b328-8902-4632-bf2d-d2eb4244de2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=993553005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.993553005
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.609982188
Short name T237
Test name
Test status
Simulation time 5788714877 ps
CPU time 57.17 seconds
Started Jul 10 05:10:14 PM PDT 24
Finished Jul 10 05:11:17 PM PDT 24
Peak memory 200368 kb
Host smart-d1f5a59f-4128-4ab3-a70b-b544f1e3f07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609982188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.609982188
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3255009093
Short name T280
Test name
Test status
Simulation time 49276776 ps
CPU time 0.59 seconds
Started Jul 10 05:10:16 PM PDT 24
Finished Jul 10 05:10:22 PM PDT 24
Peak memory 196100 kb
Host smart-ceac8912-d37c-40c8-a985-e0d09f098ce7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255009093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3255009093
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2807103417
Short name T277
Test name
Test status
Simulation time 536056344 ps
CPU time 31.66 seconds
Started Jul 10 05:10:24 PM PDT 24
Finished Jul 10 05:11:00 PM PDT 24
Peak memory 200152 kb
Host smart-e368c3c2-60f8-4c8c-a81f-3e9b396bc033
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2807103417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2807103417
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1120726950
Short name T50
Test name
Test status
Simulation time 3294657778 ps
CPU time 12.54 seconds
Started Jul 10 05:10:24 PM PDT 24
Finished Jul 10 05:10:41 PM PDT 24
Peak memory 200224 kb
Host smart-a0b3b573-529c-415f-ac8f-e846eef3bf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120726950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1120726950
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3812455329
Short name T48
Test name
Test status
Simulation time 7623100595 ps
CPU time 157.7 seconds
Started Jul 10 05:10:19 PM PDT 24
Finished Jul 10 05:13:02 PM PDT 24
Peak memory 563184 kb
Host smart-72260dd8-0180-495d-abf6-614be0a78132
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3812455329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3812455329
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.4079877618
Short name T123
Test name
Test status
Simulation time 19311746574 ps
CPU time 44.3 seconds
Started Jul 10 05:10:16 PM PDT 24
Finished Jul 10 05:11:06 PM PDT 24
Peak memory 200260 kb
Host smart-0ea59149-6d42-4810-9d1d-40e5ed335b80
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079877618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.4079877618
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1032764548
Short name T311
Test name
Test status
Simulation time 509724307 ps
CPU time 29.68 seconds
Started Jul 10 05:10:24 PM PDT 24
Finished Jul 10 05:10:58 PM PDT 24
Peak memory 200272 kb
Host smart-c2f4d986-56cd-4056-b8b6-003ff7017c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032764548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1032764548
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1821212746
Short name T317
Test name
Test status
Simulation time 3167468996 ps
CPU time 11.96 seconds
Started Jul 10 05:10:18 PM PDT 24
Finished Jul 10 05:10:35 PM PDT 24
Peak memory 200344 kb
Host smart-05d16c53-3ae8-44a9-adac-4090cc3df95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821212746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1821212746
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.590652126
Short name T67
Test name
Test status
Simulation time 155871537663 ps
CPU time 1010.82 seconds
Started Jul 10 05:10:15 PM PDT 24
Finished Jul 10 05:27:12 PM PDT 24
Peak memory 216668 kb
Host smart-3e9d6d54-4bee-4752-9005-343527c4a004
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590652126 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.590652126
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.730817952
Short name T348
Test name
Test status
Simulation time 138519946482 ps
CPU time 111.76 seconds
Started Jul 10 05:10:25 PM PDT 24
Finished Jul 10 05:12:21 PM PDT 24
Peak memory 200348 kb
Host smart-3b2a125d-ea39-4cb4-8fd1-ab7159561476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730817952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.730817952
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.753693250
Short name T361
Test name
Test status
Simulation time 14906652 ps
CPU time 0.59 seconds
Started Jul 10 05:10:18 PM PDT 24
Finished Jul 10 05:10:24 PM PDT 24
Peak memory 195848 kb
Host smart-4ad6dc45-6ad2-4b5d-a761-cb7ca5b402e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753693250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.753693250
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.4120146826
Short name T134
Test name
Test status
Simulation time 573408170 ps
CPU time 33.63 seconds
Started Jul 10 05:10:26 PM PDT 24
Finished Jul 10 05:11:04 PM PDT 24
Peak memory 200252 kb
Host smart-b8ffe20a-520d-4e52-9fc6-0bf6acc77f83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4120146826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.4120146826
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3329960035
Short name T167
Test name
Test status
Simulation time 5111393440 ps
CPU time 16 seconds
Started Jul 10 05:10:19 PM PDT 24
Finished Jul 10 05:10:40 PM PDT 24
Peak memory 200276 kb
Host smart-25686c2e-f2ab-4ef4-a5b5-ea3a29059a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329960035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3329960035
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.3031294182
Short name T156
Test name
Test status
Simulation time 270967693 ps
CPU time 39.94 seconds
Started Jul 10 05:10:16 PM PDT 24
Finished Jul 10 05:11:01 PM PDT 24
Peak memory 306808 kb
Host smart-03abae81-8f59-4676-913c-7ecf5d8a92a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3031294182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.3031294182
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2851420551
Short name T287
Test name
Test status
Simulation time 12185159475 ps
CPU time 146.67 seconds
Started Jul 10 05:10:18 PM PDT 24
Finished Jul 10 05:12:50 PM PDT 24
Peak memory 200372 kb
Host smart-b28e60a8-5a2a-458f-b2b8-94dd579e610a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851420551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2851420551
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.2488124821
Short name T256
Test name
Test status
Simulation time 1176268344 ps
CPU time 6.99 seconds
Started Jul 10 05:10:19 PM PDT 24
Finished Jul 10 05:10:31 PM PDT 24
Peak memory 200336 kb
Host smart-9bb02c0d-9716-4dac-998c-ccce933da930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488124821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2488124821
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.633389491
Short name T314
Test name
Test status
Simulation time 250327347 ps
CPU time 3.53 seconds
Started Jul 10 05:10:18 PM PDT 24
Finished Jul 10 05:10:27 PM PDT 24
Peak memory 200220 kb
Host smart-9f150af2-35c7-4d53-8fdb-fbe45cf851d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633389491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.633389491
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.746558562
Short name T401
Test name
Test status
Simulation time 146903429309 ps
CPU time 5560.94 seconds
Started Jul 10 05:10:24 PM PDT 24
Finished Jul 10 06:43:10 PM PDT 24
Peak memory 884940 kb
Host smart-7c8c4283-5d2c-4fee-bdc9-443827b28de6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746558562 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.746558562
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.1910583973
Short name T21
Test name
Test status
Simulation time 93856023286 ps
CPU time 4749.46 seconds
Started Jul 10 05:10:19 PM PDT 24
Finished Jul 10 06:29:34 PM PDT 24
Peak memory 795432 kb
Host smart-1c07c5b5-613d-4ff7-bb24-58f400db89ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1910583973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.1910583973
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1825608272
Short name T234
Test name
Test status
Simulation time 2384562225 ps
CPU time 109.84 seconds
Started Jul 10 05:10:21 PM PDT 24
Finished Jul 10 05:12:16 PM PDT 24
Peak memory 200316 kb
Host smart-cdf6a964-e16a-45b5-9c1c-8eb629e92c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825608272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1825608272
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.4146804243
Short name T30
Test name
Test status
Simulation time 36722391 ps
CPU time 0.55 seconds
Started Jul 10 05:10:33 PM PDT 24
Finished Jul 10 05:10:36 PM PDT 24
Peak memory 195064 kb
Host smart-a71cde73-624f-4ae1-889b-45736176769e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146804243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.4146804243
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1326262977
Short name T334
Test name
Test status
Simulation time 1900623187 ps
CPU time 24.95 seconds
Started Jul 10 05:10:24 PM PDT 24
Finished Jul 10 05:10:53 PM PDT 24
Peak memory 200316 kb
Host smart-9b1d00a2-ec61-4168-b5db-472202e5207e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1326262977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1326262977
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2466093152
Short name T478
Test name
Test status
Simulation time 268104015 ps
CPU time 14.57 seconds
Started Jul 10 05:10:15 PM PDT 24
Finished Jul 10 05:10:35 PM PDT 24
Peak memory 200216 kb
Host smart-0b4093ab-6c94-47fc-8fd0-7fd0778277dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466093152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2466093152
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.133337321
Short name T206
Test name
Test status
Simulation time 16409289419 ps
CPU time 776.42 seconds
Started Jul 10 05:10:19 PM PDT 24
Finished Jul 10 05:23:20 PM PDT 24
Peak memory 712088 kb
Host smart-04dc8461-2f8f-4d39-ae50-360fe5286338
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=133337321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.133337321
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2455550443
Short name T119
Test name
Test status
Simulation time 1538380174 ps
CPU time 29.04 seconds
Started Jul 10 05:10:22 PM PDT 24
Finished Jul 10 05:10:56 PM PDT 24
Peak memory 200276 kb
Host smart-d236adfd-17bb-4149-a2fc-17116b026201
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455550443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2455550443
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2487435925
Short name T318
Test name
Test status
Simulation time 986870343 ps
CPU time 4.53 seconds
Started Jul 10 05:10:21 PM PDT 24
Finished Jul 10 05:10:30 PM PDT 24
Peak memory 200260 kb
Host smart-c02132d9-e1f2-4159-997b-0e27d481e682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487435925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2487435925
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1485075129
Short name T121
Test name
Test status
Simulation time 380428824 ps
CPU time 3.42 seconds
Started Jul 10 05:10:17 PM PDT 24
Finished Jul 10 05:10:25 PM PDT 24
Peak memory 200288 kb
Host smart-cb3ba3d1-8091-4d89-af13-72fafbaedbe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485075129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1485075129
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2601296505
Short name T114
Test name
Test status
Simulation time 46856435428 ps
CPU time 406.87 seconds
Started Jul 10 05:10:17 PM PDT 24
Finished Jul 10 05:17:09 PM PDT 24
Peak memory 208512 kb
Host smart-2bc703e2-305c-4724-8aff-f17f7d7fae25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601296505 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2601296505
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1232490680
Short name T57
Test name
Test status
Simulation time 16688256650 ps
CPU time 320.15 seconds
Started Jul 10 05:10:21 PM PDT 24
Finished Jul 10 05:15:47 PM PDT 24
Peak memory 209368 kb
Host smart-0e9b8a85-adb6-4708-ac9f-d71ef6d1d7bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1232490680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.1232490680
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3782920060
Short name T175
Test name
Test status
Simulation time 7216173941 ps
CPU time 80.97 seconds
Started Jul 10 05:10:18 PM PDT 24
Finished Jul 10 05:11:44 PM PDT 24
Peak memory 200280 kb
Host smart-f40734f3-f9d0-4984-9805-c561d18141a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782920060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3782920060
Directory /workspace/9.hmac_wipe_secret/latest
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