Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	18406237	1			T1	1323		T3	19232		T4	64113
all_values[1]	18406237	1			T1	1323		T3	19232		T4	64113
all_values[2]	18406237	1			T1	1323		T3	19232		T4	64113

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

296593

1

T1

45

T4

4

T8

44

auto[1]

54922118

1

T1

3924

T3

57696

T4

192335

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46990770

1

T1

3432

T3

44331

T4

161686

auto[1]

8227941

1

T1

537

T3

13365

T4

30653

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	88068	1			T7	6575		T20	1015		T9	7
all_values[0]	auto[0]	auto[1]	403	1			T7	2		T20	3		T9	6
all_values[0]	auto[1]	auto[0]	18297496	1			T1	1304		T3	19222		T4	64088
all_values[0]	auto[1]	auto[1]	20270	1			T1	19		T3	10		T4	25
all_values[1]	auto[0]	auto[0]	90732	1			T1	45		T8	22		T12	803
all_values[1]	auto[0]	auto[1]	220	1			T20	1		T9	4		T13	2
all_values[1]	auto[1]	auto[0]	18314937	1			T1	1278		T3	19232		T4	64113
all_values[1]	auto[1]	auto[1]	348	1			T9	4		T13	8		T25	5
all_values[2]	auto[0]	auto[0]	65787	1			T4	4		T8	7		T20	3
all_values[2]	auto[0]	auto[1]	51383	1			T8	15		T20	1		T6	2
all_values[2]	auto[1]	auto[0]	10133750	1			T1	805		T3	5877		T4	33481
all_values[2]	auto[1]	auto[1]	8155317	1			T1	518		T3	13355		T4	30628