Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

136862

1

T1

28

T8

4

T5

16

auto[1]

142150

1

T1

22

T3

26

T4

78

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	101822	1			T3	2		T4	13		T7	4
len_1026_2046	7137	1			T20	15		T24	1		T9	42
len_514_1022	4485	1			T1	3		T8	2		T20	14
len_2_510	4919	1			T1	2		T20	15		T24	2
len_2056	230	1			T3	4		T20	7		T9	4
len_2048	367	1			T5	1		T20	3		T9	4
len_2040	187	1			T1	2		T13	1		T25	16
len_1032	158	1			T4	2		T20	5		T9	2
len_1024	1790	1			T1	2		T4	1		T20	5
len_1016	182	1			T1	4		T20	8		T9	4
len_520	247	1			T1	3		T20	10		T9	4
len_512	399	1			T1	1		T8	2		T5	1
len_504	206	1			T20	5		T13	5		T25	11
len_8	1342	1			T3	7		T4	23		T20	4
len_0	16034	1			T1	8		T8	1		T5	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

103

1

T5

2

T21

3

T22

1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	52350	1			T5	8		T12	3		T20	190
auto[0]	len_1026_2046	3216	1			T20	7		T24	1		T9	11
auto[0]	len_514_1022	2348	1			T1	1		T8	1		T20	10
auto[0]	len_2_510	3420	1			T1	1		T20	9		T24	2
auto[0]	len_2056	130	1			T20	6		T9	2		T13	3
auto[0]	len_2048	208	1			T20	1		T9	3		T21	1
auto[0]	len_2040	105	1			T1	1		T25	10		T76	2
auto[0]	len_1032	96	1			T20	3		T9	2		T13	1
auto[0]	len_1024	259	1			T1	1		T20	4		T9	4
auto[0]	len_1016	104	1			T1	2		T20	6		T9	3
auto[0]	len_520	94	1			T20	4		T9	4		T13	3
auto[0]	len_512	237	1			T1	1		T20	4		T24	1
auto[0]	len_504	95	1			T20	2		T13	4		T25	5
auto[0]	len_8	374	1			T75	1		T10	2		T120	1
auto[0]	len_0	5394	1			T1	7		T8	1		T20	13
auto[1]	len_2050_plus	49472	1			T3	2		T4	13		T7	4
auto[1]	len_1026_2046	3921	1			T20	8		T9	31		T22	1
auto[1]	len_514_1022	2137	1			T1	2		T8	1		T20	4
auto[1]	len_2_510	1499	1			T1	1		T20	6		T9	12
auto[1]	len_2056	100	1			T3	4		T20	1		T9	2
auto[1]	len_2048	159	1			T5	1		T20	2		T9	1
auto[1]	len_2040	82	1			T1	1		T13	1		T25	6
auto[1]	len_1032	62	1			T4	2		T20	2		T13	4
auto[1]	len_1024	1531	1			T1	1		T4	1		T20	1
auto[1]	len_1016	78	1			T1	2		T20	2		T9	1
auto[1]	len_520	153	1			T1	3		T20	6		T13	3
auto[1]	len_512	162	1			T8	2		T5	1		T20	4
auto[1]	len_504	111	1			T20	3		T13	1		T25	6
auto[1]	len_8	968	1			T3	7		T4	23		T20	4
auto[1]	len_0	10640	1			T1	1		T5	1		T20	7

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

55

1

T5

2

T21

3

T22

1

auto[1]

len_upper

48

1

T29

3

T25

1

T121

2