Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4573024 1 T1 353 T3 545 T4 13870
auto[1] 2911672 1 T1 286 T3 8857 T4 17799


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2848360 1 T1 231 T3 2140 T4 13007
auto[1] 4636336 1 T1 408 T3 7262 T4 18662


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3437165 1 T1 308 T8 58 T5 8
auto[1] 4047531 1 T1 331 T3 9402 T4 31669


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4569756 1 T1 305 T3 3908 T4 14310
auto[1] 2914940 1 T1 334 T3 5494 T4 17359


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 6693066 1 T1 568 T3 9228 T4 28710
fifo_depth[1] 126725 1 T1 11 T3 34 T4 496
fifo_depth[2] 101420 1 T1 16 T3 23 T4 482
fifo_depth[3] 81990 1 T1 9 T3 34 T4 464
fifo_depth[4] 74509 1 T1 7 T3 31 T4 480
fifo_depth[5] 58420 1 T1 12 T3 23 T4 368
fifo_depth[6] 47327 1 T1 8 T3 18 T4 294
fifo_depth[7] 31226 1 T1 3 T3 9 T4 186


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 791630 1 T1 71 T3 174 T4 2959
auto[1] 6693066 1 T1 568 T3 9228 T4 28710


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7471105 1 T1 639 T3 9402 T4 31669
auto[1] 13591 1 T9 42 T13 147 T25 341


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 34649 1 T20 2 T24 2 T9 67
auto[0] auto[0] auto[0] auto[0] auto[1] 37815 1 T5 1 T20 1 T9 854
auto[0] auto[0] auto[0] auto[1] auto[0] 37881 1 T20 9 T9 409 T21 1
auto[0] auto[0] auto[0] auto[1] auto[1] 40986 1 T5 1 T20 22 T24 1
auto[0] auto[0] auto[1] auto[0] auto[0] 157355 1 T5 2 T20 31 T9 75
auto[0] auto[0] auto[1] auto[0] auto[1] 34643 1 T1 10 T20 68 T24 3
auto[0] auto[0] auto[1] auto[1] auto[0] 36048 1 T1 4 T5 1 T20 94
auto[0] auto[0] auto[1] auto[1] auto[1] 38858 1 T12 42 T20 71 T9 346
auto[0] auto[1] auto[0] auto[0] auto[0] 42272 1 T1 5 T3 161 T7 486
auto[0] auto[1] auto[0] auto[0] auto[1] 46815 1 T4 582 T20 2 T9 1190
auto[0] auto[1] auto[0] auto[1] auto[0] 42544 1 T4 689 T8 1 T12 160
auto[0] auto[1] auto[0] auto[1] auto[1] 36589 1 T1 17 T5 2 T20 84
auto[0] auto[1] auto[1] auto[0] auto[0] 54921 1 T1 12 T3 13 T4 779
auto[0] auto[1] auto[1] auto[0] auto[1] 52420 1 T1 10 T4 485 T5 1
auto[0] auto[1] auto[1] auto[1] auto[0] 46182 1 T1 8 T12 62 T20 8
auto[0] auto[1] auto[1] auto[1] auto[1] 51652 1 T1 5 T4 424 T9 2613
auto[1] auto[0] auto[0] auto[0] auto[0] 190900 1 T1 50 T5 2 T20 1234
auto[1] auto[0] auto[0] auto[0] auto[1] 184405 1 T1 38 T8 28 T5 1
auto[1] auto[0] auto[0] auto[1] auto[0] 169029 1 T1 48 T12 497 T20 608
auto[1] auto[0] auto[0] auto[1] auto[1] 196711 1 T12 214 T20 1913 T24 80
auto[1] auto[0] auto[1] auto[0] auto[0] 1738571 1 T1 9 T12 310 T20 1153
auto[1] auto[0] auto[1] auto[0] auto[1] 166921 1 T1 55 T8 11 T12 186
auto[1] auto[0] auto[1] auto[1] auto[0] 167827 1 T1 36 T8 19 T20 4053
auto[1] auto[0] auto[1] auto[1] auto[1] 204566 1 T1 58 T12 167 T20 3879
auto[1] auto[1] auto[0] auto[0] auto[0] 434772 1 T1 29 T3 336 T4 3719
auto[1] auto[1] auto[0] auto[0] auto[1] 477179 1 T1 6 T3 2 T4 3594
auto[1] auto[1] auto[0] auto[1] auto[0] 437987 1 T1 10 T3 1640 T4 3555
auto[1] auto[1] auto[0] auto[1] auto[1] 437826 1 T1 28 T3 1 T4 868
auto[1] auto[1] auto[1] auto[0] auto[0] 480338 1 T1 87 T3 32 T4 2815
auto[1] auto[1] auto[1] auto[0] auto[1] 439048 1 T1 42 T3 1 T4 1896
auto[1] auto[1] auto[1] auto[1] auto[0] 498480 1 T1 7 T3 1726 T4 2753
auto[1] auto[1] auto[1] auto[1] auto[1] 468506 1 T1 65 T3 5490 T4 9510


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 225070 1 T1 50 T5 2 T20 1236
auto[0] auto[0] auto[0] auto[0] auto[1] 219310 1 T1 38 T8 28 T5 2
auto[0] auto[0] auto[0] auto[1] auto[0] 206243 1 T1 48 T12 497 T20 617
auto[0] auto[0] auto[0] auto[1] auto[1] 236889 1 T5 1 T12 214 T20 1935
auto[0] auto[0] auto[1] auto[0] auto[0] 1895164 1 T1 9 T5 2 T12 310
auto[0] auto[0] auto[1] auto[0] auto[1] 201058 1 T1 65 T8 11 T12 186
auto[0] auto[0] auto[1] auto[1] auto[0] 203234 1 T1 40 T8 19 T5 1
auto[0] auto[0] auto[1] auto[1] auto[1] 241534 1 T1 58 T12 209 T20 3950
auto[0] auto[1] auto[0] auto[0] auto[0] 476696 1 T1 34 T3 497 T4 3719
auto[0] auto[1] auto[0] auto[0] auto[1] 523430 1 T1 6 T3 2 T4 4176
auto[0] auto[1] auto[0] auto[1] auto[0] 480206 1 T1 10 T3 1640 T4 4244
auto[0] auto[1] auto[0] auto[1] auto[1] 474089 1 T1 45 T3 1 T4 868
auto[0] auto[1] auto[1] auto[0] auto[0] 534678 1 T1 99 T3 45 T4 3594
auto[0] auto[1] auto[1] auto[0] auto[1] 490643 1 T1 52 T3 1 T4 2381
auto[0] auto[1] auto[1] auto[1] auto[0] 543475 1 T1 15 T3 1726 T4 2753
auto[0] auto[1] auto[1] auto[1] auto[1] 519386 1 T1 70 T3 5490 T4 9934
auto[1] auto[0] auto[0] auto[0] auto[0] 479 1 T13 2 T25 2 T77 46
auto[1] auto[0] auto[0] auto[0] auto[1] 2910 1 T9 16 T13 11 T25 1
auto[1] auto[0] auto[0] auto[1] auto[0] 667 1 T9 4 T25 14 T107 126
auto[1] auto[0] auto[0] auto[1] auto[1] 808 1 T25 70 T77 1 T124 254
auto[1] auto[0] auto[1] auto[0] auto[0] 762 1 T25 8 T37 9 T10 27
auto[1] auto[0] auto[1] auto[0] auto[1] 506 1 T37 3 T11 11 T125 34
auto[1] auto[0] auto[1] auto[1] auto[0] 641 1 T13 15 T77 22 T11 4
auto[1] auto[0] auto[1] auto[1] auto[1] 1890 1 T13 35 T25 8 T77 15
auto[1] auto[1] auto[0] auto[0] auto[0] 348 1 T13 4 T25 1 T10 15
auto[1] auto[1] auto[0] auto[0] auto[1] 564 1 T25 57 T23 20 T126 426
auto[1] auto[1] auto[0] auto[1] auto[0] 325 1 T25 25 T11 137 T23 7
auto[1] auto[1] auto[0] auto[1] auto[1] 326 1 T9 22 T37 8 T11 7
auto[1] auto[1] auto[1] auto[0] auto[0] 581 1 T77 1 T37 4 T10 3
auto[1] auto[1] auto[1] auto[0] auto[1] 825 1 T13 62 T77 6 T37 202
auto[1] auto[1] auto[1] auto[1] auto[0] 1187 1 T13 8 T10 7 T11 24
auto[1] auto[1] auto[1] auto[1] auto[1] 772 1 T13 10 T25 155 T37 4


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 190900 1 T1 50 T5 2 T20 1234
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 184405 1 T1 38 T8 28 T5 1
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 169029 1 T1 48 T12 497 T20 608
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 196711 1 T12 214 T20 1913 T24 80
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1738571 1 T1 9 T12 310 T20 1153
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 166921 1 T1 55 T8 11 T12 186
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 167827 1 T1 36 T8 19 T20 4053
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 204566 1 T1 58 T12 167 T20 3879
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 434772 1 T1 29 T3 336 T4 3719
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 477179 1 T1 6 T3 2 T4 3594
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 437987 1 T1 10 T3 1640 T4 3555
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 437826 1 T1 28 T3 1 T4 868
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 480338 1 T1 87 T3 32 T4 2815
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 439048 1 T1 42 T3 1 T4 1896
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 498480 1 T1 7 T3 1726 T4 2753
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 468506 1 T1 65 T3 5490 T4 9510
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 4081 1 T20 1 T24 1 T9 15
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 3918 1 T20 1 T9 107 T41 14
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 3625 1 T20 3 T9 42 T41 56
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 4423 1 T20 19 T24 1 T9 215
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 43706 1 T5 2 T20 21 T9 22
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 3719 1 T1 2 T20 52 T24 1
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 3632 1 T1 1 T20 74 T9 97
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 4493 1 T12 5 T20 56 T9 54
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 6013 1 T3 33 T7 73 T20 53
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 7602 1 T4 113 T9 241 T13 202
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 6289 1 T4 105 T8 1 T12 38
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 5433 1 T1 3 T20 60 T9 121
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 8230 1 T1 1 T3 1 T4 111
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 6324 1 T1 2 T4 105 T20 17
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 7479 1 T1 2 T12 9 T20 8
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 7758 1 T4 62 T9 473 T13 15
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 3405 1 T20 1 T9 17 T13 4
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 3276 1 T9 77 T41 12 T13 17
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 2933 1 T20 1 T9 40 T41 56
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 3559 1 T20 2 T9 214 T41 8
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 29931 1 T20 10 T9 14 T41 11
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 3301 1 T1 1 T20 14 T24 1
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 3216 1 T1 1 T20 16 T9 90
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 3578 1 T12 10 T20 13 T9 54
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 5117 1 T1 1 T3 22 T7 73
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 6530 1 T4 113 T20 1 T9 223
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 5566 1 T4 96 T12 24 T20 2
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 5037 1 T1 7 T20 15 T9 133
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 6911 1 T1 3 T3 1 T4 116
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 5322 1 T1 2 T4 92 T20 5
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 6558 1 T1 1 T12 12 T6 19
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 7180 1 T4 65 T9 453 T13 17
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 2671 1 T9 10 T13 5 T25 38
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 2365 1 T9 70 T41 11 T13 14
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 2488 1 T20 1 T9 41 T41 52
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 2946 1 T20 1 T9 186 T41 12
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 21732 1 T9 15 T41 11 T13 8
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 2743 1 T1 1 T20 2 T9 254
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 2552 1 T1 1 T20 4 T9 105
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 2770 1 T12 9 T20 1 T9 60
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 4285 1 T1 1 T3 32 T7 73
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 5619 1 T4 103 T20 1 T9 185
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 4984 1 T4 113 T12 29 T9 112
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 4393 1 T1 2 T20 8 T9 97
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 5650 1 T1 1 T3 2 T4 109
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 4822 1 T1 1 T4 82 T20 1
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 5756 1 T1 1 T12 8 T6 27
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 6214 1 T1 1 T4 57 T9 379
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2880 1 T24 1 T9 12 T13 8
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 2498 1 T9 88 T41 14 T13 19
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 2540 1 T20 4 T9 34 T41 54
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 2999 1 T9 163 T41 6 T22 1
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 16171 1 T9 12 T41 10 T13 27
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 2957 1 T1 1 T24 1 T9 217
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 2540 1 T1 1 T9 87 T41 29
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 2502 1 T12 2 T20 1 T9 54
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 4151 1 T3 30 T7 66 T6 100
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 5374 1 T4 101 T9 168 T13 220
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 4624 1 T4 93 T12 23 T20 1
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 4184 1 T1 1 T20 1 T9 94
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 5251 1 T1 1 T3 1 T4 124
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 4551 1 T1 1 T4 90 T5 1
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 5356 1 T1 1 T12 8 T6 28
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 5931 1 T1 1 T4 72 T9 320
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 2081 1 T9 5 T13 4 T25 59
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 1753 1 T9 57 T21 1 T41 11
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 1937 1 T9 33 T41 44 T13 16
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 2265 1 T9 122 T41 9 T13 46
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 11097 1 T9 5 T41 13 T13 4
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 2116 1 T1 4 T9 153 T65 1
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 2027 1 T9 68 T21 1 T41 22
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 2008 1 T12 6 T9 36 T13 12
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 3388 1 T1 1 T3 22 T7 68
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 4339 1 T4 77 T9 173 T13 189
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 3969 1 T4 80 T12 25 T9 94
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 3429 1 T1 2 T9 93 T41 45
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 4361 1 T1 3 T3 1 T4 104
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 3837 1 T1 1 T4 56 T6 54
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 4680 1 T12 8 T6 21 T9 190
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 5133 1 T1 1 T4 51 T9 286
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1822 1 T9 4 T13 4 T25 127
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1433 1 T9 38 T41 9 T13 11
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1700 1 T9 27 T41 33 T13 15
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1776 1 T9 91 T41 4 T22 1
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 7942 1 T9 5 T41 10 T25 40
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 1827 1 T1 1 T9 116 T13 1
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1720 1 T9 57 T41 13 T13 59
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1721 1 T12 1 T9 40 T13 9
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 2893 1 T3 17 T7 49 T6 85
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 3534 1 T4 47 T9 113 T13 151
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 3191 1 T4 81 T12 14 T9 59
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 2784 1 T1 2 T5 1 T9 74
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3643 1 T1 2 T3 1 T4 80
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 3354 1 T4 33 T6 26 T9 31
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 3814 1 T1 2 T12 6 T6 15
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 4173 1 T1 1 T4 53 T9 184
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 1193 1 T9 3 T13 6 T25 93
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 950 1 T9 20 T41 7 T13 15
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 1306 1 T9 21 T21 1 T41 33
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 1109 1 T9 39 T41 7 T13 16
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 4735 1 T9 2 T41 5 T13 3
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 1181 1 T9 73 T13 3 T25 21
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 1136 1 T9 25 T41 13 T13 37
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 1208 1 T12 4 T9 29 T13 5
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 2009 1 T3 5 T7 38 T6 60
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 2325 1 T4 17 T9 54 T13 97
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 2319 1 T4 52 T12 5 T9 51
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 1835 1 T5 1 T9 47 T41 36
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2532 1 T3 4 T4 58 T9 123
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 2130 1 T1 1 T4 23 T6 17
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 2473 1 T1 1 T12 6 T6 13
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 2785 1 T1 1 T4 36 T9 85

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