Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	18406237	1			T1	1323		T3	19232		T4	64113
all_pins[1]	18406237	1			T1	1323		T3	19232		T4	64113
all_pins[2]	18406237	1			T1	1323		T3	19232		T4	64113

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	47041923	1			T1	3432		T3	44330		T4	161681
values[0x1]	8176788	1			T1	537		T3	13366		T4	30658
transitions[0x0=>0x1]	8176641	1			T1	537		T3	13366		T4	30658
transitions[0x1=>0x0]	8176651	1			T1	537		T3	13366		T4	30658

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	18385144	1			T1	1304		T3	19221		T4	64083
all_pins[0]	values[0x1]	21093	1			T1	19		T3	11		T4	30
all_pins[0]	transitions[0x0=>0x1]	21030	1			T1	19		T3	11		T4	30
all_pins[0]	transitions[0x1=>0x0]	8155264	1			T1	518		T3	13355		T4	30628
all_pins[1]	values[0x0]	18405859	1			T1	1323		T3	19232		T4	64113
all_pins[1]	values[0x1]	378	1			T9	4		T13	10		T25	6
all_pins[1]	transitions[0x0=>0x1]	342	1			T9	4		T13	10		T25	6
all_pins[1]	transitions[0x1=>0x0]	21057	1			T1	19		T3	11		T4	30
all_pins[2]	values[0x0]	10250920	1			T1	805		T3	5877		T4	33485
all_pins[2]	values[0x1]	8155317	1			T1	518		T3	13355		T4	30628
all_pins[2]	transitions[0x0=>0x1]	8155269	1			T1	518		T3	13355		T4	30628
all_pins[2]	transitions[0x1=>0x0]	330	1			T9	4		T13	10		T25	5