Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 959 1 T20 4 T9 17 T13 10
all_values[1] 959 1 T20 4 T9 17 T13 10
all_values[2] 959 1 T20 4 T9 17 T13 10


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1558 1 T20 8 T9 32 T13 16
auto[1] 1319 1 T20 4 T9 19 T13 14


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1037 1 T20 4 T9 17 T13 18
auto[1] 1840 1 T20 8 T9 34 T13 12


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1670 1 T20 6 T9 30 T13 22
auto[1] 1207 1 T20 6 T9 21 T13 8


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 210 1 T20 1 T9 1 T13 1
all_values[0] auto[0] auto[0] auto[1] 97 1 T20 1 T9 5 T13 2
all_values[0] auto[0] auto[1] auto[0] 187 1 T9 3 T13 4 T25 6
all_values[0] auto[0] auto[1] auto[1] 86 1 T25 5 T110 3 T79 1
all_values[0] auto[1] auto[0] auto[1] 202 1 T20 1 T9 6 T13 1
all_values[0] auto[1] auto[1] auto[1] 177 1 T20 1 T9 2 T13 2
all_values[1] auto[0] auto[0] auto[0] 171 1 T9 3 T13 1 T25 3
all_values[1] auto[0] auto[0] auto[1] 133 1 T20 1 T9 3 T13 1
all_values[1] auto[0] auto[1] auto[0] 118 1 T20 2 T9 6 T13 4
all_values[1] auto[0] auto[1] auto[1] 117 1 T13 1 T25 2 T107 1
all_values[1] auto[1] auto[0] auto[1] 221 1 T9 3 T13 2 T25 5
all_values[1] auto[1] auto[1] auto[1] 199 1 T20 1 T9 2 T13 1
all_values[2] auto[0] auto[0] auto[0] 189 1 T20 1 T9 3 T13 6
all_values[2] auto[0] auto[0] auto[1] 115 1 T9 4 T25 4 T110 2
all_values[2] auto[0] auto[1] auto[0] 162 1 T9 1 T13 2 T25 2
all_values[2] auto[0] auto[1] auto[1] 85 1 T9 1 T25 1 T110 4
all_values[2] auto[1] auto[0] auto[1] 220 1 T20 3 T9 4 T13 2
all_values[2] auto[1] auto[1] auto[1] 188 1 T9 4 T25 5 T110 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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