Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4662	1			T1	10		T4	5		T7	1
sha2_none	4588	1			T1	4		T3	3		T4	16
sha2_512	7921	1			T1	6		T3	2		T4	12
sha2_384	7668	1			T1	3		T3	2		T4	9
sha2_256	6586	1			T1	11		T3	5		T4	8

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19492

1

T1

20

T3

5

T4

25

auto[1]

12336

1

T1

14

T3

7

T4

25

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12028

1

T1

12

T3

5

T4

21

auto[1]

19800

1

T1

22

T3

7

T4

29

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

16310

1

T1

14

T3

12

T4

50

disabled

15518

1

T1

20

T8

4

T5

9

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5095	1			T1	3		T3	1		T4	7
key_none	7981	1			T1	3		T3	3		T4	6
key_1024	4504	1			T1	5		T4	7		T8	1
key_512	3987	1			T1	4		T3	3		T4	5
key_384	3571	1			T1	4		T3	2		T4	8
key_256	3347	1			T1	8		T3	1		T4	10
key_128	3262	1			T1	6		T3	2		T4	7

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19881

1

T1

17

T3

5

T4

25

auto[1]

11947

1

T1

17

T3

7

T4

25

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

31600

1

T1

34

T3

12

T4

50

disabled

228

1

T20

4

T9

9

T13

1

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1696

1

T1

2

T3

2

T4

5

enabled

auto[0]

auto[0]

auto[1]

1650

1

T1

1

T3

1

T4

7

enabled

auto[0]

auto[1]

auto[0]

1745

1

T1

1

T3

1

T4

7

enabled

auto[0]

auto[1]

auto[1]

1610

1

T1

1

T3

1

T4

2

enabled

auto[1]

auto[0]

auto[0]

4376

1

T1

4

T3

1

T4

9

enabled

auto[1]

auto[0]

auto[1]

1620

1

T1

2

T3

1

T4

4

enabled

auto[1]

auto[1]

auto[0]

1878

1

T1

1

T3

1

T4

4

enabled

auto[1]

auto[1]

auto[1]

1735

1

T1

2

T3

4

T4

12

disabled

auto[0]

auto[0]

auto[0]

1324

1

T1

3

T5

2

T20

12

disabled

auto[0]

auto[0]

auto[1]

1329

1

T1

3

T8

2

T5

2

disabled

auto[0]

auto[1]

auto[0]

1291

1

T1

1

T12

1

T20

16

disabled

auto[0]

auto[1]

auto[1]

1383

1

T5

2

T12

2

T20

15

disabled

auto[1]

auto[0]

auto[0]

6230

1

T1

1

T5

2

T12

1

disabled

auto[1]

auto[0]

auto[1]

1267

1

T1

4

T8

1

T12

1

disabled

auto[1]

auto[1]

auto[0]

1341

1

T1

4

T8

1

T5

1

disabled

auto[1]

auto[1]

auto[1]

1353

1

T1

4

T12

1

T20

19

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

16217

1

T1

14

T3

12

T4

50

enabled

disabled

93

1

T20

2

T9

3

T13

1

disabled

disabled

135

1

T20

2

T9

6

T25

6

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15383

1

T1

20

T8

4

T5

9

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1226	1			T1	1		T20	8		T9	27
key_invalid	sha2_none	954	1			T4	3		T8	1		T5	1
key_invalid	sha2_512	916	1			T7	1		T5	2		T12	1
key_invalid	sha2_384	978	1			T4	3		T12	1		T20	14
key_invalid	sha2_256	903	1			T1	2		T3	1		T4	1
key_none	sha2_invalid	586	1			T4	2		T5	1		T20	7
key_none	sha2_none	599	1			T1	1		T3	1		T4	1
key_none	sha2_512	2561	1			T1	1		T3	1		T4	2
key_none	sha2_384	2558	1			T3	1		T20	2		T9	8
key_none	sha2_256	1621	1			T1	1		T4	1		T5	1
key_1024	sha2_invalid	536	1			T1	1		T4	2		T20	4
key_1024	sha2_none	604	1			T1	2		T5	1		T20	1
key_1024	sha2_512	1780	1			T1	1		T4	2		T5	2
key_1024	sha2_384	911	1			T4	2		T8	1		T7	1
key_512	sha2_invalid	589	1			T1	1		T12	1		T20	8
key_512	sha2_none	590	1			T3	1		T4	3		T20	1
key_512	sha2_512	629	1			T1	2		T7	1		T20	8
key_512	sha2_384	1268	1			T4	1		T20	7		T9	8
key_512	sha2_256	862	1			T1	1		T3	2		T4	1
key_384	sha2_invalid	523	1			T1	1		T7	1		T12	1
key_384	sha2_none	582	1			T4	2		T8	1		T7	1
key_384	sha2_512	642	1			T4	2		T8	1		T5	2
key_384	sha2_384	639	1			T1	1		T4	1		T20	9
key_384	sha2_256	1139	1			T1	2		T3	2		T4	3
key_256	sha2_invalid	566	1			T1	3		T4	1		T20	7
key_256	sha2_none	609	1			T4	3		T5	2		T12	1
key_256	sha2_512	688	1			T1	1		T3	1		T4	4
key_256	sha2_384	650	1			T1	2		T4	2		T8	1
key_256	sha2_256	783	1			T1	2		T20	2		T24	1
key_128	sha2_invalid	618	1			T1	2		T20	7		T6	1
key_128	sha2_none	631	1			T1	1		T3	1		T4	4
key_128	sha2_512	692	1			T1	1		T4	2		T20	11
key_128	sha2_384	649	1			T3	1		T20	3		T6	2
key_128	sha2_256	633	1			T1	2		T4	1		T5	4

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

629

1

T1

1

T4

1

T20

6

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1226	1			T1	1		T20	8		T9	27
key_invalid	sha2_none	954	1			T4	3		T8	1		T5	1
key_invalid	sha2_512	916	1			T7	1		T5	2		T12	1
key_invalid	sha2_384	978	1			T4	3		T12	1		T20	14
key_invalid	sha2_256	903	1			T1	2		T3	1		T4	1
key_none	sha2_invalid	586	1			T4	2		T5	1		T20	7
key_none	sha2_none	599	1			T1	1		T3	1		T4	1
key_none	sha2_512	2561	1			T1	1		T3	1		T4	2
key_none	sha2_384	2558	1			T3	1		T20	2		T9	8
key_none	sha2_256	1621	1			T1	1		T4	1		T5	1
key_1024	sha2_invalid	536	1			T1	1		T4	2		T20	4
key_1024	sha2_none	604	1			T1	2		T5	1		T20	1
key_1024	sha2_512	1780	1			T1	1		T4	2		T5	2
key_1024	sha2_384	911	1			T4	2		T8	1		T7	1
key_1024	sha2_256	629	1			T1	1		T4	1		T20	6
key_512	sha2_invalid	589	1			T1	1		T12	1		T20	8
key_512	sha2_none	590	1			T3	1		T4	3		T20	1
key_512	sha2_512	629	1			T1	2		T7	1		T20	8
key_512	sha2_384	1268	1			T4	1		T20	7		T9	8
key_512	sha2_256	862	1			T1	1		T3	2		T4	1
key_384	sha2_invalid	523	1			T1	1		T7	1		T12	1
key_384	sha2_none	582	1			T4	2		T8	1		T7	1
key_384	sha2_512	642	1			T4	2		T8	1		T5	2
key_384	sha2_384	639	1			T1	1		T4	1		T20	9
key_384	sha2_256	1139	1			T1	2		T3	2		T4	3
key_256	sha2_invalid	566	1			T1	3		T4	1		T20	7
key_256	sha2_none	609	1			T4	3		T5	2		T12	1
key_256	sha2_512	688	1			T1	1		T3	1		T4	4
key_256	sha2_384	650	1			T1	2		T4	2		T8	1
key_256	sha2_256	783	1			T1	2		T20	2		T24	1
key_128	sha2_invalid	618	1			T1	2		T20	7		T6	1
key_128	sha2_none	631	1			T1	1		T3	1		T4	4
key_128	sha2_512	692	1			T1	1		T4	2		T20	11
key_128	sha2_384	649	1			T3	1		T20	3		T6	2
key_128	sha2_256	633	1			T1	2		T4	1		T5	4