Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.94 95.26 97.33 100.00 97.06 98.12 97.97 99.85


Total test records in report: 659
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T101 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1824410175 Jul 11 05:22:05 PM PDT 24 Jul 11 05:22:16 PM PDT 24 43990439 ps
T86 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.936964318 Jul 11 05:22:09 PM PDT 24 Jul 11 05:22:20 PM PDT 24 91435614 ps
T533 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2270841305 Jul 11 05:22:14 PM PDT 24 Jul 11 05:22:25 PM PDT 24 28052390 ps
T534 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.171793213 Jul 11 05:22:14 PM PDT 24 Jul 11 05:22:28 PM PDT 24 1363619201 ps
T102 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.553357387 Jul 11 05:22:15 PM PDT 24 Jul 11 05:22:26 PM PDT 24 69115466 ps
T535 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1662228475 Jul 11 05:22:26 PM PDT 24 Jul 11 05:22:35 PM PDT 24 44226444 ps
T57 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.183540816 Jul 11 05:22:06 PM PDT 24 Jul 11 05:22:17 PM PDT 24 51674528 ps
T103 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1211124719 Jul 11 05:22:25 PM PDT 24 Jul 11 05:22:35 PM PDT 24 106367976 ps
T104 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1562199769 Jul 11 05:22:22 PM PDT 24 Jul 11 05:22:31 PM PDT 24 49418427 ps
T105 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.493082250 Jul 11 05:22:11 PM PDT 24 Jul 11 05:22:22 PM PDT 24 50432088 ps
T536 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1980308863 Jul 11 05:22:05 PM PDT 24 Jul 11 05:22:18 PM PDT 24 768556758 ps
T537 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1518764825 Jul 11 05:22:28 PM PDT 24 Jul 11 05:22:36 PM PDT 24 100846055 ps
T106 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1725498149 Jul 11 05:22:05 PM PDT 24 Jul 11 05:22:17 PM PDT 24 405293906 ps
T538 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2663891304 Jul 11 05:22:14 PM PDT 24 Jul 11 05:22:27 PM PDT 24 117047120 ps
T96 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.848827472 Jul 11 05:21:52 PM PDT 24 Jul 11 05:22:05 PM PDT 24 431233011 ps
T58 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.107720918 Jul 11 05:22:20 PM PDT 24 Jul 11 05:22:33 PM PDT 24 233614474 ps
T539 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3504701114 Jul 11 05:22:04 PM PDT 24 Jul 11 05:22:13 PM PDT 24 24840105 ps
T87 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.4244450819 Jul 11 05:22:24 PM PDT 24 Jul 11 05:22:33 PM PDT 24 17026472 ps
T111 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3672480792 Jul 11 05:22:13 PM PDT 24 Jul 11 05:22:26 PM PDT 24 218560328 ps
T540 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.203121214 Jul 11 05:22:14 PM PDT 24 Jul 11 05:22:25 PM PDT 24 13023223 ps
T541 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1588303973 Jul 11 05:22:20 PM PDT 24 Jul 11 05:22:29 PM PDT 24 32120153 ps
T542 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3305524737 Jul 11 05:22:22 PM PDT 24 Jul 11 05:22:31 PM PDT 24 26580862 ps
T543 /workspace/coverage/cover_reg_top/17.hmac_intr_test.1518125585 Jul 11 05:22:22 PM PDT 24 Jul 11 05:22:31 PM PDT 24 48423705 ps
T544 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2966385181 Jul 11 05:22:09 PM PDT 24 Jul 11 05:22:20 PM PDT 24 45780729 ps
T545 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1965579671 Jul 11 05:22:16 PM PDT 24 Jul 11 05:22:27 PM PDT 24 44533314 ps
T546 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3998160048 Jul 11 05:22:17 PM PDT 24 Jul 11 05:22:30 PM PDT 24 478398463 ps
T88 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3007672070 Jul 11 05:22:14 PM PDT 24 Jul 11 05:22:25 PM PDT 24 415072125 ps
T547 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2789131949 Jul 11 05:22:17 PM PDT 24 Jul 11 05:22:26 PM PDT 24 14505095 ps
T114 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2264853401 Jul 11 05:22:21 PM PDT 24 Jul 11 05:22:31 PM PDT 24 97634945 ps
T89 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.69431007 Jul 11 05:22:00 PM PDT 24 Jul 11 05:22:06 PM PDT 24 44872652 ps
T548 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3955798932 Jul 11 05:22:05 PM PDT 24 Jul 11 05:22:20 PM PDT 24 787076813 ps
T549 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1905501109 Jul 11 05:22:31 PM PDT 24 Jul 11 05:22:40 PM PDT 24 33441518 ps
T550 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3587975340 Jul 11 05:22:19 PM PDT 24 Jul 11 05:22:28 PM PDT 24 201794669 ps
T551 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2141467665 Jul 11 05:22:29 PM PDT 24 Jul 11 05:22:37 PM PDT 24 39385994 ps
T552 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.634885372 Jul 11 05:22:04 PM PDT 24 Jul 11 05:22:13 PM PDT 24 72755735 ps
T553 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1580049886 Jul 11 05:22:24 PM PDT 24 Jul 11 05:22:32 PM PDT 24 26854484 ps
T554 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3802818491 Jul 11 05:22:08 PM PDT 24 Jul 11 05:22:20 PM PDT 24 76658696 ps
T555 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.687815565 Jul 11 05:22:17 PM PDT 24 Jul 11 05:22:27 PM PDT 24 165829615 ps
T59 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3740114111 Jul 11 05:22:21 PM PDT 24 Jul 11 05:22:32 PM PDT 24 557483149 ps
T556 /workspace/coverage/cover_reg_top/20.hmac_intr_test.4216870726 Jul 11 05:22:19 PM PDT 24 Jul 11 05:22:29 PM PDT 24 41767496 ps
T557 /workspace/coverage/cover_reg_top/28.hmac_intr_test.915309615 Jul 11 05:22:31 PM PDT 24 Jul 11 05:22:39 PM PDT 24 28265333 ps
T558 /workspace/coverage/cover_reg_top/26.hmac_intr_test.460167484 Jul 11 05:22:30 PM PDT 24 Jul 11 05:22:38 PM PDT 24 13307514 ps
T559 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1940076416 Jul 11 05:22:05 PM PDT 24 Jul 11 05:22:15 PM PDT 24 374078045 ps
T560 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2063547905 Jul 11 05:22:12 PM PDT 24 Jul 11 05:22:25 PM PDT 24 184914933 ps
T561 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1550767663 Jul 11 05:22:13 PM PDT 24 Jul 11 05:22:24 PM PDT 24 119420541 ps
T90 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2601208896 Jul 11 05:22:03 PM PDT 24 Jul 11 05:22:12 PM PDT 24 35595343 ps
T91 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4180057860 Jul 11 05:22:04 PM PDT 24 Jul 11 05:22:18 PM PDT 24 1405392857 ps
T116 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1959983306 Jul 11 05:22:32 PM PDT 24 Jul 11 05:22:42 PM PDT 24 190359487 ps
T61 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1735840311 Jul 11 05:22:07 PM PDT 24 Jul 11 05:22:20 PM PDT 24 389217310 ps
T562 /workspace/coverage/cover_reg_top/41.hmac_intr_test.3148884595 Jul 11 05:22:26 PM PDT 24 Jul 11 05:22:35 PM PDT 24 18408111 ps
T563 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3079627287 Jul 11 05:22:32 PM PDT 24 Jul 11 05:22:43 PM PDT 24 187351305 ps
T119 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.837014123 Jul 11 05:22:06 PM PDT 24 Jul 11 05:22:18 PM PDT 24 855535694 ps
T564 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2803448781 Jul 11 05:22:07 PM PDT 24 Jul 11 05:22:17 PM PDT 24 15644117 ps
T565 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1450924107 Jul 11 05:22:20 PM PDT 24 Jul 11 05:22:29 PM PDT 24 11496101 ps
T112 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.399157330 Jul 11 05:21:55 PM PDT 24 Jul 11 05:22:03 PM PDT 24 312972810 ps
T566 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.779672429 Jul 11 05:22:20 PM PDT 24 Jul 11 05:22:29 PM PDT 24 26193703 ps
T113 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.741939782 Jul 11 05:22:20 PM PDT 24 Jul 11 05:22:32 PM PDT 24 201454890 ps
T567 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3085849890 Jul 11 05:22:09 PM PDT 24 Jul 11 05:22:20 PM PDT 24 39382979 ps
T568 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3496431534 Jul 11 05:22:20 PM PDT 24 Jul 11 05:22:29 PM PDT 24 63851047 ps
T569 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3635327439 Jul 11 05:22:15 PM PDT 24 Jul 11 05:22:27 PM PDT 24 305253432 ps
T570 /workspace/coverage/cover_reg_top/4.hmac_intr_test.196748735 Jul 11 05:22:05 PM PDT 24 Jul 11 05:22:15 PM PDT 24 26744118 ps
T571 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3724494111 Jul 11 05:22:25 PM PDT 24 Jul 11 05:22:34 PM PDT 24 16161578 ps
T572 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2503412536 Jul 11 05:22:08 PM PDT 24 Jul 11 05:22:19 PM PDT 24 74675867 ps
T573 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1548389404 Jul 11 05:22:24 PM PDT 24 Jul 11 05:22:34 PM PDT 24 157097614 ps
T574 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.680660039 Jul 11 05:22:07 PM PDT 24 Jul 11 05:22:18 PM PDT 24 72417176 ps
T575 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3312838023 Jul 11 05:22:26 PM PDT 24 Jul 11 05:22:34 PM PDT 24 102512682 ps
T576 /workspace/coverage/cover_reg_top/23.hmac_intr_test.1106691826 Jul 11 05:22:27 PM PDT 24 Jul 11 05:22:36 PM PDT 24 46454167 ps
T577 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2441061333 Jul 11 05:22:12 PM PDT 24 Jul 11 05:22:26 PM PDT 24 50191462 ps
T578 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3351431613 Jul 11 05:22:03 PM PDT 24 Jul 11 05:22:14 PM PDT 24 609524514 ps
T579 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3277221296 Jul 11 05:22:22 PM PDT 24 Jul 11 05:22:31 PM PDT 24 68909250 ps
T118 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2504601760 Jul 11 05:22:04 PM PDT 24 Jul 11 05:22:17 PM PDT 24 241722358 ps
T580 /workspace/coverage/cover_reg_top/46.hmac_intr_test.47790146 Jul 11 05:22:25 PM PDT 24 Jul 11 05:22:33 PM PDT 24 12010968 ps
T581 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1741356790 Jul 11 05:22:18 PM PDT 24 Jul 11 05:22:30 PM PDT 24 369095262 ps
T582 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.91766539 Jul 11 05:21:52 PM PDT 24 Jul 11 05:40:32 PM PDT 24 499040068931 ps
T583 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.216093136 Jul 11 05:22:01 PM PDT 24 Jul 11 05:22:08 PM PDT 24 32501970 ps
T584 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1215404573 Jul 11 05:22:07 PM PDT 24 Jul 11 05:22:17 PM PDT 24 43677772 ps
T585 /workspace/coverage/cover_reg_top/1.hmac_intr_test.3118619136 Jul 11 05:22:00 PM PDT 24 Jul 11 05:22:06 PM PDT 24 48001795 ps
T586 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1502613825 Jul 11 05:22:13 PM PDT 24 Jul 11 05:22:26 PM PDT 24 818282097 ps
T587 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2171231252 Jul 11 05:22:30 PM PDT 24 Jul 11 05:22:39 PM PDT 24 143214137 ps
T588 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3282461913 Jul 11 05:22:30 PM PDT 24 Jul 11 05:22:38 PM PDT 24 31018862 ps
T589 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2371394963 Jul 11 05:22:01 PM PDT 24 Jul 11 05:22:07 PM PDT 24 16633174 ps
T590 /workspace/coverage/cover_reg_top/22.hmac_intr_test.939867154 Jul 11 05:22:17 PM PDT 24 Jul 11 05:22:27 PM PDT 24 19985284 ps
T591 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2916795366 Jul 11 05:22:21 PM PDT 24 Jul 11 05:22:31 PM PDT 24 45890726 ps
T592 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1556390344 Jul 11 05:22:21 PM PDT 24 Jul 11 05:22:32 PM PDT 24 55854404 ps
T593 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2279607453 Jul 11 05:22:07 PM PDT 24 Jul 11 05:22:20 PM PDT 24 339789752 ps
T594 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3424744617 Jul 11 05:22:15 PM PDT 24 Jul 11 05:22:26 PM PDT 24 43611956 ps
T595 /workspace/coverage/cover_reg_top/35.hmac_intr_test.2862699159 Jul 11 05:22:28 PM PDT 24 Jul 11 05:22:36 PM PDT 24 40008536 ps
T596 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3211340638 Jul 11 05:22:06 PM PDT 24 Jul 11 05:22:17 PM PDT 24 236857171 ps
T597 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2030213706 Jul 11 05:22:26 PM PDT 24 Jul 11 05:22:34 PM PDT 24 30988952 ps
T598 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.703240207 Jul 11 05:22:15 PM PDT 24 Jul 11 05:22:28 PM PDT 24 190583646 ps
T599 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3917886541 Jul 11 05:22:01 PM PDT 24 Jul 11 05:22:09 PM PDT 24 89865592 ps
T600 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2318986818 Jul 11 05:22:14 PM PDT 24 Jul 11 05:22:26 PM PDT 24 94586637 ps
T601 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3358171526 Jul 11 05:22:03 PM PDT 24 Jul 11 05:22:12 PM PDT 24 42505618 ps
T602 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1233916579 Jul 11 05:22:09 PM PDT 24 Jul 11 05:22:20 PM PDT 24 27037479 ps
T603 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3546821267 Jul 11 05:22:13 PM PDT 24 Jul 11 05:22:26 PM PDT 24 47277545 ps
T604 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1799459425 Jul 11 05:22:31 PM PDT 24 Jul 11 05:22:39 PM PDT 24 57021562 ps
T92 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1128616840 Jul 11 05:22:03 PM PDT 24 Jul 11 05:22:12 PM PDT 24 39998593 ps
T605 /workspace/coverage/cover_reg_top/31.hmac_intr_test.859121727 Jul 11 05:22:27 PM PDT 24 Jul 11 05:22:36 PM PDT 24 24762013 ps
T606 /workspace/coverage/cover_reg_top/49.hmac_intr_test.169784593 Jul 11 05:22:26 PM PDT 24 Jul 11 05:22:35 PM PDT 24 16904751 ps
T607 /workspace/coverage/cover_reg_top/34.hmac_intr_test.574003911 Jul 11 05:22:32 PM PDT 24 Jul 11 05:22:39 PM PDT 24 38083484 ps
T608 /workspace/coverage/cover_reg_top/11.hmac_intr_test.408890050 Jul 11 05:22:24 PM PDT 24 Jul 11 05:22:33 PM PDT 24 51395085 ps
T609 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2760432692 Jul 11 05:22:25 PM PDT 24 Jul 11 05:22:34 PM PDT 24 51246466 ps
T610 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.4186955138 Jul 11 05:22:11 PM PDT 24 Jul 11 05:22:22 PM PDT 24 270800714 ps
T611 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.342288209 Jul 11 05:22:05 PM PDT 24 Jul 11 05:22:18 PM PDT 24 172651951 ps
T612 /workspace/coverage/cover_reg_top/33.hmac_intr_test.463901579 Jul 11 05:22:25 PM PDT 24 Jul 11 05:22:34 PM PDT 24 14017362 ps
T613 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2061777663 Jul 11 05:22:07 PM PDT 24 Jul 11 05:22:17 PM PDT 24 29634225 ps
T614 /workspace/coverage/cover_reg_top/3.hmac_intr_test.3537377869 Jul 11 05:22:03 PM PDT 24 Jul 11 05:22:12 PM PDT 24 15696973 ps
T93 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.184774583 Jul 11 05:22:07 PM PDT 24 Jul 11 05:22:20 PM PDT 24 231092900 ps
T615 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2511037098 Jul 11 05:22:26 PM PDT 24 Jul 11 05:22:36 PM PDT 24 92963987 ps
T616 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3713721884 Jul 11 05:22:25 PM PDT 24 Jul 11 05:22:34 PM PDT 24 33910230 ps
T617 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3857160481 Jul 11 05:22:24 PM PDT 24 Jul 11 05:22:32 PM PDT 24 54705433 ps
T618 /workspace/coverage/cover_reg_top/18.hmac_intr_test.808395697 Jul 11 05:22:32 PM PDT 24 Jul 11 05:22:40 PM PDT 24 15247017 ps
T94 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3057968655 Jul 11 05:22:07 PM PDT 24 Jul 11 05:22:18 PM PDT 24 62782593 ps
T115 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2717496192 Jul 11 05:22:12 PM PDT 24 Jul 11 05:22:26 PM PDT 24 135276840 ps
T619 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2349393588 Jul 11 05:22:26 PM PDT 24 Jul 11 05:22:34 PM PDT 24 62231867 ps
T95 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1650132737 Jul 11 05:22:01 PM PDT 24 Jul 11 05:22:08 PM PDT 24 37307248 ps
T620 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1614935908 Jul 11 05:22:23 PM PDT 24 Jul 11 05:22:32 PM PDT 24 46570282 ps
T621 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2215724278 Jul 11 05:22:23 PM PDT 24 Jul 11 05:22:33 PM PDT 24 199927379 ps
T622 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2554856932 Jul 11 05:22:02 PM PDT 24 Jul 11 05:37:37 PM PDT 24 263043704814 ps
T623 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.4196458645 Jul 11 05:22:03 PM PDT 24 Jul 11 05:22:11 PM PDT 24 15439860 ps
T624 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3644715402 Jul 11 05:22:02 PM PDT 24 Jul 11 05:22:17 PM PDT 24 861742790 ps
T625 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2384382612 Jul 11 05:22:12 PM PDT 24 Jul 11 05:22:23 PM PDT 24 13672349 ps
T626 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4114501378 Jul 11 05:22:17 PM PDT 24 Jul 11 05:22:27 PM PDT 24 223949723 ps
T627 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1448781293 Jul 11 05:22:19 PM PDT 24 Jul 11 05:22:28 PM PDT 24 14374083 ps
T628 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2963753582 Jul 11 05:22:06 PM PDT 24 Jul 11 05:22:22 PM PDT 24 538135426 ps
T97 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3824666809 Jul 11 05:22:04 PM PDT 24 Jul 11 05:22:21 PM PDT 24 906296770 ps
T629 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.331166765 Jul 11 05:22:12 PM PDT 24 Jul 11 05:22:24 PM PDT 24 336427611 ps
T630 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2444488960 Jul 11 05:22:10 PM PDT 24 Jul 11 05:22:21 PM PDT 24 81154067 ps
T631 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3689493794 Jul 11 05:22:06 PM PDT 24 Jul 11 05:22:17 PM PDT 24 862893629 ps
T632 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.120847393 Jul 11 05:22:25 PM PDT 24 Jul 11 05:22:34 PM PDT 24 18995527 ps
T633 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.387475513 Jul 11 05:22:20 PM PDT 24 Jul 11 05:22:30 PM PDT 24 157601006 ps
T634 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3675444558 Jul 11 05:22:00 PM PDT 24 Jul 11 05:22:19 PM PDT 24 1062046801 ps
T635 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3999734513 Jul 11 05:22:05 PM PDT 24 Jul 11 05:22:16 PM PDT 24 276878077 ps
T636 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1217027054 Jul 11 05:22:07 PM PDT 24 Jul 11 05:22:19 PM PDT 24 113797125 ps
T637 /workspace/coverage/cover_reg_top/36.hmac_intr_test.3039996528 Jul 11 05:22:30 PM PDT 24 Jul 11 05:22:38 PM PDT 24 58571580 ps
T638 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3924768072 Jul 11 05:22:01 PM PDT 24 Jul 11 05:22:09 PM PDT 24 60790085 ps
T60 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1443566844 Jul 11 05:21:52 PM PDT 24 Jul 11 05:22:03 PM PDT 24 455557397 ps
T639 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3623424580 Jul 11 05:22:06 PM PDT 24 Jul 11 05:22:17 PM PDT 24 30375898 ps
T640 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3400242557 Jul 11 05:22:03 PM PDT 24 Jul 11 05:22:13 PM PDT 24 182518075 ps
T641 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3499605844 Jul 11 05:22:07 PM PDT 24 Jul 11 05:22:20 PM PDT 24 1230657894 ps
T642 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3126971014 Jul 11 05:22:04 PM PDT 24 Jul 11 05:22:16 PM PDT 24 322509579 ps
T643 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3970785311 Jul 11 05:22:16 PM PDT 24 Jul 11 05:37:32 PM PDT 24 265624698777 ps
T644 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3517751084 Jul 11 05:22:12 PM PDT 24 Jul 11 05:22:26 PM PDT 24 57837121 ps
T645 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1409683570 Jul 11 05:22:16 PM PDT 24 Jul 11 05:22:26 PM PDT 24 14742335 ps
T646 /workspace/coverage/cover_reg_top/40.hmac_intr_test.2069184328 Jul 11 05:22:27 PM PDT 24 Jul 11 05:22:36 PM PDT 24 25927414 ps
T647 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3403835793 Jul 11 05:22:08 PM PDT 24 Jul 11 05:22:19 PM PDT 24 65961683 ps
T648 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3730608424 Jul 11 05:22:28 PM PDT 24 Jul 11 05:22:37 PM PDT 24 11964941 ps
T649 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2578200382 Jul 11 05:22:15 PM PDT 24 Jul 11 05:22:25 PM PDT 24 41520394 ps
T650 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1563113894 Jul 11 05:22:00 PM PDT 24 Jul 11 05:22:07 PM PDT 24 56619783 ps
T651 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.591215205 Jul 11 05:22:00 PM PDT 24 Jul 11 05:22:13 PM PDT 24 2956730453 ps
T652 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3157289600 Jul 11 05:22:06 PM PDT 24 Jul 11 05:22:16 PM PDT 24 13349629 ps
T653 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1151892871 Jul 11 05:22:24 PM PDT 24 Jul 11 05:22:32 PM PDT 24 40243600 ps
T654 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.16039385 Jul 11 05:22:20 PM PDT 24 Jul 11 05:22:31 PM PDT 24 484264344 ps
T655 /workspace/coverage/cover_reg_top/37.hmac_intr_test.985600900 Jul 11 05:22:28 PM PDT 24 Jul 11 05:22:37 PM PDT 24 110114564 ps
T656 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2045718220 Jul 11 05:22:04 PM PDT 24 Jul 11 05:22:15 PM PDT 24 149198831 ps
T657 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.16869296 Jul 11 05:22:32 PM PDT 24 Jul 11 05:22:41 PM PDT 24 78170318 ps
T658 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.446388134 Jul 11 05:22:12 PM PDT 24 Jul 11 05:22:24 PM PDT 24 101974350 ps
T659 /workspace/coverage/cover_reg_top/38.hmac_intr_test.2346910164 Jul 11 05:22:26 PM PDT 24 Jul 11 05:22:35 PM PDT 24 11830215 ps
T117 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.986020822 Jul 11 05:22:00 PM PDT 24 Jul 11 05:22:08 PM PDT 24 301007742 ps

Test location /workspace/coverage/default/9.hmac_smoke.3579089267
Short name T1
Test name
Test status
Simulation time 203437774 ps
CPU time 9.07 seconds
Started Jul 11 05:25:01 PM PDT 24
Finished Jul 11 05:25:14 PM PDT 24
Peak memory 200252 kb
Host smart-6e943553-45d4-443e-b688-644d01450855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579089267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3579089267
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.382295306
Short name T9
Test name
Test status
Simulation time 61028091954 ps
CPU time 3936.97 seconds
Started Jul 11 05:24:39 PM PDT 24
Finished Jul 11 06:30:18 PM PDT 24
Peak memory 778172 kb
Host smart-f24f0f58-9adf-4dbb-b336-fe771f4d447f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=382295306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.382295306
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.1138623220
Short name T23
Test name
Test status
Simulation time 485639465322 ps
CPU time 8821.03 seconds
Started Jul 11 05:24:54 PM PDT 24
Finished Jul 11 07:51:58 PM PDT 24
Peak memory 918156 kb
Host smart-7d98acfe-d0a4-40a8-9dbf-1ae38bb631f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1138623220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.1138623220
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.hmac_stress_all.477810727
Short name T25
Test name
Test status
Simulation time 23186046536 ps
CPU time 2499.65 seconds
Started Jul 11 05:25:41 PM PDT 24
Finished Jul 11 06:07:24 PM PDT 24
Peak memory 802560 kb
Host smart-45b1303a-2918-4b05-93b2-edd48567d4ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477810727 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.477810727
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3672480792
Short name T111
Test name
Test status
Simulation time 218560328 ps
CPU time 2.85 seconds
Started Jul 11 05:22:13 PM PDT 24
Finished Jul 11 05:22:26 PM PDT 24
Peak memory 200504 kb
Host smart-cde6c89b-e791-46af-a45b-d2272094f52f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672480792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3672480792
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_alert_test.1358075026
Short name T42
Test name
Test status
Simulation time 22650105 ps
CPU time 0.56 seconds
Started Jul 11 05:24:48 PM PDT 24
Finished Jul 11 05:24:51 PM PDT 24
Peak memory 196084 kb
Host smart-2ae6e394-2ec0-4e69-b460-e9733ed59578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358075026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.1358075026
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.936964318
Short name T86
Test name
Test status
Simulation time 91435614 ps
CPU time 0.87 seconds
Started Jul 11 05:22:09 PM PDT 24
Finished Jul 11 05:22:20 PM PDT 24
Peak memory 199768 kb
Host smart-0d85f613-76bd-4225-920c-d193058247fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936964318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.936964318
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2812607797
Short name T14
Test name
Test status
Simulation time 5286991514 ps
CPU time 88.42 seconds
Started Jul 11 05:25:13 PM PDT 24
Finished Jul 11 05:26:51 PM PDT 24
Peak memory 208464 kb
Host smart-b6841c35-0465-4073-b7b8-1ded903ed025
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2812607797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2812607797
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1012141008
Short name T44
Test name
Test status
Simulation time 152757648 ps
CPU time 0.93 seconds
Started Jul 11 05:24:32 PM PDT 24
Finished Jul 11 05:24:35 PM PDT 24
Peak memory 218372 kb
Host smart-61b29911-fb11-4f75-be32-a3f388c0d988
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012141008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1012141008
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2510796809
Short name T107
Test name
Test status
Simulation time 16707433972 ps
CPU time 1603.83 seconds
Started Jul 11 05:25:05 PM PDT 24
Finished Jul 11 05:51:55 PM PDT 24
Peak memory 710220 kb
Host smart-1f22d948-b86a-4ab1-96c8-c01e8f245c79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510796809 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2510796809
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_stress_all.2587083318
Short name T69
Test name
Test status
Simulation time 286884169424 ps
CPU time 2428.94 seconds
Started Jul 11 05:25:50 PM PDT 24
Finished Jul 11 06:06:26 PM PDT 24
Peak memory 801844 kb
Host smart-49bd0729-25f4-4cb2-8b14-70446b779df9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587083318 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2587083318
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.399157330
Short name T112
Test name
Test status
Simulation time 312972810 ps
CPU time 1.98 seconds
Started Jul 11 05:21:55 PM PDT 24
Finished Jul 11 05:22:03 PM PDT 24
Peak memory 200224 kb
Host smart-9cec77c6-6827-4019-843a-cdf70e3811cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399157330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.399157330
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.741939782
Short name T113
Test name
Test status
Simulation time 201454890 ps
CPU time 3.86 seconds
Started Jul 11 05:22:20 PM PDT 24
Finished Jul 11 05:22:32 PM PDT 24
Peak memory 200152 kb
Host smart-b404dd54-ed69-4539-84d2-c6f5bd293412
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741939782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.741939782
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.3740114111
Short name T59
Test name
Test status
Simulation time 557483149 ps
CPU time 2.97 seconds
Started Jul 11 05:22:21 PM PDT 24
Finished Jul 11 05:22:32 PM PDT 24
Peak memory 200176 kb
Host smart-6f948acb-83e6-4b93-851e-9280ed80776c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740114111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.3740114111
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/25.hmac_stress_all.590546705
Short name T37
Test name
Test status
Simulation time 75236705043 ps
CPU time 2513.41 seconds
Started Jul 11 05:25:24 PM PDT 24
Finished Jul 11 06:07:22 PM PDT 24
Peak memory 767752 kb
Host smart-16fb2a46-c49d-4da7-85d7-0f72221c8957
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590546705 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.590546705
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1443566844
Short name T60
Test name
Test status
Simulation time 455557397 ps
CPU time 3.17 seconds
Started Jul 11 05:21:52 PM PDT 24
Finished Jul 11 05:22:03 PM PDT 24
Peak memory 200268 kb
Host smart-7a9d968c-a6ab-4afa-81fc-6d6ed88ccf4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443566844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1443566844
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1735840311
Short name T61
Test name
Test status
Simulation time 389217310 ps
CPU time 2.75 seconds
Started Jul 11 05:22:07 PM PDT 24
Finished Jul 11 05:22:20 PM PDT 24
Peak memory 200212 kb
Host smart-d7187803-8a6e-4e20-82b6-2db68daa9aec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735840311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1735840311
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.4246750187
Short name T64
Test name
Test status
Simulation time 1614795380991 ps
CPU time 1750.91 seconds
Started Jul 11 05:24:44 PM PDT 24
Finished Jul 11 05:53:58 PM PDT 24
Peak memory 693244 kb
Host smart-053664e0-caa5-4667-985c-01bea2356f65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4246750187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.4246750187
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3824666809
Short name T97
Test name
Test status
Simulation time 906296770 ps
CPU time 8.7 seconds
Started Jul 11 05:22:04 PM PDT 24
Finished Jul 11 05:22:21 PM PDT 24
Peak memory 200180 kb
Host smart-ea8bff25-7fde-4f3f-81a7-59a6dd9706d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824666809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3824666809
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.848827472
Short name T96
Test name
Test status
Simulation time 431233011 ps
CPU time 5.34 seconds
Started Jul 11 05:21:52 PM PDT 24
Finished Jul 11 05:22:05 PM PDT 24
Peak memory 200244 kb
Host smart-431c966a-0985-4a56-a754-5ea789c05fb8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848827472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.848827472
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2061777663
Short name T613
Test name
Test status
Simulation time 29634225 ps
CPU time 0.88 seconds
Started Jul 11 05:22:07 PM PDT 24
Finished Jul 11 05:22:17 PM PDT 24
Peak memory 199596 kb
Host smart-e361e121-94db-432f-8e43-6a3f94a77341
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061777663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2061777663
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.91766539
Short name T582
Test name
Test status
Simulation time 499040068931 ps
CPU time 1113.03 seconds
Started Jul 11 05:21:52 PM PDT 24
Finished Jul 11 05:40:32 PM PDT 24
Peak memory 216744 kb
Host smart-b99d2796-eaf5-4932-9acc-dce12488a89c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91766539 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.91766539
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1650132737
Short name T95
Test name
Test status
Simulation time 37307248 ps
CPU time 0.97 seconds
Started Jul 11 05:22:01 PM PDT 24
Finished Jul 11 05:22:08 PM PDT 24
Peak memory 199712 kb
Host smart-0f55c145-e45f-4723-a16a-0068184d8531
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650132737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1650132737
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2371394963
Short name T589
Test name
Test status
Simulation time 16633174 ps
CPU time 0.62 seconds
Started Jul 11 05:22:01 PM PDT 24
Finished Jul 11 05:22:07 PM PDT 24
Peak memory 195188 kb
Host smart-90f2f385-04b3-40d7-a7f6-d5812c9d4b2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371394963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2371394963
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3400242557
Short name T640
Test name
Test status
Simulation time 182518075 ps
CPU time 1.68 seconds
Started Jul 11 05:22:03 PM PDT 24
Finished Jul 11 05:22:13 PM PDT 24
Peak memory 200188 kb
Host smart-2def819b-e8a9-42b4-8fcf-b73e63833b21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400242557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3400242557
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3917886541
Short name T599
Test name
Test status
Simulation time 89865592 ps
CPU time 1.98 seconds
Started Jul 11 05:22:01 PM PDT 24
Finished Jul 11 05:22:09 PM PDT 24
Peak memory 200264 kb
Host smart-ad84d571-6c6f-48fd-b190-96c3caf0aee9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917886541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.3917886541
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.591215205
Short name T651
Test name
Test status
Simulation time 2956730453 ps
CPU time 8.35 seconds
Started Jul 11 05:22:00 PM PDT 24
Finished Jul 11 05:22:13 PM PDT 24
Peak memory 200304 kb
Host smart-eff44b33-768d-4cfa-a740-ebbad7a52657
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591215205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.591215205
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3644715402
Short name T624
Test name
Test status
Simulation time 861742790 ps
CPU time 9.49 seconds
Started Jul 11 05:22:02 PM PDT 24
Finished Jul 11 05:22:17 PM PDT 24
Peak memory 200184 kb
Host smart-b6159e57-5db5-428d-96ac-ef515144d313
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644715402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3644715402
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3358171526
Short name T601
Test name
Test status
Simulation time 42505618 ps
CPU time 1 seconds
Started Jul 11 05:22:03 PM PDT 24
Finished Jul 11 05:22:12 PM PDT 24
Peak memory 200060 kb
Host smart-abd70917-69fd-4239-95a9-357de17a275e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358171526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3358171526
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.3924768072
Short name T638
Test name
Test status
Simulation time 60790085 ps
CPU time 1.85 seconds
Started Jul 11 05:22:01 PM PDT 24
Finished Jul 11 05:22:09 PM PDT 24
Peak memory 200324 kb
Host smart-3a78a82c-5241-455f-a27a-c5768a05c516
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924768072 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.3924768072
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.216093136
Short name T583
Test name
Test status
Simulation time 32501970 ps
CPU time 0.71 seconds
Started Jul 11 05:22:01 PM PDT 24
Finished Jul 11 05:22:08 PM PDT 24
Peak memory 198264 kb
Host smart-41bd4c5a-2f27-4003-ab5d-cb16139af215
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216093136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.216093136
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.3118619136
Short name T585
Test name
Test status
Simulation time 48001795 ps
CPU time 0.61 seconds
Started Jul 11 05:22:00 PM PDT 24
Finished Jul 11 05:22:06 PM PDT 24
Peak memory 195260 kb
Host smart-bbfeff02-c8ae-4569-8b90-2b0dcc5267a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118619136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3118619136
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.331166765
Short name T629
Test name
Test status
Simulation time 336427611 ps
CPU time 1.73 seconds
Started Jul 11 05:22:12 PM PDT 24
Finished Jul 11 05:22:24 PM PDT 24
Peak memory 200072 kb
Host smart-e1aef897-425b-4ead-acf9-407d18087d93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331166765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.331166765
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3351431613
Short name T578
Test name
Test status
Simulation time 609524514 ps
CPU time 3.2 seconds
Started Jul 11 05:22:03 PM PDT 24
Finished Jul 11 05:22:14 PM PDT 24
Peak memory 199816 kb
Host smart-7273435a-a6f8-4233-a200-027c90a8bfc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351431613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3351431613
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1550767663
Short name T561
Test name
Test status
Simulation time 119420541 ps
CPU time 1.23 seconds
Started Jul 11 05:22:13 PM PDT 24
Finished Jul 11 05:22:24 PM PDT 24
Peak memory 200072 kb
Host smart-f7cb27d2-82cd-4243-876d-ed16963eeab8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550767663 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1550767663
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2444488960
Short name T630
Test name
Test status
Simulation time 81154067 ps
CPU time 0.69 seconds
Started Jul 11 05:22:10 PM PDT 24
Finished Jul 11 05:22:21 PM PDT 24
Peak memory 197760 kb
Host smart-0117519f-daf8-4080-b495-211d266a8519
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444488960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2444488960
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1409683570
Short name T645
Test name
Test status
Simulation time 14742335 ps
CPU time 0.6 seconds
Started Jul 11 05:22:16 PM PDT 24
Finished Jul 11 05:22:26 PM PDT 24
Peak memory 195208 kb
Host smart-fa0dc3f0-b021-4e53-a7e1-34686a293fdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409683570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1409683570
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3635327439
Short name T569
Test name
Test status
Simulation time 305253432 ps
CPU time 2.4 seconds
Started Jul 11 05:22:15 PM PDT 24
Finished Jul 11 05:22:27 PM PDT 24
Peak memory 200172 kb
Host smart-c8d7fda9-bbe0-4b60-843f-740b5b97c697
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635327439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3635327439
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3623424580
Short name T639
Test name
Test status
Simulation time 30375898 ps
CPU time 1.56 seconds
Started Jul 11 05:22:06 PM PDT 24
Finished Jul 11 05:22:17 PM PDT 24
Peak memory 200232 kb
Host smart-f0d4a9bf-d6e3-4232-aaf9-05409a16e4ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623424580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3623424580
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.183540816
Short name T57
Test name
Test status
Simulation time 51674528 ps
CPU time 1.71 seconds
Started Jul 11 05:22:06 PM PDT 24
Finished Jul 11 05:22:17 PM PDT 24
Peak memory 200240 kb
Host smart-03cfffe3-b10c-4303-9f57-d9c3a8d0a753
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183540816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.183540816
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3970785311
Short name T643
Test name
Test status
Simulation time 265624698777 ps
CPU time 906.77 seconds
Started Jul 11 05:22:16 PM PDT 24
Finished Jul 11 05:37:32 PM PDT 24
Peak memory 216764 kb
Host smart-2a86d3c6-7d82-4d6f-b550-c386cd9d1db8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970785311 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3970785311
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.203121214
Short name T540
Test name
Test status
Simulation time 13023223 ps
CPU time 0.72 seconds
Started Jul 11 05:22:14 PM PDT 24
Finished Jul 11 05:22:25 PM PDT 24
Peak memory 198308 kb
Host smart-e971b3ac-2eed-463b-b66d-4968bd043899
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203121214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.203121214
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.408890050
Short name T608
Test name
Test status
Simulation time 51395085 ps
CPU time 0.65 seconds
Started Jul 11 05:22:24 PM PDT 24
Finished Jul 11 05:22:33 PM PDT 24
Peak memory 195096 kb
Host smart-eaa8bf2d-b5bd-41cb-a82e-3063cf94d8d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408890050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.408890050
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.687815565
Short name T555
Test name
Test status
Simulation time 165829615 ps
CPU time 1.13 seconds
Started Jul 11 05:22:17 PM PDT 24
Finished Jul 11 05:22:27 PM PDT 24
Peak memory 200280 kb
Host smart-625bdb73-89d9-4758-a7dd-9d7630e50d41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687815565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.687815565
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3998160048
Short name T546
Test name
Test status
Simulation time 478398463 ps
CPU time 4.24 seconds
Started Jul 11 05:22:17 PM PDT 24
Finished Jul 11 05:22:30 PM PDT 24
Peak memory 200332 kb
Host smart-cdc7b82c-277c-42bb-bd7d-abe563272348
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998160048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3998160048
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2717496192
Short name T115
Test name
Test status
Simulation time 135276840 ps
CPU time 4.01 seconds
Started Jul 11 05:22:12 PM PDT 24
Finished Jul 11 05:22:26 PM PDT 24
Peak memory 200180 kb
Host smart-7640ebb2-97f9-4a98-a51d-b876b9f1eec5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717496192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2717496192
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2063547905
Short name T560
Test name
Test status
Simulation time 184914933 ps
CPU time 2.96 seconds
Started Jul 11 05:22:12 PM PDT 24
Finished Jul 11 05:22:25 PM PDT 24
Peak memory 215840 kb
Host smart-a6046e6f-fecd-405a-84f0-d1868b0096a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063547905 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2063547905
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1580049886
Short name T553
Test name
Test status
Simulation time 26854484 ps
CPU time 0.81 seconds
Started Jul 11 05:22:24 PM PDT 24
Finished Jul 11 05:22:32 PM PDT 24
Peak memory 199336 kb
Host smart-3041ef5b-3821-403b-9627-f46851390e91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580049886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1580049886
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2789131949
Short name T547
Test name
Test status
Simulation time 14505095 ps
CPU time 0.64 seconds
Started Jul 11 05:22:17 PM PDT 24
Finished Jul 11 05:22:26 PM PDT 24
Peak memory 195200 kb
Host smart-f4162f91-a151-41bc-9d1d-398228ee2834
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789131949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2789131949
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2318986818
Short name T600
Test name
Test status
Simulation time 94586637 ps
CPU time 1.76 seconds
Started Jul 11 05:22:14 PM PDT 24
Finished Jul 11 05:22:26 PM PDT 24
Peak memory 200296 kb
Host smart-f3a3f87a-7dc3-4341-98c0-86971d9e29cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318986818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2318986818
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.703240207
Short name T598
Test name
Test status
Simulation time 190583646 ps
CPU time 3.9 seconds
Started Jul 11 05:22:15 PM PDT 24
Finished Jul 11 05:22:28 PM PDT 24
Peak memory 200144 kb
Host smart-04319b38-d5c1-4f2f-9d3d-e20ce2b4bad8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703240207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.703240207
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.3424744617
Short name T594
Test name
Test status
Simulation time 43611956 ps
CPU time 1.29 seconds
Started Jul 11 05:22:15 PM PDT 24
Finished Jul 11 05:22:26 PM PDT 24
Peak memory 200080 kb
Host smart-a4de15df-e62a-43f8-aed0-25003f9f839a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424744617 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.3424744617
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.1588303973
Short name T541
Test name
Test status
Simulation time 32120153 ps
CPU time 0.92 seconds
Started Jul 11 05:22:20 PM PDT 24
Finished Jul 11 05:22:29 PM PDT 24
Peak memory 199580 kb
Host smart-03be2628-7194-436f-9bde-7b9a42563a62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588303973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.1588303973
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3857160481
Short name T617
Test name
Test status
Simulation time 54705433 ps
CPU time 0.62 seconds
Started Jul 11 05:22:24 PM PDT 24
Finished Jul 11 05:22:32 PM PDT 24
Peak memory 195144 kb
Host smart-9fe73ebc-838b-49ae-aac1-456bd552fdb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857160481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3857160481
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1965579671
Short name T545
Test name
Test status
Simulation time 44533314 ps
CPU time 1.16 seconds
Started Jul 11 05:22:16 PM PDT 24
Finished Jul 11 05:22:27 PM PDT 24
Peak memory 200308 kb
Host smart-da8e5c55-0c2b-4e7b-89f5-4911fc2f2400
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965579671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1965579671
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.171793213
Short name T534
Test name
Test status
Simulation time 1363619201 ps
CPU time 3.26 seconds
Started Jul 11 05:22:14 PM PDT 24
Finished Jul 11 05:22:28 PM PDT 24
Peak memory 200200 kb
Host smart-681991cd-4e17-4b8f-9ce2-a6a5ff997ed2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171793213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.171793213
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.446388134
Short name T658
Test name
Test status
Simulation time 101974350 ps
CPU time 1.77 seconds
Started Jul 11 05:22:12 PM PDT 24
Finished Jul 11 05:22:24 PM PDT 24
Peak memory 200252 kb
Host smart-6e8c5a66-edac-4d06-8c4c-ebb4e6c90513
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446388134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.446388134
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.3546821267
Short name T603
Test name
Test status
Simulation time 47277545 ps
CPU time 2.57 seconds
Started Jul 11 05:22:13 PM PDT 24
Finished Jul 11 05:22:26 PM PDT 24
Peak memory 200228 kb
Host smart-a168110a-bdf2-43f2-a47d-530b6a1f44f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546821267 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.3546821267
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3007672070
Short name T88
Test name
Test status
Simulation time 415072125 ps
CPU time 1 seconds
Started Jul 11 05:22:14 PM PDT 24
Finished Jul 11 05:22:25 PM PDT 24
Peak memory 200056 kb
Host smart-b3296c99-d988-4075-ba2c-b9b82b92f7dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007672070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3007672070
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2270841305
Short name T533
Test name
Test status
Simulation time 28052390 ps
CPU time 0.63 seconds
Started Jul 11 05:22:14 PM PDT 24
Finished Jul 11 05:22:25 PM PDT 24
Peak memory 195056 kb
Host smart-027c01fa-8179-47a0-bbb2-1d4b52baeb4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270841305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2270841305
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2663891304
Short name T538
Test name
Test status
Simulation time 117047120 ps
CPU time 2.24 seconds
Started Jul 11 05:22:14 PM PDT 24
Finished Jul 11 05:22:27 PM PDT 24
Peak memory 200280 kb
Host smart-70b667a4-9a25-4e3f-b3eb-f2e9ac0a5373
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663891304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2663891304
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.387475513
Short name T633
Test name
Test status
Simulation time 157601006 ps
CPU time 1.38 seconds
Started Jul 11 05:22:20 PM PDT 24
Finished Jul 11 05:22:30 PM PDT 24
Peak memory 200320 kb
Host smart-41e48eed-fcac-4996-bce4-ea68b662cfe4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387475513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.387475513
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1741356790
Short name T581
Test name
Test status
Simulation time 369095262 ps
CPU time 2.55 seconds
Started Jul 11 05:22:18 PM PDT 24
Finished Jul 11 05:22:30 PM PDT 24
Peak memory 200376 kb
Host smart-6a5119fd-c690-4aed-a05a-71c036d561f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741356790 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1741356790
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.493082250
Short name T105
Test name
Test status
Simulation time 50432088 ps
CPU time 0.84 seconds
Started Jul 11 05:22:11 PM PDT 24
Finished Jul 11 05:22:22 PM PDT 24
Peak memory 199176 kb
Host smart-980226fc-46f1-435b-8dea-b90b4b66093a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493082250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.493082250
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2578200382
Short name T649
Test name
Test status
Simulation time 41520394 ps
CPU time 0.6 seconds
Started Jul 11 05:22:15 PM PDT 24
Finished Jul 11 05:22:25 PM PDT 24
Peak memory 195112 kb
Host smart-d50600fa-376a-4561-9e58-f5646e9889a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578200382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2578200382
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2916795366
Short name T591
Test name
Test status
Simulation time 45890726 ps
CPU time 1.15 seconds
Started Jul 11 05:22:21 PM PDT 24
Finished Jul 11 05:22:31 PM PDT 24
Peak memory 198720 kb
Host smart-8ff65344-9b1d-4188-9664-94378e942c01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916795366 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2916795366
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1406704192
Short name T532
Test name
Test status
Simulation time 144865147 ps
CPU time 1.41 seconds
Started Jul 11 05:22:14 PM PDT 24
Finished Jul 11 05:22:26 PM PDT 24
Peak memory 200228 kb
Host smart-0324dcf7-eacb-4b47-b783-e097a4e73253
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406704192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1406704192
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.107720918
Short name T58
Test name
Test status
Simulation time 233614474 ps
CPU time 4.53 seconds
Started Jul 11 05:22:20 PM PDT 24
Finished Jul 11 05:22:33 PM PDT 24
Peak memory 200260 kb
Host smart-81a6a9b2-afcb-4b17-8f53-30a58278216e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107720918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.107720918
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.16869296
Short name T657
Test name
Test status
Simulation time 78170318 ps
CPU time 1.81 seconds
Started Jul 11 05:22:32 PM PDT 24
Finished Jul 11 05:22:41 PM PDT 24
Peak memory 200264 kb
Host smart-e69020c9-b3d6-47e1-bf74-42587a25b301
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16869296 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.16869296
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.4244450819
Short name T87
Test name
Test status
Simulation time 17026472 ps
CPU time 0.98 seconds
Started Jul 11 05:22:24 PM PDT 24
Finished Jul 11 05:22:33 PM PDT 24
Peak memory 200100 kb
Host smart-645451a3-a2c4-42fc-9530-fbd3753132b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244450819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.4244450819
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3282461913
Short name T588
Test name
Test status
Simulation time 31018862 ps
CPU time 0.57 seconds
Started Jul 11 05:22:30 PM PDT 24
Finished Jul 11 05:22:38 PM PDT 24
Peak memory 195248 kb
Host smart-b9a0a70a-2940-4f6c-98f2-9bce1d12b445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282461913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3282461913
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1548389404
Short name T573
Test name
Test status
Simulation time 157097614 ps
CPU time 2.11 seconds
Started Jul 11 05:22:24 PM PDT 24
Finished Jul 11 05:22:34 PM PDT 24
Peak memory 200324 kb
Host smart-b650977b-186d-4df7-b977-4d28099c87ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548389404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1548389404
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.16039385
Short name T654
Test name
Test status
Simulation time 484264344 ps
CPU time 2.74 seconds
Started Jul 11 05:22:20 PM PDT 24
Finished Jul 11 05:22:31 PM PDT 24
Peak memory 200272 kb
Host smart-9ec8d04f-e571-47b6-8c29-59e42bc21765
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16039385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.16039385
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.4114501378
Short name T626
Test name
Test status
Simulation time 223949723 ps
CPU time 1.7 seconds
Started Jul 11 05:22:17 PM PDT 24
Finished Jul 11 05:22:27 PM PDT 24
Peak memory 200360 kb
Host smart-0681cace-f6e0-44a0-b82d-bb05ad36fa6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114501378 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.4114501378
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.779672429
Short name T566
Test name
Test status
Simulation time 26193703 ps
CPU time 0.83 seconds
Started Jul 11 05:22:20 PM PDT 24
Finished Jul 11 05:22:29 PM PDT 24
Peak memory 199712 kb
Host smart-c457f99b-0313-4ace-a279-72defaf16bed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779672429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.779672429
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1518125585
Short name T543
Test name
Test status
Simulation time 48423705 ps
CPU time 0.62 seconds
Started Jul 11 05:22:22 PM PDT 24
Finished Jul 11 05:22:31 PM PDT 24
Peak memory 195320 kb
Host smart-8fbe2ec5-c326-4788-b1f3-3e7c80360ec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518125585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1518125585
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1905501109
Short name T549
Test name
Test status
Simulation time 33441518 ps
CPU time 1.59 seconds
Started Jul 11 05:22:31 PM PDT 24
Finished Jul 11 05:22:40 PM PDT 24
Peak memory 200264 kb
Host smart-4deb2fe5-cf48-4dd6-9c6e-622240dce3ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905501109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1905501109
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1556390344
Short name T592
Test name
Test status
Simulation time 55854404 ps
CPU time 2.97 seconds
Started Jul 11 05:22:21 PM PDT 24
Finished Jul 11 05:22:32 PM PDT 24
Peak memory 200256 kb
Host smart-ee3320f4-b8dd-4b00-b7ac-0d0918643c4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556390344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1556390344
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1959983306
Short name T116
Test name
Test status
Simulation time 190359487 ps
CPU time 3.12 seconds
Started Jul 11 05:22:32 PM PDT 24
Finished Jul 11 05:22:42 PM PDT 24
Peak memory 200276 kb
Host smart-b183e322-d4c8-4b02-b406-044fee4e6be4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959983306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1959983306
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1568502651
Short name T531
Test name
Test status
Simulation time 49157607 ps
CPU time 1.48 seconds
Started Jul 11 05:22:19 PM PDT 24
Finished Jul 11 05:22:29 PM PDT 24
Peak memory 200320 kb
Host smart-13ee7e3b-2cd9-416e-986d-1151a3358db3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568502651 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1568502651
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3496431534
Short name T568
Test name
Test status
Simulation time 63851047 ps
CPU time 0.72 seconds
Started Jul 11 05:22:20 PM PDT 24
Finished Jul 11 05:22:29 PM PDT 24
Peak memory 198208 kb
Host smart-35488640-e0d6-464d-b624-09607da974d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496431534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3496431534
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.808395697
Short name T618
Test name
Test status
Simulation time 15247017 ps
CPU time 0.63 seconds
Started Jul 11 05:22:32 PM PDT 24
Finished Jul 11 05:22:40 PM PDT 24
Peak memory 195172 kb
Host smart-35560f97-0542-41b9-a8b9-17409392ddc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808395697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.808395697
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1211124719
Short name T103
Test name
Test status
Simulation time 106367976 ps
CPU time 1.2 seconds
Started Jul 11 05:22:25 PM PDT 24
Finished Jul 11 05:22:35 PM PDT 24
Peak memory 200336 kb
Host smart-3bea1ab5-63da-403c-95c0-b89eaead4906
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211124719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1211124719
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2215724278
Short name T621
Test name
Test status
Simulation time 199927379 ps
CPU time 1.52 seconds
Started Jul 11 05:22:23 PM PDT 24
Finished Jul 11 05:22:33 PM PDT 24
Peak memory 200280 kb
Host smart-00bcf057-ed20-4e93-b288-f92f0389c370
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215724278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2215724278
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2511037098
Short name T615
Test name
Test status
Simulation time 92963987 ps
CPU time 1.85 seconds
Started Jul 11 05:22:26 PM PDT 24
Finished Jul 11 05:22:36 PM PDT 24
Peak memory 200276 kb
Host smart-f29c8898-0f9d-41d3-823c-dc14afecd0d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511037098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2511037098
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2171231252
Short name T587
Test name
Test status
Simulation time 143214137 ps
CPU time 1.16 seconds
Started Jul 11 05:22:30 PM PDT 24
Finished Jul 11 05:22:39 PM PDT 24
Peak memory 200108 kb
Host smart-001bdb15-2c5c-4b22-8fbe-1284aee9cea3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171231252 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2171231252
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.120847393
Short name T632
Test name
Test status
Simulation time 18995527 ps
CPU time 0.72 seconds
Started Jul 11 05:22:25 PM PDT 24
Finished Jul 11 05:22:34 PM PDT 24
Peak memory 198068 kb
Host smart-8af9f517-5b61-499e-89d4-7437d835c38a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120847393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.120847393
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1450924107
Short name T565
Test name
Test status
Simulation time 11496101 ps
CPU time 0.62 seconds
Started Jul 11 05:22:20 PM PDT 24
Finished Jul 11 05:22:29 PM PDT 24
Peak memory 195160 kb
Host smart-38a579e9-5715-4534-b577-c9df068a2b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450924107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1450924107
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3587975340
Short name T550
Test name
Test status
Simulation time 201794669 ps
CPU time 1.26 seconds
Started Jul 11 05:22:19 PM PDT 24
Finished Jul 11 05:22:28 PM PDT 24
Peak memory 200104 kb
Host smart-bdf05641-b6ce-455b-9fb5-5af8df051f9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587975340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3587975340
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3079627287
Short name T563
Test name
Test status
Simulation time 187351305 ps
CPU time 3.96 seconds
Started Jul 11 05:22:32 PM PDT 24
Finished Jul 11 05:22:43 PM PDT 24
Peak memory 200332 kb
Host smart-b73a8d80-55ce-4e5a-9900-e94f96f47765
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079627287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3079627287
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2264853401
Short name T114
Test name
Test status
Simulation time 97634945 ps
CPU time 1.79 seconds
Started Jul 11 05:22:21 PM PDT 24
Finished Jul 11 05:22:31 PM PDT 24
Peak memory 200192 kb
Host smart-43bdee93-c169-438a-85f8-a4fc4a2d6737
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264853401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2264853401
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1217027054
Short name T636
Test name
Test status
Simulation time 113797125 ps
CPU time 2.91 seconds
Started Jul 11 05:22:07 PM PDT 24
Finished Jul 11 05:22:19 PM PDT 24
Peak memory 199084 kb
Host smart-dbb02e00-3c8d-4f48-a81b-08e358687674
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217027054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1217027054
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2963753582
Short name T628
Test name
Test status
Simulation time 538135426 ps
CPU time 6.24 seconds
Started Jul 11 05:22:06 PM PDT 24
Finished Jul 11 05:22:22 PM PDT 24
Peak memory 200256 kb
Host smart-813d7e56-e7f8-4880-9789-98c803d3e8d8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963753582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2963753582
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.1128616840
Short name T92
Test name
Test status
Simulation time 39998593 ps
CPU time 0.99 seconds
Started Jul 11 05:22:03 PM PDT 24
Finished Jul 11 05:22:12 PM PDT 24
Peak memory 199492 kb
Host smart-12ff5360-d298-4cf8-a816-d1331265a2de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128616840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.1128616840
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2441061333
Short name T577
Test name
Test status
Simulation time 50191462 ps
CPU time 3.46 seconds
Started Jul 11 05:22:12 PM PDT 24
Finished Jul 11 05:22:26 PM PDT 24
Peak memory 200304 kb
Host smart-bf276d5b-539e-4662-b6ec-aa9afa5abd05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441061333 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2441061333
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.634885372
Short name T552
Test name
Test status
Simulation time 72755735 ps
CPU time 0.71 seconds
Started Jul 11 05:22:04 PM PDT 24
Finished Jul 11 05:22:13 PM PDT 24
Peak memory 198240 kb
Host smart-099392d2-0b8a-4998-8638-8a24ce900b0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634885372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.634885372
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2384382612
Short name T625
Test name
Test status
Simulation time 13672349 ps
CPU time 0.6 seconds
Started Jul 11 05:22:12 PM PDT 24
Finished Jul 11 05:22:23 PM PDT 24
Peak memory 195024 kb
Host smart-e33b243b-0aba-4e59-8d9d-80718d372a35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384382612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2384382612
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.852598428
Short name T98
Test name
Test status
Simulation time 47864625 ps
CPU time 2.26 seconds
Started Jul 11 05:21:59 PM PDT 24
Finished Jul 11 05:22:06 PM PDT 24
Peak memory 200132 kb
Host smart-6cfad499-b67b-4646-8c21-51114f707cec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852598428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.852598428
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1980308863
Short name T536
Test name
Test status
Simulation time 768556758 ps
CPU time 4.2 seconds
Started Jul 11 05:22:05 PM PDT 24
Finished Jul 11 05:22:18 PM PDT 24
Peak memory 200132 kb
Host smart-dcd306f4-2e70-4501-a718-f367a6c0da8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980308863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1980308863
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.986020822
Short name T117
Test name
Test status
Simulation time 301007742 ps
CPU time 3.01 seconds
Started Jul 11 05:22:00 PM PDT 24
Finished Jul 11 05:22:08 PM PDT 24
Peak memory 200192 kb
Host smart-cd0f4b91-b44e-4898-aa4e-1ebcc6f413fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986020822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.986020822
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.4216870726
Short name T556
Test name
Test status
Simulation time 41767496 ps
CPU time 0.59 seconds
Started Jul 11 05:22:19 PM PDT 24
Finished Jul 11 05:22:29 PM PDT 24
Peak memory 195108 kb
Host smart-43d0ab67-4817-4336-9c8c-ddaebe18267e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216870726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.4216870726
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1448781293
Short name T627
Test name
Test status
Simulation time 14374083 ps
CPU time 0.6 seconds
Started Jul 11 05:22:19 PM PDT 24
Finished Jul 11 05:22:28 PM PDT 24
Peak memory 195092 kb
Host smart-c471ccdf-3fd3-42dc-bb5e-d3a6e9eaa733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448781293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1448781293
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.939867154
Short name T590
Test name
Test status
Simulation time 19985284 ps
CPU time 0.58 seconds
Started Jul 11 05:22:17 PM PDT 24
Finished Jul 11 05:22:27 PM PDT 24
Peak memory 195044 kb
Host smart-44149ae0-964c-4a0c-9bfd-e32a82a12608
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939867154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.939867154
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.1106691826
Short name T576
Test name
Test status
Simulation time 46454167 ps
CPU time 0.63 seconds
Started Jul 11 05:22:27 PM PDT 24
Finished Jul 11 05:22:36 PM PDT 24
Peak memory 195136 kb
Host smart-b6d362f9-984d-4698-b610-8c6e2ced47e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106691826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.1106691826
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2760432692
Short name T609
Test name
Test status
Simulation time 51246466 ps
CPU time 0.63 seconds
Started Jul 11 05:22:25 PM PDT 24
Finished Jul 11 05:22:34 PM PDT 24
Peak memory 195080 kb
Host smart-4fb3a311-fe8a-4be7-97d3-f9f69ca23f7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760432692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2760432692
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1151892871
Short name T653
Test name
Test status
Simulation time 40243600 ps
CPU time 0.58 seconds
Started Jul 11 05:22:24 PM PDT 24
Finished Jul 11 05:22:32 PM PDT 24
Peak memory 195128 kb
Host smart-ee41bcbc-e372-4cba-b8e2-2f9793709fda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151892871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1151892871
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.460167484
Short name T558
Test name
Test status
Simulation time 13307514 ps
CPU time 0.6 seconds
Started Jul 11 05:22:30 PM PDT 24
Finished Jul 11 05:22:38 PM PDT 24
Peak memory 195152 kb
Host smart-8bdafd16-9689-463b-b8d3-f80f3a0d4952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460167484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.460167484
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1518764825
Short name T537
Test name
Test status
Simulation time 100846055 ps
CPU time 0.63 seconds
Started Jul 11 05:22:28 PM PDT 24
Finished Jul 11 05:22:36 PM PDT 24
Peak memory 195324 kb
Host smart-0f4f6279-0bbd-40d5-a12a-a05506217a33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518764825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1518764825
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.915309615
Short name T557
Test name
Test status
Simulation time 28265333 ps
CPU time 0.63 seconds
Started Jul 11 05:22:31 PM PDT 24
Finished Jul 11 05:22:39 PM PDT 24
Peak memory 195192 kb
Host smart-54e68029-6d05-44bf-9428-f043c5a77ff6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915309615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.915309615
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2349393588
Short name T619
Test name
Test status
Simulation time 62231867 ps
CPU time 0.56 seconds
Started Jul 11 05:22:26 PM PDT 24
Finished Jul 11 05:22:34 PM PDT 24
Peak memory 195124 kb
Host smart-35720ec1-1372-4843-9a44-559571b19b2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349393588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2349393588
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.4180057860
Short name T91
Test name
Test status
Simulation time 1405392857 ps
CPU time 5.97 seconds
Started Jul 11 05:22:04 PM PDT 24
Finished Jul 11 05:22:18 PM PDT 24
Peak memory 200184 kb
Host smart-4a6d80b5-22c3-4c7b-a472-e10b9d20743a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180057860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.4180057860
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3955798932
Short name T548
Test name
Test status
Simulation time 787076813 ps
CPU time 5.71 seconds
Started Jul 11 05:22:05 PM PDT 24
Finished Jul 11 05:22:20 PM PDT 24
Peak memory 200256 kb
Host smart-1fb73818-8a82-4381-8a78-25735ccdf68e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955798932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3955798932
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.4196458645
Short name T623
Test name
Test status
Simulation time 15439860 ps
CPU time 0.71 seconds
Started Jul 11 05:22:03 PM PDT 24
Finished Jul 11 05:22:11 PM PDT 24
Peak memory 197940 kb
Host smart-8bed1404-5ec0-49c5-b66f-77b3e53e8e45
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196458645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.4196458645
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2554856932
Short name T622
Test name
Test status
Simulation time 263043704814 ps
CPU time 928.23 seconds
Started Jul 11 05:22:02 PM PDT 24
Finished Jul 11 05:37:37 PM PDT 24
Peak memory 224872 kb
Host smart-bcf414dc-e563-4abd-bd74-3decbda27d8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554856932 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2554856932
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.2601208896
Short name T90
Test name
Test status
Simulation time 35595343 ps
CPU time 0.92 seconds
Started Jul 11 05:22:03 PM PDT 24
Finished Jul 11 05:22:12 PM PDT 24
Peak memory 200008 kb
Host smart-4b77c457-62d9-47d4-89ea-146194950240
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601208896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.2601208896
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.3537377869
Short name T614
Test name
Test status
Simulation time 15696973 ps
CPU time 0.62 seconds
Started Jul 11 05:22:03 PM PDT 24
Finished Jul 11 05:22:12 PM PDT 24
Peak memory 195188 kb
Host smart-1fa96c80-dcd5-4b9c-ba3d-a6d97981a5cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537377869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.3537377869
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1824410175
Short name T101
Test name
Test status
Simulation time 43990439 ps
CPU time 2.13 seconds
Started Jul 11 05:22:05 PM PDT 24
Finished Jul 11 05:22:16 PM PDT 24
Peak memory 200192 kb
Host smart-3831eb7f-9ba3-4bfb-87ae-a36b77c0f215
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824410175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1824410175
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1563113894
Short name T650
Test name
Test status
Simulation time 56619783 ps
CPU time 1.48 seconds
Started Jul 11 05:22:00 PM PDT 24
Finished Jul 11 05:22:07 PM PDT 24
Peak memory 200176 kb
Host smart-bf604cb5-9191-4d8a-b68b-889067a83edb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563113894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1563113894
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2265325758
Short name T56
Test name
Test status
Simulation time 308702482 ps
CPU time 1.94 seconds
Started Jul 11 05:22:07 PM PDT 24
Finished Jul 11 05:22:18 PM PDT 24
Peak memory 200276 kb
Host smart-39903ac3-9138-4229-adba-036669ed9c3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265325758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2265325758
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3312838023
Short name T575
Test name
Test status
Simulation time 102512682 ps
CPU time 0.61 seconds
Started Jul 11 05:22:26 PM PDT 24
Finished Jul 11 05:22:34 PM PDT 24
Peak memory 195192 kb
Host smart-4bdd91a6-b9ad-4a76-9781-9e3304cb8fc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312838023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3312838023
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.859121727
Short name T605
Test name
Test status
Simulation time 24762013 ps
CPU time 0.62 seconds
Started Jul 11 05:22:27 PM PDT 24
Finished Jul 11 05:22:36 PM PDT 24
Peak memory 195048 kb
Host smart-c0fd81ae-1620-45a1-8215-43d3f7425278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859121727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.859121727
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1614935908
Short name T620
Test name
Test status
Simulation time 46570282 ps
CPU time 0.62 seconds
Started Jul 11 05:22:23 PM PDT 24
Finished Jul 11 05:22:32 PM PDT 24
Peak memory 195200 kb
Host smart-6562b356-29cd-46d4-8ac2-55912cdf320d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614935908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1614935908
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.463901579
Short name T612
Test name
Test status
Simulation time 14017362 ps
CPU time 0.59 seconds
Started Jul 11 05:22:25 PM PDT 24
Finished Jul 11 05:22:34 PM PDT 24
Peak memory 195140 kb
Host smart-82dedd8b-d513-4f2a-950b-2075ed685110
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463901579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.463901579
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.574003911
Short name T607
Test name
Test status
Simulation time 38083484 ps
CPU time 0.62 seconds
Started Jul 11 05:22:32 PM PDT 24
Finished Jul 11 05:22:39 PM PDT 24
Peak memory 195248 kb
Host smart-31958121-2126-48e0-9041-45d0ed13d723
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574003911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.574003911
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2862699159
Short name T595
Test name
Test status
Simulation time 40008536 ps
CPU time 0.59 seconds
Started Jul 11 05:22:28 PM PDT 24
Finished Jul 11 05:22:36 PM PDT 24
Peak memory 195052 kb
Host smart-50134d20-5e09-472b-9b50-17622c3cdc2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862699159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2862699159
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.3039996528
Short name T637
Test name
Test status
Simulation time 58571580 ps
CPU time 0.63 seconds
Started Jul 11 05:22:30 PM PDT 24
Finished Jul 11 05:22:38 PM PDT 24
Peak memory 195228 kb
Host smart-f79725f6-e79e-4b1d-8539-b3e5dc955341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039996528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.3039996528
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.985600900
Short name T655
Test name
Test status
Simulation time 110114564 ps
CPU time 0.59 seconds
Started Jul 11 05:22:28 PM PDT 24
Finished Jul 11 05:22:37 PM PDT 24
Peak memory 195188 kb
Host smart-dcf099ed-68cb-4489-9455-e875918bf91a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985600900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.985600900
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.2346910164
Short name T659
Test name
Test status
Simulation time 11830215 ps
CPU time 0.58 seconds
Started Jul 11 05:22:26 PM PDT 24
Finished Jul 11 05:22:35 PM PDT 24
Peak memory 195132 kb
Host smart-6c223ed2-929a-4195-8d96-fcae2c2107c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346910164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.2346910164
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3730608424
Short name T648
Test name
Test status
Simulation time 11964941 ps
CPU time 0.62 seconds
Started Jul 11 05:22:28 PM PDT 24
Finished Jul 11 05:22:37 PM PDT 24
Peak memory 195124 kb
Host smart-f48e7ae1-4f6c-458e-bead-39f474eea866
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730608424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3730608424
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.184774583
Short name T93
Test name
Test status
Simulation time 231092900 ps
CPU time 3.14 seconds
Started Jul 11 05:22:07 PM PDT 24
Finished Jul 11 05:22:20 PM PDT 24
Peak memory 200052 kb
Host smart-c37b18a1-64a0-440a-8c5d-e55aa74a1487
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184774583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.184774583
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3675444558
Short name T634
Test name
Test status
Simulation time 1062046801 ps
CPU time 15.31 seconds
Started Jul 11 05:22:00 PM PDT 24
Finished Jul 11 05:22:19 PM PDT 24
Peak memory 199496 kb
Host smart-5bbcfdaa-2e1d-4834-b8d9-178ed740bf55
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675444558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3675444558
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.69431007
Short name T89
Test name
Test status
Simulation time 44872652 ps
CPU time 1.05 seconds
Started Jul 11 05:22:00 PM PDT 24
Finished Jul 11 05:22:06 PM PDT 24
Peak memory 199560 kb
Host smart-852849d3-363c-4b01-8fb6-09d985bd9d98
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69431007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.69431007
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3802818491
Short name T554
Test name
Test status
Simulation time 76658696 ps
CPU time 1.41 seconds
Started Jul 11 05:22:08 PM PDT 24
Finished Jul 11 05:22:20 PM PDT 24
Peak memory 200264 kb
Host smart-2ac7f72e-58b5-4351-987d-59dc0dd3133d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802818491 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3802818491
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3504701114
Short name T539
Test name
Test status
Simulation time 24840105 ps
CPU time 0.81 seconds
Started Jul 11 05:22:04 PM PDT 24
Finished Jul 11 05:22:13 PM PDT 24
Peak memory 199552 kb
Host smart-47a16e28-4551-4791-824b-b8d9b8aa7280
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504701114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3504701114
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.196748735
Short name T570
Test name
Test status
Simulation time 26744118 ps
CPU time 0.61 seconds
Started Jul 11 05:22:05 PM PDT 24
Finished Jul 11 05:22:15 PM PDT 24
Peak memory 195160 kb
Host smart-552f161d-4821-4695-8b32-1a294ba07269
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196748735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.196748735
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.3126971014
Short name T642
Test name
Test status
Simulation time 322509579 ps
CPU time 1.99 seconds
Started Jul 11 05:22:04 PM PDT 24
Finished Jul 11 05:22:16 PM PDT 24
Peak memory 200176 kb
Host smart-8de6cb22-663f-4bf2-8c0b-6bab436593aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126971014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.3126971014
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2045718220
Short name T656
Test name
Test status
Simulation time 149198831 ps
CPU time 2.06 seconds
Started Jul 11 05:22:04 PM PDT 24
Finished Jul 11 05:22:15 PM PDT 24
Peak memory 200256 kb
Host smart-5bb07bae-396f-49f0-a144-63be443b3505
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045718220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.2045718220
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2504601760
Short name T118
Test name
Test status
Simulation time 241722358 ps
CPU time 4.09 seconds
Started Jul 11 05:22:04 PM PDT 24
Finished Jul 11 05:22:17 PM PDT 24
Peak memory 200312 kb
Host smart-6369f860-c19c-49fb-9f07-acd379afaacb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504601760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2504601760
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2069184328
Short name T646
Test name
Test status
Simulation time 25927414 ps
CPU time 0.61 seconds
Started Jul 11 05:22:27 PM PDT 24
Finished Jul 11 05:22:36 PM PDT 24
Peak memory 195304 kb
Host smart-0872f408-419b-451f-84fa-7d13c90cf6f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069184328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2069184328
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3148884595
Short name T562
Test name
Test status
Simulation time 18408111 ps
CPU time 0.61 seconds
Started Jul 11 05:22:26 PM PDT 24
Finished Jul 11 05:22:35 PM PDT 24
Peak memory 195156 kb
Host smart-a5e4aee8-33a7-459e-82d6-636791ae24c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148884595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3148884595
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1662228475
Short name T535
Test name
Test status
Simulation time 44226444 ps
CPU time 0.58 seconds
Started Jul 11 05:22:26 PM PDT 24
Finished Jul 11 05:22:35 PM PDT 24
Peak memory 195132 kb
Host smart-45e7613d-f35b-4c66-97e7-5517985e0ec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662228475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1662228475
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3724494111
Short name T571
Test name
Test status
Simulation time 16161578 ps
CPU time 0.64 seconds
Started Jul 11 05:22:25 PM PDT 24
Finished Jul 11 05:22:34 PM PDT 24
Peak memory 195184 kb
Host smart-102e11eb-9324-4f49-b751-a58c60bf6e4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724494111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3724494111
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3713721884
Short name T616
Test name
Test status
Simulation time 33910230 ps
CPU time 0.58 seconds
Started Jul 11 05:22:25 PM PDT 24
Finished Jul 11 05:22:34 PM PDT 24
Peak memory 195044 kb
Host smart-b0423242-56f1-41c5-b005-0b1fc334e6d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713721884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3713721884
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1799459425
Short name T604
Test name
Test status
Simulation time 57021562 ps
CPU time 0.62 seconds
Started Jul 11 05:22:31 PM PDT 24
Finished Jul 11 05:22:39 PM PDT 24
Peak memory 195132 kb
Host smart-a8fbe2e2-49fd-48a0-b75a-aa85425d814e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799459425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1799459425
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.47790146
Short name T580
Test name
Test status
Simulation time 12010968 ps
CPU time 0.62 seconds
Started Jul 11 05:22:25 PM PDT 24
Finished Jul 11 05:22:33 PM PDT 24
Peak memory 195128 kb
Host smart-1fcdae33-b8d2-44a3-a810-26bc28aa3d22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47790146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.47790146
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2141467665
Short name T551
Test name
Test status
Simulation time 39385994 ps
CPU time 0.59 seconds
Started Jul 11 05:22:29 PM PDT 24
Finished Jul 11 05:22:37 PM PDT 24
Peak memory 195140 kb
Host smart-8c72bdcb-1559-494e-810f-4f1b2e0caff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141467665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2141467665
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2030213706
Short name T597
Test name
Test status
Simulation time 30988952 ps
CPU time 0.57 seconds
Started Jul 11 05:22:26 PM PDT 24
Finished Jul 11 05:22:34 PM PDT 24
Peak memory 195176 kb
Host smart-d791bf68-e4a0-424f-8c8d-0dab7a2b23a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030213706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2030213706
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.169784593
Short name T606
Test name
Test status
Simulation time 16904751 ps
CPU time 0.61 seconds
Started Jul 11 05:22:26 PM PDT 24
Finished Jul 11 05:22:35 PM PDT 24
Peak memory 195116 kb
Host smart-78ccf461-cd73-4a69-8b6e-f40d5c7cec7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169784593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.169784593
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3211340638
Short name T596
Test name
Test status
Simulation time 236857171 ps
CPU time 1.73 seconds
Started Jul 11 05:22:06 PM PDT 24
Finished Jul 11 05:22:17 PM PDT 24
Peak memory 200384 kb
Host smart-96f99b77-79bf-4a24-9b56-d74815fad576
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211340638 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3211340638
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1215404573
Short name T584
Test name
Test status
Simulation time 43677772 ps
CPU time 0.6 seconds
Started Jul 11 05:22:07 PM PDT 24
Finished Jul 11 05:22:17 PM PDT 24
Peak memory 195244 kb
Host smart-4063795e-ec2b-442b-9a1c-2c49761baade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215404573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1215404573
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1725498149
Short name T106
Test name
Test status
Simulation time 405293906 ps
CPU time 2.11 seconds
Started Jul 11 05:22:05 PM PDT 24
Finished Jul 11 05:22:17 PM PDT 24
Peak memory 200240 kb
Host smart-b50580bf-859a-4c6d-8c14-8b456bbeee60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725498149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1725498149
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.4186955138
Short name T610
Test name
Test status
Simulation time 270800714 ps
CPU time 1.41 seconds
Started Jul 11 05:22:11 PM PDT 24
Finished Jul 11 05:22:22 PM PDT 24
Peak memory 200248 kb
Host smart-1a3f1734-8de2-43de-be3d-7dcb3314a7a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186955138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.4186955138
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.837014123
Short name T119
Test name
Test status
Simulation time 855535694 ps
CPU time 1.89 seconds
Started Jul 11 05:22:06 PM PDT 24
Finished Jul 11 05:22:18 PM PDT 24
Peak memory 200256 kb
Host smart-e411d0a1-d050-482f-988e-a037694c7abe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837014123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.837014123
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.680660039
Short name T574
Test name
Test status
Simulation time 72417176 ps
CPU time 1.71 seconds
Started Jul 11 05:22:07 PM PDT 24
Finished Jul 11 05:22:18 PM PDT 24
Peak memory 200324 kb
Host smart-fc00754a-e45b-4360-9ecb-80e13f745647
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680660039 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.680660039
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.960711329
Short name T99
Test name
Test status
Simulation time 14592446 ps
CPU time 0.71 seconds
Started Jul 11 05:22:12 PM PDT 24
Finished Jul 11 05:22:23 PM PDT 24
Peak memory 197848 kb
Host smart-eed454da-1677-4e8e-979f-f8f1eb3afdb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960711329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.960711329
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3277221296
Short name T579
Test name
Test status
Simulation time 68909250 ps
CPU time 0.65 seconds
Started Jul 11 05:22:22 PM PDT 24
Finished Jul 11 05:22:31 PM PDT 24
Peak memory 195108 kb
Host smart-5ff37308-1303-46e9-b568-72c4328de2e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277221296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3277221296
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.553357387
Short name T102
Test name
Test status
Simulation time 69115466 ps
CPU time 1.72 seconds
Started Jul 11 05:22:15 PM PDT 24
Finished Jul 11 05:22:26 PM PDT 24
Peak memory 200212 kb
Host smart-8c40657d-f067-4999-826e-769ff662d993
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553357387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.553357387
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2503412536
Short name T572
Test name
Test status
Simulation time 74675867 ps
CPU time 1.72 seconds
Started Jul 11 05:22:08 PM PDT 24
Finished Jul 11 05:22:19 PM PDT 24
Peak memory 200188 kb
Host smart-274cf8eb-eafd-4584-a6de-6b578df5848e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503412536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2503412536
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3689493794
Short name T631
Test name
Test status
Simulation time 862893629 ps
CPU time 1.89 seconds
Started Jul 11 05:22:06 PM PDT 24
Finished Jul 11 05:22:17 PM PDT 24
Peak memory 200204 kb
Host smart-b3e2ba04-7061-4855-a841-b689a5ba8015
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689493794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3689493794
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1502613825
Short name T586
Test name
Test status
Simulation time 818282097 ps
CPU time 2.54 seconds
Started Jul 11 05:22:13 PM PDT 24
Finished Jul 11 05:22:26 PM PDT 24
Peak memory 200272 kb
Host smart-9640b6f4-893c-4107-a91d-438b78f4e544
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502613825 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1502613825
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3057968655
Short name T94
Test name
Test status
Simulation time 62782593 ps
CPU time 0.91 seconds
Started Jul 11 05:22:07 PM PDT 24
Finished Jul 11 05:22:18 PM PDT 24
Peak memory 199796 kb
Host smart-24fcbc1e-7a58-4d3e-9412-5a5614702cb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057968655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3057968655
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2966385181
Short name T544
Test name
Test status
Simulation time 45780729 ps
CPU time 0.59 seconds
Started Jul 11 05:22:09 PM PDT 24
Finished Jul 11 05:22:20 PM PDT 24
Peak memory 195096 kb
Host smart-8bf95abb-e66a-4ebe-b91e-6f197b3ed22a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966385181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2966385181
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3158165099
Short name T100
Test name
Test status
Simulation time 540291606 ps
CPU time 2.25 seconds
Started Jul 11 05:22:15 PM PDT 24
Finished Jul 11 05:22:27 PM PDT 24
Peak memory 200204 kb
Host smart-33c34700-7d13-4a50-85ff-a5c2fcd6feee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158165099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3158165099
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2279607453
Short name T593
Test name
Test status
Simulation time 339789752 ps
CPU time 3.42 seconds
Started Jul 11 05:22:07 PM PDT 24
Finished Jul 11 05:22:20 PM PDT 24
Peak memory 200176 kb
Host smart-da69ab93-4cd7-4802-bf47-a83f638ba86d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279607453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2279607453
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3085849890
Short name T567
Test name
Test status
Simulation time 39382979 ps
CPU time 1.19 seconds
Started Jul 11 05:22:09 PM PDT 24
Finished Jul 11 05:22:20 PM PDT 24
Peak memory 200084 kb
Host smart-ee50d61c-f9af-4ebd-ba7f-1377e10bcbe4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085849890 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3085849890
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3305524737
Short name T542
Test name
Test status
Simulation time 26580862 ps
CPU time 0.86 seconds
Started Jul 11 05:22:22 PM PDT 24
Finished Jul 11 05:22:31 PM PDT 24
Peak memory 199992 kb
Host smart-beb27941-2901-454b-80f2-1c46998efc2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305524737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3305524737
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3157289600
Short name T652
Test name
Test status
Simulation time 13349629 ps
CPU time 0.59 seconds
Started Jul 11 05:22:06 PM PDT 24
Finished Jul 11 05:22:16 PM PDT 24
Peak memory 195124 kb
Host smart-2b33eeae-5631-4658-823f-4164bf87c220
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157289600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3157289600
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3999734513
Short name T635
Test name
Test status
Simulation time 276878077 ps
CPU time 1.77 seconds
Started Jul 11 05:22:05 PM PDT 24
Finished Jul 11 05:22:16 PM PDT 24
Peak memory 200156 kb
Host smart-1a9b873e-6a1b-4bbb-ad34-d0b902de3dd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999734513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3999734513
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.342288209
Short name T611
Test name
Test status
Simulation time 172651951 ps
CPU time 3.34 seconds
Started Jul 11 05:22:05 PM PDT 24
Finished Jul 11 05:22:18 PM PDT 24
Peak memory 200264 kb
Host smart-1c3af088-b2c7-4c5b-9da7-06e866c427e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342288209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.342288209
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1940076416
Short name T559
Test name
Test status
Simulation time 374078045 ps
CPU time 1.74 seconds
Started Jul 11 05:22:05 PM PDT 24
Finished Jul 11 05:22:15 PM PDT 24
Peak memory 200192 kb
Host smart-b3f78826-d012-44d1-bf0f-508a1fcec064
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940076416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1940076416
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3403835793
Short name T647
Test name
Test status
Simulation time 65961683 ps
CPU time 1.61 seconds
Started Jul 11 05:22:08 PM PDT 24
Finished Jul 11 05:22:19 PM PDT 24
Peak memory 200240 kb
Host smart-cc063eb0-8348-4caf-9056-1dab0b1821e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403835793 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3403835793
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1233916579
Short name T602
Test name
Test status
Simulation time 27037479 ps
CPU time 0.72 seconds
Started Jul 11 05:22:09 PM PDT 24
Finished Jul 11 05:22:20 PM PDT 24
Peak memory 198368 kb
Host smart-9e1de4fb-fd58-40a2-bdfb-f2a493fca9ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233916579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1233916579
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2803448781
Short name T564
Test name
Test status
Simulation time 15644117 ps
CPU time 0.62 seconds
Started Jul 11 05:22:07 PM PDT 24
Finished Jul 11 05:22:17 PM PDT 24
Peak memory 195188 kb
Host smart-a43321f0-03e8-4a61-87c3-df88ccf803e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803448781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2803448781
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.1562199769
Short name T104
Test name
Test status
Simulation time 49418427 ps
CPU time 1.24 seconds
Started Jul 11 05:22:22 PM PDT 24
Finished Jul 11 05:22:31 PM PDT 24
Peak memory 198624 kb
Host smart-e68ddc7f-cd11-47db-b225-da0fb20d46f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562199769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.1562199769
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3517751084
Short name T644
Test name
Test status
Simulation time 57837121 ps
CPU time 2.81 seconds
Started Jul 11 05:22:12 PM PDT 24
Finished Jul 11 05:22:26 PM PDT 24
Peak memory 200256 kb
Host smart-1b746fb5-583d-486e-88bf-5c2638825389
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517751084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3517751084
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3499605844
Short name T641
Test name
Test status
Simulation time 1230657894 ps
CPU time 3.8 seconds
Started Jul 11 05:22:07 PM PDT 24
Finished Jul 11 05:22:20 PM PDT 24
Peak memory 200204 kb
Host smart-144caf00-a28d-4c83-bfe1-1a11c80fd733
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499605844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3499605844
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.287993981
Short name T525
Test name
Test status
Simulation time 75517635 ps
CPU time 0.61 seconds
Started Jul 11 05:24:32 PM PDT 24
Finished Jul 11 05:24:35 PM PDT 24
Peak memory 196168 kb
Host smart-1970d988-2276-44c1-b3ad-cd9d7772ae1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287993981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.287993981
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.546748742
Short name T39
Test name
Test status
Simulation time 725634661 ps
CPU time 37.58 seconds
Started Jul 11 05:24:52 PM PDT 24
Finished Jul 11 05:25:32 PM PDT 24
Peak memory 200300 kb
Host smart-71b2c4c4-5dc4-4230-8887-d18b58ea59ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=546748742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.546748742
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1315091547
Short name T440
Test name
Test status
Simulation time 43396894585 ps
CPU time 38.8 seconds
Started Jul 11 05:24:37 PM PDT 24
Finished Jul 11 05:25:19 PM PDT 24
Peak memory 200368 kb
Host smart-81cea7d9-fae0-43dd-b837-38b75adfbc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315091547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1315091547
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2942602263
Short name T164
Test name
Test status
Simulation time 7645806269 ps
CPU time 409.06 seconds
Started Jul 11 05:24:34 PM PDT 24
Finished Jul 11 05:31:27 PM PDT 24
Peak memory 704392 kb
Host smart-a6c94dcc-7082-4745-bd91-e508d79af150
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2942602263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2942602263
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.3654742810
Short name T238
Test name
Test status
Simulation time 36884285589 ps
CPU time 167.7 seconds
Started Jul 11 05:24:34 PM PDT 24
Finished Jul 11 05:27:25 PM PDT 24
Peak memory 200300 kb
Host smart-b62e8454-a523-47f8-af53-8730c612a27b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654742810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.3654742810
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.208136771
Short name T260
Test name
Test status
Simulation time 1787211968 ps
CPU time 20.55 seconds
Started Jul 11 05:24:50 PM PDT 24
Finished Jul 11 05:25:13 PM PDT 24
Peak memory 200164 kb
Host smart-974daffd-3bb0-4762-bf9f-c64dde061abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208136771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.208136771
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.3537547863
Short name T409
Test name
Test status
Simulation time 423214985 ps
CPU time 5.65 seconds
Started Jul 11 05:24:39 PM PDT 24
Finished Jul 11 05:24:47 PM PDT 24
Peak memory 200212 kb
Host smart-5d523297-04d1-44d8-bf4b-38467a40b2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537547863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3537547863
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.890725459
Short name T505
Test name
Test status
Simulation time 93017734734 ps
CPU time 1079.23 seconds
Started Jul 11 05:24:50 PM PDT 24
Finished Jul 11 05:42:51 PM PDT 24
Peak memory 681868 kb
Host smart-b9beea41-a8a4-41ad-ae7a-965e02757048
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890725459 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.890725459
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.525273747
Short name T62
Test name
Test status
Simulation time 215133849488 ps
CPU time 2788.46 seconds
Started Jul 11 05:24:52 PM PDT 24
Finished Jul 11 06:11:23 PM PDT 24
Peak memory 798800 kb
Host smart-9db9cc74-cac1-4527-82b0-7bf4ee7722c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=525273747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.525273747
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.1778956717
Short name T319
Test name
Test status
Simulation time 6643213816 ps
CPU time 72.08 seconds
Started Jul 11 05:24:35 PM PDT 24
Finished Jul 11 05:25:50 PM PDT 24
Peak memory 200360 kb
Host smart-c5350357-532c-4977-9b0c-b0b93451a2f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1778956717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.1778956717
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.3346629040
Short name T152
Test name
Test status
Simulation time 6967780964 ps
CPU time 58.34 seconds
Started Jul 11 05:24:35 PM PDT 24
Finished Jul 11 05:25:36 PM PDT 24
Peak memory 200384 kb
Host smart-5fb6f389-b9d4-46c2-831a-3a72d7dfaf63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3346629040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.3346629040
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.1424805318
Short name T448
Test name
Test status
Simulation time 4834958300 ps
CPU time 108.25 seconds
Started Jul 11 05:24:35 PM PDT 24
Finished Jul 11 05:26:27 PM PDT 24
Peak memory 200356 kb
Host smart-cc78b65d-d52c-4d13-bf3f-e1ba0e397d06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1424805318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.1424805318
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.1174750669
Short name T265
Test name
Test status
Simulation time 39405371894 ps
CPU time 532.02 seconds
Started Jul 11 05:24:34 PM PDT 24
Finished Jul 11 05:33:29 PM PDT 24
Peak memory 200304 kb
Host smart-197b127a-4171-4a73-a083-85fbfad4ac68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1174750669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.1174750669
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.2066988953
Short name T172
Test name
Test status
Simulation time 221520565603 ps
CPU time 2666.17 seconds
Started Jul 11 05:24:49 PM PDT 24
Finished Jul 11 06:09:18 PM PDT 24
Peak memory 216276 kb
Host smart-31dad19f-a11a-4254-9fae-642d4dc2409d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2066988953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.2066988953
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.2356984852
Short name T316
Test name
Test status
Simulation time 377063796355 ps
CPU time 2411.28 seconds
Started Jul 11 05:24:33 PM PDT 24
Finished Jul 11 06:04:47 PM PDT 24
Peak memory 215220 kb
Host smart-f2391d3b-814d-47eb-8a16-2ea97d6c53a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2356984852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.2356984852
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.419637853
Short name T49
Test name
Test status
Simulation time 131212491 ps
CPU time 7.36 seconds
Started Jul 11 05:24:38 PM PDT 24
Finished Jul 11 05:24:48 PM PDT 24
Peak memory 200248 kb
Host smart-77501100-3f37-4e50-b294-8bef86c85414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419637853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.419637853
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3134267922
Short name T50
Test name
Test status
Simulation time 3990046724 ps
CPU time 33.98 seconds
Started Jul 11 05:24:39 PM PDT 24
Finished Jul 11 05:25:15 PM PDT 24
Peak memory 200312 kb
Host smart-b1fc8975-1668-4873-93fa-01e422e1e558
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3134267922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3134267922
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3442287163
Short name T125
Test name
Test status
Simulation time 1108678082 ps
CPU time 60.03 seconds
Started Jul 11 05:24:37 PM PDT 24
Finished Jul 11 05:25:40 PM PDT 24
Peak memory 200296 kb
Host smart-b50eff59-c3df-4dee-be08-3322e6decd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442287163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3442287163
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.792607713
Short name T434
Test name
Test status
Simulation time 575939015 ps
CPU time 70.38 seconds
Started Jul 11 05:24:36 PM PDT 24
Finished Jul 11 05:25:49 PM PDT 24
Peak memory 335068 kb
Host smart-9032d61c-77e4-48ea-81b5-2cff614f3383
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=792607713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.792607713
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.709756156
Short name T181
Test name
Test status
Simulation time 6630043566 ps
CPU time 118.65 seconds
Started Jul 11 05:24:45 PM PDT 24
Finished Jul 11 05:26:47 PM PDT 24
Peak memory 200304 kb
Host smart-2d1e37ad-4f0a-4ad8-9514-4000f2dc6fc5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709756156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.709756156
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.938931181
Short name T343
Test name
Test status
Simulation time 2094682369 ps
CPU time 36.83 seconds
Started Jul 11 05:24:35 PM PDT 24
Finished Jul 11 05:25:15 PM PDT 24
Peak memory 200212 kb
Host smart-cb4f6d62-0cd3-4d23-834d-cefd3c86cdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938931181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.938931181
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1064270822
Short name T43
Test name
Test status
Simulation time 315894106 ps
CPU time 1.02 seconds
Started Jul 11 05:24:35 PM PDT 24
Finished Jul 11 05:24:39 PM PDT 24
Peak memory 219416 kb
Host smart-5c10373a-37cb-43c6-88c6-83eaa6008374
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064270822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1064270822
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3429392484
Short name T277
Test name
Test status
Simulation time 1503908678 ps
CPU time 13.09 seconds
Started Jul 11 05:24:34 PM PDT 24
Finished Jul 11 05:24:51 PM PDT 24
Peak memory 200176 kb
Host smart-c1744068-9222-4e36-a139-af1784390065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429392484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3429392484
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2101828859
Short name T286
Test name
Test status
Simulation time 49411099822 ps
CPU time 1739.27 seconds
Started Jul 11 05:24:31 PM PDT 24
Finished Jul 11 05:53:33 PM PDT 24
Peak memory 755912 kb
Host smart-37c0e2d8-6605-4e94-b025-3cabbb63b5cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101828859 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2101828859
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.896944261
Short name T423
Test name
Test status
Simulation time 6885274407 ps
CPU time 70.22 seconds
Started Jul 11 05:24:33 PM PDT 24
Finished Jul 11 05:25:46 PM PDT 24
Peak memory 200356 kb
Host smart-32c7bb85-8aa8-4b22-a43d-5a4c3c00311a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=896944261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.896944261
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.1215925567
Short name T404
Test name
Test status
Simulation time 7249929568 ps
CPU time 51.92 seconds
Started Jul 11 05:24:36 PM PDT 24
Finished Jul 11 05:25:31 PM PDT 24
Peak memory 200356 kb
Host smart-60a20fe6-7ab1-4917-b69e-a3e6b2d99903
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1215925567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.1215925567
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.420019481
Short name T472
Test name
Test status
Simulation time 52919977774 ps
CPU time 144.49 seconds
Started Jul 11 05:24:32 PM PDT 24
Finished Jul 11 05:26:59 PM PDT 24
Peak memory 200352 kb
Host smart-67ad99d6-3bd4-4912-b4b9-fc374a449e12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=420019481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.420019481
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.2951538499
Short name T510
Test name
Test status
Simulation time 200305352609 ps
CPU time 620.98 seconds
Started Jul 11 05:24:50 PM PDT 24
Finished Jul 11 05:35:13 PM PDT 24
Peak memory 200244 kb
Host smart-ecf45a13-af52-4daf-b00c-5f8c174887e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2951538499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.2951538499
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.2234154102
Short name T241
Test name
Test status
Simulation time 143520690515 ps
CPU time 2381.62 seconds
Started Jul 11 05:24:44 PM PDT 24
Finished Jul 11 06:04:28 PM PDT 24
Peak memory 216760 kb
Host smart-744a91aa-fc37-4e55-a5ba-f0931ee89994
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2234154102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.2234154102
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.3861428444
Short name T420
Test name
Test status
Simulation time 461055830445 ps
CPU time 2184.92 seconds
Started Jul 11 05:24:31 PM PDT 24
Finished Jul 11 06:00:57 PM PDT 24
Peak memory 216332 kb
Host smart-5895554b-7f00-464f-8297-1d6a6bcda6ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3861428444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.3861428444
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.211232341
Short name T295
Test name
Test status
Simulation time 773078091 ps
CPU time 35.4 seconds
Started Jul 11 05:24:33 PM PDT 24
Finished Jul 11 05:25:12 PM PDT 24
Peak memory 200352 kb
Host smart-47666c34-cac1-4f75-bd3d-8a91cac2eff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211232341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.211232341
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2612557411
Short name T301
Test name
Test status
Simulation time 12992922 ps
CPU time 0.59 seconds
Started Jul 11 05:24:55 PM PDT 24
Finished Jul 11 05:24:59 PM PDT 24
Peak memory 196192 kb
Host smart-28101c8c-51f8-4254-a57c-f679811d8c3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612557411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2612557411
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.1180380051
Short name T166
Test name
Test status
Simulation time 285452139 ps
CPU time 16.66 seconds
Started Jul 11 05:24:57 PM PDT 24
Finished Jul 11 05:25:17 PM PDT 24
Peak memory 200192 kb
Host smart-69c8d01d-d6be-4cb0-8da3-40f043fcc749
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1180380051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.1180380051
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3306313794
Short name T255
Test name
Test status
Simulation time 1931679685 ps
CPU time 25.33 seconds
Started Jul 11 05:25:19 PM PDT 24
Finished Jul 11 05:25:51 PM PDT 24
Peak memory 200308 kb
Host smart-451cc86b-ceca-44c1-b615-15c7da30404c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306313794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3306313794
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.1090401690
Short name T452
Test name
Test status
Simulation time 7708887782 ps
CPU time 332.57 seconds
Started Jul 11 05:24:56 PM PDT 24
Finished Jul 11 05:30:32 PM PDT 24
Peak memory 607696 kb
Host smart-b23e7563-2a09-444b-84c1-2a7bc45a79be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1090401690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.1090401690
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.2484137008
Short name T170
Test name
Test status
Simulation time 1875415389 ps
CPU time 26.81 seconds
Started Jul 11 05:24:56 PM PDT 24
Finished Jul 11 05:25:26 PM PDT 24
Peak memory 200288 kb
Host smart-b3644821-b84e-490e-a0b9-582340a5a631
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484137008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2484137008
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3533849134
Short name T325
Test name
Test status
Simulation time 11497552699 ps
CPU time 128.75 seconds
Started Jul 11 05:24:52 PM PDT 24
Finished Jul 11 05:27:04 PM PDT 24
Peak memory 200280 kb
Host smart-ed6f9180-4f19-4e11-bc5e-bfa9f8a3a5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533849134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3533849134
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.2486230610
Short name T471
Test name
Test status
Simulation time 236138164 ps
CPU time 10.1 seconds
Started Jul 11 05:25:00 PM PDT 24
Finished Jul 11 05:25:14 PM PDT 24
Peak memory 200360 kb
Host smart-66ffbe8a-9102-4bab-90e9-e9409d8d3664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486230610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2486230610
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1983586392
Short name T379
Test name
Test status
Simulation time 42857873958 ps
CPU time 1121.81 seconds
Started Jul 11 05:25:23 PM PDT 24
Finished Jul 11 05:44:10 PM PDT 24
Peak memory 703348 kb
Host smart-3a6fafbe-7928-4b16-a46d-1959312526fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983586392 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1983586392
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.3276714012
Short name T192
Test name
Test status
Simulation time 5385444228 ps
CPU time 96.32 seconds
Started Jul 11 05:24:54 PM PDT 24
Finished Jul 11 05:26:34 PM PDT 24
Peak memory 200284 kb
Host smart-8039f849-bed9-4479-91e1-5aec1efe11fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276714012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.3276714012
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.4200260151
Short name T443
Test name
Test status
Simulation time 36101090 ps
CPU time 0.58 seconds
Started Jul 11 05:24:50 PM PDT 24
Finished Jul 11 05:24:53 PM PDT 24
Peak memory 195144 kb
Host smart-38b58abd-ab26-43d2-84ba-75142903057a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200260151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.4200260151
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3184447026
Short name T394
Test name
Test status
Simulation time 4341281826 ps
CPU time 62.42 seconds
Started Jul 11 05:25:19 PM PDT 24
Finished Jul 11 05:26:28 PM PDT 24
Peak memory 200352 kb
Host smart-e372f598-ac8f-4448-9b29-d5bf03838496
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3184447026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3184447026
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3602798186
Short name T327
Test name
Test status
Simulation time 5520214855 ps
CPU time 46.86 seconds
Started Jul 11 05:24:55 PM PDT 24
Finished Jul 11 05:25:45 PM PDT 24
Peak memory 200384 kb
Host smart-e78c769d-9100-4ad6-a57c-b24207155731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602798186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3602798186
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1836639664
Short name T167
Test name
Test status
Simulation time 3008432970 ps
CPU time 280.33 seconds
Started Jul 11 05:24:56 PM PDT 24
Finished Jul 11 05:29:40 PM PDT 24
Peak memory 686768 kb
Host smart-cb94f850-00cd-47c1-bbac-f85173bfcbdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1836639664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1836639664
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2584286846
Short name T283
Test name
Test status
Simulation time 4619666080 ps
CPU time 61.87 seconds
Started Jul 11 05:24:52 PM PDT 24
Finished Jul 11 05:25:56 PM PDT 24
Peak memory 200380 kb
Host smart-2e7e3f4a-33ad-4cbc-8b68-7c8115988632
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584286846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2584286846
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3178060730
Short name T248
Test name
Test status
Simulation time 41262215195 ps
CPU time 197.25 seconds
Started Jul 11 05:25:19 PM PDT 24
Finished Jul 11 05:28:42 PM PDT 24
Peak memory 208580 kb
Host smart-f6018846-bd8f-45db-9b9b-1281b9d3ff9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178060730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3178060730
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3744562927
Short name T406
Test name
Test status
Simulation time 100985598 ps
CPU time 2.05 seconds
Started Jul 11 05:24:54 PM PDT 24
Finished Jul 11 05:25:00 PM PDT 24
Peak memory 200168 kb
Host smart-02b67820-142a-445d-ab24-73e95234f0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744562927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3744562927
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.817866858
Short name T263
Test name
Test status
Simulation time 30240562982 ps
CPU time 730.03 seconds
Started Jul 11 05:24:51 PM PDT 24
Finished Jul 11 05:37:04 PM PDT 24
Peak memory 680696 kb
Host smart-a42379a4-2707-4371-b5b6-e88f47937e5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817866858 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.817866858
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.165878651
Short name T83
Test name
Test status
Simulation time 31323199792 ps
CPU time 103.87 seconds
Started Jul 11 05:24:53 PM PDT 24
Finished Jul 11 05:26:40 PM PDT 24
Peak memory 200252 kb
Host smart-cfd58f26-02c2-426a-a7d6-649b78bbca77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165878651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.165878651
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2780295557
Short name T511
Test name
Test status
Simulation time 13116064 ps
CPU time 0.61 seconds
Started Jul 11 05:25:07 PM PDT 24
Finished Jul 11 05:25:17 PM PDT 24
Peak memory 195744 kb
Host smart-7f490837-35e1-4fe3-b434-4ffbfd200dd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780295557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2780295557
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.4260273204
Short name T212
Test name
Test status
Simulation time 1474232265 ps
CPU time 76.65 seconds
Started Jul 11 05:24:59 PM PDT 24
Finished Jul 11 05:26:19 PM PDT 24
Peak memory 200296 kb
Host smart-e2900d96-4353-45b1-a187-270f34fbad0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4260273204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.4260273204
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1398249921
Short name T401
Test name
Test status
Simulation time 2941229362 ps
CPU time 22.63 seconds
Started Jul 11 05:24:56 PM PDT 24
Finished Jul 11 05:25:22 PM PDT 24
Peak memory 200300 kb
Host smart-8425fb94-5290-485b-9150-3bbb4ce7e2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398249921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1398249921
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3525891606
Short name T253
Test name
Test status
Simulation time 3749559308 ps
CPU time 677.47 seconds
Started Jul 11 05:25:00 PM PDT 24
Finished Jul 11 05:36:21 PM PDT 24
Peak memory 737140 kb
Host smart-e618917a-e161-43b8-a884-b4c087215205
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3525891606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3525891606
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2549780660
Short name T131
Test name
Test status
Simulation time 4229261824 ps
CPU time 221.82 seconds
Started Jul 11 05:25:20 PM PDT 24
Finished Jul 11 05:29:08 PM PDT 24
Peak memory 200396 kb
Host smart-18d537d3-a259-46e1-beb3-9612cf2a21f7
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549780660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2549780660
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.4169885316
Short name T149
Test name
Test status
Simulation time 42555200851 ps
CPU time 208.69 seconds
Started Jul 11 05:24:56 PM PDT 24
Finished Jul 11 05:28:29 PM PDT 24
Peak memory 216604 kb
Host smart-76a20459-29fa-4e22-9554-5f078cd3a5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169885316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.4169885316
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2676341837
Short name T453
Test name
Test status
Simulation time 281085576 ps
CPU time 6.21 seconds
Started Jul 11 05:24:55 PM PDT 24
Finished Jul 11 05:25:05 PM PDT 24
Peak memory 200308 kb
Host smart-23ce596d-2280-41d5-9e32-b7564197a7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676341837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2676341837
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1864243877
Short name T449
Test name
Test status
Simulation time 4603894625 ps
CPU time 108.25 seconds
Started Jul 11 05:25:02 PM PDT 24
Finished Jul 11 05:26:56 PM PDT 24
Peak memory 200280 kb
Host smart-982142d5-6bb8-44f9-b15a-bf3a6aae2b4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864243877 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1864243877
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1054089908
Short name T211
Test name
Test status
Simulation time 41194645206 ps
CPU time 110.16 seconds
Started Jul 11 05:25:16 PM PDT 24
Finished Jul 11 05:27:14 PM PDT 24
Peak memory 200248 kb
Host smart-64a811bd-bd5d-40de-a8f6-e088f8b308f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054089908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1054089908
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3962745066
Short name T234
Test name
Test status
Simulation time 16344801 ps
CPU time 0.62 seconds
Started Jul 11 05:25:06 PM PDT 24
Finished Jul 11 05:25:15 PM PDT 24
Peak memory 196208 kb
Host smart-d818e03a-8aa2-415f-afcf-545b89d996fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962745066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3962745066
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2211383505
Short name T52
Test name
Test status
Simulation time 1371616581 ps
CPU time 76 seconds
Started Jul 11 05:25:05 PM PDT 24
Finished Jul 11 05:26:29 PM PDT 24
Peak memory 200304 kb
Host smart-41bf28a1-0e0c-4cb7-8c82-30582629b13f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2211383505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2211383505
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1040520989
Short name T217
Test name
Test status
Simulation time 24597913985 ps
CPU time 85.5 seconds
Started Jul 11 05:25:04 PM PDT 24
Finished Jul 11 05:26:35 PM PDT 24
Peak memory 216692 kb
Host smart-5efdbe22-b6e3-4486-b224-cf32ce7832cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040520989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1040520989
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.651342234
Short name T226
Test name
Test status
Simulation time 14425673989 ps
CPU time 366.24 seconds
Started Jul 11 05:25:04 PM PDT 24
Finished Jul 11 05:31:17 PM PDT 24
Peak memory 497480 kb
Host smart-1abe4780-1653-4850-8860-070a17d98422
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=651342234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.651342234
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2145733162
Short name T142
Test name
Test status
Simulation time 3860158181 ps
CPU time 206.67 seconds
Started Jul 11 05:25:05 PM PDT 24
Finished Jul 11 05:28:39 PM PDT 24
Peak memory 200224 kb
Host smart-558c9cdb-1a06-427e-94db-8dad7265dc5e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145733162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2145733162
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2363302334
Short name T199
Test name
Test status
Simulation time 12473228614 ps
CPU time 160.27 seconds
Started Jul 11 05:25:06 PM PDT 24
Finished Jul 11 05:27:54 PM PDT 24
Peak memory 216668 kb
Host smart-50b6d9c0-e0dc-442d-9585-2d068f5c9efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363302334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2363302334
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2083815980
Short name T8
Test name
Test status
Simulation time 738600920 ps
CPU time 2.66 seconds
Started Jul 11 05:25:01 PM PDT 24
Finished Jul 11 05:25:09 PM PDT 24
Peak memory 200200 kb
Host smart-e068a253-051e-45d3-8a3c-78964c0233e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083815980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2083815980
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1194946220
Short name T515
Test name
Test status
Simulation time 1134459740 ps
CPU time 27.45 seconds
Started Jul 11 05:25:05 PM PDT 24
Finished Jul 11 05:25:40 PM PDT 24
Peak memory 200344 kb
Host smart-a3cbb01c-d93f-4ab5-a190-5d9d9555fc09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194946220 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1194946220
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1607974847
Short name T392
Test name
Test status
Simulation time 1817228310 ps
CPU time 74.59 seconds
Started Jul 11 05:25:07 PM PDT 24
Finished Jul 11 05:26:31 PM PDT 24
Peak memory 200200 kb
Host smart-09eef348-f8e3-47a3-9da6-ee8fe8ab991a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607974847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1607974847
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1828979618
Short name T51
Test name
Test status
Simulation time 34003890 ps
CPU time 0.57 seconds
Started Jul 11 05:25:05 PM PDT 24
Finished Jul 11 05:25:13 PM PDT 24
Peak memory 195084 kb
Host smart-a2863503-b4ff-4563-9f55-dafe4fbd632c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828979618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1828979618
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2768813145
Short name T464
Test name
Test status
Simulation time 524497856 ps
CPU time 23.67 seconds
Started Jul 11 05:25:02 PM PDT 24
Finished Jul 11 05:25:32 PM PDT 24
Peak memory 200296 kb
Host smart-523626af-b710-4bbf-b786-af4bf194c7f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2768813145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2768813145
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.4265282674
Short name T221
Test name
Test status
Simulation time 763543739 ps
CPU time 41.44 seconds
Started Jul 11 05:25:01 PM PDT 24
Finished Jul 11 05:25:48 PM PDT 24
Peak memory 200240 kb
Host smart-c7e2c365-eea1-4625-a699-42f596679f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265282674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.4265282674
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2849069631
Short name T509
Test name
Test status
Simulation time 7553629540 ps
CPU time 262.14 seconds
Started Jul 11 05:25:08 PM PDT 24
Finished Jul 11 05:29:39 PM PDT 24
Peak memory 659052 kb
Host smart-15ddc0db-fa73-469b-a05a-d49c8ecbc0ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2849069631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2849069631
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3354958066
Short name T405
Test name
Test status
Simulation time 1996416992 ps
CPU time 89.35 seconds
Started Jul 11 05:25:20 PM PDT 24
Finished Jul 11 05:26:55 PM PDT 24
Peak memory 200260 kb
Host smart-804d9236-515a-44dd-b937-1e3385b80686
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354958066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3354958066
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.2659695988
Short name T447
Test name
Test status
Simulation time 6000331567 ps
CPU time 101.57 seconds
Started Jul 11 05:25:14 PM PDT 24
Finished Jul 11 05:27:05 PM PDT 24
Peak memory 200328 kb
Host smart-0684eb6f-32fd-4eb8-951e-2a3a2c2d6570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659695988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.2659695988
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.728552221
Short name T339
Test name
Test status
Simulation time 1118520238 ps
CPU time 3.97 seconds
Started Jul 11 05:25:12 PM PDT 24
Finished Jul 11 05:25:24 PM PDT 24
Peak memory 199584 kb
Host smart-70a88c69-0047-4bed-b8a4-9ed0e2738391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728552221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.728552221
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.400313374
Short name T81
Test name
Test status
Simulation time 58221267202 ps
CPU time 929.15 seconds
Started Jul 11 05:25:00 PM PDT 24
Finished Jul 11 05:40:33 PM PDT 24
Peak memory 647132 kb
Host smart-02f88524-6420-4df5-b483-1ea5f10895b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400313374 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.400313374
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.1338525025
Short name T305
Test name
Test status
Simulation time 3559823502 ps
CPU time 61.67 seconds
Started Jul 11 05:25:12 PM PDT 24
Finished Jul 11 05:26:22 PM PDT 24
Peak memory 200344 kb
Host smart-fbbc9022-04ba-4823-a4fa-314f088af895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338525025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1338525025
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3102543408
Short name T178
Test name
Test status
Simulation time 11270304 ps
CPU time 0.56 seconds
Started Jul 11 05:25:18 PM PDT 24
Finished Jul 11 05:25:25 PM PDT 24
Peak memory 195068 kb
Host smart-ba7acedd-9568-4d3d-b42d-8aa5681752ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102543408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3102543408
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.2256270889
Short name T197
Test name
Test status
Simulation time 1251455107 ps
CPU time 65.07 seconds
Started Jul 11 05:25:08 PM PDT 24
Finished Jul 11 05:26:22 PM PDT 24
Peak memory 200212 kb
Host smart-96ee61a1-acbc-43df-a4d8-8c45df4f7854
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2256270889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.2256270889
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.884133153
Short name T24
Test name
Test status
Simulation time 1289506630 ps
CPU time 8.67 seconds
Started Jul 11 05:25:02 PM PDT 24
Finished Jul 11 05:25:17 PM PDT 24
Peak memory 200212 kb
Host smart-a02e1f44-e534-4bbb-a2ca-7290e216ebd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884133153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.884133153
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2408640043
Short name T183
Test name
Test status
Simulation time 3779116638 ps
CPU time 787.94 seconds
Started Jul 11 05:25:01 PM PDT 24
Finished Jul 11 05:38:14 PM PDT 24
Peak memory 740788 kb
Host smart-2539dbbf-6460-4de6-bacd-946b1e45cc11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2408640043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2408640043
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1125335908
Short name T282
Test name
Test status
Simulation time 11715125269 ps
CPU time 161.35 seconds
Started Jul 11 05:25:06 PM PDT 24
Finished Jul 11 05:27:55 PM PDT 24
Peak memory 200224 kb
Host smart-23b1fca0-5a0f-48d7-9df6-058242a488b4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125335908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1125335908
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2847816318
Short name T194
Test name
Test status
Simulation time 17845844468 ps
CPU time 140.94 seconds
Started Jul 11 05:25:00 PM PDT 24
Finished Jul 11 05:27:26 PM PDT 24
Peak memory 208576 kb
Host smart-9c53a739-035f-4a8f-b190-8224ea08b574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847816318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2847816318
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.94888871
Short name T144
Test name
Test status
Simulation time 1769187863 ps
CPU time 3.69 seconds
Started Jul 11 05:25:08 PM PDT 24
Finished Jul 11 05:25:20 PM PDT 24
Peak memory 200308 kb
Host smart-ba8c3370-1294-4b40-a555-b8f5ecee3630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94888871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.94888871
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3598581234
Short name T110
Test name
Test status
Simulation time 34462229715 ps
CPU time 426.05 seconds
Started Jul 11 05:25:08 PM PDT 24
Finished Jul 11 05:32:22 PM PDT 24
Peak memory 664332 kb
Host smart-89ea5cb4-08dc-4702-80e8-30f614688586
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598581234 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3598581234
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.4107903148
Short name T155
Test name
Test status
Simulation time 4748880851 ps
CPU time 78.84 seconds
Started Jul 11 05:25:14 PM PDT 24
Finished Jul 11 05:26:42 PM PDT 24
Peak memory 200280 kb
Host smart-bd7fc51d-b707-4613-8299-3fc6ec946587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107903148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.4107903148
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.510158615
Short name T205
Test name
Test status
Simulation time 10784348 ps
CPU time 0.6 seconds
Started Jul 11 05:25:02 PM PDT 24
Finished Jul 11 05:25:09 PM PDT 24
Peak memory 195252 kb
Host smart-61b456af-7656-455d-b5ee-4c475af41c12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510158615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.510158615
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3076304884
Short name T169
Test name
Test status
Simulation time 28658165027 ps
CPU time 62.08 seconds
Started Jul 11 05:25:07 PM PDT 24
Finished Jul 11 05:26:17 PM PDT 24
Peak memory 200348 kb
Host smart-85d4fa2c-a443-415f-a246-a737f80dcfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076304884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3076304884
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3220475014
Short name T502
Test name
Test status
Simulation time 5031373825 ps
CPU time 243.19 seconds
Started Jul 11 05:25:07 PM PDT 24
Finished Jul 11 05:29:18 PM PDT 24
Peak memory 635556 kb
Host smart-3cd53128-0556-42ac-b9c5-b8803e622349
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3220475014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3220475014
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.244479890
Short name T493
Test name
Test status
Simulation time 2229341049 ps
CPU time 126.9 seconds
Started Jul 11 05:25:05 PM PDT 24
Finished Jul 11 05:27:20 PM PDT 24
Peak memory 200396 kb
Host smart-a9ad3cde-e173-4e83-8b8f-e510a57b58b0
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244479890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.244479890
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1768503910
Short name T235
Test name
Test status
Simulation time 182050135 ps
CPU time 10.04 seconds
Started Jul 11 05:25:03 PM PDT 24
Finished Jul 11 05:25:18 PM PDT 24
Peak memory 200312 kb
Host smart-62ec4de2-a9d6-4fc9-bc4f-21bd15cb4ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768503910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1768503910
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1926601834
Short name T210
Test name
Test status
Simulation time 3787819941 ps
CPU time 15.54 seconds
Started Jul 11 05:25:14 PM PDT 24
Finished Jul 11 05:25:38 PM PDT 24
Peak memory 200272 kb
Host smart-56f69509-f2c5-455f-b875-6dacc174c5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926601834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1926601834
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2481362476
Short name T398
Test name
Test status
Simulation time 7404268524 ps
CPU time 129.36 seconds
Started Jul 11 05:25:01 PM PDT 24
Finished Jul 11 05:27:14 PM PDT 24
Peak memory 200324 kb
Host smart-5baf40b3-1c4d-4b13-b57c-50554032392c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481362476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2481362476
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1963641903
Short name T381
Test name
Test status
Simulation time 32427021 ps
CPU time 0.59 seconds
Started Jul 11 05:25:18 PM PDT 24
Finished Jul 11 05:25:26 PM PDT 24
Peak memory 195068 kb
Host smart-43c14019-4093-422a-be9b-5a6bf125e691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963641903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1963641903
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.4118339816
Short name T296
Test name
Test status
Simulation time 286078660 ps
CPU time 16.51 seconds
Started Jul 11 05:25:01 PM PDT 24
Finished Jul 11 05:25:23 PM PDT 24
Peak memory 200200 kb
Host smart-02697302-3047-44f9-821f-11aa94aed1e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4118339816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.4118339816
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.130543864
Short name T77
Test name
Test status
Simulation time 1150856775 ps
CPU time 62.51 seconds
Started Jul 11 05:25:11 PM PDT 24
Finished Jul 11 05:26:22 PM PDT 24
Peak memory 200328 kb
Host smart-44bf9790-7228-4939-8375-8df5147f84f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130543864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.130543864
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.709465867
Short name T508
Test name
Test status
Simulation time 50441072 ps
CPU time 0.81 seconds
Started Jul 11 05:25:04 PM PDT 24
Finished Jul 11 05:25:12 PM PDT 24
Peak memory 198752 kb
Host smart-c8d7e9c3-e73a-470a-a65b-d6dd46e3598c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=709465867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.709465867
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.3198999009
Short name T468
Test name
Test status
Simulation time 465368781 ps
CPU time 6.35 seconds
Started Jul 11 05:25:08 PM PDT 24
Finished Jul 11 05:25:24 PM PDT 24
Peak memory 200308 kb
Host smart-d0d32ada-cafa-4ba3-94cd-9c87e3486e35
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198999009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.3198999009
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2840259281
Short name T203
Test name
Test status
Simulation time 56624380796 ps
CPU time 150.37 seconds
Started Jul 11 05:25:12 PM PDT 24
Finished Jul 11 05:27:51 PM PDT 24
Peak memory 199976 kb
Host smart-820379fb-6c96-44b7-81a2-ffede422eef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840259281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2840259281
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.1330684728
Short name T246
Test name
Test status
Simulation time 2832023962 ps
CPU time 6.12 seconds
Started Jul 11 05:25:03 PM PDT 24
Finished Jul 11 05:25:14 PM PDT 24
Peak memory 200456 kb
Host smart-e9c6b931-f2e9-475b-84e9-e73777a740d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330684728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.1330684728
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3647153868
Short name T519
Test name
Test status
Simulation time 21029325683 ps
CPU time 949.96 seconds
Started Jul 11 05:25:09 PM PDT 24
Finished Jul 11 05:41:08 PM PDT 24
Peak memory 767400 kb
Host smart-88642143-ecfd-44bb-8f59-0b96eced6908
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647153868 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3647153868
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1257449438
Short name T240
Test name
Test status
Simulation time 507980036 ps
CPU time 10.24 seconds
Started Jul 11 05:25:09 PM PDT 24
Finished Jul 11 05:25:28 PM PDT 24
Peak memory 200184 kb
Host smart-cdcea9bc-fddb-49ae-ba65-1e956b2344c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257449438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1257449438
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3138557131
Short name T351
Test name
Test status
Simulation time 20120650 ps
CPU time 0.57 seconds
Started Jul 11 05:25:10 PM PDT 24
Finished Jul 11 05:25:20 PM PDT 24
Peak memory 196124 kb
Host smart-477b3db5-610c-435e-9894-b15e90b27657
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138557131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3138557131
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2477345981
Short name T230
Test name
Test status
Simulation time 3384088548 ps
CPU time 46.78 seconds
Started Jul 11 05:25:08 PM PDT 24
Finished Jul 11 05:26:03 PM PDT 24
Peak memory 200284 kb
Host smart-52cc766c-42de-4db7-b688-bb7b193e3cf8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2477345981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2477345981
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3278410576
Short name T65
Test name
Test status
Simulation time 217214398 ps
CPU time 3.52 seconds
Started Jul 11 05:25:07 PM PDT 24
Finished Jul 11 05:25:18 PM PDT 24
Peak memory 200200 kb
Host smart-61013e06-5b5b-4052-9f70-7c63eaa9a7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278410576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3278410576
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3198487113
Short name T481
Test name
Test status
Simulation time 17626461726 ps
CPU time 776.69 seconds
Started Jul 11 05:25:12 PM PDT 24
Finished Jul 11 05:38:18 PM PDT 24
Peak memory 747744 kb
Host smart-8b74df02-892f-40d4-96e9-4860903444c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3198487113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3198487113
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2729846921
Short name T425
Test name
Test status
Simulation time 34292021 ps
CPU time 0.68 seconds
Started Jul 11 05:25:06 PM PDT 24
Finished Jul 11 05:25:14 PM PDT 24
Peak memory 196680 kb
Host smart-35e777bc-a16d-489a-946a-b9903607771c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729846921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2729846921
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2255001482
Short name T330
Test name
Test status
Simulation time 707466602 ps
CPU time 3.26 seconds
Started Jul 11 05:25:15 PM PDT 24
Finished Jul 11 05:25:26 PM PDT 24
Peak memory 200352 kb
Host smart-96284579-881c-4be4-9062-a0421819a7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255001482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2255001482
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.2987130866
Short name T395
Test name
Test status
Simulation time 1738093028 ps
CPU time 5.9 seconds
Started Jul 11 05:25:17 PM PDT 24
Finished Jul 11 05:25:30 PM PDT 24
Peak memory 200212 kb
Host smart-f25530ab-c0f9-4e26-8abe-13841c5ca9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987130866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.2987130866
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.992542296
Short name T204
Test name
Test status
Simulation time 37323096 ps
CPU time 0.63 seconds
Started Jul 11 05:25:08 PM PDT 24
Finished Jul 11 05:25:17 PM PDT 24
Peak memory 195924 kb
Host smart-4de7e87c-4b0b-466a-8190-bc6358312c97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992542296 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.992542296
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2030650063
Short name T299
Test name
Test status
Simulation time 5499388274 ps
CPU time 48.64 seconds
Started Jul 11 05:25:09 PM PDT 24
Finished Jul 11 05:26:07 PM PDT 24
Peak memory 200280 kb
Host smart-bdb126d9-a797-495b-83f7-86419d3949e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030650063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2030650063
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.4231848240
Short name T256
Test name
Test status
Simulation time 123599099 ps
CPU time 0.6 seconds
Started Jul 11 05:25:07 PM PDT 24
Finished Jul 11 05:25:16 PM PDT 24
Peak memory 196768 kb
Host smart-4fe60055-a003-4cd6-a0a3-1e2a76ee9f20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231848240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.4231848240
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3558051872
Short name T38
Test name
Test status
Simulation time 2145965128 ps
CPU time 62.02 seconds
Started Jul 11 05:25:09 PM PDT 24
Finished Jul 11 05:26:20 PM PDT 24
Peak memory 200248 kb
Host smart-85527497-36ce-44d6-b7ff-f4d2358d8080
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3558051872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3558051872
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1760028754
Short name T390
Test name
Test status
Simulation time 127800910 ps
CPU time 6.66 seconds
Started Jul 11 05:25:14 PM PDT 24
Finished Jul 11 05:25:29 PM PDT 24
Peak memory 200284 kb
Host smart-68b71469-1329-4372-b650-9946c59b3a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760028754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1760028754
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.3022460236
Short name T214
Test name
Test status
Simulation time 403482614 ps
CPU time 39.24 seconds
Started Jul 11 05:25:18 PM PDT 24
Finished Jul 11 05:26:04 PM PDT 24
Peak memory 253680 kb
Host smart-1c59ed1d-2407-44a3-b10d-c4756020b34b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3022460236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.3022460236
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.1169890178
Short name T337
Test name
Test status
Simulation time 14900310312 ps
CPU time 89.98 seconds
Started Jul 11 05:25:11 PM PDT 24
Finished Jul 11 05:26:49 PM PDT 24
Peak memory 200368 kb
Host smart-91d244c1-56be-4b4f-bae1-f28610defcb8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169890178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.1169890178
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1836477689
Short name T201
Test name
Test status
Simulation time 44493407969 ps
CPU time 111.28 seconds
Started Jul 11 05:25:18 PM PDT 24
Finished Jul 11 05:27:16 PM PDT 24
Peak memory 200272 kb
Host smart-778fc771-82c4-4a31-b8bf-7ae16b475897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836477689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1836477689
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.750643727
Short name T368
Test name
Test status
Simulation time 766338594 ps
CPU time 8.63 seconds
Started Jul 11 05:25:10 PM PDT 24
Finished Jul 11 05:25:28 PM PDT 24
Peak memory 200308 kb
Host smart-771c1e76-09e6-40bd-a7b7-e8fa324bb43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750643727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.750643727
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.3848683260
Short name T71
Test name
Test status
Simulation time 169101079965 ps
CPU time 1089.64 seconds
Started Jul 11 05:25:10 PM PDT 24
Finished Jul 11 05:43:28 PM PDT 24
Peak memory 216636 kb
Host smart-da1e1369-921a-4cf6-ac58-51cc284c38d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848683260 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.3848683260
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.4132784825
Short name T373
Test name
Test status
Simulation time 4876845583 ps
CPU time 81.72 seconds
Started Jul 11 05:25:13 PM PDT 24
Finished Jul 11 05:26:44 PM PDT 24
Peak memory 200320 kb
Host smart-3e9d70a1-6535-49fe-ac91-31d76e890668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132784825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.4132784825
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.299438315
Short name T402
Test name
Test status
Simulation time 45155037 ps
CPU time 0.62 seconds
Started Jul 11 05:24:46 PM PDT 24
Finished Jul 11 05:24:50 PM PDT 24
Peak memory 196180 kb
Host smart-3097c535-203f-47d1-a1b1-fefb108dfe95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299438315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.299438315
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.2909959145
Short name T5
Test name
Test status
Simulation time 4491505244 ps
CPU time 32.14 seconds
Started Jul 11 05:24:32 PM PDT 24
Finished Jul 11 05:25:06 PM PDT 24
Peak memory 200248 kb
Host smart-e63c0ca9-de1f-4fe8-bfdc-058b431a628b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2909959145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2909959145
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1678597139
Short name T174
Test name
Test status
Simulation time 16599256621 ps
CPU time 56.08 seconds
Started Jul 11 05:24:38 PM PDT 24
Finished Jul 11 05:25:37 PM PDT 24
Peak memory 200408 kb
Host smart-5d6b875f-d463-4b17-80a2-11b0ac2f2adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678597139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1678597139
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3337907606
Short name T4
Test name
Test status
Simulation time 5458833413 ps
CPU time 978.52 seconds
Started Jul 11 05:24:35 PM PDT 24
Finished Jul 11 05:40:57 PM PDT 24
Peak memory 742280 kb
Host smart-4fd0b080-da4a-465f-827b-a932adfeedb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3337907606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3337907606
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3652055205
Short name T458
Test name
Test status
Simulation time 14953566665 ps
CPU time 170.71 seconds
Started Jul 11 05:24:36 PM PDT 24
Finished Jul 11 05:27:30 PM PDT 24
Peak memory 200348 kb
Host smart-1d52e007-18ca-4e83-9bce-1a40fce64258
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652055205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3652055205
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3054043690
Short name T67
Test name
Test status
Simulation time 31393831 ps
CPU time 0.9 seconds
Started Jul 11 05:24:53 PM PDT 24
Finished Jul 11 05:24:57 PM PDT 24
Peak memory 200100 kb
Host smart-2621e1c4-3a92-49d1-b868-1cb36b790cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054043690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3054043690
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.4224564154
Short name T46
Test name
Test status
Simulation time 94242462 ps
CPU time 1.07 seconds
Started Jul 11 05:24:42 PM PDT 24
Finished Jul 11 05:24:46 PM PDT 24
Peak memory 219456 kb
Host smart-d7944c52-3466-4964-a5ab-db82d46206d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224564154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.4224564154
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2229584692
Short name T310
Test name
Test status
Simulation time 511992679 ps
CPU time 3.63 seconds
Started Jul 11 05:24:37 PM PDT 24
Finished Jul 11 05:24:44 PM PDT 24
Peak memory 200288 kb
Host smart-001e07b2-d537-478b-a68c-f3d6c7c92f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229584692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2229584692
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3061374680
Short name T281
Test name
Test status
Simulation time 10784162524 ps
CPU time 191.03 seconds
Started Jul 11 05:24:35 PM PDT 24
Finished Jul 11 05:27:49 PM PDT 24
Peak memory 208560 kb
Host smart-6f6a90a0-d261-46ae-9550-05a162eb4ad1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061374680 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3061374680
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.3084874945
Short name T134
Test name
Test status
Simulation time 19063382348 ps
CPU time 65.15 seconds
Started Jul 11 05:24:58 PM PDT 24
Finished Jul 11 05:26:07 PM PDT 24
Peak memory 200356 kb
Host smart-7ebfa7cc-8f4c-47d3-aea8-28ebf6a5cf61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3084874945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.3084874945
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.1010876946
Short name T410
Test name
Test status
Simulation time 6226319292 ps
CPU time 92.8 seconds
Started Jul 11 05:24:37 PM PDT 24
Finished Jul 11 05:26:13 PM PDT 24
Peak memory 200396 kb
Host smart-96c10911-24d1-43c8-82fc-47a20568bd19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1010876946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.1010876946
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.4273100111
Short name T492
Test name
Test status
Simulation time 28109618385 ps
CPU time 78.17 seconds
Started Jul 11 05:24:58 PM PDT 24
Finished Jul 11 05:26:20 PM PDT 24
Peak memory 200356 kb
Host smart-dfd0f81e-fc77-419d-9650-982f258fcaf4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4273100111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.4273100111
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.2132151994
Short name T438
Test name
Test status
Simulation time 59344367769 ps
CPU time 713.86 seconds
Started Jul 11 05:24:58 PM PDT 24
Finished Jul 11 05:36:56 PM PDT 24
Peak memory 200352 kb
Host smart-b5a479ce-c15e-47d4-8671-e3de370b2209
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2132151994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.2132151994
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.1808454932
Short name T195
Test name
Test status
Simulation time 43687667194 ps
CPU time 2318.99 seconds
Started Jul 11 05:24:34 PM PDT 24
Finished Jul 11 06:03:17 PM PDT 24
Peak memory 215936 kb
Host smart-68c68517-53e2-4737-af6d-625303092180
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1808454932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.1808454932
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.1360064463
Short name T333
Test name
Test status
Simulation time 269363528801 ps
CPU time 2304.94 seconds
Started Jul 11 05:24:50 PM PDT 24
Finished Jul 11 06:03:17 PM PDT 24
Peak memory 216564 kb
Host smart-b2189082-efa1-4b3e-abd9-5005928f8647
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1360064463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1360064463
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1045525755
Short name T31
Test name
Test status
Simulation time 18348392000 ps
CPU time 117.92 seconds
Started Jul 11 05:24:36 PM PDT 24
Finished Jul 11 05:26:38 PM PDT 24
Peak memory 200412 kb
Host smart-c90ac777-5f4a-4787-bc26-69c5ba2c456e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045525755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1045525755
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2984573643
Short name T321
Test name
Test status
Simulation time 46857235 ps
CPU time 0.61 seconds
Started Jul 11 05:26:21 PM PDT 24
Finished Jul 11 05:26:25 PM PDT 24
Peak memory 196192 kb
Host smart-5bc3ad40-f854-4e2f-9836-75924c1d0a03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984573643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2984573643
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2249424867
Short name T451
Test name
Test status
Simulation time 642399684 ps
CPU time 38.4 seconds
Started Jul 11 05:25:10 PM PDT 24
Finished Jul 11 05:25:58 PM PDT 24
Peak memory 200152 kb
Host smart-dbf16cdd-36ce-4b27-b934-bcf48f669e94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2249424867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2249424867
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3131631252
Short name T35
Test name
Test status
Simulation time 4276152130 ps
CPU time 39.6 seconds
Started Jul 11 05:25:10 PM PDT 24
Finished Jul 11 05:25:59 PM PDT 24
Peak memory 200288 kb
Host smart-cde2cd00-8e81-4d0b-8691-90de0835e0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131631252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3131631252
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3004701806
Short name T315
Test name
Test status
Simulation time 15248566526 ps
CPU time 1262.41 seconds
Started Jul 11 05:25:10 PM PDT 24
Finished Jul 11 05:46:22 PM PDT 24
Peak memory 752288 kb
Host smart-3460b498-997a-406b-880a-1978361cc4c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3004701806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3004701806
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3014962793
Short name T187
Test name
Test status
Simulation time 33600770914 ps
CPU time 107.11 seconds
Started Jul 11 05:25:17 PM PDT 24
Finished Jul 11 05:27:11 PM PDT 24
Peak memory 200248 kb
Host smart-31a181f9-703d-46e4-8ece-3ff4fe92dea4
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014962793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3014962793
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.4161396031
Short name T326
Test name
Test status
Simulation time 28900894814 ps
CPU time 112.8 seconds
Started Jul 11 05:25:10 PM PDT 24
Finished Jul 11 05:27:11 PM PDT 24
Peak memory 200476 kb
Host smart-039dedb5-9d1f-4596-86bd-89330680f25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161396031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.4161396031
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.4013226762
Short name T317
Test name
Test status
Simulation time 2030348294 ps
CPU time 13.52 seconds
Started Jul 11 05:25:10 PM PDT 24
Finished Jul 11 05:25:32 PM PDT 24
Peak memory 200212 kb
Host smart-a3f97fe0-23f7-481e-bad9-de2640cb3da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013226762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.4013226762
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.694453701
Short name T498
Test name
Test status
Simulation time 82328512007 ps
CPU time 1647.5 seconds
Started Jul 11 05:25:09 PM PDT 24
Finished Jul 11 05:52:45 PM PDT 24
Peak memory 700224 kb
Host smart-abe3b536-f1d2-4983-9b46-002ff3f2bd22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694453701 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.694453701
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2351056129
Short name T441
Test name
Test status
Simulation time 3128877856 ps
CPU time 38.33 seconds
Started Jul 11 05:25:18 PM PDT 24
Finished Jul 11 05:26:03 PM PDT 24
Peak memory 200312 kb
Host smart-f172a29a-159a-46f6-b863-6bb78508de1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351056129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2351056129
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2765904511
Short name T494
Test name
Test status
Simulation time 43376151 ps
CPU time 0.6 seconds
Started Jul 11 05:25:18 PM PDT 24
Finished Jul 11 05:25:25 PM PDT 24
Peak memory 196212 kb
Host smart-2994dd89-50e9-432b-a667-316bbcd72b6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765904511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2765904511
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.803298299
Short name T367
Test name
Test status
Simulation time 424627803 ps
CPU time 12.61 seconds
Started Jul 11 05:25:25 PM PDT 24
Finished Jul 11 05:25:43 PM PDT 24
Peak memory 200220 kb
Host smart-ffa09dd5-944b-4903-8b26-83cc6297d34f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=803298299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.803298299
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2173804731
Short name T524
Test name
Test status
Simulation time 624299122 ps
CPU time 16.83 seconds
Started Jul 11 05:25:13 PM PDT 24
Finished Jul 11 05:25:38 PM PDT 24
Peak memory 200352 kb
Host smart-dff5c97f-b518-4b32-ba3c-1c079288e22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173804731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2173804731
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.831162495
Short name T400
Test name
Test status
Simulation time 13071995815 ps
CPU time 517.98 seconds
Started Jul 11 05:25:13 PM PDT 24
Finished Jul 11 05:34:01 PM PDT 24
Peak memory 684204 kb
Host smart-eb6b6df1-5ee5-4607-9193-f918d727f885
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=831162495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.831162495
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2553300173
Short name T189
Test name
Test status
Simulation time 33096819196 ps
CPU time 109.15 seconds
Started Jul 11 05:25:25 PM PDT 24
Finished Jul 11 05:27:19 PM PDT 24
Peak memory 200260 kb
Host smart-579a8f0c-c7bf-4ba8-b7bb-a7f6e83905ba
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553300173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2553300173
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.3874320498
Short name T141
Test name
Test status
Simulation time 21039402623 ps
CPU time 88.96 seconds
Started Jul 11 05:25:13 PM PDT 24
Finished Jul 11 05:26:51 PM PDT 24
Peak memory 216544 kb
Host smart-38a79f05-92b1-4b23-8f3f-1d390af93d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874320498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3874320498
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2681792761
Short name T182
Test name
Test status
Simulation time 624046652 ps
CPU time 8.11 seconds
Started Jul 11 05:25:13 PM PDT 24
Finished Jul 11 05:25:30 PM PDT 24
Peak memory 200260 kb
Host smart-bf8a7af9-9272-4157-ab4a-46274fac4aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681792761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2681792761
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1663108342
Short name T340
Test name
Test status
Simulation time 1053136505 ps
CPU time 8.53 seconds
Started Jul 11 05:25:17 PM PDT 24
Finished Jul 11 05:25:32 PM PDT 24
Peak memory 200348 kb
Host smart-04dd8130-5e4a-45e1-bb1c-c7ded629fa56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663108342 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1663108342
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.368057891
Short name T237
Test name
Test status
Simulation time 1880612107 ps
CPU time 100.29 seconds
Started Jul 11 05:25:12 PM PDT 24
Finished Jul 11 05:27:01 PM PDT 24
Peak memory 200280 kb
Host smart-384952b7-915a-43f1-9907-603cdb378055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368057891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.368057891
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3978986699
Short name T270
Test name
Test status
Simulation time 20945148 ps
CPU time 0.6 seconds
Started Jul 11 05:25:12 PM PDT 24
Finished Jul 11 05:25:21 PM PDT 24
Peak memory 195068 kb
Host smart-af7e3fa1-6871-4ecc-bcb7-01ebb1026e3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978986699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3978986699
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.379618909
Short name T156
Test name
Test status
Simulation time 193692810 ps
CPU time 5.54 seconds
Started Jul 11 05:25:25 PM PDT 24
Finished Jul 11 05:25:36 PM PDT 24
Peak memory 200296 kb
Host smart-3ee8aa52-fb49-453c-a6ff-32242d272084
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=379618909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.379618909
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.4089825291
Short name T424
Test name
Test status
Simulation time 57601023 ps
CPU time 2.28 seconds
Started Jul 11 05:25:15 PM PDT 24
Finished Jul 11 05:25:25 PM PDT 24
Peak memory 200352 kb
Host smart-accb477d-75f3-4251-9f66-2f44a58b9fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089825291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.4089825291
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.648815875
Short name T193
Test name
Test status
Simulation time 5422755310 ps
CPU time 1001.19 seconds
Started Jul 11 05:25:15 PM PDT 24
Finished Jul 11 05:42:04 PM PDT 24
Peak memory 762928 kb
Host smart-11efe6fc-205e-46b9-b9d7-668dc20c6668
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=648815875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.648815875
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.1854188913
Short name T74
Test name
Test status
Simulation time 13210918695 ps
CPU time 226.26 seconds
Started Jul 11 05:25:13 PM PDT 24
Finished Jul 11 05:29:08 PM PDT 24
Peak memory 200336 kb
Host smart-ba83faec-6299-4422-b4b3-a4aa5b7c801c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854188913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1854188913
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1766378485
Short name T356
Test name
Test status
Simulation time 25115231578 ps
CPU time 214.62 seconds
Started Jul 11 05:25:11 PM PDT 24
Finished Jul 11 05:28:55 PM PDT 24
Peak memory 200272 kb
Host smart-d5f5da33-78ce-4b07-8e88-47d53c69cd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766378485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1766378485
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1727592397
Short name T396
Test name
Test status
Simulation time 1226702034 ps
CPU time 13.72 seconds
Started Jul 11 05:25:18 PM PDT 24
Finished Jul 11 05:25:38 PM PDT 24
Peak memory 200316 kb
Host smart-0c3601fe-6b42-49bf-8962-dd177618e2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727592397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1727592397
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1230500372
Short name T126
Test name
Test status
Simulation time 9358537713 ps
CPU time 518.31 seconds
Started Jul 11 05:25:11 PM PDT 24
Finished Jul 11 05:33:58 PM PDT 24
Peak memory 200260 kb
Host smart-61b628a9-5643-444d-9c3d-fb8c68ddeee2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230500372 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1230500372
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.1931510302
Short name T184
Test name
Test status
Simulation time 8579947665 ps
CPU time 61.95 seconds
Started Jul 11 05:25:11 PM PDT 24
Finished Jul 11 05:26:22 PM PDT 24
Peak memory 200412 kb
Host smart-5e6617fd-f7cf-49e7-8457-f97eeeb52eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931510302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.1931510302
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3236202816
Short name T408
Test name
Test status
Simulation time 46918681 ps
CPU time 0.59 seconds
Started Jul 11 05:25:29 PM PDT 24
Finished Jul 11 05:25:34 PM PDT 24
Peak memory 196168 kb
Host smart-b8a53429-9db3-4119-b887-e7da23c2999c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236202816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3236202816
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1247196853
Short name T357
Test name
Test status
Simulation time 5174901615 ps
CPU time 72.18 seconds
Started Jul 11 05:25:19 PM PDT 24
Finished Jul 11 05:26:38 PM PDT 24
Peak memory 200364 kb
Host smart-b72e05a7-67ca-4021-8fa9-1caa019cbfb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1247196853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1247196853
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1119178241
Short name T383
Test name
Test status
Simulation time 1363760771 ps
CPU time 24.22 seconds
Started Jul 11 05:25:11 PM PDT 24
Finished Jul 11 05:25:44 PM PDT 24
Peak memory 200236 kb
Host smart-862ee473-4c8e-4c12-a1ff-364ec188dee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119178241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1119178241
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.968493745
Short name T474
Test name
Test status
Simulation time 1087381747 ps
CPU time 172.14 seconds
Started Jul 11 05:25:13 PM PDT 24
Finished Jul 11 05:28:14 PM PDT 24
Peak memory 610408 kb
Host smart-9eb23796-b24f-423e-886d-26050ee9a4f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=968493745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.968493745
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2390435293
Short name T55
Test name
Test status
Simulation time 1941159645 ps
CPU time 25.66 seconds
Started Jul 11 05:25:17 PM PDT 24
Finished Jul 11 05:25:50 PM PDT 24
Peak memory 200204 kb
Host smart-30cf7607-d433-443f-8b1c-8e97bb5e31a8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390435293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2390435293
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.680630103
Short name T433
Test name
Test status
Simulation time 4079533857 ps
CPU time 126.87 seconds
Started Jul 11 05:25:15 PM PDT 24
Finished Jul 11 05:27:30 PM PDT 24
Peak memory 208584 kb
Host smart-7c9c374e-139b-47ba-8b44-76df3c72ef8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680630103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.680630103
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1941124288
Short name T243
Test name
Test status
Simulation time 2036752375 ps
CPU time 8.35 seconds
Started Jul 11 05:25:18 PM PDT 24
Finished Jul 11 05:25:33 PM PDT 24
Peak memory 200316 kb
Host smart-31641d65-e568-4301-8d38-487df3b1aa08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941124288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1941124288
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1767238885
Short name T475
Test name
Test status
Simulation time 56526212520 ps
CPU time 205.67 seconds
Started Jul 11 05:25:28 PM PDT 24
Finished Jul 11 05:28:59 PM PDT 24
Peak memory 208544 kb
Host smart-ba01206f-0d9c-47a1-8ed2-c08419d052aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767238885 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1767238885
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3195501909
Short name T465
Test name
Test status
Simulation time 2286053074 ps
CPU time 74.86 seconds
Started Jul 11 05:25:20 PM PDT 24
Finished Jul 11 05:26:41 PM PDT 24
Peak memory 200320 kb
Host smart-b370ea87-d698-4508-a97e-b60739ccb52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195501909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3195501909
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.1733302106
Short name T520
Test name
Test status
Simulation time 11040283 ps
CPU time 0.57 seconds
Started Jul 11 05:25:19 PM PDT 24
Finished Jul 11 05:25:26 PM PDT 24
Peak memory 195856 kb
Host smart-ed971636-8990-443a-b189-6a0fe3e4088c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733302106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1733302106
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2320467762
Short name T40
Test name
Test status
Simulation time 8356926433 ps
CPU time 68.24 seconds
Started Jul 11 05:25:27 PM PDT 24
Finished Jul 11 05:26:40 PM PDT 24
Peak memory 200360 kb
Host smart-ba1a2be8-a282-444f-85f8-7f3f424a0be1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2320467762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2320467762
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.57357749
Short name T123
Test name
Test status
Simulation time 1869174858 ps
CPU time 16.66 seconds
Started Jul 11 05:25:19 PM PDT 24
Finished Jul 11 05:25:42 PM PDT 24
Peak memory 200324 kb
Host smart-92ccaf8c-edde-44fe-bc5f-b53fa71d21d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57357749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.57357749
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3490347773
Short name T450
Test name
Test status
Simulation time 21205628597 ps
CPU time 842.97 seconds
Started Jul 11 05:25:20 PM PDT 24
Finished Jul 11 05:39:29 PM PDT 24
Peak memory 716024 kb
Host smart-243b22cc-0476-4e91-9926-a788a6870abb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3490347773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3490347773
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.215631737
Short name T140
Test name
Test status
Simulation time 819969082 ps
CPU time 26.98 seconds
Started Jul 11 05:25:20 PM PDT 24
Finished Jul 11 05:25:53 PM PDT 24
Peak memory 200200 kb
Host smart-9ff5e0bc-7d90-4bf4-91f4-758992acd5f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215631737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.215631737
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.4293433590
Short name T30
Test name
Test status
Simulation time 17847838474 ps
CPU time 182.39 seconds
Started Jul 11 05:25:20 PM PDT 24
Finished Jul 11 05:28:29 PM PDT 24
Peak memory 200384 kb
Host smart-db57c768-7d7d-4346-8c60-9cf9e0f90e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293433590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.4293433590
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1441581074
Short name T121
Test name
Test status
Simulation time 1018294110 ps
CPU time 11.42 seconds
Started Jul 11 05:25:23 PM PDT 24
Finished Jul 11 05:25:39 PM PDT 24
Peak memory 200260 kb
Host smart-e4f7aa02-080d-463f-8166-d693765b8c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441581074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1441581074
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.4237573780
Short name T209
Test name
Test status
Simulation time 90760613412 ps
CPU time 764.47 seconds
Started Jul 11 05:25:27 PM PDT 24
Finished Jul 11 05:38:16 PM PDT 24
Peak memory 200272 kb
Host smart-b1fd0844-c92c-41c4-b78c-ace2b84dc772
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237573780 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.4237573780
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3154983347
Short name T350
Test name
Test status
Simulation time 14721446539 ps
CPU time 136.99 seconds
Started Jul 11 05:25:18 PM PDT 24
Finished Jul 11 05:27:42 PM PDT 24
Peak memory 200376 kb
Host smart-b6de8fd5-24ac-482c-a6b5-cf8a82e90e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154983347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3154983347
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2751602848
Short name T521
Test name
Test status
Simulation time 35308234 ps
CPU time 0.59 seconds
Started Jul 11 05:25:25 PM PDT 24
Finished Jul 11 05:25:31 PM PDT 24
Peak memory 196196 kb
Host smart-c7527cc1-5df1-4345-b9f0-c7483909ec2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751602848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2751602848
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1048163143
Short name T177
Test name
Test status
Simulation time 10088796370 ps
CPU time 47.73 seconds
Started Jul 11 05:25:22 PM PDT 24
Finished Jul 11 05:26:15 PM PDT 24
Peak memory 200360 kb
Host smart-17af2fa3-21af-4779-a4e9-6a03b3e46c20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1048163143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1048163143
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3033581415
Short name T496
Test name
Test status
Simulation time 2656148317 ps
CPU time 35.65 seconds
Started Jul 11 05:25:25 PM PDT 24
Finished Jul 11 05:26:06 PM PDT 24
Peak memory 200316 kb
Host smart-20ed8395-16c6-4271-bbc9-e0a6059a087a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033581415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3033581415
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1314364058
Short name T34
Test name
Test status
Simulation time 12218518147 ps
CPU time 375.13 seconds
Started Jul 11 05:25:24 PM PDT 24
Finished Jul 11 05:31:44 PM PDT 24
Peak memory 649656 kb
Host smart-aff650f5-1d70-4a8b-9521-570c669c7f1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1314364058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1314364058
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.768093997
Short name T442
Test name
Test status
Simulation time 1063758500 ps
CPU time 56.1 seconds
Started Jul 11 05:25:25 PM PDT 24
Finished Jul 11 05:26:25 PM PDT 24
Peak memory 200320 kb
Host smart-0e81868a-e967-408b-973e-66a5d10d4f8f
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768093997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.768093997
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3578647222
Short name T501
Test name
Test status
Simulation time 827565029 ps
CPU time 45.25 seconds
Started Jul 11 05:25:22 PM PDT 24
Finished Jul 11 05:26:13 PM PDT 24
Peak memory 200224 kb
Host smart-08436698-adab-429b-b9ad-e11a90c474f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578647222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3578647222
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3431003153
Short name T369
Test name
Test status
Simulation time 615025002 ps
CPU time 13.95 seconds
Started Jul 11 05:25:29 PM PDT 24
Finished Jul 11 05:25:48 PM PDT 24
Peak memory 200296 kb
Host smart-a8480aeb-ac63-44fe-a1ac-2291d6cedf35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431003153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3431003153
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.338796534
Short name T272
Test name
Test status
Simulation time 15450134110 ps
CPU time 43.55 seconds
Started Jul 11 05:25:26 PM PDT 24
Finished Jul 11 05:26:14 PM PDT 24
Peak memory 200240 kb
Host smart-bba472d9-d826-4818-b061-87d424de10fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338796534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.338796534
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.700501535
Short name T456
Test name
Test status
Simulation time 12154166 ps
CPU time 0.58 seconds
Started Jul 11 05:25:28 PM PDT 24
Finished Jul 11 05:25:33 PM PDT 24
Peak memory 196788 kb
Host smart-64ba3b32-8c54-4e6f-a3a1-19632f51d3d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700501535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.700501535
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3186566719
Short name T487
Test name
Test status
Simulation time 407004906 ps
CPU time 23.74 seconds
Started Jul 11 05:25:27 PM PDT 24
Finished Jul 11 05:25:55 PM PDT 24
Peak memory 200256 kb
Host smart-03be3c1b-bf92-4e49-9887-c962cb5e1ed3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3186566719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3186566719
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.957877140
Short name T275
Test name
Test status
Simulation time 673443465 ps
CPU time 35.31 seconds
Started Jul 11 05:25:26 PM PDT 24
Finished Jul 11 05:26:06 PM PDT 24
Peak memory 200324 kb
Host smart-5394dc22-86fb-47d7-8afd-258b3e2759fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957877140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.957877140
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.4103210794
Short name T271
Test name
Test status
Simulation time 2537066255 ps
CPU time 397.89 seconds
Started Jul 11 05:25:26 PM PDT 24
Finished Jul 11 05:32:08 PM PDT 24
Peak memory 617644 kb
Host smart-800c3d62-29a5-4f13-aaf7-0cf82626bf9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4103210794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.4103210794
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2086736596
Short name T162
Test name
Test status
Simulation time 20647478022 ps
CPU time 251.9 seconds
Started Jul 11 05:25:26 PM PDT 24
Finished Jul 11 05:29:42 PM PDT 24
Peak memory 200340 kb
Host smart-e62fff5d-d010-43d2-86ae-35c86953f5c1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086736596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2086736596
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2099131772
Short name T312
Test name
Test status
Simulation time 21802331252 ps
CPU time 148.31 seconds
Started Jul 11 05:25:29 PM PDT 24
Finished Jul 11 05:28:03 PM PDT 24
Peak memory 200352 kb
Host smart-0466302d-bab3-48cc-ad5d-dd169aa41f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099131772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2099131772
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3823325193
Short name T298
Test name
Test status
Simulation time 2121250021 ps
CPU time 5.44 seconds
Started Jul 11 05:25:29 PM PDT 24
Finished Jul 11 05:25:40 PM PDT 24
Peak memory 200520 kb
Host smart-ef93fb57-77aa-4ce2-bc5d-72f4cda327c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823325193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3823325193
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3306489674
Short name T499
Test name
Test status
Simulation time 309390425887 ps
CPU time 2042.43 seconds
Started Jul 11 05:25:27 PM PDT 24
Finished Jul 11 05:59:34 PM PDT 24
Peak memory 764072 kb
Host smart-5ec11c9c-a981-4ac4-8261-485ac108753b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306489674 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3306489674
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.4270858429
Short name T108
Test name
Test status
Simulation time 7977625610 ps
CPU time 98.31 seconds
Started Jul 11 05:25:26 PM PDT 24
Finished Jul 11 05:27:09 PM PDT 24
Peak memory 200320 kb
Host smart-a865df27-f5d7-46a9-ac3c-c8fbe60fa7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270858429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.4270858429
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1874313664
Short name T163
Test name
Test status
Simulation time 14427843 ps
CPU time 0.63 seconds
Started Jul 11 05:25:25 PM PDT 24
Finished Jul 11 05:25:31 PM PDT 24
Peak memory 196824 kb
Host smart-58299435-0f42-44cc-aaa5-f4ef2d76740f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874313664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1874313664
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.181882346
Short name T412
Test name
Test status
Simulation time 763305533 ps
CPU time 45.07 seconds
Started Jul 11 05:25:25 PM PDT 24
Finished Jul 11 05:26:15 PM PDT 24
Peak memory 200192 kb
Host smart-c5790e3d-ed76-423f-93ba-351004ce0b8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=181882346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.181882346
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3932137248
Short name T291
Test name
Test status
Simulation time 1569206729 ps
CPU time 44.2 seconds
Started Jul 11 05:25:26 PM PDT 24
Finished Jul 11 05:26:15 PM PDT 24
Peak memory 200344 kb
Host smart-5fa61d3c-fa45-4e20-88c2-1f0c5dda76ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932137248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3932137248
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.188671558
Short name T292
Test name
Test status
Simulation time 11239897996 ps
CPU time 880.45 seconds
Started Jul 11 05:25:25 PM PDT 24
Finished Jul 11 05:40:11 PM PDT 24
Peak memory 716300 kb
Host smart-06796966-4cfe-48ac-a1f1-85f5ff6891e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=188671558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.188671558
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3491085923
Short name T146
Test name
Test status
Simulation time 14061329594 ps
CPU time 183.25 seconds
Started Jul 11 05:25:26 PM PDT 24
Finished Jul 11 05:28:34 PM PDT 24
Peak memory 200248 kb
Host smart-fa4d632c-fe6f-4ca0-bd4d-f677ac245877
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491085923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3491085923
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.4236098163
Short name T219
Test name
Test status
Simulation time 6598139275 ps
CPU time 47.43 seconds
Started Jul 11 05:25:28 PM PDT 24
Finished Jul 11 05:26:21 PM PDT 24
Peak memory 200372 kb
Host smart-8d67bd1d-678d-4189-a5d4-c48c4e48100f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236098163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.4236098163
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.3336343393
Short name T457
Test name
Test status
Simulation time 2953099695 ps
CPU time 11.35 seconds
Started Jul 11 05:25:26 PM PDT 24
Finished Jul 11 05:25:43 PM PDT 24
Peak memory 200252 kb
Host smart-80df3c53-353f-4553-9d5f-a9e5ee74f0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336343393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.3336343393
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.579858262
Short name T72
Test name
Test status
Simulation time 45261711117 ps
CPU time 289.55 seconds
Started Jul 11 05:25:29 PM PDT 24
Finished Jul 11 05:30:23 PM PDT 24
Peak memory 233692 kb
Host smart-39c98768-130c-48db-ae97-6fd5156605ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579858262 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.579858262
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3951108671
Short name T455
Test name
Test status
Simulation time 481091166 ps
CPU time 14.03 seconds
Started Jul 11 05:25:25 PM PDT 24
Finished Jul 11 05:25:44 PM PDT 24
Peak memory 200292 kb
Host smart-c26ce241-c6b4-4c8b-a899-cce678dbbeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951108671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3951108671
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.467753021
Short name T488
Test name
Test status
Simulation time 13776750 ps
CPU time 0.61 seconds
Started Jul 11 05:25:31 PM PDT 24
Finished Jul 11 05:25:36 PM PDT 24
Peak memory 196900 kb
Host smart-7dc4fd33-d8bb-44c2-b4e5-4990f370a7cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467753021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.467753021
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.948405119
Short name T21
Test name
Test status
Simulation time 1391149565 ps
CPU time 52.06 seconds
Started Jul 11 05:25:28 PM PDT 24
Finished Jul 11 05:26:25 PM PDT 24
Peak memory 200236 kb
Host smart-6a820790-7c81-47e7-a500-6f801a85cc98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=948405119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.948405119
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1616894421
Short name T389
Test name
Test status
Simulation time 11399234769 ps
CPU time 19.59 seconds
Started Jul 11 05:25:27 PM PDT 24
Finished Jul 11 05:25:51 PM PDT 24
Peak memory 200376 kb
Host smart-dcdeea27-7e97-46ae-aada-da541f20c5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616894421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1616894421
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3746745973
Short name T313
Test name
Test status
Simulation time 3091741086 ps
CPU time 160.8 seconds
Started Jul 11 05:25:26 PM PDT 24
Finished Jul 11 05:28:11 PM PDT 24
Peak memory 475560 kb
Host smart-fdbc0068-d524-45d4-aec1-942d00064a7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3746745973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3746745973
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.353900910
Short name T485
Test name
Test status
Simulation time 2544949020 ps
CPU time 66.45 seconds
Started Jul 11 05:25:28 PM PDT 24
Finished Jul 11 05:26:39 PM PDT 24
Peak memory 200304 kb
Host smart-cd17bcbc-1865-4968-a627-d9ee0bd0249d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353900910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.353900910
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2115919620
Short name T41
Test name
Test status
Simulation time 9245938197 ps
CPU time 82.27 seconds
Started Jul 11 05:25:29 PM PDT 24
Finished Jul 11 05:26:57 PM PDT 24
Peak memory 200388 kb
Host smart-f5f6e2a5-c92a-4131-85e7-ce1b969d6731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115919620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2115919620
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1883023443
Short name T33
Test name
Test status
Simulation time 654836780 ps
CPU time 6.88 seconds
Started Jul 11 05:25:28 PM PDT 24
Finished Jul 11 05:25:40 PM PDT 24
Peak memory 200212 kb
Host smart-cc72c430-2c01-438f-81e1-c036d47df818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883023443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1883023443
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3426504209
Short name T435
Test name
Test status
Simulation time 9816385715 ps
CPU time 1003.2 seconds
Started Jul 11 05:25:32 PM PDT 24
Finished Jul 11 05:42:19 PM PDT 24
Peak memory 686428 kb
Host smart-a2413a73-2910-452f-93e4-d8f5609633be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426504209 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3426504209
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.4081923575
Short name T128
Test name
Test status
Simulation time 5045030393 ps
CPU time 80.24 seconds
Started Jul 11 05:25:25 PM PDT 24
Finished Jul 11 05:26:50 PM PDT 24
Peak memory 200308 kb
Host smart-5b07f3cc-414b-4a09-95ea-1cc13bb68f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081923575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.4081923575
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.128007921
Short name T302
Test name
Test status
Simulation time 39886042 ps
CPU time 0.6 seconds
Started Jul 11 05:25:33 PM PDT 24
Finished Jul 11 05:25:37 PM PDT 24
Peak memory 196176 kb
Host smart-ed0e0f20-1d94-4088-aadb-0005ac21d28d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128007921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.128007921
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3909786189
Short name T297
Test name
Test status
Simulation time 86506457 ps
CPU time 5.11 seconds
Started Jul 11 05:25:33 PM PDT 24
Finished Jul 11 05:25:42 PM PDT 24
Peak memory 200220 kb
Host smart-aac4ce93-7a8d-4e97-8be4-6f81c44fcc85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3909786189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3909786189
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2891257929
Short name T436
Test name
Test status
Simulation time 10606643991 ps
CPU time 52.31 seconds
Started Jul 11 05:25:32 PM PDT 24
Finished Jul 11 05:26:28 PM PDT 24
Peak memory 200240 kb
Host smart-46488f3e-8a7c-4362-97c6-5c68fbefa0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891257929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2891257929
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2325077002
Short name T267
Test name
Test status
Simulation time 2179956147 ps
CPU time 77.54 seconds
Started Jul 11 05:25:32 PM PDT 24
Finished Jul 11 05:26:54 PM PDT 24
Peak memory 342192 kb
Host smart-d423ce54-b5fb-41fd-b60b-32e3a6ebbbc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2325077002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2325077002
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2580557293
Short name T506
Test name
Test status
Simulation time 1067385317 ps
CPU time 14.29 seconds
Started Jul 11 05:25:31 PM PDT 24
Finished Jul 11 05:25:50 PM PDT 24
Peak memory 200332 kb
Host smart-90abd8f5-c5bf-4ac3-828a-917068c4fc82
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580557293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2580557293
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1070748221
Short name T233
Test name
Test status
Simulation time 13542614424 ps
CPU time 46.17 seconds
Started Jul 11 05:25:33 PM PDT 24
Finished Jul 11 05:26:23 PM PDT 24
Peak memory 200372 kb
Host smart-6c2036bf-56ba-44d3-aefa-ba48b86f0e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070748221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1070748221
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1396383977
Short name T372
Test name
Test status
Simulation time 2128592108 ps
CPU time 6.61 seconds
Started Jul 11 05:25:30 PM PDT 24
Finished Jul 11 05:25:41 PM PDT 24
Peak memory 200288 kb
Host smart-0a592203-000d-47c1-a83d-b0789c1b766b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396383977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1396383977
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3122437538
Short name T342
Test name
Test status
Simulation time 71994227914 ps
CPU time 1653.67 seconds
Started Jul 11 05:25:30 PM PDT 24
Finished Jul 11 05:53:09 PM PDT 24
Peak memory 749332 kb
Host smart-725763bd-8af1-4b86-959b-66d56cf29374
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122437538 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3122437538
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1308684227
Short name T85
Test name
Test status
Simulation time 30829689392 ps
CPU time 109.24 seconds
Started Jul 11 05:25:30 PM PDT 24
Finished Jul 11 05:27:24 PM PDT 24
Peak memory 200368 kb
Host smart-23cbde2f-723d-4dba-8d64-ecb3cdcdd6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308684227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1308684227
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3603291831
Short name T427
Test name
Test status
Simulation time 26264774 ps
CPU time 0.61 seconds
Started Jul 11 05:24:52 PM PDT 24
Finished Jul 11 05:24:55 PM PDT 24
Peak memory 196056 kb
Host smart-648e9419-9a2d-4e52-92de-727dcf8fd4cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603291831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3603291831
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.4056316624
Short name T454
Test name
Test status
Simulation time 5271365744 ps
CPU time 79.98 seconds
Started Jul 11 05:24:51 PM PDT 24
Finished Jul 11 05:26:14 PM PDT 24
Peak memory 200408 kb
Host smart-82ee3dc7-a746-49f0-9a64-f485631ef122
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4056316624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.4056316624
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.2940087722
Short name T124
Test name
Test status
Simulation time 278462974 ps
CPU time 7.49 seconds
Started Jul 11 05:24:42 PM PDT 24
Finished Jul 11 05:24:53 PM PDT 24
Peak memory 200204 kb
Host smart-ebd4c385-254a-4b3f-bb33-16d283ceae92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940087722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2940087722
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2897085810
Short name T387
Test name
Test status
Simulation time 5244354137 ps
CPU time 192.62 seconds
Started Jul 11 05:24:46 PM PDT 24
Finished Jul 11 05:28:01 PM PDT 24
Peak memory 437776 kb
Host smart-cb257daa-7362-410a-9a1a-226bf1d5f3b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2897085810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2897085810
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.463555289
Short name T518
Test name
Test status
Simulation time 62283147067 ps
CPU time 222.85 seconds
Started Jul 11 05:24:45 PM PDT 24
Finished Jul 11 05:28:30 PM PDT 24
Peak memory 200392 kb
Host smart-72a6df3b-5e98-4a42-8a44-b624ae0614b9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463555289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.463555289
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1185846617
Short name T491
Test name
Test status
Simulation time 8891651917 ps
CPU time 89.07 seconds
Started Jul 11 05:24:41 PM PDT 24
Finished Jul 11 05:26:12 PM PDT 24
Peak memory 200272 kb
Host smart-d7c0c2a6-df92-4d3c-a04d-d7068ad01d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185846617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1185846617
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.4225414797
Short name T45
Test name
Test status
Simulation time 88993291 ps
CPU time 1.02 seconds
Started Jul 11 05:24:41 PM PDT 24
Finished Jul 11 05:24:43 PM PDT 24
Peak memory 219528 kb
Host smart-f252e1ca-d3ea-4afd-b34b-42d89a077cb2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225414797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.4225414797
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3425281048
Short name T331
Test name
Test status
Simulation time 1034859534 ps
CPU time 12.47 seconds
Started Jul 11 05:24:44 PM PDT 24
Finished Jul 11 05:24:59 PM PDT 24
Peak memory 200284 kb
Host smart-9e71915c-8b68-44cd-83cd-15879d10ee51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425281048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3425281048
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.2576355447
Short name T28
Test name
Test status
Simulation time 37499872255 ps
CPU time 1372.66 seconds
Started Jul 11 05:24:49 PM PDT 24
Finished Jul 11 05:47:45 PM PDT 24
Peak memory 716376 kb
Host smart-1d02aa47-801c-4a6c-aad0-b70cb7d7520d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576355447 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.2576355447
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.3471596571
Short name T16
Test name
Test status
Simulation time 24665289566 ps
CPU time 499.63 seconds
Started Jul 11 05:24:59 PM PDT 24
Finished Jul 11 05:33:22 PM PDT 24
Peak memory 481280 kb
Host smart-0ca05b01-b087-41cd-8692-733ad11cc4d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3471596571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.3471596571
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.1945323160
Short name T252
Test name
Test status
Simulation time 4500343014 ps
CPU time 41.53 seconds
Started Jul 11 05:24:52 PM PDT 24
Finished Jul 11 05:25:36 PM PDT 24
Peak memory 200256 kb
Host smart-6e6401ac-a32f-4a5f-bbac-472be2212125
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1945323160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.1945323160
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.3030386317
Short name T418
Test name
Test status
Simulation time 5326325623 ps
CPU time 55.77 seconds
Started Jul 11 05:24:54 PM PDT 24
Finished Jul 11 05:25:54 PM PDT 24
Peak memory 200268 kb
Host smart-3fd391f8-1060-46c5-ae0b-af8be10958ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3030386317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.3030386317
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.2222916276
Short name T523
Test name
Test status
Simulation time 47492960210 ps
CPU time 121.35 seconds
Started Jul 11 05:24:46 PM PDT 24
Finished Jul 11 05:26:50 PM PDT 24
Peak memory 200356 kb
Host smart-75af3c62-89b2-4bc4-a5f7-f4926db53139
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2222916276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.2222916276
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.3297550862
Short name T215
Test name
Test status
Simulation time 10387467344 ps
CPU time 499.47 seconds
Started Jul 11 05:24:42 PM PDT 24
Finished Jul 11 05:33:03 PM PDT 24
Peak memory 200224 kb
Host smart-660b2e7a-6c57-4055-95dd-08b7a2fadf65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3297550862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.3297550862
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.2308914912
Short name T247
Test name
Test status
Simulation time 39447589916 ps
CPU time 2064.7 seconds
Started Jul 11 05:24:54 PM PDT 24
Finished Jul 11 05:59:23 PM PDT 24
Peak memory 216284 kb
Host smart-fe2f5196-2ac6-4b46-acab-c95ef0b1045e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2308914912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.2308914912
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2758531163
Short name T136
Test name
Test status
Simulation time 38304263200 ps
CPU time 2117.45 seconds
Started Jul 11 05:24:41 PM PDT 24
Finished Jul 11 06:00:00 PM PDT 24
Peak memory 216764 kb
Host smart-465858ed-b416-4132-b671-c0d3571ebda8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2758531163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2758531163
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.3009010879
Short name T318
Test name
Test status
Simulation time 8535153086 ps
CPU time 58.67 seconds
Started Jul 11 05:24:44 PM PDT 24
Finished Jul 11 05:25:46 PM PDT 24
Peak memory 200368 kb
Host smart-c6798793-ef78-4549-966f-06f9a8f53f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009010879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.3009010879
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1537512694
Short name T232
Test name
Test status
Simulation time 39528589 ps
CPU time 0.61 seconds
Started Jul 11 05:25:38 PM PDT 24
Finished Jul 11 05:25:41 PM PDT 24
Peak memory 195768 kb
Host smart-6deceaf8-bc57-4a0c-851d-88bfa3bb39df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537512694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1537512694
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.3912462315
Short name T335
Test name
Test status
Simulation time 3207218952 ps
CPU time 15.51 seconds
Started Jul 11 05:25:31 PM PDT 24
Finished Jul 11 05:25:51 PM PDT 24
Peak memory 200260 kb
Host smart-0bba66ad-3e5a-4529-ae0b-bd08e4073ee7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3912462315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3912462315
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1348655875
Short name T294
Test name
Test status
Simulation time 12223923753 ps
CPU time 64.83 seconds
Started Jul 11 05:25:41 PM PDT 24
Finished Jul 11 05:26:49 PM PDT 24
Peak memory 216808 kb
Host smart-3b22a980-2104-409f-a61e-130f941de563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348655875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1348655875
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2610599252
Short name T360
Test name
Test status
Simulation time 1615247115 ps
CPU time 50.81 seconds
Started Jul 11 05:25:30 PM PDT 24
Finished Jul 11 05:26:26 PM PDT 24
Peak memory 313620 kb
Host smart-f2ce6f95-3ef3-4d29-82a4-5b4d113b607d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2610599252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2610599252
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.2919544252
Short name T386
Test name
Test status
Simulation time 2009585042 ps
CPU time 9.48 seconds
Started Jul 11 05:25:38 PM PDT 24
Finished Jul 11 05:25:50 PM PDT 24
Peak memory 200172 kb
Host smart-ee872e50-9530-4ee0-9dee-102d54f9b1bd
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919544252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2919544252
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3460398633
Short name T463
Test name
Test status
Simulation time 2973673083 ps
CPU time 177.11 seconds
Started Jul 11 05:25:31 PM PDT 24
Finished Jul 11 05:28:32 PM PDT 24
Peak memory 200252 kb
Host smart-e770e499-a5a7-4d31-b7bc-877b9ace7c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460398633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3460398633
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2660001509
Short name T526
Test name
Test status
Simulation time 1206938613 ps
CPU time 5.72 seconds
Started Jul 11 05:25:31 PM PDT 24
Finished Jul 11 05:25:41 PM PDT 24
Peak memory 200200 kb
Host smart-e2773b9d-09ad-4517-a7bc-84b4b61fc084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660001509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2660001509
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2993639682
Short name T308
Test name
Test status
Simulation time 259157442106 ps
CPU time 1914.24 seconds
Started Jul 11 05:25:38 PM PDT 24
Finished Jul 11 05:57:35 PM PDT 24
Peak memory 728476 kb
Host smart-fe7525ae-fc5d-4f72-8626-40f4f2ce731c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993639682 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2993639682
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1877716410
Short name T185
Test name
Test status
Simulation time 4179200594 ps
CPU time 112.71 seconds
Started Jul 11 05:25:35 PM PDT 24
Finished Jul 11 05:27:30 PM PDT 24
Peak memory 200328 kb
Host smart-10ac1ee0-df9d-4264-aa8e-0bdfc7a3badf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877716410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1877716410
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1840025228
Short name T483
Test name
Test status
Simulation time 11498991 ps
CPU time 0.59 seconds
Started Jul 11 05:25:39 PM PDT 24
Finished Jul 11 05:25:42 PM PDT 24
Peak memory 195120 kb
Host smart-0fe78ee7-d391-40ae-98f7-3e2da1d6a622
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840025228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1840025228
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3916341066
Short name T139
Test name
Test status
Simulation time 1352173514 ps
CPU time 20.32 seconds
Started Jul 11 05:25:40 PM PDT 24
Finished Jul 11 05:26:04 PM PDT 24
Peak memory 200188 kb
Host smart-2fd98dcb-d824-4890-b9ec-1d5d3bd9eb64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3916341066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3916341066
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1482921835
Short name T514
Test name
Test status
Simulation time 8559200575 ps
CPU time 38.42 seconds
Started Jul 11 05:25:37 PM PDT 24
Finished Jul 11 05:26:18 PM PDT 24
Peak memory 200384 kb
Host smart-54fea9ac-6fb3-4d52-8939-30855bcc9dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482921835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1482921835
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.885555520
Short name T328
Test name
Test status
Simulation time 2944651288 ps
CPU time 83.63 seconds
Started Jul 11 05:25:40 PM PDT 24
Finished Jul 11 05:27:07 PM PDT 24
Peak memory 273484 kb
Host smart-aba2bd39-c3f1-4ba0-91c6-e2d2439e1142
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=885555520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.885555520
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.811492149
Short name T158
Test name
Test status
Simulation time 9810133928 ps
CPU time 95.42 seconds
Started Jul 11 05:25:49 PM PDT 24
Finished Jul 11 05:27:31 PM PDT 24
Peak memory 200344 kb
Host smart-35662e9c-f91f-461c-9aa3-6141fed71bf2
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811492149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.811492149
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1885611252
Short name T208
Test name
Test status
Simulation time 12497518582 ps
CPU time 135.74 seconds
Started Jul 11 05:25:38 PM PDT 24
Finished Jul 11 05:27:56 PM PDT 24
Peak memory 200336 kb
Host smart-e8ea286b-0d53-49dd-a09a-3a59cc832189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885611252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1885611252
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3636200709
Short name T236
Test name
Test status
Simulation time 4796492755 ps
CPU time 14.89 seconds
Started Jul 11 05:25:35 PM PDT 24
Finished Jul 11 05:25:53 PM PDT 24
Peak memory 200368 kb
Host smart-1cb430c2-1b77-41e3-bb05-26a5c699d15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636200709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3636200709
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1021379532
Short name T407
Test name
Test status
Simulation time 242719044 ps
CPU time 12.57 seconds
Started Jul 11 05:25:39 PM PDT 24
Finished Jul 11 05:25:55 PM PDT 24
Peak memory 200188 kb
Host smart-953144fb-92b8-4197-bd7f-d9d6421ef801
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021379532 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1021379532
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1130435014
Short name T78
Test name
Test status
Simulation time 2761861714 ps
CPU time 79.49 seconds
Started Jul 11 05:25:39 PM PDT 24
Finished Jul 11 05:27:01 PM PDT 24
Peak memory 200364 kb
Host smart-5e559894-3d6b-43b5-b8c5-0df3d5b5f85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130435014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1130435014
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.799346633
Short name T428
Test name
Test status
Simulation time 20283775 ps
CPU time 0.58 seconds
Started Jul 11 05:25:50 PM PDT 24
Finished Jul 11 05:25:57 PM PDT 24
Peak memory 195160 kb
Host smart-7ce5afcd-b6e4-487e-9c32-7aceb4c84986
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799346633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.799346633
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1849787609
Short name T153
Test name
Test status
Simulation time 361338800 ps
CPU time 22.13 seconds
Started Jul 11 05:25:42 PM PDT 24
Finished Jul 11 05:26:07 PM PDT 24
Peak memory 200540 kb
Host smart-2a413a00-7c58-4e3c-a6d2-9d0ec5077ddf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1849787609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1849787609
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3105161551
Short name T417
Test name
Test status
Simulation time 19141419903 ps
CPU time 63.47 seconds
Started Jul 11 05:25:53 PM PDT 24
Finished Jul 11 05:27:03 PM PDT 24
Peak memory 200320 kb
Host smart-66750fc8-7308-445f-89ea-b0f3e47f0598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105161551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3105161551
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2155274141
Short name T191
Test name
Test status
Simulation time 6425159273 ps
CPU time 315.83 seconds
Started Jul 11 05:25:53 PM PDT 24
Finished Jul 11 05:31:15 PM PDT 24
Peak memory 689748 kb
Host smart-5c8577c1-d41a-4b1c-bf4a-9747297e6d21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2155274141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2155274141
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.2817294146
Short name T527
Test name
Test status
Simulation time 5125886241 ps
CPU time 24.53 seconds
Started Jul 11 05:25:50 PM PDT 24
Finished Jul 11 05:26:21 PM PDT 24
Peak memory 200288 kb
Host smart-ab783c02-1f04-4d26-a4e3-648dfe53764c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817294146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2817294146
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1308728109
Short name T249
Test name
Test status
Simulation time 252862572 ps
CPU time 4 seconds
Started Jul 11 05:25:37 PM PDT 24
Finished Jul 11 05:25:43 PM PDT 24
Peak memory 200248 kb
Host smart-2a089675-332f-4558-a323-a701e3b56bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308728109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1308728109
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2331196914
Short name T354
Test name
Test status
Simulation time 6156924893 ps
CPU time 12.41 seconds
Started Jul 11 05:25:39 PM PDT 24
Finished Jul 11 05:25:55 PM PDT 24
Peak memory 200384 kb
Host smart-fa4a8933-7dd2-4a0f-aff4-86444129b1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331196914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2331196914
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.840195625
Short name T257
Test name
Test status
Simulation time 19346067579 ps
CPU time 64.38 seconds
Started Jul 11 05:25:49 PM PDT 24
Finished Jul 11 05:27:01 PM PDT 24
Peak memory 200344 kb
Host smart-68c5bf2c-8428-4d79-b6c1-49e29244eb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840195625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.840195625
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.730011976
Short name T48
Test name
Test status
Simulation time 11431860 ps
CPU time 0.6 seconds
Started Jul 11 05:25:39 PM PDT 24
Finished Jul 11 05:25:43 PM PDT 24
Peak memory 195848 kb
Host smart-c5d49e3e-9c3a-48f2-9ff6-2d9afe69ef6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730011976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.730011976
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.1100561228
Short name T15
Test name
Test status
Simulation time 1927294044 ps
CPU time 55.59 seconds
Started Jul 11 05:25:39 PM PDT 24
Finished Jul 11 05:26:37 PM PDT 24
Peak memory 200236 kb
Host smart-02a262ab-7fe8-4898-b39c-22e87892580e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1100561228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1100561228
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1206306059
Short name T348
Test name
Test status
Simulation time 6781350236 ps
CPU time 1294.36 seconds
Started Jul 11 05:25:36 PM PDT 24
Finished Jul 11 05:47:13 PM PDT 24
Peak memory 786464 kb
Host smart-b29f704e-8b69-4f64-bb88-9bd289570b15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1206306059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1206306059
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.3622810495
Short name T222
Test name
Test status
Simulation time 7600234100 ps
CPU time 107.49 seconds
Started Jul 11 05:25:36 PM PDT 24
Finished Jul 11 05:27:26 PM PDT 24
Peak memory 200348 kb
Host smart-9c66ffcb-25cb-40bf-91e4-c7d5fb52abbb
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622810495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3622810495
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1312628843
Short name T280
Test name
Test status
Simulation time 7461565599 ps
CPU time 100.27 seconds
Started Jul 11 05:25:39 PM PDT 24
Finished Jul 11 05:27:22 PM PDT 24
Peak memory 200360 kb
Host smart-4145988e-b934-43b6-ba91-225a93f25ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312628843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1312628843
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1943263734
Short name T120
Test name
Test status
Simulation time 1561029811 ps
CPU time 11.04 seconds
Started Jul 11 05:25:53 PM PDT 24
Finished Jul 11 05:26:10 PM PDT 24
Peak memory 200356 kb
Host smart-b4f5bde7-bf70-45d4-bca2-2ee7846dcbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943263734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1943263734
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.757237747
Short name T422
Test name
Test status
Simulation time 7020570940 ps
CPU time 97.79 seconds
Started Jul 11 05:25:39 PM PDT 24
Finished Jul 11 05:27:19 PM PDT 24
Peak memory 200356 kb
Host smart-efc68029-0b3d-41ab-b9bb-3e20f3301ec3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757237747 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.757237747
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3509847607
Short name T476
Test name
Test status
Simulation time 12028943287 ps
CPU time 89.97 seconds
Started Jul 11 05:25:50 PM PDT 24
Finished Jul 11 05:27:27 PM PDT 24
Peak memory 200352 kb
Host smart-7817daac-c79d-48c5-88a1-bb6cb3be9346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509847607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3509847607
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.162545259
Short name T346
Test name
Test status
Simulation time 16391485 ps
CPU time 0.61 seconds
Started Jul 11 05:25:44 PM PDT 24
Finished Jul 11 05:25:49 PM PDT 24
Peak memory 196096 kb
Host smart-bfb10e61-4159-41e6-82d3-e3dea0a6e6d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162545259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.162545259
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3436957849
Short name T22
Test name
Test status
Simulation time 4585653894 ps
CPU time 69.42 seconds
Started Jul 11 05:25:54 PM PDT 24
Finished Jul 11 05:27:09 PM PDT 24
Peak memory 200480 kb
Host smart-343d9321-c6e2-4aa6-af55-ebdc23fda640
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3436957849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3436957849
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2797321849
Short name T54
Test name
Test status
Simulation time 452341174 ps
CPU time 8.32 seconds
Started Jul 11 05:25:44 PM PDT 24
Finished Jul 11 05:25:56 PM PDT 24
Peak memory 200280 kb
Host smart-c03ceb61-106e-44b0-a9a3-e5b263d60f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797321849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2797321849
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1049643238
Short name T370
Test name
Test status
Simulation time 2776013213 ps
CPU time 477.01 seconds
Started Jul 11 05:25:42 PM PDT 24
Finished Jul 11 05:33:43 PM PDT 24
Peak memory 658912 kb
Host smart-489fabbe-f2a2-4326-9d84-cc3affd21ef1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1049643238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1049643238
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.4227981125
Short name T459
Test name
Test status
Simulation time 33443749049 ps
CPU time 79.76 seconds
Started Jul 11 05:25:48 PM PDT 24
Finished Jul 11 05:27:14 PM PDT 24
Peak memory 200216 kb
Host smart-d01de0ab-b48e-4da5-b6c9-b5b8f4f25b6b
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227981125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.4227981125
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.4172292250
Short name T227
Test name
Test status
Simulation time 12002032605 ps
CPU time 213.11 seconds
Started Jul 11 05:25:41 PM PDT 24
Finished Jul 11 05:29:18 PM PDT 24
Peak memory 216792 kb
Host smart-038187bc-9f42-48f5-9854-f81333cd0c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172292250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.4172292250
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1525356779
Short name T159
Test name
Test status
Simulation time 233012975 ps
CPU time 4.33 seconds
Started Jul 11 05:25:38 PM PDT 24
Finished Jul 11 05:25:44 PM PDT 24
Peak memory 200268 kb
Host smart-73dd1ce5-51b7-43d2-a715-e7f2584bee33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525356779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1525356779
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3851674185
Short name T27
Test name
Test status
Simulation time 56014705635 ps
CPU time 2996.35 seconds
Started Jul 11 05:25:46 PM PDT 24
Finished Jul 11 06:15:49 PM PDT 24
Peak memory 808280 kb
Host smart-5c2402d8-7756-45ce-b37d-f9c8ce735247
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851674185 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3851674185
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3188688470
Short name T293
Test name
Test status
Simulation time 2179940213 ps
CPU time 26.14 seconds
Started Jul 11 05:25:44 PM PDT 24
Finished Jul 11 05:26:15 PM PDT 24
Peak memory 200244 kb
Host smart-0d474b1a-e570-433f-9713-5ce8eb05dadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188688470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3188688470
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.88415447
Short name T2
Test name
Test status
Simulation time 11717644 ps
CPU time 0.64 seconds
Started Jul 11 05:25:47 PM PDT 24
Finished Jul 11 05:25:55 PM PDT 24
Peak memory 196192 kb
Host smart-97250dcc-e677-4dc1-b080-3189b24dd9ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88415447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.88415447
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.3896345321
Short name T66
Test name
Test status
Simulation time 123963046 ps
CPU time 6.79 seconds
Started Jul 11 05:25:42 PM PDT 24
Finished Jul 11 05:25:52 PM PDT 24
Peak memory 200204 kb
Host smart-9d93df04-b85e-452e-86f3-de88a2b7a207
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3896345321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.3896345321
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.4015244868
Short name T231
Test name
Test status
Simulation time 4299947315 ps
CPU time 8.62 seconds
Started Jul 11 05:25:44 PM PDT 24
Finished Jul 11 05:25:57 PM PDT 24
Peak memory 200328 kb
Host smart-5ec0d5af-3e1c-4b8d-80df-71addf0c66c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015244868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.4015244868
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2196435405
Short name T290
Test name
Test status
Simulation time 2266359017 ps
CPU time 157.94 seconds
Started Jul 11 05:25:42 PM PDT 24
Finished Jul 11 05:28:25 PM PDT 24
Peak memory 356656 kb
Host smart-2465a1a4-2c04-4812-a287-b8bebb88c56d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2196435405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2196435405
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.410657172
Short name T190
Test name
Test status
Simulation time 35683451900 ps
CPU time 184.76 seconds
Started Jul 11 05:25:44 PM PDT 24
Finished Jul 11 05:28:54 PM PDT 24
Peak memory 200328 kb
Host smart-3fa97548-42fa-4c79-b1ff-a25e79351315
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410657172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.410657172
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.2289960168
Short name T223
Test name
Test status
Simulation time 9132358878 ps
CPU time 134.71 seconds
Started Jul 11 05:25:45 PM PDT 24
Finished Jul 11 05:28:05 PM PDT 24
Peak memory 216680 kb
Host smart-3d160e70-255f-4303-a687-16388222f769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289960168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2289960168
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.761116263
Short name T171
Test name
Test status
Simulation time 815550900 ps
CPU time 4.6 seconds
Started Jul 11 05:25:51 PM PDT 24
Finished Jul 11 05:26:02 PM PDT 24
Peak memory 200208 kb
Host smart-6d014279-3852-46a7-be19-2014d67a2440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761116263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.761116263
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.2362882992
Short name T411
Test name
Test status
Simulation time 17676773150 ps
CPU time 158.85 seconds
Started Jul 11 05:25:44 PM PDT 24
Finished Jul 11 05:28:28 PM PDT 24
Peak memory 216628 kb
Host smart-77b062c4-6c40-411f-812f-bf7ea8e5ccb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362882992 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2362882992
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3139721916
Short name T437
Test name
Test status
Simulation time 4425046883 ps
CPU time 74.67 seconds
Started Jul 11 05:25:47 PM PDT 24
Finished Jul 11 05:27:07 PM PDT 24
Peak memory 200624 kb
Host smart-03980fc7-a86a-4359-97d4-d8c298659dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139721916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3139721916
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.579707331
Short name T19
Test name
Test status
Simulation time 41446731 ps
CPU time 0.63 seconds
Started Jul 11 05:25:45 PM PDT 24
Finished Jul 11 05:25:51 PM PDT 24
Peak memory 196192 kb
Host smart-29545be2-9692-4e1e-bcf0-fa06c2575b4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579707331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.579707331
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1882378842
Short name T26
Test name
Test status
Simulation time 903466052 ps
CPU time 13.46 seconds
Started Jul 11 05:25:46 PM PDT 24
Finished Jul 11 05:26:06 PM PDT 24
Peak memory 200280 kb
Host smart-d2253c38-b4be-47f4-998f-989b79e8173a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1882378842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1882378842
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2745849809
Short name T258
Test name
Test status
Simulation time 4859280873 ps
CPU time 46.41 seconds
Started Jul 11 05:25:42 PM PDT 24
Finished Jul 11 05:26:32 PM PDT 24
Peak memory 200292 kb
Host smart-3b69f901-5925-420e-a1ac-e8329ff09231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745849809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2745849809
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2760623728
Short name T413
Test name
Test status
Simulation time 24039790714 ps
CPU time 1010.31 seconds
Started Jul 11 05:25:46 PM PDT 24
Finished Jul 11 05:42:43 PM PDT 24
Peak memory 636428 kb
Host smart-a7c4745e-60ce-4fe6-b76d-438c65c4ef84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2760623728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2760623728
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1335814175
Short name T229
Test name
Test status
Simulation time 4044530762 ps
CPU time 69.76 seconds
Started Jul 11 05:25:43 PM PDT 24
Finished Jul 11 05:26:57 PM PDT 24
Peak memory 200248 kb
Host smart-22cb1552-b2a8-48bb-91e8-1f583688546d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335814175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1335814175
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2300788184
Short name T378
Test name
Test status
Simulation time 20143991965 ps
CPU time 67.64 seconds
Started Jul 11 05:25:46 PM PDT 24
Finished Jul 11 05:26:59 PM PDT 24
Peak memory 200368 kb
Host smart-bd91fafb-ab65-4645-9664-83ea74b33430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300788184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2300788184
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2409434362
Short name T479
Test name
Test status
Simulation time 219049737 ps
CPU time 9.73 seconds
Started Jul 11 05:25:44 PM PDT 24
Finished Jul 11 05:25:59 PM PDT 24
Peak memory 200372 kb
Host smart-a91b2c67-250f-4c4a-967c-43f26250e2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409434362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2409434362
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.119510824
Short name T151
Test name
Test status
Simulation time 365685298267 ps
CPU time 2362.28 seconds
Started Jul 11 05:25:44 PM PDT 24
Finished Jul 11 06:05:12 PM PDT 24
Peak memory 742648 kb
Host smart-675ec89a-88e3-471e-b5be-d5340e33b2ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119510824 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.119510824
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1225402450
Short name T216
Test name
Test status
Simulation time 3137861640 ps
CPU time 22.82 seconds
Started Jul 11 05:25:46 PM PDT 24
Finished Jul 11 05:26:15 PM PDT 24
Peak memory 200620 kb
Host smart-6f652855-a823-4b91-ae9b-4422ca9c98a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225402450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1225402450
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.1423410154
Short name T397
Test name
Test status
Simulation time 25044350 ps
CPU time 0.61 seconds
Started Jul 11 05:25:53 PM PDT 24
Finished Jul 11 05:26:00 PM PDT 24
Peak memory 196216 kb
Host smart-2fa6bf94-7724-4aa0-adfc-da1f0337ee56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423410154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.1423410154
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.4182306850
Short name T304
Test name
Test status
Simulation time 8975205817 ps
CPU time 71.03 seconds
Started Jul 11 05:25:46 PM PDT 24
Finished Jul 11 05:27:03 PM PDT 24
Peak memory 200408 kb
Host smart-832452a0-093e-49c0-ba17-05999b221c3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182306850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.4182306850
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3627957908
Short name T206
Test name
Test status
Simulation time 1283387086 ps
CPU time 32.51 seconds
Started Jul 11 05:25:44 PM PDT 24
Finished Jul 11 05:26:22 PM PDT 24
Peak memory 200300 kb
Host smart-c57cedc8-7c08-4a7d-ad46-d2dc44e8dda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627957908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3627957908
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.4073245651
Short name T137
Test name
Test status
Simulation time 1137684638 ps
CPU time 114.45 seconds
Started Jul 11 05:25:46 PM PDT 24
Finished Jul 11 05:27:47 PM PDT 24
Peak memory 598888 kb
Host smart-b0797b86-d5cd-46f0-b646-6698cf4c1e40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4073245651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.4073245651
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3151482039
Short name T266
Test name
Test status
Simulation time 2672908372 ps
CPU time 39.74 seconds
Started Jul 11 05:25:50 PM PDT 24
Finished Jul 11 05:26:36 PM PDT 24
Peak memory 200268 kb
Host smart-0d536ef5-b8d0-437e-8dd1-ffe2a383462d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151482039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3151482039
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1793029871
Short name T486
Test name
Test status
Simulation time 40582722 ps
CPU time 0.69 seconds
Started Jul 11 05:25:51 PM PDT 24
Finished Jul 11 05:25:58 PM PDT 24
Peak memory 196676 kb
Host smart-1c5bb22d-8062-4302-8b3c-7a493894bd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793029871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1793029871
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2425339331
Short name T324
Test name
Test status
Simulation time 1183170223 ps
CPU time 11.25 seconds
Started Jul 11 05:25:46 PM PDT 24
Finished Jul 11 05:26:04 PM PDT 24
Peak memory 200368 kb
Host smart-963cad76-568b-4093-a03d-bacc17aa13f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425339331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2425339331
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2637110646
Short name T138
Test name
Test status
Simulation time 175264749281 ps
CPU time 155.98 seconds
Started Jul 11 05:25:50 PM PDT 24
Finished Jul 11 05:28:32 PM PDT 24
Peak memory 200392 kb
Host smart-52eab5c9-5e3d-490f-a5b6-1ee0d23663b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637110646 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2637110646
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.696705921
Short name T80
Test name
Test status
Simulation time 16003329798 ps
CPU time 34.08 seconds
Started Jul 11 05:25:54 PM PDT 24
Finished Jul 11 05:26:34 PM PDT 24
Peak memory 200212 kb
Host smart-13db7ad3-8719-4a3c-8ab2-88ab2843f46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696705921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.696705921
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.2959993874
Short name T345
Test name
Test status
Simulation time 22575876 ps
CPU time 0.61 seconds
Started Jul 11 05:25:52 PM PDT 24
Finished Jul 11 05:25:59 PM PDT 24
Peak memory 196768 kb
Host smart-5b21ba5a-d637-48cd-94be-0931c88e4cf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959993874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.2959993874
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3172625339
Short name T332
Test name
Test status
Simulation time 37717971 ps
CPU time 2.21 seconds
Started Jul 11 05:25:55 PM PDT 24
Finished Jul 11 05:26:03 PM PDT 24
Peak memory 200140 kb
Host smart-638b726c-6f85-4e0d-b8b7-61943c7f4f93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3172625339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3172625339
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.4158034783
Short name T262
Test name
Test status
Simulation time 4010435846 ps
CPU time 11.09 seconds
Started Jul 11 05:25:51 PM PDT 24
Finished Jul 11 05:26:09 PM PDT 24
Peak memory 200384 kb
Host smart-f600afff-fb8e-42e0-8bdf-fe93bfbf40b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158034783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.4158034783
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3745968317
Short name T186
Test name
Test status
Simulation time 3038013676 ps
CPU time 534.63 seconds
Started Jul 11 05:25:51 PM PDT 24
Finished Jul 11 05:34:53 PM PDT 24
Peak memory 708564 kb
Host smart-0425b4c3-8e71-4419-a533-36f956209dcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3745968317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3745968317
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3258610670
Short name T513
Test name
Test status
Simulation time 447506416 ps
CPU time 6.62 seconds
Started Jul 11 05:25:49 PM PDT 24
Finished Jul 11 05:26:03 PM PDT 24
Peak memory 200128 kb
Host smart-ed614831-89e9-4bc2-87af-70f21d5b7c1e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258610670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3258610670
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1257849358
Short name T218
Test name
Test status
Simulation time 47075770322 ps
CPU time 170.83 seconds
Started Jul 11 05:25:52 PM PDT 24
Finished Jul 11 05:28:49 PM PDT 24
Peak memory 200460 kb
Host smart-2e685a2f-3685-46f0-b2d0-315d87b9a129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257849358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1257849358
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2296238860
Short name T307
Test name
Test status
Simulation time 568326858 ps
CPU time 12.83 seconds
Started Jul 11 05:25:49 PM PDT 24
Finished Jul 11 05:26:08 PM PDT 24
Peak memory 200212 kb
Host smart-b79f37a8-12de-4f0d-9956-8904f195bbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296238860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2296238860
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.635867584
Short name T466
Test name
Test status
Simulation time 6645967003 ps
CPU time 23.49 seconds
Started Jul 11 05:25:51 PM PDT 24
Finished Jul 11 05:26:22 PM PDT 24
Peak memory 200248 kb
Host smart-41be38cf-fbf6-4215-8681-2b8da79f7920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635867584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.635867584
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3426929236
Short name T225
Test name
Test status
Simulation time 20108388 ps
CPU time 0.6 seconds
Started Jul 11 05:25:52 PM PDT 24
Finished Jul 11 05:25:59 PM PDT 24
Peak memory 196872 kb
Host smart-5f076126-60ba-45e2-95a8-0209e4b58b62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426929236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3426929236
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3263309794
Short name T445
Test name
Test status
Simulation time 8919314716 ps
CPU time 53.43 seconds
Started Jul 11 05:25:50 PM PDT 24
Finished Jul 11 05:26:50 PM PDT 24
Peak memory 216524 kb
Host smart-f9479e2f-33d3-4dfb-99d5-e4ae308e6b8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3263309794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3263309794
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.484269878
Short name T273
Test name
Test status
Simulation time 1623920839 ps
CPU time 6.33 seconds
Started Jul 11 05:25:51 PM PDT 24
Finished Jul 11 05:26:05 PM PDT 24
Peak memory 200440 kb
Host smart-02607c08-70a3-44bd-bfcd-7ef58f73f7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484269878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.484269878
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3378420564
Short name T430
Test name
Test status
Simulation time 4880053520 ps
CPU time 171.37 seconds
Started Jul 11 05:25:51 PM PDT 24
Finished Jul 11 05:28:50 PM PDT 24
Peak memory 455560 kb
Host smart-8481b61b-84e7-400c-9254-b152c8d9fe57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3378420564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3378420564
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.518408561
Short name T224
Test name
Test status
Simulation time 207515194 ps
CPU time 10.76 seconds
Started Jul 11 05:25:48 PM PDT 24
Finished Jul 11 05:26:05 PM PDT 24
Peak memory 200220 kb
Host smart-3e4de7e6-4ced-4be7-a417-5d51c6f05b04
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518408561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.518408561
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.2532970805
Short name T12
Test name
Test status
Simulation time 1218456954 ps
CPU time 35.21 seconds
Started Jul 11 05:25:50 PM PDT 24
Finished Jul 11 05:26:32 PM PDT 24
Peak memory 200208 kb
Host smart-55fcdf4f-6e7a-4d7c-a1eb-fa297ccd856f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532970805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2532970805
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.4215611495
Short name T374
Test name
Test status
Simulation time 1587711332 ps
CPU time 9.6 seconds
Started Jul 11 05:25:50 PM PDT 24
Finished Jul 11 05:26:06 PM PDT 24
Peak memory 200312 kb
Host smart-dfbdc4c8-71e7-42f3-81e1-d4f7538dcbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215611495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.4215611495
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.4293671275
Short name T20
Test name
Test status
Simulation time 284466127930 ps
CPU time 773.34 seconds
Started Jul 11 05:27:19 PM PDT 24
Finished Jul 11 05:40:15 PM PDT 24
Peak memory 617712 kb
Host smart-47597092-2fee-45b7-b6f9-423547c0f5bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293671275 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.4293671275
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.804795114
Short name T391
Test name
Test status
Simulation time 25757602206 ps
CPU time 133.18 seconds
Started Jul 11 05:25:52 PM PDT 24
Finished Jul 11 05:28:12 PM PDT 24
Peak memory 200368 kb
Host smart-05035b04-fef5-4a9d-86e4-5a907b8ebce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804795114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.804795114
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1307425822
Short name T522
Test name
Test status
Simulation time 13050557 ps
CPU time 0.57 seconds
Started Jul 11 05:24:44 PM PDT 24
Finished Jul 11 05:24:48 PM PDT 24
Peak memory 195828 kb
Host smart-bc4ee59c-6dfe-4676-a5f2-b71ef2ef2366
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307425822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1307425822
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.1791944628
Short name T341
Test name
Test status
Simulation time 1730685630 ps
CPU time 98.93 seconds
Started Jul 11 05:24:43 PM PDT 24
Finished Jul 11 05:26:25 PM PDT 24
Peak memory 200204 kb
Host smart-c27abf31-b50b-4651-b172-9984dcdb4b6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1791944628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.1791944628
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3052021912
Short name T135
Test name
Test status
Simulation time 10788960367 ps
CPU time 33.79 seconds
Started Jul 11 05:24:43 PM PDT 24
Finished Jul 11 05:25:20 PM PDT 24
Peak memory 200384 kb
Host smart-4e6010a4-0f78-4c46-a134-68e7b7138ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052021912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3052021912
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2614944181
Short name T507
Test name
Test status
Simulation time 13529048899 ps
CPU time 1040.15 seconds
Started Jul 11 05:24:50 PM PDT 24
Finished Jul 11 05:42:13 PM PDT 24
Peak memory 743828 kb
Host smart-f56a2be1-4c4b-4f19-929c-12d7dfc99187
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2614944181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2614944181
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.694863502
Short name T363
Test name
Test status
Simulation time 110502368257 ps
CPU time 169.95 seconds
Started Jul 11 05:24:40 PM PDT 24
Finished Jul 11 05:27:32 PM PDT 24
Peak memory 200340 kb
Host smart-e47c2bea-ce57-493f-bc04-517be3678e2a
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694863502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.694863502
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1125603064
Short name T431
Test name
Test status
Simulation time 2455910623 ps
CPU time 35.3 seconds
Started Jul 11 05:24:43 PM PDT 24
Finished Jul 11 05:25:21 PM PDT 24
Peak memory 200312 kb
Host smart-c4210923-b095-402e-8478-e85578d633dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125603064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1125603064
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3960175638
Short name T47
Test name
Test status
Simulation time 104247762 ps
CPU time 0.91 seconds
Started Jul 11 05:24:42 PM PDT 24
Finished Jul 11 05:24:46 PM PDT 24
Peak memory 218308 kb
Host smart-edf5d0e8-5ad1-40a0-aa55-f9024479aa72
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960175638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3960175638
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1049241238
Short name T314
Test name
Test status
Simulation time 1722308373 ps
CPU time 7.67 seconds
Started Jul 11 05:24:42 PM PDT 24
Finished Jul 11 05:24:53 PM PDT 24
Peak memory 200196 kb
Host smart-b0ae32ab-ac32-43da-a4db-519c3203625e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049241238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1049241238
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.1119745186
Short name T353
Test name
Test status
Simulation time 25372909560 ps
CPU time 3288.11 seconds
Started Jul 11 05:24:52 PM PDT 24
Finished Jul 11 06:19:43 PM PDT 24
Peak memory 831216 kb
Host smart-f691252c-f3c7-4929-9fde-ca5d20fd603b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119745186 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.1119745186
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.1920997019
Short name T11
Test name
Test status
Simulation time 305982976140 ps
CPU time 7426.34 seconds
Started Jul 11 05:24:45 PM PDT 24
Finished Jul 11 07:28:35 PM PDT 24
Peak memory 920196 kb
Host smart-cf0583bf-2ebe-4681-9e6a-5195ecf0f792
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1920997019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.1920997019
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.898328953
Short name T244
Test name
Test status
Simulation time 1058916237 ps
CPU time 39 seconds
Started Jul 11 05:24:42 PM PDT 24
Finished Jul 11 05:25:23 PM PDT 24
Peak memory 200252 kb
Host smart-5e1c3acb-6fce-4b5d-94f5-5a1d0950a12f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=898328953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.898328953
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.1855821480
Short name T180
Test name
Test status
Simulation time 36473265384 ps
CPU time 111.77 seconds
Started Jul 11 05:24:47 PM PDT 24
Finished Jul 11 05:26:42 PM PDT 24
Peak memory 200332 kb
Host smart-ed1afdde-b6b1-4159-bd32-f7f0c6947786
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1855821480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.1855821480
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.1847347161
Short name T145
Test name
Test status
Simulation time 8699917733 ps
CPU time 134.5 seconds
Started Jul 11 05:24:42 PM PDT 24
Finished Jul 11 05:26:59 PM PDT 24
Peak memory 200224 kb
Host smart-2d533a8f-5a9e-403c-91a7-c97af8c7df42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1847347161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.1847347161
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.585127133
Short name T426
Test name
Test status
Simulation time 210015695178 ps
CPU time 627.37 seconds
Started Jul 11 05:24:54 PM PDT 24
Finished Jul 11 05:35:25 PM PDT 24
Peak memory 200252 kb
Host smart-34d060b9-f26d-4168-b425-7b5bbd6c14d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=585127133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.585127133
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.2867599219
Short name T250
Test name
Test status
Simulation time 1151517998594 ps
CPU time 2331.09 seconds
Started Jul 11 05:24:46 PM PDT 24
Finished Jul 11 06:03:40 PM PDT 24
Peak memory 216120 kb
Host smart-63b99ad7-3a51-46da-868c-c5dd53588256
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2867599219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.2867599219
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.525793025
Short name T75
Test name
Test status
Simulation time 272013336566 ps
CPU time 2377.99 seconds
Started Jul 11 05:24:53 PM PDT 24
Finished Jul 11 06:04:34 PM PDT 24
Peak memory 215864 kb
Host smart-552f95e1-e3d9-4cde-b846-e80d921cb6d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=3_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=525793025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.525793025
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1402976624
Short name T384
Test name
Test status
Simulation time 16288186487 ps
CPU time 110.48 seconds
Started Jul 11 05:24:52 PM PDT 24
Finished Jul 11 05:26:45 PM PDT 24
Peak memory 200220 kb
Host smart-77a0fa97-687e-423c-bb07-08923a8bf44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402976624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1402976624
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.104579258
Short name T349
Test name
Test status
Simulation time 13147049 ps
CPU time 0.62 seconds
Started Jul 11 05:25:55 PM PDT 24
Finished Jul 11 05:26:01 PM PDT 24
Peak memory 196116 kb
Host smart-477507a0-5c07-477a-a1e9-0553f8076489
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104579258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.104579258
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2515443122
Short name T268
Test name
Test status
Simulation time 938480770 ps
CPU time 54.45 seconds
Started Jul 11 05:25:54 PM PDT 24
Finished Jul 11 05:26:55 PM PDT 24
Peak memory 200188 kb
Host smart-f42136e4-441d-487b-8f01-2d5e5cc49b66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2515443122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2515443122
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3030087395
Short name T529
Test name
Test status
Simulation time 10477334130 ps
CPU time 34.31 seconds
Started Jul 11 05:25:57 PM PDT 24
Finished Jul 11 05:26:35 PM PDT 24
Peak memory 208524 kb
Host smart-f176eb2f-99e2-4ffe-9898-39b40d8af224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030087395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3030087395
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2432441512
Short name T439
Test name
Test status
Simulation time 7236601414 ps
CPU time 309.27 seconds
Started Jul 11 05:25:49 PM PDT 24
Finished Jul 11 05:31:05 PM PDT 24
Peak memory 623368 kb
Host smart-09518bb3-47a2-4e6b-8110-05ae99b7ff2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2432441512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2432441512
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.4278196361
Short name T497
Test name
Test status
Simulation time 2066222040 ps
CPU time 102.24 seconds
Started Jul 11 05:25:58 PM PDT 24
Finished Jul 11 05:27:45 PM PDT 24
Peak memory 200288 kb
Host smart-cac8abd7-32ba-4252-8231-554909eea1ee
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278196361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.4278196361
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.4224208646
Short name T168
Test name
Test status
Simulation time 2309713637 ps
CPU time 66.35 seconds
Started Jul 11 05:25:51 PM PDT 24
Finished Jul 11 05:27:05 PM PDT 24
Peak memory 200464 kb
Host smart-f465eaf9-b5e2-4245-a461-3b19992aa1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224208646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.4224208646
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.2815156996
Short name T143
Test name
Test status
Simulation time 1769872801 ps
CPU time 8.65 seconds
Started Jul 11 05:25:52 PM PDT 24
Finished Jul 11 05:26:07 PM PDT 24
Peak memory 200224 kb
Host smart-994d860a-768b-4552-ba85-24079d9ee4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815156996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.2815156996
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1324745319
Short name T484
Test name
Test status
Simulation time 207425156763 ps
CPU time 659.46 seconds
Started Jul 11 05:25:58 PM PDT 24
Finished Jul 11 05:37:02 PM PDT 24
Peak memory 208456 kb
Host smart-c1931fc2-38f1-449b-bd15-66b389bf1074
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324745319 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1324745319
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3590927336
Short name T264
Test name
Test status
Simulation time 4539636733 ps
CPU time 82.12 seconds
Started Jul 11 05:26:01 PM PDT 24
Finished Jul 11 05:27:26 PM PDT 24
Peak memory 200272 kb
Host smart-523f86fb-5ca1-41ad-b0b0-dc77661902f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590927336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3590927336
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1902862375
Short name T530
Test name
Test status
Simulation time 52225569 ps
CPU time 0.6 seconds
Started Jul 11 05:25:58 PM PDT 24
Finished Jul 11 05:26:03 PM PDT 24
Peak memory 196084 kb
Host smart-b0de4d1a-28cc-4c76-ac35-bf78ccf0bbad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902862375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1902862375
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.1778091405
Short name T29
Test name
Test status
Simulation time 5939663028 ps
CPU time 88.2 seconds
Started Jul 11 05:26:03 PM PDT 24
Finished Jul 11 05:27:35 PM PDT 24
Peak memory 208568 kb
Host smart-382e6b0d-0fe4-4812-b21a-cbd17b49ca64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1778091405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.1778091405
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2994481959
Short name T157
Test name
Test status
Simulation time 786059022 ps
CPU time 12.07 seconds
Started Jul 11 05:26:03 PM PDT 24
Finished Jul 11 05:26:18 PM PDT 24
Peak memory 200280 kb
Host smart-246e7c06-8883-490c-becb-cf542327906d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994481959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2994481959
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.3089649200
Short name T220
Test name
Test status
Simulation time 19674836959 ps
CPU time 888.17 seconds
Started Jul 11 05:25:56 PM PDT 24
Finished Jul 11 05:40:49 PM PDT 24
Peak memory 705392 kb
Host smart-d45d7db8-ca3f-4bb6-9eda-658fb5ab8515
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3089649200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3089649200
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2437347337
Short name T460
Test name
Test status
Simulation time 30792324232 ps
CPU time 34.01 seconds
Started Jul 11 05:26:01 PM PDT 24
Finished Jul 11 05:26:37 PM PDT 24
Peak memory 200292 kb
Host smart-2d322c60-6456-4c9a-bad8-c1b5ed81f641
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437347337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2437347337
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.2671944803
Short name T467
Test name
Test status
Simulation time 5111548473 ps
CPU time 64.7 seconds
Started Jul 11 05:25:58 PM PDT 24
Finished Jul 11 05:27:07 PM PDT 24
Peak memory 200368 kb
Host smart-dfd88af8-3d9c-4073-a08e-101252568701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671944803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.2671944803
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.4080546879
Short name T160
Test name
Test status
Simulation time 40709974 ps
CPU time 1.25 seconds
Started Jul 11 05:25:59 PM PDT 24
Finished Jul 11 05:26:04 PM PDT 24
Peak memory 200296 kb
Host smart-5b03dfc4-da36-4574-b139-d5e4d0635038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080546879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.4080546879
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.705115896
Short name T352
Test name
Test status
Simulation time 14202950086 ps
CPU time 787.85 seconds
Started Jul 11 05:25:58 PM PDT 24
Finished Jul 11 05:39:10 PM PDT 24
Peak memory 462880 kb
Host smart-1bdc24cb-fc92-4dee-b038-55e4db5db107
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705115896 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.705115896
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3581229666
Short name T287
Test name
Test status
Simulation time 11702866399 ps
CPU time 112.34 seconds
Started Jul 11 05:25:58 PM PDT 24
Finished Jul 11 05:27:54 PM PDT 24
Peak memory 200268 kb
Host smart-196e59a8-05e4-4eb7-ad9a-93e5b973b138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581229666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3581229666
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2582223584
Short name T285
Test name
Test status
Simulation time 25329078 ps
CPU time 0.62 seconds
Started Jul 11 05:26:38 PM PDT 24
Finished Jul 11 05:26:42 PM PDT 24
Peak memory 196224 kb
Host smart-b8e00dac-44c4-46a9-911a-57c633456dc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582223584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2582223584
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.119704196
Short name T359
Test name
Test status
Simulation time 4399475463 ps
CPU time 62.58 seconds
Started Jul 11 05:25:58 PM PDT 24
Finished Jul 11 05:27:05 PM PDT 24
Peak memory 215748 kb
Host smart-7d1979ae-63b4-4e1c-af89-f7d3a99fbb39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=119704196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.119704196
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.1567111656
Short name T322
Test name
Test status
Simulation time 6174016503 ps
CPU time 28.33 seconds
Started Jul 11 05:25:59 PM PDT 24
Finished Jul 11 05:26:31 PM PDT 24
Peak memory 200368 kb
Host smart-0c5ae361-3628-4672-96bc-2f6829b25a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567111656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.1567111656
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1691096324
Short name T3
Test name
Test status
Simulation time 1643460956 ps
CPU time 281.93 seconds
Started Jul 11 05:26:05 PM PDT 24
Finished Jul 11 05:30:50 PM PDT 24
Peak memory 654936 kb
Host smart-1f1c485b-8d23-45e8-9d7e-ec04a018959d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1691096324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1691096324
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.170818610
Short name T173
Test name
Test status
Simulation time 1908195631 ps
CPU time 100.31 seconds
Started Jul 11 05:25:59 PM PDT 24
Finished Jul 11 05:27:43 PM PDT 24
Peak memory 200200 kb
Host smart-6795a3de-87bf-43ec-be37-35bf28bad26c
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170818610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.170818610
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1660153
Short name T512
Test name
Test status
Simulation time 53094210922 ps
CPU time 38.36 seconds
Started Jul 11 05:26:01 PM PDT 24
Finished Jul 11 05:26:42 PM PDT 24
Peak memory 200556 kb
Host smart-f910e107-dcbf-4764-817e-9579d4d668b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1660153
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1422750835
Short name T361
Test name
Test status
Simulation time 78632151 ps
CPU time 3.81 seconds
Started Jul 11 05:25:59 PM PDT 24
Finished Jul 11 05:26:06 PM PDT 24
Peak memory 200336 kb
Host smart-87f528c4-2374-4485-8f95-e7ca662fd709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422750835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1422750835
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3775232512
Short name T13
Test name
Test status
Simulation time 9906025356 ps
CPU time 823.8 seconds
Started Jul 11 05:26:05 PM PDT 24
Finished Jul 11 05:39:52 PM PDT 24
Peak memory 656388 kb
Host smart-849df23d-0a7a-4e77-8fde-0dde6296f47d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775232512 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3775232512
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.4036421978
Short name T84
Test name
Test status
Simulation time 9927621483 ps
CPU time 68.32 seconds
Started Jul 11 05:25:57 PM PDT 24
Finished Jul 11 05:27:10 PM PDT 24
Peak memory 200368 kb
Host smart-fb345a82-f349-4d69-aefa-64fab4a9f513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036421978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.4036421978
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.281682175
Short name T242
Test name
Test status
Simulation time 13773867 ps
CPU time 0.6 seconds
Started Jul 11 05:26:02 PM PDT 24
Finished Jul 11 05:26:05 PM PDT 24
Peak memory 195068 kb
Host smart-d7b670da-1774-45a8-ad33-4375c798de2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281682175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.281682175
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2286614845
Short name T504
Test name
Test status
Simulation time 2177360833 ps
CPU time 33.23 seconds
Started Jul 11 05:26:01 PM PDT 24
Finished Jul 11 05:26:37 PM PDT 24
Peak memory 200312 kb
Host smart-6fc72732-97a7-44d4-85bc-e1c908cdc77e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2286614845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2286614845
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1721571814
Short name T300
Test name
Test status
Simulation time 3578197679 ps
CPU time 23.69 seconds
Started Jul 11 05:26:07 PM PDT 24
Finished Jul 11 05:26:33 PM PDT 24
Peak memory 200400 kb
Host smart-75e4b652-0d0e-4273-8d5f-d2506988b5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721571814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1721571814
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.3353085960
Short name T7
Test name
Test status
Simulation time 3003053709 ps
CPU time 122.41 seconds
Started Jul 11 05:25:58 PM PDT 24
Finished Jul 11 05:28:04 PM PDT 24
Peak memory 355424 kb
Host smart-53208cc2-8faa-4564-9bfb-2dfbe3633e4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3353085960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3353085960
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.977733808
Short name T207
Test name
Test status
Simulation time 8423242052 ps
CPU time 147.52 seconds
Started Jul 11 05:26:10 PM PDT 24
Finished Jul 11 05:28:40 PM PDT 24
Peak memory 200392 kb
Host smart-64e3fe3e-39c1-48a8-bc1e-7b2ac4613027
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977733808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.977733808
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3907367169
Short name T399
Test name
Test status
Simulation time 364325250 ps
CPU time 20.25 seconds
Started Jul 11 05:26:10 PM PDT 24
Finished Jul 11 05:26:32 PM PDT 24
Peak memory 200248 kb
Host smart-c460a9c1-a6d0-4bf7-800d-a72915a37fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907367169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3907367169
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2378301940
Short name T213
Test name
Test status
Simulation time 772445017 ps
CPU time 13.39 seconds
Started Jul 11 05:25:56 PM PDT 24
Finished Jul 11 05:26:14 PM PDT 24
Peak memory 200316 kb
Host smart-fa51a76a-0e1a-4751-8b81-910d0b206a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378301940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2378301940
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.3232019488
Short name T32
Test name
Test status
Simulation time 37631248317 ps
CPU time 920.19 seconds
Started Jul 11 05:25:58 PM PDT 24
Finished Jul 11 05:41:23 PM PDT 24
Peak memory 736560 kb
Host smart-511eee62-2d7c-4365-ba56-651c9762ea3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232019488 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.3232019488
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2524927346
Short name T461
Test name
Test status
Simulation time 592851009 ps
CPU time 32.28 seconds
Started Jul 11 05:26:10 PM PDT 24
Finished Jul 11 05:26:44 PM PDT 24
Peak memory 200352 kb
Host smart-09b2f398-be49-4153-887e-6709635d0afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524927346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2524927346
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2266942854
Short name T365
Test name
Test status
Simulation time 12295392 ps
CPU time 0.61 seconds
Started Jul 11 05:26:03 PM PDT 24
Finished Jul 11 05:26:06 PM PDT 24
Peak memory 196208 kb
Host smart-bdb514df-2f64-4338-b116-01a5ba316283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266942854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2266942854
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.401886736
Short name T175
Test name
Test status
Simulation time 808150239 ps
CPU time 47.55 seconds
Started Jul 11 05:26:00 PM PDT 24
Finished Jul 11 05:26:51 PM PDT 24
Peak memory 200196 kb
Host smart-a0abfb3e-39c6-4b1a-a74d-a7eeb80b9a09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=401886736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.401886736
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1480094086
Short name T338
Test name
Test status
Simulation time 11527202172 ps
CPU time 36.45 seconds
Started Jul 11 05:25:56 PM PDT 24
Finished Jul 11 05:26:37 PM PDT 24
Peak memory 200372 kb
Host smart-c3d9f547-ea51-4e22-8e9a-5968b5037b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480094086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1480094086
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.283106190
Short name T284
Test name
Test status
Simulation time 28345939238 ps
CPU time 720.74 seconds
Started Jul 11 05:26:03 PM PDT 24
Finished Jul 11 05:38:07 PM PDT 24
Peak memory 670456 kb
Host smart-05cf7fa9-bbc2-4978-b375-dd6beaa2736d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=283106190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.283106190
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2525812320
Short name T414
Test name
Test status
Simulation time 24284998820 ps
CPU time 82.32 seconds
Started Jul 11 05:25:55 PM PDT 24
Finished Jul 11 05:27:23 PM PDT 24
Peak memory 200408 kb
Host smart-f653794a-e7ef-497b-8873-4cfe7608eb6e
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525812320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2525812320
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.1773465847
Short name T490
Test name
Test status
Simulation time 364887702 ps
CPU time 5.09 seconds
Started Jul 11 05:25:57 PM PDT 24
Finished Jul 11 05:26:06 PM PDT 24
Peak memory 200224 kb
Host smart-f36daceb-cd95-41c0-95a3-cf870d808f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773465847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.1773465847
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2468054894
Short name T147
Test name
Test status
Simulation time 299599513 ps
CPU time 2.05 seconds
Started Jul 11 05:25:55 PM PDT 24
Finished Jul 11 05:26:03 PM PDT 24
Peak memory 200184 kb
Host smart-d212c22a-442e-4877-a0eb-27656f470290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468054894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2468054894
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.100539170
Short name T82
Test name
Test status
Simulation time 53499475424 ps
CPU time 1906.2 seconds
Started Jul 11 05:26:03 PM PDT 24
Finished Jul 11 05:57:53 PM PDT 24
Peak memory 727572 kb
Host smart-019692c6-0038-483c-906b-f844dc8d1df5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100539170 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.100539170
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2588681891
Short name T446
Test name
Test status
Simulation time 3507096054 ps
CPU time 47.43 seconds
Started Jul 11 05:26:02 PM PDT 24
Finished Jul 11 05:26:52 PM PDT 24
Peak memory 200236 kb
Host smart-b55f4e09-13f2-4b38-9ce8-3b7c303544b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588681891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2588681891
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2526367139
Short name T480
Test name
Test status
Simulation time 14861464 ps
CPU time 0.66 seconds
Started Jul 11 05:26:07 PM PDT 24
Finished Jul 11 05:26:10 PM PDT 24
Peak memory 196204 kb
Host smart-85bcda4b-3570-4d56-85e5-d9e6e0d0608d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526367139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2526367139
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.895297339
Short name T165
Test name
Test status
Simulation time 3696354480 ps
CPU time 34.54 seconds
Started Jul 11 05:26:02 PM PDT 24
Finished Jul 11 05:26:39 PM PDT 24
Peak memory 200264 kb
Host smart-41443415-1edc-4a34-87c1-87c0ea0c9c85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=895297339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.895297339
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.1904989109
Short name T245
Test name
Test status
Simulation time 204747586 ps
CPU time 1.79 seconds
Started Jul 11 05:26:06 PM PDT 24
Finished Jul 11 05:26:11 PM PDT 24
Peak memory 200300 kb
Host smart-c020c369-5cf0-4b63-80e5-b6d5f683e05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904989109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1904989109
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.360934456
Short name T382
Test name
Test status
Simulation time 3697162197 ps
CPU time 555.1 seconds
Started Jul 11 05:26:11 PM PDT 24
Finished Jul 11 05:35:29 PM PDT 24
Peak memory 669988 kb
Host smart-ff48df7f-4e3c-44f0-a942-dd758a38b80f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=360934456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.360934456
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.2055102730
Short name T375
Test name
Test status
Simulation time 66403866169 ps
CPU time 156.59 seconds
Started Jul 11 05:26:07 PM PDT 24
Finished Jul 11 05:28:46 PM PDT 24
Peak memory 200228 kb
Host smart-ef57707f-fcc0-4bdd-9af4-1c5eef2399d5
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055102730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2055102730
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3349521554
Short name T385
Test name
Test status
Simulation time 641429401 ps
CPU time 37.18 seconds
Started Jul 11 05:26:04 PM PDT 24
Finished Jul 11 05:26:44 PM PDT 24
Peak memory 200216 kb
Host smart-0d7e0b05-aa53-40c1-8b9a-556de5df3527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349521554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3349521554
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1998246841
Short name T289
Test name
Test status
Simulation time 397612987 ps
CPU time 3.71 seconds
Started Jul 11 05:26:10 PM PDT 24
Finished Jul 11 05:26:15 PM PDT 24
Peak memory 199728 kb
Host smart-c948752a-a831-4587-b768-e1ed541488f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998246841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1998246841
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.1462646923
Short name T70
Test name
Test status
Simulation time 52863238837 ps
CPU time 63.87 seconds
Started Jul 11 05:26:10 PM PDT 24
Finished Jul 11 05:27:15 PM PDT 24
Peak memory 208624 kb
Host smart-eb54e10c-d7f2-4d64-ab6a-c2b9bdc86496
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462646923 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1462646923
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.678575877
Short name T303
Test name
Test status
Simulation time 3947160441 ps
CPU time 72.03 seconds
Started Jul 11 05:26:04 PM PDT 24
Finished Jul 11 05:27:19 PM PDT 24
Peak memory 200452 kb
Host smart-c1232551-ce41-45db-8f1c-a74ef4c4a88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678575877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.678575877
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3285116264
Short name T489
Test name
Test status
Simulation time 60856676 ps
CPU time 0.62 seconds
Started Jul 11 05:26:08 PM PDT 24
Finished Jul 11 05:26:11 PM PDT 24
Peak memory 196072 kb
Host smart-90e3c1fb-3830-48ed-a017-981d871feb98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285116264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3285116264
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.725273900
Short name T130
Test name
Test status
Simulation time 441889251 ps
CPU time 14.28 seconds
Started Jul 11 05:26:06 PM PDT 24
Finished Jul 11 05:26:23 PM PDT 24
Peak memory 200288 kb
Host smart-8b547eea-6399-4ac9-a1f0-2ddf2ee04841
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=725273900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.725273900
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.3177634967
Short name T469
Test name
Test status
Simulation time 311946624 ps
CPU time 6.12 seconds
Started Jul 11 05:26:11 PM PDT 24
Finished Jul 11 05:26:20 PM PDT 24
Peak memory 200260 kb
Host smart-9dd1a101-04eb-46a6-8a8b-1b846cc52cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177634967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3177634967
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.3929426680
Short name T415
Test name
Test status
Simulation time 4250017880 ps
CPU time 220.67 seconds
Started Jul 11 05:26:04 PM PDT 24
Finished Jul 11 05:29:48 PM PDT 24
Peak memory 629476 kb
Host smart-db1dc5f5-85cf-4a22-ab92-754713fe2873
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3929426680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.3929426680
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1694458273
Short name T362
Test name
Test status
Simulation time 31194979454 ps
CPU time 95.68 seconds
Started Jul 11 05:26:08 PM PDT 24
Finished Jul 11 05:27:46 PM PDT 24
Peak memory 200216 kb
Host smart-be827ee5-6167-43d1-acef-e5e764f895f1
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694458273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1694458273
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.2095884748
Short name T154
Test name
Test status
Simulation time 13939304707 ps
CPU time 143.71 seconds
Started Jul 11 05:26:03 PM PDT 24
Finished Jul 11 05:28:29 PM PDT 24
Peak memory 200276 kb
Host smart-171c8a4c-9407-421f-a320-21b8beb04227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095884748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.2095884748
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.1366960953
Short name T320
Test name
Test status
Simulation time 166547470 ps
CPU time 6.79 seconds
Started Jul 11 05:26:10 PM PDT 24
Finished Jul 11 05:26:19 PM PDT 24
Peak memory 199680 kb
Host smart-a4a9ccd7-2232-463a-98aa-16453fa850ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366960953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.1366960953
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1978710408
Short name T79
Test name
Test status
Simulation time 93422959735 ps
CPU time 3042.98 seconds
Started Jul 11 05:26:04 PM PDT 24
Finished Jul 11 06:16:50 PM PDT 24
Peak memory 800188 kb
Host smart-251a311d-b7c6-4cfb-a93c-7a294c18fb85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978710408 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1978710408
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1912691074
Short name T473
Test name
Test status
Simulation time 2350077584 ps
CPU time 54.95 seconds
Started Jul 11 05:26:05 PM PDT 24
Finished Jul 11 05:27:03 PM PDT 24
Peak memory 200368 kb
Host smart-e9a0dfba-9de0-4496-9752-d15704962e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912691074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1912691074
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1221419844
Short name T179
Test name
Test status
Simulation time 15777453 ps
CPU time 0.61 seconds
Started Jul 11 05:26:07 PM PDT 24
Finished Jul 11 05:26:10 PM PDT 24
Peak memory 196088 kb
Host smart-c8c06a44-e277-4fd1-810e-419768bfdbae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221419844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1221419844
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.955925432
Short name T150
Test name
Test status
Simulation time 5821368901 ps
CPU time 78.42 seconds
Started Jul 11 05:26:07 PM PDT 24
Finished Jul 11 05:27:28 PM PDT 24
Peak memory 200372 kb
Host smart-0dd4bfff-982f-4907-881a-3b77179e5802
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=955925432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.955925432
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1101957164
Short name T503
Test name
Test status
Simulation time 274063027 ps
CPU time 4.01 seconds
Started Jul 11 05:26:04 PM PDT 24
Finished Jul 11 05:26:11 PM PDT 24
Peak memory 200316 kb
Host smart-9eeb3fa5-e492-42a5-bc6d-4190dce22239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101957164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1101957164
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.4285865428
Short name T309
Test name
Test status
Simulation time 28066892145 ps
CPU time 324.61 seconds
Started Jul 11 05:26:08 PM PDT 24
Finished Jul 11 05:31:34 PM PDT 24
Peak memory 449580 kb
Host smart-a2f41b12-cb05-457e-9fbe-7e5fdc88da98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4285865428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.4285865428
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3990779132
Short name T198
Test name
Test status
Simulation time 11508902637 ps
CPU time 147.89 seconds
Started Jul 11 05:26:08 PM PDT 24
Finished Jul 11 05:28:38 PM PDT 24
Peak memory 200328 kb
Host smart-c04a3681-cb42-4873-84fb-fc0b32172e8d
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990779132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3990779132
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.4281218293
Short name T380
Test name
Test status
Simulation time 7228410046 ps
CPU time 103.64 seconds
Started Jul 11 05:26:05 PM PDT 24
Finished Jul 11 05:27:52 PM PDT 24
Peak memory 200324 kb
Host smart-19080971-871c-4470-ac25-763d68068baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281218293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.4281218293
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3064546374
Short name T259
Test name
Test status
Simulation time 106453358 ps
CPU time 5.01 seconds
Started Jul 11 05:26:03 PM PDT 24
Finished Jul 11 05:26:12 PM PDT 24
Peak memory 200312 kb
Host smart-192e28e8-c592-45e8-83c9-e4a6d70f35ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064546374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3064546374
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.463565416
Short name T188
Test name
Test status
Simulation time 294036903355 ps
CPU time 663.38 seconds
Started Jul 11 05:26:02 PM PDT 24
Finished Jul 11 05:37:08 PM PDT 24
Peak memory 344084 kb
Host smart-c29a0c86-80cf-4c0a-903a-da6a0eaf9d91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463565416 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.463565416
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.3877393958
Short name T133
Test name
Test status
Simulation time 9386784806 ps
CPU time 19.09 seconds
Started Jul 11 05:26:08 PM PDT 24
Finished Jul 11 05:26:29 PM PDT 24
Peak memory 200248 kb
Host smart-dd5865fb-972e-4b0d-ab50-680a0b9d371c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877393958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.3877393958
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.858717778
Short name T347
Test name
Test status
Simulation time 18032560 ps
CPU time 0.58 seconds
Started Jul 11 05:26:10 PM PDT 24
Finished Jul 11 05:26:13 PM PDT 24
Peak memory 195760 kb
Host smart-174c90fb-bd09-40b3-8776-b7ad1cd19a45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858717778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.858717778
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.1039177306
Short name T528
Test name
Test status
Simulation time 5012777490 ps
CPU time 65.88 seconds
Started Jul 11 05:26:11 PM PDT 24
Finished Jul 11 05:27:19 PM PDT 24
Peak memory 216644 kb
Host smart-d1e4a970-3504-473a-9f1f-a04e26b60f35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1039177306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.1039177306
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.863593553
Short name T279
Test name
Test status
Simulation time 2169384698 ps
CPU time 24.87 seconds
Started Jul 11 05:26:16 PM PDT 24
Finished Jul 11 05:26:42 PM PDT 24
Peak memory 200296 kb
Host smart-fd00ded6-05c6-4e30-a671-c05de24a28f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863593553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.863593553
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1146496182
Short name T477
Test name
Test status
Simulation time 3758960677 ps
CPU time 463.31 seconds
Started Jul 11 05:26:16 PM PDT 24
Finished Jul 11 05:34:01 PM PDT 24
Peak memory 657148 kb
Host smart-64d8ebed-facd-42a4-aec6-1b1a5450edec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1146496182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1146496182
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1430374406
Short name T470
Test name
Test status
Simulation time 4849914595 ps
CPU time 22.51 seconds
Started Jul 11 05:26:16 PM PDT 24
Finished Jul 11 05:26:40 PM PDT 24
Peak memory 200328 kb
Host smart-ff9267af-6167-491b-b508-7885397f72bc
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430374406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1430374406
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3506015502
Short name T482
Test name
Test status
Simulation time 4143633752 ps
CPU time 37.94 seconds
Started Jul 11 05:26:12 PM PDT 24
Finished Jul 11 05:26:52 PM PDT 24
Peak memory 200384 kb
Host smart-f09871c4-d835-4c19-97ae-7c4d31f1ed21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506015502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3506015502
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.4042684658
Short name T176
Test name
Test status
Simulation time 146041808 ps
CPU time 6.61 seconds
Started Jul 11 05:26:08 PM PDT 24
Finished Jul 11 05:26:17 PM PDT 24
Peak memory 200256 kb
Host smart-588c8760-f8ec-4b85-aebf-e1dc39bb6a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042684658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.4042684658
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3353498304
Short name T462
Test name
Test status
Simulation time 46031957058 ps
CPU time 906.53 seconds
Started Jul 11 05:26:16 PM PDT 24
Finished Jul 11 05:41:24 PM PDT 24
Peak memory 617756 kb
Host smart-3a161948-d9da-459f-b8d0-f6ec4556ec4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353498304 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3353498304
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3443288331
Short name T269
Test name
Test status
Simulation time 8329733171 ps
CPU time 115.69 seconds
Started Jul 11 05:26:17 PM PDT 24
Finished Jul 11 05:28:14 PM PDT 24
Peak memory 200272 kb
Host smart-ffff0fc4-ed99-4e1e-abca-3864c7cdfb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443288331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3443288331
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2429673583
Short name T377
Test name
Test status
Simulation time 60119080 ps
CPU time 0.59 seconds
Started Jul 11 05:26:16 PM PDT 24
Finished Jul 11 05:26:18 PM PDT 24
Peak memory 195692 kb
Host smart-4f41920c-f4b8-428d-ae6e-2e45e5e03238
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429673583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2429673583
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2156820903
Short name T516
Test name
Test status
Simulation time 2258024116 ps
CPU time 26.1 seconds
Started Jul 11 05:26:11 PM PDT 24
Finished Jul 11 05:26:40 PM PDT 24
Peak memory 200384 kb
Host smart-db8f97d5-2111-4a56-b65d-c7aba7a05029
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2156820903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2156820903
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2050795560
Short name T200
Test name
Test status
Simulation time 2427090226 ps
CPU time 39.82 seconds
Started Jul 11 05:26:10 PM PDT 24
Finished Jul 11 05:26:52 PM PDT 24
Peak memory 200424 kb
Host smart-f8a1d1f2-25e5-4fdd-8036-6baff7dc6e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050795560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2050795560
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.4173380496
Short name T36
Test name
Test status
Simulation time 29719412628 ps
CPU time 1074.24 seconds
Started Jul 11 05:26:12 PM PDT 24
Finished Jul 11 05:44:09 PM PDT 24
Peak memory 703148 kb
Host smart-0a0bc1e6-c61b-4172-b4f7-216314fec3b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4173380496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.4173380496
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1036884156
Short name T366
Test name
Test status
Simulation time 4297745860 ps
CPU time 11.36 seconds
Started Jul 11 05:26:12 PM PDT 24
Finished Jul 11 05:26:25 PM PDT 24
Peak memory 200284 kb
Host smart-f841f1b9-026a-47d7-82d9-3f06f228bdc8
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036884156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1036884156
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.718103621
Short name T500
Test name
Test status
Simulation time 8432464856 ps
CPU time 147.57 seconds
Started Jul 11 05:26:15 PM PDT 24
Finished Jul 11 05:28:44 PM PDT 24
Peak memory 208588 kb
Host smart-27db6798-5bed-439b-b7b2-8e4f5c839940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718103621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.718103621
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2211529511
Short name T432
Test name
Test status
Simulation time 2190798696 ps
CPU time 15.37 seconds
Started Jul 11 05:26:10 PM PDT 24
Finished Jul 11 05:26:27 PM PDT 24
Peak memory 200324 kb
Host smart-794d35ab-463e-4544-9413-b0fe6e6b6c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211529511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2211529511
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.1940835357
Short name T73
Test name
Test status
Simulation time 362186923592 ps
CPU time 1202.11 seconds
Started Jul 11 05:26:12 PM PDT 24
Finished Jul 11 05:46:16 PM PDT 24
Peak memory 200360 kb
Host smart-36c71abb-d6c8-4ad5-bf1f-0d4c540a306a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940835357 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.1940835357
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.4066068058
Short name T148
Test name
Test status
Simulation time 3808933787 ps
CPU time 64.11 seconds
Started Jul 11 05:26:14 PM PDT 24
Finished Jul 11 05:27:20 PM PDT 24
Peak memory 200272 kb
Host smart-cbe05d7e-f2c0-43fa-9c9d-f56010cca3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066068058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.4066068058
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1007687375
Short name T371
Test name
Test status
Simulation time 20069641 ps
CPU time 0.61 seconds
Started Jul 11 05:25:01 PM PDT 24
Finished Jul 11 05:25:07 PM PDT 24
Peak memory 196192 kb
Host smart-9e225658-84e7-44f1-96f8-668541b8f51a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007687375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1007687375
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1339482703
Short name T364
Test name
Test status
Simulation time 4066782346 ps
CPU time 74.78 seconds
Started Jul 11 05:24:44 PM PDT 24
Finished Jul 11 05:26:01 PM PDT 24
Peak memory 200396 kb
Host smart-e5bbe1a9-2e82-4d70-8528-3bdf5c4154df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1339482703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1339482703
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3496053259
Short name T276
Test name
Test status
Simulation time 42619359 ps
CPU time 1.33 seconds
Started Jul 11 05:24:41 PM PDT 24
Finished Jul 11 05:24:45 PM PDT 24
Peak memory 200116 kb
Host smart-2a931884-c47b-40b7-9a98-828635525ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496053259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3496053259
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3855954
Short name T358
Test name
Test status
Simulation time 11866588891 ps
CPU time 276.41 seconds
Started Jul 11 05:24:52 PM PDT 24
Finished Jul 11 05:29:31 PM PDT 24
Peak memory 479320 kb
Host smart-32ebf8ae-5285-4a98-941a-6f6196b85425
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3855954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3855954
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.1192031967
Short name T355
Test name
Test status
Simulation time 5650810083 ps
CPU time 73.06 seconds
Started Jul 11 05:25:01 PM PDT 24
Finished Jul 11 05:26:19 PM PDT 24
Peak memory 200352 kb
Host smart-aab7998d-c968-40d4-b3bc-428675426163
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192031967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.1192031967
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.1137054053
Short name T288
Test name
Test status
Simulation time 55746427951 ps
CPU time 185.06 seconds
Started Jul 11 05:24:46 PM PDT 24
Finished Jul 11 05:27:54 PM PDT 24
Peak memory 200360 kb
Host smart-d2e33f17-f29c-446f-9470-e07cebf613ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137054053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.1137054053
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3383704785
Short name T495
Test name
Test status
Simulation time 157002173 ps
CPU time 7.38 seconds
Started Jul 11 05:24:45 PM PDT 24
Finished Jul 11 05:24:55 PM PDT 24
Peak memory 200556 kb
Host smart-78b5cb1c-b6d2-41a1-acba-73930acfa7bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383704785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3383704785
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1787684266
Short name T416
Test name
Test status
Simulation time 13372578442 ps
CPU time 896.7 seconds
Started Jul 11 05:25:01 PM PDT 24
Finished Jul 11 05:40:03 PM PDT 24
Peak memory 676960 kb
Host smart-3660b0c5-c4ce-483f-a2d4-a70a9f21be73
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787684266 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1787684266
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.510613561
Short name T63
Test name
Test status
Simulation time 20069652544 ps
CPU time 1156.92 seconds
Started Jul 11 05:24:43 PM PDT 24
Finished Jul 11 05:44:03 PM PDT 24
Peak memory 453136 kb
Host smart-393c5667-3088-43ba-8ea0-4d69dd4f4728
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=510613561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.510613561
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.3874007698
Short name T127
Test name
Test status
Simulation time 4422736912 ps
CPU time 18.77 seconds
Started Jul 11 05:24:53 PM PDT 24
Finished Jul 11 05:25:14 PM PDT 24
Peak memory 200268 kb
Host smart-140cf177-fb33-4aba-8b75-b32005de9b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874007698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.3874007698
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1523584412
Short name T336
Test name
Test status
Simulation time 28343310 ps
CPU time 0.6 seconds
Started Jul 11 05:25:01 PM PDT 24
Finished Jul 11 05:25:06 PM PDT 24
Peak memory 196192 kb
Host smart-6009ad86-7b27-4cd7-af31-3f48f1e514c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523584412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1523584412
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2976633935
Short name T132
Test name
Test status
Simulation time 2577381226 ps
CPU time 36.99 seconds
Started Jul 11 05:25:01 PM PDT 24
Finished Jul 11 05:25:44 PM PDT 24
Peak memory 200392 kb
Host smart-164f2813-46ea-4d61-b889-93711b323180
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2976633935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2976633935
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2049956707
Short name T278
Test name
Test status
Simulation time 17999202401 ps
CPU time 35.57 seconds
Started Jul 11 05:24:42 PM PDT 24
Finished Jul 11 05:25:19 PM PDT 24
Peak memory 200416 kb
Host smart-b851836e-a6d4-4417-b8d8-138f2cdeffa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049956707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2049956707
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1924870961
Short name T6
Test name
Test status
Simulation time 10694841981 ps
CPU time 480.78 seconds
Started Jul 11 05:24:46 PM PDT 24
Finished Jul 11 05:32:50 PM PDT 24
Peak memory 675800 kb
Host smart-a9575baf-6a98-4687-9335-c573efdb1d0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1924870961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1924870961
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2712579471
Short name T261
Test name
Test status
Simulation time 22400507252 ps
CPU time 148.27 seconds
Started Jul 11 05:24:50 PM PDT 24
Finished Jul 11 05:27:20 PM PDT 24
Peak memory 200228 kb
Host smart-5d522a42-bbf5-4939-acf0-e3a333ccf439
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712579471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2712579471
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.59954909
Short name T228
Test name
Test status
Simulation time 1492100560 ps
CPU time 82.62 seconds
Started Jul 11 05:24:43 PM PDT 24
Finished Jul 11 05:26:08 PM PDT 24
Peak memory 200320 kb
Host smart-3c42a124-3faf-4254-ba5f-928f8cec7689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59954909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.59954909
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.4085525641
Short name T311
Test name
Test status
Simulation time 1160971411 ps
CPU time 13 seconds
Started Jul 11 05:24:54 PM PDT 24
Finished Jul 11 05:25:10 PM PDT 24
Peak memory 200208 kb
Host smart-c2c2e8fb-c1a4-4058-ab0c-b272e1841f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085525641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.4085525641
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2994163075
Short name T109
Test name
Test status
Simulation time 45535137944 ps
CPU time 815.92 seconds
Started Jul 11 05:24:43 PM PDT 24
Finished Jul 11 05:38:22 PM PDT 24
Peak memory 305552 kb
Host smart-5c8f1324-a9c5-4894-b65c-035cf23ba916
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994163075 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2994163075
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.2371761784
Short name T17
Test name
Test status
Simulation time 297355809055 ps
CPU time 1030.68 seconds
Started Jul 11 05:24:46 PM PDT 24
Finished Jul 11 05:41:59 PM PDT 24
Peak memory 718180 kb
Host smart-b1cd512f-3678-4947-89b0-e5cdb741e9db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2371761784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.2371761784
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1861959412
Short name T239
Test name
Test status
Simulation time 2232520003 ps
CPU time 40.89 seconds
Started Jul 11 05:24:46 PM PDT 24
Finished Jul 11 05:25:30 PM PDT 24
Peak memory 200372 kb
Host smart-7a058d02-a128-4b28-abb2-74002d27280e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861959412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1861959412
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1797961016
Short name T196
Test name
Test status
Simulation time 56644512 ps
CPU time 0.6 seconds
Started Jul 11 05:24:46 PM PDT 24
Finished Jul 11 05:24:49 PM PDT 24
Peak memory 196108 kb
Host smart-43ed075f-1de7-4b86-8ff1-3fda3cb6beea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797961016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1797961016
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.3838854037
Short name T254
Test name
Test status
Simulation time 3898007691 ps
CPU time 53.85 seconds
Started Jul 11 05:24:50 PM PDT 24
Finished Jul 11 05:25:47 PM PDT 24
Peak memory 200240 kb
Host smart-a736cd30-9a5a-46ec-b839-82645115d86e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3838854037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.3838854037
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3059951008
Short name T344
Test name
Test status
Simulation time 21919372412 ps
CPU time 79.73 seconds
Started Jul 11 05:24:46 PM PDT 24
Finished Jul 11 05:26:09 PM PDT 24
Peak memory 208552 kb
Host smart-5db6b7a2-3f79-4f7f-93f9-83a96817094a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059951008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3059951008
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2290815422
Short name T202
Test name
Test status
Simulation time 1423534927 ps
CPU time 36.21 seconds
Started Jul 11 05:24:47 PM PDT 24
Finished Jul 11 05:25:26 PM PDT 24
Peak memory 253548 kb
Host smart-dfa0b22d-893d-4899-857f-6ae96f0bec32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2290815422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2290815422
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1003115596
Short name T444
Test name
Test status
Simulation time 4951439712 ps
CPU time 142.82 seconds
Started Jul 11 05:24:55 PM PDT 24
Finished Jul 11 05:27:21 PM PDT 24
Peak memory 200232 kb
Host smart-a29e8b6c-2041-4f12-b4b7-38870ff012e9
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003115596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1003115596
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.85097718
Short name T161
Test name
Test status
Simulation time 1466985420 ps
CPU time 25.56 seconds
Started Jul 11 05:24:59 PM PDT 24
Finished Jul 11 05:25:28 PM PDT 24
Peak memory 200236 kb
Host smart-e78d3a84-c1f1-491b-a3a2-b0bfcfdb5582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85097718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.85097718
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3510825556
Short name T76
Test name
Test status
Simulation time 259993243 ps
CPU time 12.76 seconds
Started Jul 11 05:24:51 PM PDT 24
Finished Jul 11 05:25:06 PM PDT 24
Peak memory 200240 kb
Host smart-ff15402d-c46c-42fe-aeb0-f18917cc1777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510825556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3510825556
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1996717830
Short name T478
Test name
Test status
Simulation time 25414562820 ps
CPU time 37.56 seconds
Started Jul 11 05:24:56 PM PDT 24
Finished Jul 11 05:25:37 PM PDT 24
Peak memory 200240 kb
Host smart-76599ddc-028d-4818-9f9b-12f859c5b8dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996717830 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1996717830
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.4242326375
Short name T251
Test name
Test status
Simulation time 2512408455 ps
CPU time 125.4 seconds
Started Jul 11 05:25:01 PM PDT 24
Finished Jul 11 05:27:12 PM PDT 24
Peak memory 200412 kb
Host smart-6979cf8f-b46e-4bff-bee0-5e97d6f5d809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242326375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.4242326375
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1612105659
Short name T129
Test name
Test status
Simulation time 22034112 ps
CPU time 0.61 seconds
Started Jul 11 05:26:09 PM PDT 24
Finished Jul 11 05:26:12 PM PDT 24
Peak memory 196068 kb
Host smart-001752a8-bde5-4b7e-bf26-77c9b9882c96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612105659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1612105659
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3225028646
Short name T334
Test name
Test status
Simulation time 17026033343 ps
CPU time 59.83 seconds
Started Jul 11 05:24:54 PM PDT 24
Finished Jul 11 05:25:57 PM PDT 24
Peak memory 200424 kb
Host smart-68d33b9f-44fc-43ea-a81c-ecb8ed0381c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3225028646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3225028646
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3500975156
Short name T393
Test name
Test status
Simulation time 3569001247 ps
CPU time 55.43 seconds
Started Jul 11 05:24:53 PM PDT 24
Finished Jul 11 05:25:51 PM PDT 24
Peak memory 200316 kb
Host smart-48f445c6-4315-4153-934a-e9bed4e97443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500975156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3500975156
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.4061122564
Short name T429
Test name
Test status
Simulation time 26322798457 ps
CPU time 1140.02 seconds
Started Jul 11 05:25:19 PM PDT 24
Finished Jul 11 05:44:26 PM PDT 24
Peak memory 762348 kb
Host smart-1f34c8c3-2baa-4b3d-91d2-3f59cf7dc3fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4061122564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.4061122564
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3756470218
Short name T53
Test name
Test status
Simulation time 2291927051 ps
CPU time 125.66 seconds
Started Jul 11 05:25:01 PM PDT 24
Finished Jul 11 05:27:11 PM PDT 24
Peak memory 200352 kb
Host smart-a2fe2ef4-4be6-4b8b-bb0e-96bb442f4eaf
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756470218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3756470218
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1505832074
Short name T323
Test name
Test status
Simulation time 4457926604 ps
CPU time 39.4 seconds
Started Jul 11 05:24:58 PM PDT 24
Finished Jul 11 05:25:41 PM PDT 24
Peak memory 200264 kb
Host smart-454b4dd5-370f-4a8e-b647-b8318ca0a06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505832074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1505832074
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3148011175
Short name T419
Test name
Test status
Simulation time 2459070584 ps
CPU time 3.07 seconds
Started Jul 11 05:25:01 PM PDT 24
Finished Jul 11 05:25:08 PM PDT 24
Peak memory 200324 kb
Host smart-e4bd9d14-6c17-4d6f-9fbb-70c7d045ccf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148011175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3148011175
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1442953248
Short name T421
Test name
Test status
Simulation time 2093904725 ps
CPU time 38.08 seconds
Started Jul 11 05:24:58 PM PDT 24
Finished Jul 11 05:25:39 PM PDT 24
Peak memory 200268 kb
Host smart-29d254b3-e306-4833-9a86-9334c0fc5579
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442953248 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1442953248
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.3987948732
Short name T10
Test name
Test status
Simulation time 42696724744 ps
CPU time 4252.42 seconds
Started Jul 11 05:24:52 PM PDT 24
Finished Jul 11 06:35:48 PM PDT 24
Peak memory 842500 kb
Host smart-85001abd-445d-45e4-8625-8925bd7f59be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3987948732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.3987948732
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2010435913
Short name T388
Test name
Test status
Simulation time 5950545590 ps
CPU time 81.14 seconds
Started Jul 11 05:24:55 PM PDT 24
Finished Jul 11 05:26:20 PM PDT 24
Peak memory 200396 kb
Host smart-7746ab4f-a29f-45b8-8f1d-98f77a87a41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010435913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2010435913
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2564501239
Short name T274
Test name
Test status
Simulation time 152635415 ps
CPU time 0.58 seconds
Started Jul 11 05:24:59 PM PDT 24
Finished Jul 11 05:25:03 PM PDT 24
Peak memory 195828 kb
Host smart-336f26f9-fd01-42ee-a2b2-712577a7c027
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564501239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2564501239
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2123986741
Short name T329
Test name
Test status
Simulation time 8373464546 ps
CPU time 99.7 seconds
Started Jul 11 05:24:55 PM PDT 24
Finished Jul 11 05:26:38 PM PDT 24
Peak memory 200220 kb
Host smart-ff336c59-ef82-45a9-a40b-b4fe9608eebd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2123986741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2123986741
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.4231813671
Short name T517
Test name
Test status
Simulation time 9861941624 ps
CPU time 42.57 seconds
Started Jul 11 05:24:59 PM PDT 24
Finished Jul 11 05:25:46 PM PDT 24
Peak memory 200376 kb
Host smart-a7fc5091-1ffc-4ac5-87b5-d13c27142ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231813671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.4231813671
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1354087316
Short name T376
Test name
Test status
Simulation time 5974495370 ps
CPU time 1131.86 seconds
Started Jul 11 05:24:51 PM PDT 24
Finished Jul 11 05:43:46 PM PDT 24
Peak memory 767312 kb
Host smart-34cdc58c-3970-4bcc-8704-138f47e288ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1354087316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1354087316
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.4140811332
Short name T306
Test name
Test status
Simulation time 2797471162 ps
CPU time 11.1 seconds
Started Jul 11 05:24:59 PM PDT 24
Finished Jul 11 05:25:13 PM PDT 24
Peak memory 200168 kb
Host smart-129b4d5a-99e1-4ecd-871f-6e365302c468
User root
Command /workspace/default/simv +test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140811332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.4140811332
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.70317607
Short name T122
Test name
Test status
Simulation time 15958812762 ps
CPU time 141.06 seconds
Started Jul 11 05:24:54 PM PDT 24
Finished Jul 11 05:27:18 PM PDT 24
Peak memory 200568 kb
Host smart-0f509e4b-ba10-4057-be8b-2e26f50a38ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70317607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.70317607
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2558054149
Short name T68
Test name
Test status
Simulation time 39581415537 ps
CPU time 105.94 seconds
Started Jul 11 05:25:20 PM PDT 24
Finished Jul 11 05:27:12 PM PDT 24
Peak memory 208516 kb
Host smart-ab97130f-f8ed-45ad-b4e0-cb6e81c10744
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558054149 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2558054149
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1392051494
Short name T18
Test name
Test status
Simulation time 424554823619 ps
CPU time 1462.4 seconds
Started Jul 11 05:25:19 PM PDT 24
Finished Jul 11 05:49:48 PM PDT 24
Peak memory 637128 kb
Host smart-c21c153f-a7e4-4b26-943a-391fa31dc953
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1392051494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.1392051494
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.419507839
Short name T403
Test name
Test status
Simulation time 2864830184 ps
CPU time 13.07 seconds
Started Jul 11 05:24:58 PM PDT 24
Finished Jul 11 05:25:14 PM PDT 24
Peak memory 200240 kb
Host smart-a89e6c71-de2d-406a-b165-37ca54ed084a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419507839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.419507839
Directory /workspace/9.hmac_wipe_secret/latest
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