Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	19425452	1			T1	1703		T2	200		T3	440014
all_values[1]	19425452	1			T1	1703		T2	200		T3	440014
all_values[2]	19425452	1			T1	1703		T2	200		T3	440014

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

261800

1

T2

2

T5

966

T6

2

auto[1]

58014556

1

T1

5109

T2

598

T3

132004

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49645720

1

T1

4613

T2

573

T3

117500

auto[1]

8630636

1

T1

496

T2

27

T3

145042

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	79492	1			T8	3		T38	43		T20	3588
all_values[0]	auto[0]	auto[1]	384	1			T8	1		T20	12		T129	2
all_values[0]	auto[1]	auto[0]	19324200	1			T1	1674		T2	195		T3	439628
all_values[0]	auto[1]	auto[1]	21376	1			T1	29		T2	5		T3	386
all_values[1]	auto[0]	auto[0]	109829	1			T2	2		T5	966		T8	5
all_values[1]	auto[0]	auto[1]	216	1			T20	4		T18	2		T124	6
all_values[1]	auto[1]	auto[0]	19315022	1			T1	1703		T2	198		T3	440014
all_values[1]	auto[1]	auto[1]	385	1			T8	6		T20	4		T18	7
all_values[2]	auto[0]	auto[0]	27765	1			T6	2		T8	162		T25	91
all_values[2]	auto[0]	auto[1]	44114	1			T8	466		T26	69		T20	23
all_values[2]	auto[1]	auto[0]	10789412	1			T1	1236		T2	178		T3	295358
all_values[2]	auto[1]	auto[1]	8564161	1			T1	467		T2	22		T3	144656