Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	32	0	32	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	0	15	100.00	100	1	1	0
msg_len_upper_cp	1	0	1	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	0	30	100.00	100	1	1	0
msg_len_upper_cross	2	0	2	100.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

139855

1

T1

28

T2

6

T3

386

auto[1]

162432

1

T1

40

T2

2

T15

10

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len_lower_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	116377	1			T3	68		T7	2		T4	835
len_1026_2046	8130	1			T1	4		T2	1		T3	1
len_514_1022	4500	1			T1	2		T3	56		T4	12
len_2_510	4751	1			T3	61		T4	3		T8	12
len_2056	192	1			T1	2		T25	1		T77	3
len_2048	364	1			T1	3		T8	1		T25	3
len_2040	206	1			T1	4		T2	1		T25	3
len_1032	225	1			T20	2		T76	1		T129	1
len_1024	1948	1			T1	3		T3	1		T4	2
len_1016	250	1			T1	1		T3	2		T25	2
len_520	188	1			T1	1		T3	1		T25	1
len_512	400	1			T1	3		T3	1		T4	1
len_504	209	1			T1	3		T3	1		T25	2
len_8	1238	1			T3	1		T8	25		T20	26
len_0	12166	1			T1	8		T2	2		T15	11

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for msg_len_upper_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

len_upper

124

1

T6

1

T40

1

T17

4

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for msg_len_lower_cross

Bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	54393	1			T3	68		T7	2		T4	469
auto[0]	len_1026_2046	4432	1			T1	2		T2	1		T3	1
auto[0]	len_514_1022	2303	1			T3	56		T4	11		T8	6
auto[0]	len_2_510	2699	1			T3	61		T4	3		T8	6
auto[0]	len_2056	92	1			T39	2		T18	1		T124	4
auto[0]	len_2048	202	1			T1	1		T25	2		T76	1
auto[0]	len_2040	120	1			T1	4		T25	1		T39	3
auto[0]	len_1032	118	1			T20	2		T18	2		T124	3
auto[0]	len_1024	316	1			T1	1		T3	1		T76	2
auto[0]	len_1016	176	1			T3	2		T25	2		T81	2
auto[0]	len_520	101	1			T3	1		T25	1		T77	2
auto[0]	len_512	238	1			T1	2		T3	1		T4	1
auto[0]	len_504	129	1			T3	1		T25	2		T76	4
auto[0]	len_8	58	1			T3	1		T20	2		T81	1
auto[0]	len_0	4551	1			T1	4		T2	2		T15	6
auto[1]	len_2050_plus	61984	1			T4	366		T5	16		T6	6
auto[1]	len_1026_2046	3698	1			T1	2		T4	5		T5	1
auto[1]	len_514_1022	2197	1			T1	2		T4	1		T6	1
auto[1]	len_2_510	2052	1			T8	6		T38	3		T20	12
auto[1]	len_2056	100	1			T1	2		T25	1		T77	3
auto[1]	len_2048	162	1			T1	2		T8	1		T25	1
auto[1]	len_2040	86	1			T2	1		T25	2		T77	1
auto[1]	len_1032	107	1			T76	1		T129	1		T18	1
auto[1]	len_1024	1632	1			T1	2		T4	2		T8	1
auto[1]	len_1016	74	1			T1	1		T77	1		T124	1
auto[1]	len_520	87	1			T1	1		T20	2		T28	1
auto[1]	len_512	162	1			T1	1		T25	1		T38	2
auto[1]	len_504	80	1			T1	3		T76	4		T77	3
auto[1]	len_8	1180	1			T8	25		T20	24		T40	6
auto[1]	len_0	7615	1			T1	4		T15	5		T4	95

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	0	2	100.00

Automatically Generated Cross Bins for msg_len_upper_cross

Bins

hmac_en

msg_len_upper_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

len_upper

68

1

T6

1

T17

2

T139

1

auto[1]

len_upper

56

1

T40

1

T17

2

T140

1