Group : hmac_env_pkg::hmac_env_cov::status_cg
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Group : hmac_env_pkg::hmac_env_cov::status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv


Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 0 20 100.00
Crosses 192 0 192 100.00


Variables for Group hmac_env_pkg::hmac_env_cov::status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 2
key_swap 2 0 2 100.00 100 1 1 2
sta_fifo_depth 8 0 8 100.00 100 1 1 0
sta_fifo_empty 2 0 2 100.00 100 1 1 2
sta_fifo_full 2 0 2 100.00 100 1 1 2


Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
fifo_empty_cross 32 0 32 100.00 100 1 1 0
fifo_full_cross 32 0 32 100.00 100 1 1 0
fifo_depth_cross 128 0 128 100.00 100 1 1 0


Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4928923 1 T1 250 T2 42 T3 147649
auto[1] 3193658 1 T1 577 T2 53 T7 1462


Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3163177 1 T1 334 T2 94 T7 529
auto[1] 4959404 1 T1 493 T2 1 T3 147649


Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3487467 1 T1 418 T2 83 T3 147649
auto[1] 4635114 1 T1 409 T2 12 T7 731


Summary for Variable key_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for key_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4911917 1 T1 492 T2 94 T3 147649
auto[1] 3210664 1 T1 335 T2 1 T7 798


Summary for Variable sta_fifo_depth

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for sta_fifo_depth

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] 7317342 1 T1 814 T2 76 T3 125871
fifo_depth[1] 127357 1 T1 11 T2 2 T3 4793
fifo_depth[2] 96655 1 T1 1 T2 5 T3 4623
fifo_depth[3] 75067 1 T1 1 T2 4 T3 3899
fifo_depth[4] 70040 1 T2 3 T3 2948 T4 34
fifo_depth[5] 54493 1 T2 2 T3 2117 T4 16
fifo_depth[6] 44778 1 T2 3 T3 1555 T4 23
fifo_depth[7] 29333 1 T3 977 T4 11 T8 1068


Summary for Variable sta_fifo_empty

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_empty

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 805239 1 T1 13 T2 19 T3 21778
auto[1] 7317342 1 T1 814 T2 76 T3 125871


Summary for Variable sta_fifo_full

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sta_fifo_full

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8107216 1 T1 827 T2 95 T3 147649
auto[1] 15365 1 T8 6 T18 462 T28 638


Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_empty_cross

Bins
sta_fifo_emptyhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 31645 1 T1 1 T2 6 T7 5
auto[0] auto[0] auto[0] auto[0] auto[1] 34990 1 T4 13 T8 169 T38 19
auto[0] auto[0] auto[0] auto[1] auto[0] 37524 1 T2 13 T4 12 T5 9
auto[0] auto[0] auto[0] auto[1] auto[1] 40638 1 T5 2 T6 18 T8 987
auto[0] auto[0] auto[1] auto[0] auto[0] 147803 1 T3 21778 T4 30 T5 28
auto[0] auto[0] auto[1] auto[0] auto[1] 48347 1 T4 14 T6 4 T8 597
auto[0] auto[0] auto[1] auto[1] auto[0] 38155 1 T1 2 T7 6 T4 21
auto[0] auto[0] auto[1] auto[1] auto[1] 30910 1 T7 14 T4 57 T5 63
auto[0] auto[1] auto[0] auto[0] auto[0] 45950 1 T4 14 T5 38 T8 1594
auto[0] auto[1] auto[0] auto[0] auto[1] 42885 1 T5 24 T6 7 T8 821
auto[0] auto[1] auto[0] auto[1] auto[0] 47883 1 T1 1 T5 50 T8 1100
auto[0] auto[1] auto[0] auto[1] auto[1] 43048 1 T7 8 T6 12 T8 722
auto[0] auto[1] auto[1] auto[0] auto[0] 49219 1 T1 1 T4 36 T5 35
auto[0] auto[1] auto[1] auto[0] auto[1] 60399 1 T5 12 T8 2250 T25 4
auto[0] auto[1] auto[1] auto[1] auto[0] 53697 1 T1 5 T8 1089 T25 3
auto[0] auto[1] auto[1] auto[1] auto[1] 52146 1 T1 3 T4 10 T5 23
auto[1] auto[0] auto[0] auto[0] auto[0] 188255 1 T1 44 T2 35 T7 174
auto[1] auto[0] auto[0] auto[0] auto[1] 197276 1 T1 26 T2 1 T15 298
auto[1] auto[0] auto[0] auto[1] auto[0] 194682 1 T1 59 T2 27 T15 1
auto[1] auto[0] auto[0] auto[1] auto[1] 184397 1 T1 58 T15 1 T4 444
auto[1] auto[0] auto[1] auto[0] auto[0] 1737431 1 T3 125871 T15 3 T4 852
auto[1] auto[0] auto[1] auto[0] auto[1] 191591 1 T1 82 T15 243 T4 146
auto[1] auto[0] auto[1] auto[1] auto[0] 183237 1 T1 145 T2 1 T7 277
auto[1] auto[0] auto[1] auto[1] auto[1] 200586 1 T1 1 T7 434 T15 1
auto[1] auto[1] auto[0] auto[0] auto[0] 548208 1 T1 55 T15 1 T4 52
auto[1] auto[1] auto[0] auto[0] auto[1] 482170 1 T1 14 T15 231 T4 102
auto[1] auto[1] auto[0] auto[1] auto[0] 505287 1 T1 61 T2 12 T5 1538
auto[1] auto[1] auto[0] auto[1] auto[1] 538339 1 T1 15 T7 342 T15 278
auto[1] auto[1] auto[1] auto[0] auto[0] 575014 1 T1 27 T15 2 T4 365
auto[1] auto[1] auto[1] auto[0] auto[1] 547740 1 T15 1 T5 916 T8 13402
auto[1] auto[1] auto[1] auto[1] auto[0] 527927 1 T1 91 T7 381 T15 1
auto[1] auto[1] auto[1] auto[1] auto[1] 515202 1 T1 136 T4 295 T5 1118


Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for fifo_full_cross

Bins
sta_fifo_fullhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 219663 1 T1 45 T2 41 T7 179
auto[0] auto[0] auto[0] auto[0] auto[1] 230906 1 T1 26 T2 1 T15 298
auto[0] auto[0] auto[0] auto[1] auto[0] 231456 1 T1 59 T2 40 T15 1
auto[0] auto[0] auto[0] auto[1] auto[1] 223594 1 T1 58 T15 1 T4 444
auto[0] auto[0] auto[1] auto[0] auto[0] 1884437 1 T3 147649 T15 3 T4 882
auto[0] auto[0] auto[1] auto[0] auto[1] 238891 1 T1 82 T15 243 T4 160
auto[0] auto[0] auto[1] auto[1] auto[0] 219791 1 T1 147 T2 1 T7 283
auto[0] auto[0] auto[1] auto[1] auto[1] 230692 1 T1 1 T7 448 T15 1
auto[0] auto[1] auto[0] auto[0] auto[0] 593756 1 T1 55 T15 1 T4 66
auto[0] auto[1] auto[0] auto[0] auto[1] 524463 1 T1 14 T15 231 T4 102
auto[0] auto[1] auto[0] auto[1] auto[0] 552919 1 T1 62 T2 12 T5 1588
auto[0] auto[1] auto[0] auto[1] auto[1] 580717 1 T1 15 T7 350 T15 278
auto[0] auto[1] auto[1] auto[0] auto[0] 623115 1 T1 28 T15 2 T4 401
auto[0] auto[1] auto[1] auto[0] auto[1] 605639 1 T15 1 T5 928 T8 15652
auto[0] auto[1] auto[1] auto[1] auto[0] 580681 1 T1 96 T7 381 T15 1
auto[0] auto[1] auto[1] auto[1] auto[1] 566496 1 T1 139 T4 305 T5 1141
auto[1] auto[0] auto[0] auto[0] auto[0] 237 1 T28 1 T36 1 T145 17
auto[1] auto[0] auto[0] auto[0] auto[1] 1360 1 T28 26 T33 225 T19 37
auto[1] auto[0] auto[0] auto[1] auto[0] 750 1 T18 11 T28 439 T33 3
auto[1] auto[0] auto[0] auto[1] auto[1] 1441 1 T28 12 T33 73 T36 41
auto[1] auto[0] auto[1] auto[0] auto[0] 797 1 T28 37 T19 6 T36 280
auto[1] auto[0] auto[1] auto[0] auto[1] 1047 1 T18 42 T28 98 T36 98
auto[1] auto[0] auto[1] auto[1] auto[0] 1601 1 T8 6 T33 1 T19 7
auto[1] auto[0] auto[1] auto[1] auto[1] 804 1 T33 17 T19 2 T9 21
auto[1] auto[1] auto[0] auto[0] auto[0] 402 1 T19 62 T36 16 T146 100
auto[1] auto[1] auto[0] auto[0] auto[1] 592 1 T33 5 T9 12 T86 78
auto[1] auto[1] auto[0] auto[1] auto[0] 251 1 T33 27 T147 1 T148 76
auto[1] auto[1] auto[0] auto[1] auto[1] 670 1 T18 18 T33 4 T9 26
auto[1] auto[1] auto[1] auto[0] auto[0] 1118 1 T33 39 T149 11 T150 6
auto[1] auto[1] auto[1] auto[0] auto[1] 2500 1 T28 4 T36 39 T9 38
auto[1] auto[1] auto[1] auto[1] auto[0] 943 1 T18 391 T28 18 T33 16
auto[1] auto[1] auto[1] auto[1] auto[1] 852 1 T28 3 T9 8 T148 2


Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap key_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for fifo_depth_cross

Bins
sta_fifo_depthhmac_enendian_swapdigest_swapkey_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fifo_depth[0] auto[0] auto[0] auto[0] auto[0] 188255 1 T1 44 T2 35 T7 174
fifo_depth[0] auto[0] auto[0] auto[0] auto[1] 197276 1 T1 26 T2 1 T15 298
fifo_depth[0] auto[0] auto[0] auto[1] auto[0] 194682 1 T1 59 T2 27 T15 1
fifo_depth[0] auto[0] auto[0] auto[1] auto[1] 184397 1 T1 58 T15 1 T4 444
fifo_depth[0] auto[0] auto[1] auto[0] auto[0] 1737431 1 T3 125871 T15 3 T4 852
fifo_depth[0] auto[0] auto[1] auto[0] auto[1] 191591 1 T1 82 T15 243 T4 146
fifo_depth[0] auto[0] auto[1] auto[1] auto[0] 183237 1 T1 145 T2 1 T7 277
fifo_depth[0] auto[0] auto[1] auto[1] auto[1] 200586 1 T1 1 T7 434 T15 1
fifo_depth[0] auto[1] auto[0] auto[0] auto[0] 548208 1 T1 55 T15 1 T4 52
fifo_depth[0] auto[1] auto[0] auto[0] auto[1] 482170 1 T1 14 T15 231 T4 102
fifo_depth[0] auto[1] auto[0] auto[1] auto[0] 505287 1 T1 61 T2 12 T5 1538
fifo_depth[0] auto[1] auto[0] auto[1] auto[1] 538339 1 T1 15 T7 342 T15 278
fifo_depth[0] auto[1] auto[1] auto[0] auto[0] 575014 1 T1 27 T15 2 T4 365
fifo_depth[0] auto[1] auto[1] auto[0] auto[1] 547740 1 T15 1 T5 916 T8 13402
fifo_depth[0] auto[1] auto[1] auto[1] auto[0] 527927 1 T1 91 T7 381 T15 1
fifo_depth[0] auto[1] auto[1] auto[1] auto[1] 515202 1 T1 136 T4 295 T5 1118
fifo_depth[1] auto[0] auto[0] auto[0] auto[0] 3454 1 T1 1 T2 1 T7 4
fifo_depth[1] auto[0] auto[0] auto[0] auto[1] 3782 1 T4 1 T8 40 T38 2
fifo_depth[1] auto[0] auto[0] auto[1] auto[0] 4595 1 T2 1 T4 3 T5 5
fifo_depth[1] auto[0] auto[0] auto[1] auto[1] 3916 1 T5 1 T6 16 T8 116
fifo_depth[1] auto[0] auto[1] auto[0] auto[0] 40889 1 T3 4793 T5 18 T6 5
fifo_depth[1] auto[0] auto[1] auto[0] auto[1] 4686 1 T4 3 T6 4 T8 85
fifo_depth[1] auto[0] auto[1] auto[1] auto[0] 4304 1 T1 2 T7 5 T5 80
fifo_depth[1] auto[0] auto[1] auto[1] auto[1] 4064 1 T7 11 T4 2 T5 33
fifo_depth[1] auto[1] auto[0] auto[0] auto[0] 7195 1 T4 2 T5 23 T8 264
fifo_depth[1] auto[1] auto[0] auto[0] auto[1] 6976 1 T5 16 T6 6 T8 119
fifo_depth[1] auto[1] auto[0] auto[1] auto[0] 6705 1 T1 1 T5 23 T8 112
fifo_depth[1] auto[1] auto[0] auto[1] auto[1] 6540 1 T7 5 T6 7 T8 109
fifo_depth[1] auto[1] auto[1] auto[0] auto[0] 7920 1 T4 4 T5 17 T6 3
fifo_depth[1] auto[1] auto[1] auto[0] auto[1] 7127 1 T5 6 T8 278 T25 2
fifo_depth[1] auto[1] auto[1] auto[1] auto[0] 7444 1 T1 4 T8 159 T25 2
fifo_depth[1] auto[1] auto[1] auto[1] auto[1] 7760 1 T1 3 T4 1 T5 12
fifo_depth[2] auto[0] auto[0] auto[0] auto[0] 2919 1 T2 1 T7 1 T8 36
fifo_depth[2] auto[0] auto[0] auto[0] auto[1] 2968 1 T4 1 T8 40 T38 7
fifo_depth[2] auto[0] auto[0] auto[1] auto[0] 3888 1 T2 4 T4 3 T5 3
fifo_depth[2] auto[0] auto[0] auto[1] auto[1] 3367 1 T5 1 T6 2 T8 140
fifo_depth[2] auto[0] auto[1] auto[0] auto[0] 25691 1 T3 4623 T4 30 T5 7
fifo_depth[2] auto[0] auto[1] auto[0] auto[1] 3805 1 T4 3 T8 81 T38 5
fifo_depth[2] auto[0] auto[1] auto[1] auto[0] 3377 1 T7 1 T4 6 T5 24
fifo_depth[2] auto[0] auto[1] auto[1] auto[1] 3179 1 T7 2 T4 14 T5 24
fifo_depth[2] auto[1] auto[0] auto[0] auto[0] 6052 1 T4 3 T5 11 T8 261
fifo_depth[2] auto[1] auto[0] auto[0] auto[1] 5296 1 T5 4 T6 1 T8 102
fifo_depth[2] auto[1] auto[0] auto[1] auto[0] 5756 1 T5 23 T8 108 T38 5
fifo_depth[2] auto[1] auto[0] auto[1] auto[1] 5412 1 T7 3 T6 5 T8 105
fifo_depth[2] auto[1] auto[1] auto[0] auto[0] 6072 1 T4 4 T5 9 T6 1
fifo_depth[2] auto[1] auto[1] auto[0] auto[1] 5761 1 T5 4 T8 256 T25 1
fifo_depth[2] auto[1] auto[1] auto[1] auto[0] 6457 1 T1 1 T8 174 T25 1
fifo_depth[2] auto[1] auto[1] auto[1] auto[1] 6655 1 T5 10 T8 113 T25 1
fifo_depth[3] auto[0] auto[0] auto[0] auto[0] 2260 1 T8 48 T20 1 T76 1
fifo_depth[3] auto[0] auto[0] auto[0] auto[1] 2209 1 T8 41 T20 3 T76 1
fifo_depth[3] auto[0] auto[0] auto[1] auto[0] 2793 1 T2 4 T5 1 T8 135
fifo_depth[3] auto[0] auto[0] auto[1] auto[1] 2606 1 T8 131 T20 9 T72 2
fifo_depth[3] auto[0] auto[1] auto[0] auto[0] 18037 1 T3 3899 T5 3 T6 1
fifo_depth[3] auto[0] auto[1] auto[0] auto[1] 2990 1 T4 1 T8 90 T38 2
fifo_depth[3] auto[0] auto[1] auto[1] auto[0] 2706 1 T5 5 T6 2 T8 90
fifo_depth[3] auto[0] auto[1] auto[1] auto[1] 2423 1 T7 1 T4 3 T5 4
fifo_depth[3] auto[1] auto[0] auto[0] auto[0] 5036 1 T4 2 T5 4 T8 243
fifo_depth[3] auto[1] auto[0] auto[0] auto[1] 4232 1 T5 3 T8 94 T38 1
fifo_depth[3] auto[1] auto[0] auto[1] auto[0] 4628 1 T5 1 T8 84 T38 5
fifo_depth[3] auto[1] auto[0] auto[1] auto[1] 4305 1 T8 100 T38 1 T20 2
fifo_depth[3] auto[1] auto[1] auto[0] auto[0] 4905 1 T1 1 T4 5 T5 6
fifo_depth[3] auto[1] auto[1] auto[0] auto[1] 4675 1 T5 2 T8 281 T38 5
fifo_depth[3] auto[1] auto[1] auto[1] auto[0] 5341 1 T8 173 T38 2 T20 1
fifo_depth[3] auto[1] auto[1] auto[1] auto[1] 5921 1 T5 1 T8 122 T20 9
fifo_depth[4] auto[0] auto[0] auto[0] auto[0] 2342 1 T2 1 T8 34 T76 1
fifo_depth[4] auto[0] auto[0] auto[0] auto[1] 2152 1 T4 3 T8 22 T38 6
fifo_depth[4] auto[0] auto[0] auto[1] auto[0] 2860 1 T2 2 T8 117 T38 24
fifo_depth[4] auto[0] auto[0] auto[1] auto[1] 2584 1 T8 143 T20 7 T72 1
fifo_depth[4] auto[0] auto[1] auto[0] auto[0] 13359 1 T3 2948 T8 84 T38 3
fifo_depth[4] auto[0] auto[1] auto[0] auto[1] 3512 1 T4 3 T8 100 T20 2
fifo_depth[4] auto[0] auto[1] auto[1] auto[0] 2658 1 T4 6 T5 1 T8 71
fifo_depth[4] auto[0] auto[1] auto[1] auto[1] 2398 1 T4 12 T5 2 T8 74
fifo_depth[4] auto[1] auto[0] auto[0] auto[0] 4851 1 T4 2 T8 233 T38 1
fifo_depth[4] auto[1] auto[0] auto[0] auto[1] 4078 1 T5 1 T8 79 T38 1
fifo_depth[4] auto[1] auto[0] auto[1] auto[0] 4939 1 T5 3 T8 117 T38 1
fifo_depth[4] auto[1] auto[0] auto[1] auto[1] 4179 1 T8 104 T38 3 T20 5
fifo_depth[4] auto[1] auto[1] auto[0] auto[0] 4742 1 T4 4 T5 2 T8 413
fifo_depth[4] auto[1] auto[1] auto[0] auto[1] 4696 1 T8 241 T25 1 T20 1
fifo_depth[4] auto[1] auto[1] auto[1] auto[0] 5089 1 T8 169 T38 1 T72 2
fifo_depth[4] auto[1] auto[1] auto[1] auto[1] 5601 1 T4 4 T8 122 T39 1
fifo_depth[5] auto[0] auto[0] auto[0] auto[0] 1743 1 T2 1 T8 43 T76 1
fifo_depth[5] auto[0] auto[0] auto[0] auto[1] 1594 1 T4 1 T8 13 T42 46
fifo_depth[5] auto[0] auto[0] auto[1] auto[0] 2031 1 T2 1 T4 2 T8 119
fifo_depth[5] auto[0] auto[0] auto[1] auto[1] 1966 1 T8 125 T20 1 T39 1
fifo_depth[5] auto[0] auto[1] auto[0] auto[0] 9269 1 T3 2117 T8 61 T38 2
fifo_depth[5] auto[0] auto[1] auto[0] auto[1] 2413 1 T4 1 T8 68 T20 1
fifo_depth[5] auto[0] auto[1] auto[1] auto[0] 2035 1 T8 77 T38 2 T76 1
fifo_depth[5] auto[0] auto[1] auto[1] auto[1] 1841 1 T4 3 T8 67 T20 4
fifo_depth[5] auto[1] auto[0] auto[0] auto[0] 4072 1 T4 4 T8 193 T38 1
fifo_depth[5] auto[1] auto[0] auto[0] auto[1] 3449 1 T8 71 T38 1 T40 16
fifo_depth[5] auto[1] auto[0] auto[1] auto[0] 3806 1 T8 100 T38 3 T20 3
fifo_depth[5] auto[1] auto[0] auto[1] auto[1] 3551 1 T8 104 T20 1 T39 3
fifo_depth[5] auto[1] auto[1] auto[0] auto[0] 3778 1 T4 4 T8 340 T39 3
fifo_depth[5] auto[1] auto[1] auto[0] auto[1] 3876 1 T8 215 T20 1 T17 1
fifo_depth[5] auto[1] auto[1] auto[1] auto[0] 4306 1 T8 133 T39 1 T151 5
fifo_depth[5] auto[1] auto[1] auto[1] auto[1] 4763 1 T4 1 T8 98 T20 1
fifo_depth[6] auto[0] auto[0] auto[0] auto[0] 1485 1 T2 2 T8 19 T76 1
fifo_depth[6] auto[0] auto[0] auto[0] auto[1] 1326 1 T8 11 T38 3 T76 1
fifo_depth[6] auto[0] auto[0] auto[1] auto[0] 1754 1 T2 1 T4 2 T8 85
fifo_depth[6] auto[0] auto[0] auto[1] auto[1] 1692 1 T8 112 T20 3 T39 1
fifo_depth[6] auto[0] auto[1] auto[0] auto[0] 6778 1 T3 1555 T8 56 T38 1
fifo_depth[6] auto[0] auto[1] auto[0] auto[1] 2094 1 T4 1 T8 68 T38 1
fifo_depth[6] auto[0] auto[1] auto[1] auto[0] 1668 1 T4 6 T8 51 T18 42
fifo_depth[6] auto[0] auto[1] auto[1] auto[1] 1450 1 T4 10 T8 33 T20 1
fifo_depth[6] auto[1] auto[0] auto[0] auto[0] 3359 1 T8 178 T39 1 T151 117
fifo_depth[6] auto[1] auto[0] auto[0] auto[1] 2867 1 T8 68 T20 4 T40 12
fifo_depth[6] auto[1] auto[0] auto[1] auto[0] 3452 1 T8 77 T20 5 T18 13
fifo_depth[6] auto[1] auto[0] auto[1] auto[1] 2830 1 T8 84 T20 1 T39 1
fifo_depth[6] auto[1] auto[1] auto[0] auto[0] 3136 1 T4 4 T5 1 T8 279
fifo_depth[6] auto[1] auto[1] auto[0] auto[1] 3224 1 T8 188 T20 1 T18 17
fifo_depth[6] auto[1] auto[1] auto[1] auto[0] 3682 1 T8 123 T39 1 T151 3
fifo_depth[6] auto[1] auto[1] auto[1] auto[1] 3981 1 T8 72 T152 41 T18 24
fifo_depth[7] auto[0] auto[0] auto[0] auto[0] 1006 1 T8 19 T152 35 T28 37
fifo_depth[7] auto[0] auto[0] auto[0] auto[1] 848 1 T4 1 T8 2 T76 1
fifo_depth[7] auto[0] auto[0] auto[1] auto[0] 1051 1 T4 1 T8 68 T39 1
fifo_depth[7] auto[0] auto[0] auto[1] auto[1] 1106 1 T8 68 T20 1 T39 2
fifo_depth[7] auto[0] auto[1] auto[0] auto[0] 4150 1 T3 977 T8 40 T42 19
fifo_depth[7] auto[0] auto[1] auto[0] auto[1] 1311 1 T8 58 T42 1 T18 26
fifo_depth[7] auto[0] auto[1] auto[1] auto[0] 1136 1 T8 49 T18 31 T124 1
fifo_depth[7] auto[0] auto[1] auto[1] auto[1] 925 1 T4 3 T8 27 T20 1
fifo_depth[7] auto[1] auto[0] auto[0] auto[0] 2280 1 T4 1 T8 122 T38 1
fifo_depth[7] auto[1] auto[0] auto[0] auto[1] 2062 1 T8 37 T40 6 T41 61
fifo_depth[7] auto[1] auto[0] auto[1] auto[0] 2094 1 T8 61 T20 2 T18 11
fifo_depth[7] auto[1] auto[0] auto[1] auto[1] 1914 1 T8 59 T20 1 T39 2
fifo_depth[7] auto[1] auto[1] auto[0] auto[0] 2033 1 T4 4 T8 199 T151 32
fifo_depth[7] auto[1] auto[1] auto[0] auto[1] 2228 1 T8 146 T20 1 T18 15
fifo_depth[7] auto[1] auto[1] auto[1] auto[0] 2550 1 T8 78 T76 1 T39 1
fifo_depth[7] auto[1] auto[1] auto[1] auto[1] 2639 1 T4 1 T8 35 T39 1

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