Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	19425452	1			T1	1703		T2	200		T3	440014
all_pins[1]	19425452	1			T1	1703		T2	200		T3	440014
all_pins[2]	19425452	1			T1	1703		T2	200		T3	440014

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	49689444	1			T1	4611		T2	573		T3	117500
values[0x1]	8586912	1			T1	498		T2	27		T3	145042
transitions[0x0=>0x1]	8586733	1			T1	498		T2	27		T3	145042
transitions[0x1=>0x0]	8586745	1			T1	498		T2	27		T3	145042

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	19403119	1			T1	1672		T2	195		T3	439628
all_pins[0]	values[0x1]	22333	1			T1	31		T2	5		T3	386
all_pins[0]	transitions[0x0=>0x1]	22263	1			T1	31		T2	5		T3	386
all_pins[0]	transitions[0x1=>0x0]	8564103	1			T1	467		T2	22		T3	144656
all_pins[1]	values[0x0]	19425034	1			T1	1703		T2	200		T3	440014
all_pins[1]	values[0x1]	418	1			T8	6		T20	4		T18	7
all_pins[1]	transitions[0x0=>0x1]	360	1			T8	5		T20	3		T18	5
all_pins[1]	transitions[0x1=>0x0]	22275	1			T1	31		T2	5		T3	386
all_pins[2]	values[0x0]	10861291	1			T1	1236		T2	178		T3	295358
all_pins[2]	values[0x1]	8564161	1			T1	467		T2	22		T3	144656
all_pins[2]	transitions[0x0=>0x1]	8564110	1			T1	467		T2	22		T3	144656
all_pins[2]	transitions[0x1=>0x0]	367	1			T8	5		T20	2		T18	7