Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1032 1 T8 10 T20 29 T18 10
all_values[1] 1032 1 T8 10 T20 29 T18 10
all_values[2] 1032 1 T8 10 T20 29 T18 10


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1591 1 T8 12 T20 45 T18 15
auto[1] 1505 1 T8 18 T20 42 T18 15


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1115 1 T8 14 T20 32 T18 10
auto[1] 1981 1 T8 16 T20 55 T18 20


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1786 1 T8 19 T20 54 T18 13
auto[1] 1310 1 T8 11 T20 33 T18 17


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 208 1 T8 1 T20 3 T18 2
all_values[0] auto[0] auto[0] auto[1] 103 1 T20 3 T124 2 T33 3
all_values[0] auto[0] auto[1] auto[0] 180 1 T8 5 T20 2 T18 1
all_values[0] auto[0] auto[1] auto[1] 104 1 T8 1 T20 6 T124 1
all_values[0] auto[1] auto[0] auto[1] 238 1 T8 2 T20 6 T18 6
all_values[0] auto[1] auto[1] auto[1] 199 1 T8 1 T20 9 T18 1
all_values[1] auto[0] auto[0] auto[0] 170 1 T8 3 T20 9 T124 2
all_values[1] auto[0] auto[0] auto[1] 132 1 T8 1 T20 3 T124 1
all_values[1] auto[0] auto[1] auto[0] 157 1 T20 6 T18 1 T124 1
all_values[1] auto[0] auto[1] auto[1] 128 1 T8 2 T20 3 T18 2
all_values[1] auto[1] auto[0] auto[1] 224 1 T8 1 T20 4 T18 2
all_values[1] auto[1] auto[1] auto[1] 221 1 T8 3 T20 4 T18 5
all_values[2] auto[0] auto[0] auto[0] 200 1 T8 2 T20 4 T18 2
all_values[2] auto[0] auto[0] auto[1] 96 1 T20 6 T18 1 T33 1
all_values[2] auto[0] auto[1] auto[0] 200 1 T8 3 T20 8 T18 4
all_values[2] auto[0] auto[1] auto[1] 108 1 T8 1 T20 1 T124 1
all_values[2] auto[1] auto[0] auto[1] 220 1 T8 2 T20 7 T18 2
all_values[2] auto[1] auto[1] auto[1] 208 1 T8 2 T20 3 T18 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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