Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	90	0	90	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	0	5	100.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	0	7	100.00	100	1	1	0
key_swap	2	0	2	100.00	100	1	1	2
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	16	0	16	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	0	35	100.00	100	1	1	0
key_length_x_digest_size	35	0	35	100.00	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for digest_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_invalid	4783	1			T1	3		T2	1		T15	6
sha2_none	4807	1			T1	6		T7	1		T15	3
sha2_512	8147	1			T1	11		T2	1		T3	386
sha2_384	7924	1			T1	11		T7	3		T15	3
sha2_256	6848	1			T1	5		T2	3		T7	1

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20241

1

T1

12

T2

2

T3

386

auto[1]

12706

1

T1

25

T2

3

T7

4

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12529

1

T1

20

T2

4

T7

2

auto[1]

20418

1

T1

17

T2

1

T3

386

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

17181

1

T1

20

T2

1

T7

2

disabled

15766

1

T1

17

T2

4

T3

386

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for key_length

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	5121	1			T1	5		T2	1		T7	3
key_none	8237	1			T1	3		T2	1		T3	386
key_1024	4792	1			T1	6		T15	3		T4	4
key_512	4164	1			T1	9		T2	1		T15	3
key_384	3792	1			T1	4		T7	1		T15	3
key_256	3444	1			T1	5		T2	1		T15	1
key_128	3316	1			T1	5		T2	1		T7	1

---

Summary for Variable key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for key_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20251

1

T1

21

T2

4

T3

386

auto[1]

12696

1

T1

16

T2

1

T7

2

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

32747

1

T1

37

T2

5

T3

386

disabled

200

1

T15

1

T8

2

T20

4

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap key_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en

endian_swap

digest_swap

key_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

auto[0]

auto[0]

auto[0]

1796

1

T1

3

T15

2

T4

2

enabled

auto[0]

auto[0]

auto[1]

1695

1

T1

1

T15

1

T4

2

enabled

auto[0]

auto[1]

auto[0]

1743

1

T1

4

T2

1

T15

1

enabled

auto[0]

auto[1]

auto[1]

1817

1

T1

2

T7

1

T15

2

enabled

auto[1]

auto[0]

auto[0]

4502

1

T1

2

T4

3

T5

2

enabled

auto[1]

auto[0]

auto[1]

1830

1

T4

1

T5

3

T8

31

enabled

auto[1]

auto[1]

auto[0]

1966

1

T1

4

T7

1

T15

1

enabled

auto[1]

auto[1]

auto[1]

1832

1

T1

4

T4

6

T5

4

disabled

auto[0]

auto[0]

auto[0]

1378

1

T1

1

T2

1

T7

1

disabled

auto[0]

auto[0]

auto[1]

1443

1

T1

3

T2

1

T15

4

disabled

auto[0]

auto[1]

auto[0]

1333

1

T1

3

T2

1

T4

1

disabled

auto[0]

auto[1]

auto[1]

1324

1

T1

3

T15

2

T4

2

disabled

auto[1]

auto[0]

auto[0]

6201

1

T3

386

T15

2

T4

3

disabled

auto[1]

auto[0]

auto[1]

1396

1

T1

2

T15

3

T4

2

disabled

auto[1]

auto[1]

auto[0]

1332

1

T1

4

T2

1

T7

1

disabled

auto[1]

auto[1]

auto[1]

1359

1

T1

1

T7

1

T15

1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

17111

1

T1

20

T2

1

T7

2

enabled

disabled

70

1

T20

3

T42

1

T18

1

disabled

disabled

130

1

T15

1

T8

2

T20

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

15636

1

T1

17

T2

4

T3

386

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	0	35	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1227	1			T15	3		T4	2		T6	1
key_invalid	sha2_none	926	1			T7	1		T4	1		T5	1
key_invalid	sha2_512	963	1			T1	3		T15	1		T4	1
key_invalid	sha2_384	967	1			T1	2		T7	1		T15	1
key_invalid	sha2_256	929	1			T2	1		T7	1		T15	2
key_none	sha2_invalid	655	1			T2	1		T5	1		T6	2
key_none	sha2_none	651	1			T1	2		T15	1		T4	1
key_none	sha2_512	2574	1			T3	386		T15	1		T4	2
key_none	sha2_384	2639	1			T1	1		T5	1		T8	9
key_none	sha2_256	1661	1			T5	4		T8	6		T20	9
key_1024	sha2_invalid	585	1			T1	1		T15	1		T4	1
key_1024	sha2_none	660	1			T4	1		T5	1		T6	2
key_1024	sha2_512	1824	1			T1	2		T15	1		T8	12
key_1024	sha2_384	1007	1			T4	1		T5	1		T8	13
key_512	sha2_invalid	536	1			T15	2		T8	14		T25	1
key_512	sha2_none	634	1			T1	3		T4	1		T6	2
key_512	sha2_512	700	1			T1	1		T4	2		T5	1
key_512	sha2_384	1309	1			T1	3		T4	1		T8	5
key_512	sha2_256	930	1			T1	2		T2	1		T15	1
key_384	sha2_invalid	594	1			T1	1		T4	3		T5	3
key_384	sha2_none	657	1			T1	1		T15	1		T4	1
key_384	sha2_512	695	1			T1	1		T5	3		T6	3
key_384	sha2_384	639	1			T1	1		T7	1		T15	1
key_384	sha2_256	1151	1			T15	1		T6	1		T8	9
key_256	sha2_invalid	571	1			T4	2		T5	4		T8	7
key_256	sha2_none	614	1			T5	3		T8	8		T25	3
key_256	sha2_512	702	1			T1	2		T5	1		T8	8
key_256	sha2_384	668	1			T1	3		T15	1		T4	2
key_256	sha2_256	840	1			T2	1		T5	1		T6	1
key_128	sha2_invalid	593	1			T1	1		T4	1		T5	1
key_128	sha2_none	650	1			T15	1		T4	2		T5	2
key_128	sha2_512	670	1			T1	2		T2	1		T4	1
key_128	sha2_384	681	1			T1	1		T7	1		T4	4
key_128	sha2_256	675	1			T1	1		T6	4		T8	8

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

652

1

T1

2

T15

1

T4

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	0	35	100.00

Automatically Generated Cross Bins for key_length_x_digest_size

Bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_invalid	sha2_invalid	1227	1			T15	3		T4	2		T6	1
key_invalid	sha2_none	926	1			T7	1		T4	1		T5	1
key_invalid	sha2_512	963	1			T1	3		T15	1		T4	1
key_invalid	sha2_384	967	1			T1	2		T7	1		T15	1
key_invalid	sha2_256	929	1			T2	1		T7	1		T15	2
key_none	sha2_invalid	655	1			T2	1		T5	1		T6	2
key_none	sha2_none	651	1			T1	2		T15	1		T4	1
key_none	sha2_512	2574	1			T3	386		T15	1		T4	2
key_none	sha2_384	2639	1			T1	1		T5	1		T8	9
key_none	sha2_256	1661	1			T5	4		T8	6		T20	9
key_1024	sha2_invalid	585	1			T1	1		T15	1		T4	1
key_1024	sha2_none	660	1			T4	1		T5	1		T6	2
key_1024	sha2_512	1824	1			T1	2		T15	1		T8	12
key_1024	sha2_384	1007	1			T4	1		T5	1		T8	13
key_1024	sha2_256	652	1			T1	2		T15	1		T4	1
key_512	sha2_invalid	536	1			T15	2		T8	14		T25	1
key_512	sha2_none	634	1			T1	3		T4	1		T6	2
key_512	sha2_512	700	1			T1	1		T4	2		T5	1
key_512	sha2_384	1309	1			T1	3		T4	1		T8	5
key_512	sha2_256	930	1			T1	2		T2	1		T15	1
key_384	sha2_invalid	594	1			T1	1		T4	3		T5	3
key_384	sha2_none	657	1			T1	1		T15	1		T4	1
key_384	sha2_512	695	1			T1	1		T5	3		T6	3
key_384	sha2_384	639	1			T1	1		T7	1		T15	1
key_384	sha2_256	1151	1			T15	1		T6	1		T8	9
key_256	sha2_invalid	571	1			T4	2		T5	4		T8	7
key_256	sha2_none	614	1			T5	3		T8	8		T25	3
key_256	sha2_512	702	1			T1	2		T5	1		T8	8
key_256	sha2_384	668	1			T1	3		T15	1		T4	2
key_256	sha2_256	840	1			T2	1		T5	1		T6	1
key_128	sha2_invalid	593	1			T1	1		T4	1		T5	1
key_128	sha2_none	650	1			T15	1		T4	2		T5	2
key_128	sha2_512	670	1			T1	2		T2	1		T4	1
key_128	sha2_384	681	1			T1	1		T7	1		T4	4
key_128	sha2_256	675	1			T1	1		T6	4		T8	8